This commit was manufactured by cvs2svn to create branch 'gdb_6_4-branch'.gdb_6_4-2005-11-01-branchpoint

Sprout from gdb-csl-arm-20051020-branch 2005-10-20 00:09:02 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb-csl-' Cherrypick from master 2005-11-01 22:57:23 UTC Alan Modra <amodra@gmail.com> ' PR ld/1775': ChangeLog Makefile.def Makefile.in Makefile.tpl bfd/ChangeLog bfd/Makefile.am bfd/Makefile.in bfd/aoutx.h bfd/archures.c bfd/bfd-in2.h bfd/bfdwin.c bfd/cache.c bfd/coff-rs6000.c bfd/coff-z80.c bfd/coff64-rs6000.c bfd/coffcode.h bfd/config.bfd bfd/configure bfd/configure.in bfd/cpu-ia64-opc.c bfd/cpu-z80.c bfd/dep-in.sed bfd/elf-bfd.h bfd/elf.c bfd/elf32-arm.c bfd/elf32-bfin.c bfd/elf32-cris.c bfd/elf32-hppa.c bfd/elf32-i370.c bfd/elf32-i386.c bfd/elf32-m32r.c bfd/elf32-m68k.c bfd/elf32-ppc.c bfd/elf32-s390.c bfd/elf32-sh.c bfd/elf64-ppc.c bfd/elf64-s390.c bfd/elf64-x86-64.c bfd/elflink.c bfd/elfxx-ia64.c bfd/elfxx-mips.c bfd/elfxx-mips.h bfd/elfxx-sparc.c bfd/elfxx-sparc.h bfd/hppabsd-core.c bfd/hpux-core.c bfd/libbfd-in.h bfd/libbfd.c bfd/libbfd.h bfd/linker.c bfd/osf-core.c bfd/po/SRC-POTFILES.in bfd/po/bfd.pot bfd/reloc.c bfd/rs6000-core.c bfd/sco5-core.c bfd/targets.c bfd/trad-core.c bfd/version.h bfd/xcoff-target.h cpu/ChangeLog cpu/frv.opc cpu/m32c.cpu cpu/m32c.opc cpu/m32r.opc depcomp etc/ChangeLog etc/texi2pod.pl gdb/ChangeLog gdb/Makefile.in gdb/NEWS gdb/config/i386/tm-cygwin.h gdb/config/iq2000/iq2000.mt gdb/config/ms1/ms1.mt gdb/doc/ChangeLog gdb/doc/gdb.texinfo gdb/doublest.c gdb/dwarf2read.c gdb/event-top.c gdb/gdbserver/ChangeLog gdb/gdbserver/linux-ia64-low.c gdb/gdbserver/server.c gdb/hppa-hpux-tdep.c gdb/hppa-tdep.h gdb/inf-ttrace.c gdb/main.c gdb/mi/gdb-mi.el gdb/po/gdbtext gdb/ppc-tdep.h gdb/regformats/reg-ia64.dat gdb/rs6000-tdep.c gdb/testsuite/ChangeLog gdb/testsuite/gdb.ada/array_return/p.adb gdb/testsuite/gdb.ada/array_return/pck.adb gdb/testsuite/gdb.ada/array_return/pck.ads gdb/testsuite/gdb.ada/arrayidx/p.adb gdb/testsuite/gdb.asm/asm-source.exp gdb/testsuite/gdb.base/bfp-test.exp gdb/tui/tui-command.c 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opcodes/ip2k-dis.c opcodes/ip2k-opc.c opcodes/m32c-asm.c opcodes/m32c-desc.c opcodes/m32c-desc.h opcodes/m32c-dis.c opcodes/m32c-ibld.c opcodes/m32c-opc.c opcodes/m32c-opc.h opcodes/m32r-asm.c opcodes/m32r-desc.c opcodes/m32r-desc.h opcodes/m32r-dis.c opcodes/m32r-opc.c opcodes/ms1-desc.c opcodes/ms1-desc.h opcodes/ms1-dis.c opcodes/openrisc-desc.c opcodes/openrisc-desc.h opcodes/openrisc-dis.c opcodes/openrisc-opc.c opcodes/po/POTFILES.in opcodes/po/opcodes.pot opcodes/xstormy16-desc.c opcodes/xstormy16-desc.h opcodes/xstormy16-dis.c opcodes/xstormy16-opc.c opcodes/z80-dis.c sim/frv/ChangeLog sim/frv/arch.c sim/frv/arch.h sim/frv/cpu.c sim/frv/cpu.h sim/frv/cpuall.h sim/frv/decode.c sim/frv/decode.h sim/frv/frv-sim.h sim/frv/mloop.in sim/frv/model.c sim/frv/pipeline.c sim/frv/sem.c sim/frv/traps.c Delete: intl/ChangeLog intl/Makefile.in intl/acconfig.h intl/aclocal.m4 intl/bindtextdom.c intl/cat-compat.c intl/config.in intl/configure intl/configure.in intl/dcgettext.c intl/dgettext.c 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sim/testsuite/sim/sh64/media/fsubs.cgs sim/testsuite/sim/sh64/media/ftrcdl.cgs sim/testsuite/sim/sh64/media/ftrcdq.cgs sim/testsuite/sim/sh64/media/ftrcsl.cgs sim/testsuite/sim/sh64/media/ftrcsq.cgs sim/testsuite/sim/sh64/media/ftrvs.cgs sim/testsuite/sim/sh64/media/getcfg.cgs sim/testsuite/sim/sh64/media/getcon.cgs sim/testsuite/sim/sh64/media/gettr.cgs sim/testsuite/sim/sh64/media/icbi.cgs sim/testsuite/sim/sh64/media/ldb.cgs sim/testsuite/sim/sh64/media/ldhil.cgs sim/testsuite/sim/sh64/media/ldhiq.cgs sim/testsuite/sim/sh64/media/ldl.cgs sim/testsuite/sim/sh64/media/ldlol.cgs sim/testsuite/sim/sh64/media/ldloq.cgs sim/testsuite/sim/sh64/media/ldq.cgs sim/testsuite/sim/sh64/media/ldub.cgs sim/testsuite/sim/sh64/media/lduw.cgs sim/testsuite/sim/sh64/media/ldw.cgs sim/testsuite/sim/sh64/media/ldxb.cgs sim/testsuite/sim/sh64/media/ldxl.cgs sim/testsuite/sim/sh64/media/ldxq.cgs sim/testsuite/sim/sh64/media/ldxub.cgs sim/testsuite/sim/sh64/media/ldxuw.cgs sim/testsuite/sim/sh64/media/ldxw.cgs sim/testsuite/sim/sh64/media/mabsl.cgs sim/testsuite/sim/sh64/media/mabsw.cgs sim/testsuite/sim/sh64/media/maddl.cgs sim/testsuite/sim/sh64/media/maddsl.cgs sim/testsuite/sim/sh64/media/maddsub.cgs sim/testsuite/sim/sh64/media/maddsw.cgs sim/testsuite/sim/sh64/media/maddw.cgs sim/testsuite/sim/sh64/media/mcmpeqb.cgs sim/testsuite/sim/sh64/media/mcmpeql.cgs sim/testsuite/sim/sh64/media/mcmpeqw.cgs sim/testsuite/sim/sh64/media/mcmpgtl.cgs sim/testsuite/sim/sh64/media/mcmpgtub.cgs sim/testsuite/sim/sh64/media/mcmpgtw.cgs sim/testsuite/sim/sh64/media/mcmv.cgs sim/testsuite/sim/sh64/media/mcnvslw.cgs sim/testsuite/sim/sh64/media/mcnvswb.cgs sim/testsuite/sim/sh64/media/mcnvswub.cgs sim/testsuite/sim/sh64/media/mextr1.cgs sim/testsuite/sim/sh64/media/mextr2.cgs sim/testsuite/sim/sh64/media/mextr3.cgs sim/testsuite/sim/sh64/media/mextr4.cgs sim/testsuite/sim/sh64/media/mextr5.cgs sim/testsuite/sim/sh64/media/mextr6.cgs sim/testsuite/sim/sh64/media/mextr7.cgs sim/testsuite/sim/sh64/media/mmacfxwl.cgs sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs sim/testsuite/sim/sh64/media/mmulfxl.cgs sim/testsuite/sim/sh64/media/mmulfxrpw.cgs sim/testsuite/sim/sh64/media/mmulfxw.cgs sim/testsuite/sim/sh64/media/mmulhiwl.cgs sim/testsuite/sim/sh64/media/mmull.cgs sim/testsuite/sim/sh64/media/mmullowl.cgs sim/testsuite/sim/sh64/media/mmulsumwq.cgs sim/testsuite/sim/sh64/media/mmulw.cgs sim/testsuite/sim/sh64/media/movi.cgs sim/testsuite/sim/sh64/media/mpermw.cgs sim/testsuite/sim/sh64/media/msadubq.cgs sim/testsuite/sim/sh64/media/mshaldsl.cgs sim/testsuite/sim/sh64/media/mshaldsw.cgs sim/testsuite/sim/sh64/media/mshardl.cgs sim/testsuite/sim/sh64/media/mshardsq.cgs sim/testsuite/sim/sh64/media/mshardw.cgs sim/testsuite/sim/sh64/media/mshfhib.cgs sim/testsuite/sim/sh64/media/mshfhil.cgs sim/testsuite/sim/sh64/media/mshfhiw.cgs sim/testsuite/sim/sh64/media/mshflob.cgs sim/testsuite/sim/sh64/media/mshflol.cgs sim/testsuite/sim/sh64/media/mshflow.cgs sim/testsuite/sim/sh64/media/mshlldl.cgs sim/testsuite/sim/sh64/media/mshlldw.cgs sim/testsuite/sim/sh64/media/mshlrdl.cgs sim/testsuite/sim/sh64/media/mshlrdw.cgs sim/testsuite/sim/sh64/media/msubl.cgs sim/testsuite/sim/sh64/media/msubsl.cgs sim/testsuite/sim/sh64/media/msubsub.cgs sim/testsuite/sim/sh64/media/msubsw.cgs sim/testsuite/sim/sh64/media/msubw.cgs sim/testsuite/sim/sh64/media/mulsl.cgs sim/testsuite/sim/sh64/media/mulul.cgs sim/testsuite/sim/sh64/media/nop.cgs sim/testsuite/sim/sh64/media/nsb.cgs sim/testsuite/sim/sh64/media/ocbi.cgs sim/testsuite/sim/sh64/media/ocbp.cgs sim/testsuite/sim/sh64/media/ocbwb.cgs sim/testsuite/sim/sh64/media/or.cgs sim/testsuite/sim/sh64/media/ori.cgs sim/testsuite/sim/sh64/media/prefi.cgs sim/testsuite/sim/sh64/media/pta.cgs sim/testsuite/sim/sh64/media/ptabs.cgs sim/testsuite/sim/sh64/media/ptb.cgs sim/testsuite/sim/sh64/media/ptrel.cgs sim/testsuite/sim/sh64/media/putcfg.cgs sim/testsuite/sim/sh64/media/putcon.cgs sim/testsuite/sim/sh64/media/rte.cgs sim/testsuite/sim/sh64/media/shard.cgs sim/testsuite/sim/sh64/media/shardl.cgs sim/testsuite/sim/sh64/media/shari.cgs sim/testsuite/sim/sh64/media/sharil.cgs sim/testsuite/sim/sh64/media/shlld.cgs sim/testsuite/sim/sh64/media/shlldl.cgs sim/testsuite/sim/sh64/media/shlli.cgs sim/testsuite/sim/sh64/media/shllil.cgs sim/testsuite/sim/sh64/media/shlrd.cgs sim/testsuite/sim/sh64/media/shlrdl.cgs sim/testsuite/sim/sh64/media/shlri.cgs sim/testsuite/sim/sh64/media/shlril.cgs sim/testsuite/sim/sh64/media/shori.cgs sim/testsuite/sim/sh64/media/sleep.cgs sim/testsuite/sim/sh64/media/stb.cgs sim/testsuite/sim/sh64/media/sthil.cgs sim/testsuite/sim/sh64/media/sthiq.cgs sim/testsuite/sim/sh64/media/stl.cgs sim/testsuite/sim/sh64/media/stlol.cgs sim/testsuite/sim/sh64/media/stloq.cgs sim/testsuite/sim/sh64/media/stq.cgs sim/testsuite/sim/sh64/media/stw.cgs sim/testsuite/sim/sh64/media/stxb.cgs sim/testsuite/sim/sh64/media/stxl.cgs sim/testsuite/sim/sh64/media/stxq.cgs sim/testsuite/sim/sh64/media/stxw.cgs sim/testsuite/sim/sh64/media/sub.cgs sim/testsuite/sim/sh64/media/subl.cgs sim/testsuite/sim/sh64/media/swapq.cgs sim/testsuite/sim/sh64/media/synci.cgs sim/testsuite/sim/sh64/media/synco.cgs sim/testsuite/sim/sh64/media/testutils.inc sim/testsuite/sim/sh64/media/trapa.cgs sim/testsuite/sim/sh64/media/xor.cgs sim/testsuite/sim/sh64/media/xori.cgs sim/testsuite/sim/sh64/misc/fr-dr.s
author: nobody <> 2005-11-01 22:57:24 +0000
committer: nobody <> 2005-11-01 22:57:24 +0000
commit: e97bf4462428241425b287215aa9fd48478b3c36 (patch)
tree: fc92693b860773c8fdb9bd836cae7434dc790216
parent: 25cf6930c89092db8bd48cf98b88dd2e258f93f6 (diff)
download: binutils-gdb-e97bf4462428241425b287215aa9fd48478b3c36.tar.gz
671 files changed, 33674 insertions, 101688 deletions
diff --git a/ChangeLog b/ChangeLog
index b7019094567..5f555453bd4 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,17 @@
+2005-10-22  Paolo Bonzini  <bonzini@gnu.org>
+
+	PR bootstrap/24297
+	* Makefile.tpl (do-[+make-target+], do-check, install,
+	stage[+id+]-bubble, [+compare-target+]): Ensure $$r and $$s
+	are set before recursing.
+	* Makefile.in: Regenerate.
+
+2005-10-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR bootstrap/18939
+	* Makefile.def (gcc) <target>: Fix thinko.
+	* Makefile.in: Regenerate.
+
 2005-10-17  Bernd Schmidt  <bernd.schmidt@analog.com>
 
 	* configure.in (bfin-*-*): Use test, not brackets, in if statement.
diff --git a/Makefile.def b/Makefile.def
index 9731bd66f57..035def58c52 100644
--- a/Makefile.def
+++ b/Makefile.def
@@ -60,7 +60,7 @@ host_modules= { module= fixincludes;
 host_modules= { module= flex; no_check_cross= true; };
 host_modules= { module= gas; bootstrap=true; };
 host_modules= { module= gcc; bootstrap=true; 
-		target="`if [ -f gcc/stage_last ]; then echo quickstrap ; else echo all; fi`";
+		target="`if [ -f stage_last ]; then echo quickstrap ; else echo all; fi`";
 		extra_make_flags="$(EXTRA_GCC_FLAGS)"; };
 host_modules= { module= gawk; };
 host_modules= { module= gettext; };
diff --git a/Makefile.in b/Makefile.in
index 0de1a3c7a23..0344ad3ae70 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -1001,7 +1001,9 @@ all-target:  \
 .PHONY: do-info
 do-info:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) info-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) info-host \
 	  info-target
 	@$(stage)
 
@@ -1101,7 +1103,9 @@ info-target:  \
 .PHONY: do-dvi
 do-dvi:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) dvi-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) dvi-host \
 	  dvi-target
 	@$(stage)
 
@@ -1201,7 +1205,9 @@ dvi-target:  \
 .PHONY: do-html
 do-html:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) html-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) html-host \
 	  html-target
 	@$(stage)
 
@@ -1301,7 +1307,9 @@ html-target:  \
 .PHONY: do-TAGS
 do-TAGS:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) TAGS-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) TAGS-host \
 	  TAGS-target
 	@$(stage)
 
@@ -1401,7 +1409,9 @@ TAGS-target:  \
 .PHONY: do-install-info
 do-install-info:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) install-info-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) install-info-host \
 	  install-info-target
 	@$(stage)
 
@@ -1501,7 +1511,9 @@ install-info-target:  \
 .PHONY: do-installcheck
 do-installcheck:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) installcheck-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) installcheck-host \
 	  installcheck-target
 	@$(stage)
 
@@ -1601,7 +1613,9 @@ installcheck-target:  \
 .PHONY: do-mostlyclean
 do-mostlyclean:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) mostlyclean-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) mostlyclean-host \
 	  mostlyclean-target
 	@$(stage)
 
@@ -1701,7 +1715,9 @@ mostlyclean-target:  \
 .PHONY: do-clean
 do-clean:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) clean-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) clean-host \
 	  clean-target
 	@$(stage)
 
@@ -1801,7 +1817,9 @@ clean-target:  \
 .PHONY: do-distclean
 do-distclean:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) distclean-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) distclean-host \
 	  distclean-target
 	@$(stage)
 
@@ -1901,7 +1919,9 @@ distclean-target:  \
 .PHONY: do-maintainer-clean
 do-maintainer-clean:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) maintainer-clean-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) maintainer-clean-host \
 	  maintainer-clean-target
 	@$(stage)
 
@@ -2158,7 +2178,9 @@ check-target:  \
 
 do-check:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) check-host check-target
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) check-host check-target
 	@$(stage)
 
 # Automated reporting of test results.
@@ -2187,7 +2209,9 @@ mail-report-with-warnings.log: warning.log
 .PHONY: install uninstall
 install:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) installdirs install-host install-target
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) installdirs install-host install-target
 	@$(stage)
 
 .PHONY: install-host-nogcc
@@ -11248,7 +11272,7 @@ configure-stagefeedback-gcc:
 .PHONY: all-gcc maybe-all-gcc
 maybe-all-gcc:
 @if gcc
-TARGET-gcc=`if [ -f gcc/stage_last ]; then echo quickstrap ; else echo all; fi`
+TARGET-gcc=`if [ -f stage_last ]; then echo quickstrap ; else echo all; fi`
 maybe-all-gcc: all-gcc
 all-gcc: configure-gcc
 	@test -f stage_last && exit 0; \
@@ -35259,7 +35283,9 @@ stage1-end::
 # be reconfigured as well.
 .PHONY: stage1-bubble
 stage1-bubble:: 
-	@if test -f stage1-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage1-lean  ; then \
 	  echo Skipping rebuild of stage1 ; \
 	else \
 	  $(MAKE) stage1-start; \
@@ -35443,7 +35469,9 @@ stage2-end::
 # be reconfigured as well.
 .PHONY: stage2-bubble
 stage2-bubble:: stage1-bubble
-	@if test -f stage2-lean || test -f stage1-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage2-lean || test -f stage1-lean  ; then \
 	  echo Skipping rebuild of stage2 ; \
 	else \
 	  $(MAKE) stage2-start; \
@@ -35632,7 +35660,9 @@ stage3-end::
 .PHONY: stage3-bubble
 stage3-bubble:: stage2-bubble
 	@bootstrap_lean@-rm -rf stage1-* ; $(STAMP) stage1-lean
-	@if test -f stage3-lean || test -f stage2-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage3-lean || test -f stage2-lean  ; then \
 	  echo Skipping rebuild of stage3 ; \
 	else \
 	  $(MAKE) stage3-start; \
@@ -35647,13 +35677,13 @@ do-clean: clean-stage3
 @if gcc-bootstrap
 
 compare:
-	@if test -f stage2-lean; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage2-lean; then \
 	  echo Cannot compare object files as stage 2 was deleted. ; \
 	  exit 0 ; \
 	fi; \
 	[ -f stage_current ] && $(MAKE) `cat stage_current`-end || : ; \
-	@r=`${PWD_COMMAND}`; export r; \
-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
 	rm -f .bad_compare ; \
 	cd stage3-gcc; \
 	files=`find . -name "*$(objext)" -print` ; \
@@ -35859,7 +35889,9 @@ stage4-end::
 .PHONY: stage4-bubble
 stage4-bubble:: stage3-bubble
 	@bootstrap_lean@-rm -rf stage2-* ; $(STAMP) stage2-lean
-	@if test -f stage4-lean || test -f stage3-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage4-lean || test -f stage3-lean  ; then \
 	  echo Skipping rebuild of stage4 ; \
 	else \
 	  $(MAKE) stage4-start; \
@@ -35874,13 +35906,13 @@ do-clean: clean-stage4
 @if gcc-bootstrap
 
 compare3:
-	@if test -f stage3-lean; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage3-lean; then \
 	  echo Cannot compare object files as stage 3 was deleted. ; \
 	  exit 0 ; \
 	fi; \
 	[ -f stage_current ] && $(MAKE) `cat stage_current`-end || : ; \
-	@r=`${PWD_COMMAND}`; export r; \
-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
 	rm -f .bad_compare ; \
 	cd stage4-gcc; \
 	files=`find . -name "*$(objext)" -print` ; \
@@ -36082,7 +36114,9 @@ stageprofile-end::
 # be reconfigured as well.
 .PHONY: stageprofile-bubble
 stageprofile-bubble:: stage1-bubble
-	@if test -f stageprofile-lean || test -f stage1-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stageprofile-lean || test -f stage1-lean  ; then \
 	  echo Skipping rebuild of stageprofile ; \
 	else \
 	  $(MAKE) stageprofile-start; \
@@ -36266,7 +36300,9 @@ stagefeedback-end::
 # be reconfigured as well.
 .PHONY: stagefeedback-bubble
 stagefeedback-bubble:: stageprofile-bubble
-	@if test -f stagefeedback-lean || test -f stageprofile-lean  ; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stagefeedback-lean || test -f stageprofile-lean  ; then \
 	  echo Skipping rebuild of stagefeedback ; \
 	else \
 	  $(MAKE) stagefeedback-start; \
diff --git a/Makefile.tpl b/Makefile.tpl
index 47fa0c809ce..0c3d75ed233 100644
--- a/Makefile.tpl
+++ b/Makefile.tpl
@@ -769,7 +769,9 @@ all-target: [+
 .PHONY: do-[+make_target+]
 do-[+make_target+]:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) [+make_target+]-host \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) [+make_target+]-host \
 	  [+make_target+]-target
 	@$(stage)
 
@@ -866,7 +868,9 @@ check-target: [+
 
 do-check:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) check-host check-target
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) check-host check-target
 	@$(stage)
 
 # Automated reporting of test results.
@@ -895,7 +899,9 @@ mail-report-with-warnings.log: warning.log
 .PHONY: install uninstall
 install:
 	@$(unstage)
-	@$(MAKE) $(RECURSE_FLAGS_TO_PASS) installdirs install-host install-target
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	$(MAKE) $(RECURSE_FLAGS_TO_PASS) installdirs install-host install-target
 	@$(stage)
 
 .PHONY: install-host-nogcc
@@ -1534,7 +1540,9 @@ stage[+id+]-end::
 .PHONY: stage[+id+]-bubble
 stage[+id+]-bubble:: [+ IF prev +]stage[+prev+]-bubble[+ ENDIF +][+IF lean +]
 	@bootstrap_lean@-rm -rf stage[+lean+]-* ; $(STAMP) stage[+lean+]-lean[+ ENDIF lean +]
-	@if test -f stage[+id+]-lean [+
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage[+id+]-lean [+
 	  IF prev +]|| test -f stage[+prev+]-lean [+ ENDIF prev +] ; then \
 	  echo Skipping rebuild of stage[+id+] ; \
 	else \
@@ -1550,13 +1558,13 @@ do-clean: clean-stage[+id+]
 @if gcc-bootstrap
 [+ IF compare-target +]
 [+compare-target+]:
-	@if test -f stage[+prev+]-lean; then \
+	@r=`${PWD_COMMAND}`; export r; \
+	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
+	if test -f stage[+prev+]-lean; then \
 	  echo Cannot compare object files as stage [+prev+] was deleted. ; \
 	  exit 0 ; \
 	fi; \
 	[ -f stage_current ] && $(MAKE) `cat stage_current`-end || : ; \
-	@r=`${PWD_COMMAND}`; export r; \
-	s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
 	rm -f .bad_compare ; \
 	cd stage[+id+]-gcc; \
 	files=`find . -name "*$(objext)" -print` ; \
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index ef6222d28f9..f4549c30455 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,240 @@
+2005-11-02  Alan Modra  <amodra@bigpond.net.au>
+
+	PR ld/1775
+	* elf32-m68k.c (elf_m68k_finish_dynamic_symbol): Add required
+	parentheses.
+
+2005-10-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerated.
+
+	* dep-in.sed: Replace " ./" with " ".
+
+2005-10-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* hpux-core.c: Include <machine/reg.h> only if HPUX_CORE is
+	define.
+	* osf-core.c: Include <sys/core.h> only if OSF_CORE is defined.
+	* sco5-core.c: Include <sys/paccess.h> and <sys/region.h> only
+	if SCO5_CORE is defined.
+
+2005-10-29  Mark Kettenis  <kettenis@gnu.org>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2005-10-28  Joel Brobecker  <brobecker@adacore.com>
+
+	From Eric Botcazou  <botcazou@adacore.com>
+	* coffcode.h (coff_compute_section_file_positions): Fix small
+	error in preprocessor directives.
+
+2005-10-28  Joel Brobecker  <brobecker@adacore.com>
+
+	Mostly from Eric Botcazou <botcazou@adacore.com>
+	* rs6000-core.c: ANSIfy all function definitions.
+	Add missing function prototypes.
+	(ptr_to_uint): New type.
+	(rs6000coff_core_p): Use it as intermediate step in casts.
+	(rs6000coff_core_file_matches_executable_p): Likewise.
+	* xcoff-target.h (rs6000coff_core_p): Fix prototype.
+	(rs6000coff_core_file_matches_executable_p): Likewise.
+
+2005-10-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/1472
+	* aoutx.h (NAME (aout, machine_type)): Handle
+	bfd_mach_sparc_v8plus, bfd_mach_sparc_v8plusa,
+	bfd_mach_sparc_v8plusb, bfd_mach_sparc_v9, bfd_mach_sparc_v9a
+	and bfd_mach_sparc_v9b.
+
+2005-10-28  Hans-Peter Nilsson  <hp@axis.com>
+
+	PR ld/1567
+	* elf32-cris.c (cris_elf_howto_table) <R_CRIS_32>: Set
+	complain_on_overflow field to complain_overflow_dont.
+
+2005-10-27  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 973
+	* cache.c (enum cache_flag): New.
+	(close_one): Save file mtime.
+	(bfd_cache_lookup): Add flag arg, adjust all users.
+	(bfd_cache_lookup_worker): Likewise.
+	(cache_btell): Use CACHE_NO_OPEN and return abfd->where if file
+	not open.
+	(cache_bflush): Similarly, and return success of file not open.
+	(cache_bseek): Use CACHE_NO_SEEK if SEEK_SET or SEEK_END.
+	(cache_bstat): Use CACHE_NO_SEEK_ERROR.
+
+	* bfdwin.c (bfd_get_file_window): Seek into file in place of
+	using bfd_cache_lookup.
+
+	* cache.c (BFD_CACHE_MAX_OPEN): Make private to this file.
+	(bfd_last_cache, bfd_cache_lookup, bfd_cache_lookup_worker): Likewise.
+	* libbfd-in.h (bfd_cache_lookup_worker, bfd_last_cache): Delete.
+	* libbfd.h: Regenerate.
+
+	* hppabsd-core.c (hppabsd_core_core_file_p): Use bfd_stat, not fstat.
+	* sco5-core.c (sco5_core_file_p): Likewise.
+	* trad-core.c (trad_unix_core_file_p): Likewise.
+
+	* cache.c: Reorganize file to avoid forward reference.
+
+2005-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* cache.c (bfd_cache_lookup_worker): Don't abort on failing to
+	reopen file.
+	(cache_btell, cache_bseek, cache_bflush, cache_bstat): Return -1 on
+	bfd_cache_lookup failure.
+	(cache_bread, cache_bwrite): Return 0 on the same.
+	* bfdwin.c (bfd_get_file_window): Likewise.
+	* hppabsd-core.c (hppabsd_core_core_file_p): Likewise.
+	* sco5-core.c (sco5_core_file_p): Likewise.
+	* trad-core.c (trad_unix_core_file_p): Likewise.
+
+2005-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* cache.c (bfd_cache_lookup_worker): Use bfd_error_handler
+	rather than bfd_perror.  Print file name.  Internationalise.
+
+2005-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* cache.c (bfd_open_file): Set bfd_error_system_call on failure
+	to open file.
+	(bfd_cache_lookup_worker): Remove check that file pos is in
+	unsigned long range.  Print system error before aborting.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* Makefile.am: Add rules for coff-z80 and cpu-z80.
+	* Makefile.in: Regenerated.
+	* archures.c: Add bfd_arch_z80 and support for it.
+	* coffcode.h(coff_set_arch_mach_hook): Add case Z80MAGIC.
+	(coff_set_flags): Add case bfd_arch_z80.
+	* config.bfd: Add z80coff_vec.
+	* configure.in: Add z80coff_vec.
+	* reloc.c: Add BFD_RELOC_Z80_DISP8
+	* targets.c: Add z80coff_vec.
+	* coff-z80.c: New file
+	* cpu-z80.c: New file
+	* configure: Regenerated.
+	* libbfd.h: Regenerated.
+	* bfd-in2.h: Regenerated.
+
+2005-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	PR ld/1540
+	* elf-bfd.h (elf_backend_copy_indirect_symbol): Replace pointer to
+	elf_backend_data with pointer to bfd_link_info.
+	(_bfd_elf_link_hash_copy_indirect): Likewise.
+	* elf.c (_bfd_elf_link_hash_copy_indirect): Likewise.  Handle
+	direct and indirect symbols both having dynamic link info.
+	* elf32-arm.c (elf32_arm_copy_indirect_symbol): Likewise.
+	* elf32-hppa.c (elf32_hppa_copy_indirect_symbol): Likewise.
+	* elf32-i386.c (elf_i386_copy_indirect_symbol): Likewise.
+	* elf32-m32r.c (m32r_elf_copy_indirect_symbol): Likewise.
+	* elf32-ppc.c (ppc_elf_copy_indirect_symbol): Likewise.
+	* elf32-s390.c (elf_s390_copy_indirect_symbol): Likewise.
+	* elf32-sh.c (sh_elf_copy_indirect_symbol): Likewise.
+	* elf64-ppc.c (ppc64_elf_copy_indirect_symbol): Likewise.
+	* elf64-s390.c (elf_s390_copy_indirect_symbol): Likewise.
+	* elf64-x86-64.c (elf64_x86_64_copy_indirect_symbol): Likewise.
+	* elfxx-ia64.c (elfNN_ia64_hash_copy_indirect): Likewise.
+	* elfxx-mips.c (_bfd_mips_elf_copy_indirect_symbol): Likewise.
+	* elfxx-sparc.c (_bfd_sparc_elf_copy_indirect_symbol): Likewise.
+	* elflink.c: Adjust all calls to bed->elf_backend_copy_indirect_symbol.
+	* elfxx-mips.h (_bfd_mips_elf_copy_indirect_symbol): Update prototype.
+	* elfxx-sparc.h (_bfd_sparc_elf_copy_indirect_symbol): Likewise.
+
+2005-10-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/SRC-POTFILES.in: Regenerate.
+	* po/bfd.pot: Regenerate.
+
+2005-10-24  Jie Zhang <jie.zhang@analog.com>
+
+	* elf32-bfin.c (bfd_bfin_elf32_create_embedded_relocs): Fix signedness
+	warning.
+
+2005-10-24  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* elf32-bfin.c (bfin_howto_table): Set src_mask to 0 for all relocs.
+	(bfin_imm16_reloc): Always add in the addend.  Don't fetch existing
+	contents from section.
+	(bfin_relocate_section): Rework so as to not call special_functions.
+	Handle the relocation stack here.  Treat pcrel24 relocs specially.
+
+2005-10-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* elflink.c (elf_link_input_bfd): Don't use linker_mark and
+	SEC_EXCLUDE to test for sections dropped from output.  Instead,
+	use bfd_section_removed_from_list on normal sections.  Don't
+	attempt to handle symbols with unknown reserved section indices.
+	* linker.c (_bfd_generic_link_output_symbols): Don't use
+	linker_mark to test for symbols belonging to dropped sections.
+	Do allow absolute symbols.
+
+2005-10-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* elf32-i370.c (i370_elf_fake_sections): Don't set SHF_EXCLUDE on
+	group sections.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
+	set of indirect operands.
+
+2005-10-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* elf32-ppc.c (ppc_elf_fake_sections): Don't set SHF_EXCLUDE on
+	group sections.
+
+2005-10-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* coff-rs6000.c (rs6000coff_vec): Initialize
+	_bfd_init_private_section_data with
+	_bfd_generic_init_private_section_data.
+	(pmac_xcoff_vec): Likewise.
+	* coff64-rs6000.c (rs6000coff64_vec): Likewise.
+	(aix5coff64_vec): Likewise.
+
+2005-10-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1487
+	* elf-bfd.h (_bfd_generic_init_private_section_data): New.
+	(_bfd_elf_init_private_section_data): New.
+
+	* elf.c (elf_fake_sections): Don't set SHF_GROUP for
+	relocatable link.
+	(bfd_elf_set_group_contents): Don't handle relocatable link
+	specially.
+	(assign_section_numbers): If it isn't called by assembler,
+	use the output section of elf_linked_to_section for
+	SHF_LINK_ORDER.
+	(_bfd_elf_init_private_section_data): New.
+	(_bfd_elf_copy_private_section_data): Call it.
+
+	* libbfd-in.h (_bfd_generic_init_private_section_data): New.
+
+	* libbfd.c (_bfd_generic_init_private_section_data): New.
+
+	* targets.c (BFD_JUMP_TABLE_COPY): Add
+	_bfd_generic_init_private_section_data.
+	(bfd_init_private_section_data): Likewise.
+
+	* bfd-in2.h: Regenerated.
+	* libbfd.h: Likewise.
+
+2005-10-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* elf64-ppc.c (dec_dynrel_count): Don't report errors for local
+	syms in gc'd sections.
+	(ppc64_elf_edit_opd): Don't adjust reloc counts when NO_OPD_RELOCS.
+	(elf_backend_action_discarded): Define.
+	(ppc64_elf_action_discarded): New function.
+
 2005-10-19  Paul Brook  <paul@codesourcery.com>
 
 	* elf32-arm.c (find_arm_elf_section_entry): New function.
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index d090ad3a039..aa40aa39a16 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -111,6 +111,7 @@ ALL_MACHINES = \
 	cpu-w65.lo \
 	cpu-xstormy16.lo \
 	cpu-xtensa.lo \
+	cpu-z80.lo \
 	cpu-z8k.lo
 
 ALL_MACHINES_CFILES = \
@@ -171,6 +172,7 @@ ALL_MACHINES_CFILES = \
 	cpu-w65.c \
 	cpu-xstormy16.c \
 	cpu-xtensa.c \
+	cpu-z80.c \
 	cpu-z8k.c
 
 # The .o files needed by all of the 32 bit vectors that are configured into
@@ -214,6 +216,7 @@ BFD32_BACKENDS = \
 	coff-u68k.lo \
 	coff-we32k.lo \
 	coff-w65.lo \
+	coff-z80.lo \
 	coff-z8k.lo \
 	cofflink.lo \
 	dwarf1.lo \
@@ -384,6 +387,7 @@ BFD32_BACKENDS_CFILES = \
 	coff-u68k.c \
 	coff-we32k.c \
 	coff-w65.c \
+	coff-z80.c \
 	coff-z8k.c \
 	cofflink.c \
 	dwarf1.c \
@@ -904,1003 +908,887 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/Makefile.in
 
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
-archive.lo: archive.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h \
-  $(INCDIR)/aout/ranlib.h $(INCDIR)/safe-ctype.h
-archures.lo: archures.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
-bfd.lo: bfd.c ./bfd.h ./bfdver.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
-  libcoff.h libecoff.h $(INCDIR)/coff/ecoff.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h
-bfdio.lo: bfdio.c ./config.h $(INCDIR)/filenames.h \
-  ./bfd.h $(INCDIR)/hashtab.h
-bfdwin.lo: bfdwin.c ./config.h $(INCDIR)/filenames.h \
-  ./bfd.h $(INCDIR)/hashtab.h
-cache.lo: cache.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-coffgen.lo: coffgen.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h libcoff.h \
-  $(INCDIR)/bfdlink.h
-corefile.lo: corefile.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-format.lo: format.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-init.lo: init.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-libbfd.lo: libbfd.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-opncls.lo: opncls.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-reloc.lo: reloc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h
-section.lo: section.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h
-syms.lo: syms.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-targets.lo: targets.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/fnmatch.h ./targmatch.h
-hash.lo: hash.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/objalloc.h $(INCDIR)/libiberty.h
-linker.lo: linker.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h
-srec.lo: srec.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
-binary.lo: binary.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/hashtab.h
-tekhex.lo: tekhex.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-ihex.lo: ihex.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
-stabs.lo: stabs.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h \
   $(INCDIR)/safe-ctype.h
-stab-syms.lo: stab-syms.c ./bfd.h libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab.def
-merge.lo: merge.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-dwarf2.lo: dwarf2.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/dwarf2.h
-simple.lo: simple.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h
-archive64.lo: archive64.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h
-cpu-alpha.lo: cpu-alpha.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-arc.lo: cpu-arc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-arm.lo: cpu-arm.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+archures.lo: archures.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
+bfd.lo: bfd.c bfdver.h $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h libcoff.h \
+  libecoff.h $(INCDIR)/coff/ecoff.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h
+bfdio.lo: bfdio.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+bfdwin.lo: bfdwin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cache.lo: cache.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h
+coffgen.lo: coffgen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/bfdlink.h
+corefile.lo: corefile.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+format.lo: format.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+init.lo: init.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+libbfd.lo: libbfd.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+opncls.lo: opncls.c $(INCDIR)/filenames.h $(INCDIR)/objalloc.h \
   $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-cpu-avr.lo: cpu-avr.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-bfin.lo: cpu-bfin.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-cris.lo: cpu-cris.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-cr16c.lo: cpu-cr16c.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-crx.lo: cpu-crx.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-d10v.lo: cpu-d10v.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-d30v.lo: cpu-d30v.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-dlx.lo: cpu-dlx.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-fr30.lo: cpu-fr30.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-frv.lo: cpu-frv.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-h8300.lo: cpu-h8300.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-h8500.lo: cpu-h8500.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-hppa.lo: cpu-hppa.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ia64.lo: cpu-ia64.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h
-cpu-i370.lo: cpu-i370.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i386.lo: cpu-i386.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i860.lo: cpu-i860.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i960.lo: cpu-i960.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ip2k.lo: cpu-ip2k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-iq2000.lo: cpu-iq2000.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
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-  $(INCDIR)/hashtab.h
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-  $(INCDIR)/elf/ms1.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h \
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   elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/msp430.h \
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/ms1.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/openrisc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/libiberty.h ./elf32-target.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/msp430.h $(INCDIR)/elf/reloc-macros.h \
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/openrisc.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/libiberty.h elf32-target.h
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+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
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+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/pj.h \
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/ppc.h \
   $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf-vxworks.h \
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-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/../opcodes/sh64-opc.h \
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+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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   elf32-sh64.h elf32-sh.c $(INCDIR)/hashtab.h $(INCDIR)/elf/sh.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
-  $(srcdir)/../opcodes/sh-opc.h ./bfd.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
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+  $(srcdir)/../opcodes/sh64-opc.h
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-  ./bfd.h ./config.h $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sh.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
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+  $(srcdir)/../opcodes/sh-opc.h elf32-target.h
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+  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sparc.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/sparc.h \
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sparc.h \
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/xtensa.h \
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   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/safe-ctype.h \
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   elf-vxworks.h
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   $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/hashtab.h $(INCDIR)/ieee.h libieee.h $(INCDIR)/safe-ctype.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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+  $(INCDIR)/bfdlink.h libaout.h $(INCDIR)/os9k.h
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+  $(INCDIR)/ieee.h libieee.h $(INCDIR)/safe-ctype.h
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
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+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h libaout.h $(INCDIR)/bfdlink.h aout-target.h
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+  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h
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   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h mach-o-target.c
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h
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-  $(INCDIR)/hashtab.h libnlm.h $(INCDIR)/nlm/common.h \
-  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/nlm/i386-ext.h libnlm.h \
-  $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
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+  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h mach-o-target.c
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+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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+nlm.lo: nlm.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
+  $(INCDIR)/nlm/external.h
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+  $(INCDIR)/nlm/i386-ext.h libnlm.h $(INCDIR)/nlm/common.h \
+  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h nlmswap.h \
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   $(INCDIR)/hashtab.h $(INCDIR)/nlm/sparc32-ext.h libnlm.h \
   $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
   nlmswap.h nlm-target.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/nlm/ppc-ext.h libnlm.h \
-  $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
-  nlmswap.h nlm-target.h
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-  $(INCDIR)/hashtab.h libnlm.h $(INCDIR)/nlm/common.h \
-  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/safe-ctype.h $(INCDIR)/hashtab.h $(INCDIR)/oasys.h \
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-  libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
-  aout-target.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
-  $(INCDIR)/aout/ar.h
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+  $(INCDIR)/nlm/ppc-ext.h libnlm.h $(INCDIR)/nlm/common.h \
+  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h nlmswap.h \
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+  libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
+  $(INCDIR)/nlm/external.h
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  coff-i386.c $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  coff-i386.c $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/aout/ar.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/oasys.h liboasys.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
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+  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
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-  coff-sh.c $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
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-  $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
   $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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-  pe-mips.c $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h \
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
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+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h $(INCDIR)/coff/external.h \
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+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h \
   $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
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+  libpei.h
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+  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h \
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+  $(INCDIR)/coff/pe.h libcoff.h coffcode.h peicode.h \
+  libpei.h
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+  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
   peicode.h libpei.h
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-  ./config.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h $(INCDIR)/coff/internal.h \
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
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+  $(INCDIR)/hashtab.h
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   libcoff.h
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-  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
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   aout-target.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/sun4.h libaout.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/aout/sun4.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+sparclinux.lo: sparclinux.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h libaout.h $(INCDIR)/bfdlink.h aout-target.h
+sparclynx.lo: sparclynx.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/aout/sun4.h libaout.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h aout-target.h
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h vms.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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+  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h $(INCDIR)/aout/sun4.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h aout-target.h
+vaxnetbsd.lo: vaxnetbsd.c netbsd.h $(INCDIR)/filenames.h \
+  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h
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+  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h
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+  libaout.h $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
+versados.lo: versados.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h
+vms.lo: vms.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h vms.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h vms.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/xcoff.h libcoff.h libxcoff.h
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-  $(INCDIR)/hashtab.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-isa-internal.h
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+  $(INCDIR)/hashtab.h vms.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/hashtab.h \
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+  $(INCDIR)/hashtab.h vms.h
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+  $(INCDIR)/hashtab.h vms.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/xcoff.h \
+  libcoff.h libxcoff.h
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+xtensa-isa.lo: xtensa-isa.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-isa-internal.h
 xtensa-modules.lo: xtensa-modules.c $(INCDIR)/xtensa-isa.h \
   $(INCDIR)/xtensa-isa-internal.h
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-  $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h libaout.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+  $(INCDIR)/bfdlink.h libaout.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/symconst.h $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h \
+  $(INCDIR)/aout/ar.h libcoff.h libecoff.h coffswap.h \
+  ecoffswap.h
+coff64-rs6000.lo: coff64-rs6000.c $(INCDIR)/filenames.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/ecoff.h \
-  $(INCDIR)/coff/alpha.h $(INCDIR)/aout/ar.h libcoff.h \
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/xcoff.h $(INCDIR)/coff/rs6k64.h \
-  libcoff.h libxcoff.h coffcode.h coffswap.h
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+  $(INCDIR)/coff/xcoff.h $(INCDIR)/coff/rs6k64.h libcoff.h \
+  libxcoff.h coffcode.h coffswap.h
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   $(INCDIR)/hashtab.h $(INCDIR)/aout/sun4.h libaout.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
   $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
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-  $(INCDIR)/filenames.h coff-ia64.c $(INCDIR)/hashtab.h \
-  $(INCDIR)/coff/ia64.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
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+  coff-ia64.c $(INCDIR)/hashtab.h $(INCDIR)/coff/ia64.h \
+  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
   peicode.h libpei.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
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-  $(INCDIR)/elf/external.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
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+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/x86-64.h \
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h $(INCDIR)/aout/ar.h \
-  libcoff.h libecoff.h ecoffswap.h ./elf64-target.h
+  libcoff.h libecoff.h ecoffswap.h elf64-target.h
 elf64-hppa.lo: elf64-hppa.c $(INCDIR)/alloca-conf.h \
-  ./config.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  ./elf64-target.h
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+  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \
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+elf64-gen.lo: elf64-gen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf64-target.h
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   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
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   $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/bfdlink.h \
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-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
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+  ecoffswap.h elf32-target.h
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+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-ppc.h elf64-target.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-target.h
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+  $(INCDIR)/opcode/sparc.h elfxx-sparc.h elf64-target.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
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+  $(INCDIR)/libiberty.h $(INCDIR)/elf/mmix.h $(INCDIR)/elf/reloc-macros.h \
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   $(INCDIR)/hashtab.h $(INCDIR)/nlm/alpha-ext.h libnlm.h \
   $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
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-  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h
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+  $(INCDIR)/nlm/external.h
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-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h \
-  elf32-target.h
-elf64-ia64.lo: elf64-ia64.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h \
-  elf64-target.h
-peigen.lo: peigen.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/pe.h libcoff.h \
-  $(INCDIR)/bfdlink.h libpei.h
-pepigen.lo: pepigen.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/ia64.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/pe.h libcoff.h \
-  $(INCDIR)/bfdlink.h libpei.h
+hpux-core.lo: hpux-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+irix-core.lo: irix-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+lynx-core.lo: lynx-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+osf-core.lo: osf-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+sco5-core.lo: sco5-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libaout.h $(INCDIR)/bfdlink.h
+trad-core.lo: trad-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libaout.h $(INCDIR)/bfdlink.h
+cisco-core.lo: cisco-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+elf32-ia64.lo: elf32-ia64.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h \
+  $(INCDIR)/hashtab.h elf32-target.h
+elf64-ia64.lo: elf64-ia64.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h \
+  $(INCDIR)/hashtab.h elf64-target.h
+peigen.lo: peigen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h libpei.h
+pepigen.lo: pepigen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/ia64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h libpei.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 6c3f5980e45..b65d7fe68af 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -348,6 +348,7 @@ ALL_MACHINES = \
 	cpu-w65.lo \
 	cpu-xstormy16.lo \
 	cpu-xtensa.lo \
+	cpu-z80.lo \
 	cpu-z8k.lo
 
 ALL_MACHINES_CFILES = \
@@ -408,6 +409,7 @@ ALL_MACHINES_CFILES = \
 	cpu-w65.c \
 	cpu-xstormy16.c \
 	cpu-xtensa.c \
+	cpu-z80.c \
 	cpu-z8k.c
 
 
@@ -452,6 +454,7 @@ BFD32_BACKENDS = \
 	coff-u68k.lo \
 	coff-we32k.lo \
 	coff-w65.lo \
+	coff-z80.lo \
 	coff-z8k.lo \
 	cofflink.lo \
 	dwarf1.lo \
@@ -622,6 +625,7 @@ BFD32_BACKENDS_CFILES = \
 	coff-u68k.c \
 	coff-we32k.c \
 	coff-w65.c \
+	coff-z80.c \
 	coff-z8k.c \
 	cofflink.c \
 	dwarf1.c \
@@ -1471,1005 +1475,889 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/Makefile.in
 
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
-archive.lo: archive.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h \
-  $(INCDIR)/aout/ranlib.h $(INCDIR)/safe-ctype.h
-archures.lo: archures.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
-bfd.lo: bfd.c ./bfd.h ./bfdver.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
-  libcoff.h libecoff.h $(INCDIR)/coff/ecoff.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h
-bfdio.lo: bfdio.c ./config.h $(INCDIR)/filenames.h \
-  ./bfd.h $(INCDIR)/hashtab.h
-bfdwin.lo: bfdwin.c ./config.h $(INCDIR)/filenames.h \
-  ./bfd.h $(INCDIR)/hashtab.h
-cache.lo: cache.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-coffgen.lo: coffgen.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h libcoff.h \
-  $(INCDIR)/bfdlink.h
-corefile.lo: corefile.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-format.lo: format.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-init.lo: init.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-libbfd.lo: libbfd.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-opncls.lo: opncls.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-reloc.lo: reloc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h
-section.lo: section.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h
-syms.lo: syms.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-targets.lo: targets.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/fnmatch.h ./targmatch.h
-hash.lo: hash.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/objalloc.h $(INCDIR)/libiberty.h
-linker.lo: linker.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h
-srec.lo: srec.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
-binary.lo: binary.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/hashtab.h
-tekhex.lo: tekhex.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-ihex.lo: ihex.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
-stabs.lo: stabs.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h \
   $(INCDIR)/safe-ctype.h
-stab-syms.lo: stab-syms.c ./bfd.h libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab.def
-merge.lo: merge.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-dwarf2.lo: dwarf2.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/dwarf2.h
-simple.lo: simple.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h
-archive64.lo: archive64.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h
-cpu-alpha.lo: cpu-alpha.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-arc.lo: cpu-arc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-arm.lo: cpu-arm.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+archures.lo: archures.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
+bfd.lo: bfd.c bfdver.h $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h libcoff.h \
+  libecoff.h $(INCDIR)/coff/ecoff.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h
+bfdio.lo: bfdio.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+bfdwin.lo: bfdwin.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cache.lo: cache.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h
+coffgen.lo: coffgen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/bfdlink.h
+corefile.lo: corefile.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+format.lo: format.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+init.lo: init.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+libbfd.lo: libbfd.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+opncls.lo: opncls.c $(INCDIR)/filenames.h $(INCDIR)/objalloc.h \
   $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
-cpu-avr.lo: cpu-avr.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-bfin.lo: cpu-bfin.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-cris.lo: cpu-cris.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-cr16c.lo: cpu-cr16c.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-crx.lo: cpu-crx.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-d10v.lo: cpu-d10v.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-d30v.lo: cpu-d30v.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-dlx.lo: cpu-dlx.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-fr30.lo: cpu-fr30.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-frv.lo: cpu-frv.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-h8300.lo: cpu-h8300.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-h8500.lo: cpu-h8500.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-hppa.lo: cpu-hppa.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ia64.lo: cpu-ia64.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h
-cpu-i370.lo: cpu-i370.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i386.lo: cpu-i386.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i860.lo: cpu-i860.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-i960.lo: cpu-i960.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ip2k.lo: cpu-ip2k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-iq2000.lo: cpu-iq2000.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m32c.lo: cpu-m32c.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m32r.lo: cpu-m32r.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m68hc11.lo: cpu-m68hc11.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m68hc12.lo: cpu-m68hc12.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m68k.lo: cpu-m68k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m88k.lo: cpu-m88k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m10200.lo: cpu-m10200.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-m10300.lo: cpu-m10300.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-maxq.lo: cpu-maxq.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-mcore.lo: cpu-mcore.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-mips.lo: cpu-mips.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-mmix.lo: cpu-mmix.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ms1.lo: cpu-ms1.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-msp430.lo: cpu-msp430.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-or32.lo: cpu-or32.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-ns32k.lo: cpu-ns32k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h ns32k.h
-cpu-openrisc.lo: cpu-openrisc.c ./bfd.h ./config.h \
-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
-cpu-pdp11.lo: cpu-pdp11.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-pj.lo: cpu-pj.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-powerpc.lo: cpu-powerpc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-rs6000.lo: cpu-rs6000.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-s390.lo: cpu-s390.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-sh.lo: cpu-sh.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(srcdir)/../opcodes/sh-opc.h ./bfd.h
-cpu-sparc.lo: cpu-sparc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+reloc.lo: reloc.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h
-cpu-tic30.lo: cpu-tic30.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-tic4x.lo: cpu-tic4x.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-tic54x.lo: cpu-tic54x.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-cpu-tic80.lo: cpu-tic80.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+section.lo: section.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/bfdlink.h
+syms.lo: syms.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/stab_gnu.h \
+  $(INCDIR)/aout/stab.def
+targets.lo: targets.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/fnmatch.h targmatch.h
+hash.lo: hash.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/objalloc.h $(INCDIR)/libiberty.h
+linker.lo: linker.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/bfdlink.h genlink.h
+srec.lo: srec.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+binary.lo: binary.c $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/hashtab.h
-cpu-v850.lo: cpu-v850.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
-cpu-vax.lo: cpu-vax.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+tekhex.lo: tekhex.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h
+ihex.lo: ihex.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+stabs.lo: stabs.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/safe-ctype.h
+stab-syms.lo: stab-syms.c libaout.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab.def
+merge.lo: merge.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h
+dwarf2.lo: dwarf2.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/elf/dwarf2.h
+simple.lo: simple.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/bfdlink.h
+archive64.lo: archive64.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/aout/ar.h
+cpu-alpha.lo: cpu-alpha.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cpu-arc.lo: cpu-arc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
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+elf32-hppa.lo: elf32-hppa.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h libhppa.h elf32-hppa.h \
+  elf-hppa.h elf32-target.h
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/dwarf2.h \
-  ./elf32-target.h
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+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/i370.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
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-  ./elf32-target.h
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+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf-vxworks.h \
+  $(INCDIR)/elf/i386.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/i960.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
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+  $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/reloc-macros.h \
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+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h libhppa.h \
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+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/m68k.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/i370.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
-elf32-i386.lo: elf32-i386.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-m68hc1x.h \
+  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/opcode/m68hc11.h elf32-target.h
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf-vxworks.h \
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/i960.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/reloc-macros.h \
-  ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
-  ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
-elf32-m68k.lo: elf32-m68k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-m68hc1x.h \
+  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/opcode/m68hc11.h elf32-target.h
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/m68k.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf32-m68hc1x.h \
+  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/opcode/m68hc11.h
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   elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h elf32-m68hc1x.h $(INCDIR)/elf/m68hc11.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/m68hc11.h \
-  ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf32-target.h
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   elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h elf32-m68hc1x.h $(INCDIR)/elf/m68hc11.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/m68hc11.h \
-  ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf32-target.h
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   elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h elf32-m68hc1x.h $(INCDIR)/elf/m68hc11.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/m68hc11.h
-elf32-m88k.lo: elf32-m88k.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  ./elf32-target.h
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/mn10300.h $(INCDIR)/elf/reloc-macros.h \
-  ./elf32-target.h
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+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mn10300.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/mcore.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h elfxx-mips.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/libiberty.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   elfxx-mips.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h
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+  $(INCDIR)/bfdlink.h genlink.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elfxx-mips.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/sym.h \
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   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \
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-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/ms1.h $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h \
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   elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/msp430.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/ms1.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/openrisc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/libiberty.h ./elf32-target.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/msp430.h $(INCDIR)/elf/reloc-macros.h \
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   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
-  ./elf32-target.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/openrisc.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/libiberty.h elf32-target.h
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+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
+  elf32-target.h
+elf32-pj.lo: elf32-pj.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/pj.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
-elf32-ppc.lo: elf32-ppc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-target.h
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+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/ppc.h \
   $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf-vxworks.h \
-  ./elf32-target.h
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-  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/../opcodes/sh64-opc.h \
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+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/../opcodes/sh64-opc.h \
   elf32-sh64.h elf32-sh.c $(INCDIR)/hashtab.h $(INCDIR)/elf/sh.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \
-  $(srcdir)/../opcodes/sh-opc.h ./bfd.h ./elf32-target.h
-elf32-sh64-com.lo: elf32-sh64-com.c ./bfd.h ./config.h \
-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  elf32-sh64.h $(srcdir)/../opcodes/sh64-opc.h
-elf32-s390.lo: elf32-s390.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(srcdir)/../opcodes/sh-opc.h elf32-target.h
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+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h elf32-sh64.h \
+  $(srcdir)/../opcodes/sh64-opc.h
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   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf32-target.h
-elf32-sh.lo: elf32-sh.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sh.h \
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+  $(INCDIR)/nlm/i386-ext.h libnlm.h $(INCDIR)/nlm/common.h \
+  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h nlmswap.h \
+  nlm-target.h
+nlm32-sparc.lo: nlm32-sparc.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/nlm/sparc32-ext.h libnlm.h \
   $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
   nlmswap.h nlm-target.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/nlm/ppc-ext.h libnlm.h \
-  $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
-  nlmswap.h nlm-target.h
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-  $(INCDIR)/hashtab.h libnlm.h $(INCDIR)/nlm/common.h \
-  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/safe-ctype.h $(INCDIR)/hashtab.h $(INCDIR)/oasys.h \
-  liboasys.h
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-  libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
-  aout-target.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
-  $(INCDIR)/aout/ar.h
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+nlm32-ppc.lo: nlm32-ppc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/nlm/ppc-ext.h libnlm.h $(INCDIR)/nlm/common.h \
+  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h nlmswap.h \
+  nlm-target.h
+nlm32.lo: nlm32.c nlmcode.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
+  $(INCDIR)/nlm/external.h
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
-  $(INCDIR)/aout/ar.h $(INCDIR)/safe-ctype.h
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-  pef-traceback.h ./config.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/libiberty.h
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-  coff-arm.c $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
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-  coff-arm.c $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-i386.c $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-i386.c $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-mcore.c $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-mcore.c $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-ppc.c $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-ppc.c $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
-  peicode.h libpei.h
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-  coff-sh.c $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/aout/ar.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/oasys.h liboasys.h
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+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
+  aout-target.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
+  $(INCDIR)/aout/ar.h
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+  libaout.h $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h \
+  $(INCDIR)/safe-ctype.h
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+  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
-  coffcode.h peicode.h libpei.h
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-  coff-sh.c $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
+pei-arm.lo: pei-arm.c $(INCDIR)/filenames.h coff-arm.c \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
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-  $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
   $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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-  pe-mips.c $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h \
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/powerpc.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h $(INCDIR)/coff/sh.h \
   $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/pe.h libcoff.h coffcode.h peicode.h \
+  libpei.h
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+  $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/pe.h libcoff.h coffcode.h peicode.h \
+  libpei.h
+pe-mips.lo: pe-mips.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
   peicode.h libpei.h
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-  ./config.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h $(INCDIR)/coff/internal.h \
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+  $(INCDIR)/hashtab.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h coffcode.h peicode.h libpei.h
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+  $(INCDIR)/hashtab.h
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+  $(INCDIR)/bfdlink.h genlink.h $(INCDIR)/coff/internal.h \
   libcoff.h
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-  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
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+  libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
   aout-target.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/aout/sun4.h libaout.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/aout/sun4.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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-  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h libaout.h \
-  $(INCDIR)/bfdlink.h aout-target.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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   $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
   $(INCDIR)/aout/ar.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h
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-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
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+  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h aout-target.h \
+  $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def \
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+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
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   $(INCDIR)/hashtab.h vms.h
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-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/xcoff.h libcoff.h libxcoff.h
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-  $(INCDIR)/hashtab.h $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-isa-internal.h
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   $(INCDIR)/xtensa-isa-internal.h
-aix5ppc-core.lo: aix5ppc-core.c ./bfd.h
-aout64.lo: aout64.c aoutx.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/bfdlink.h libaout.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
-coff-alpha.lo: coff-alpha.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+aix5ppc-core.lo: aix5ppc-core.c
+aout64.lo: aout64.c aoutx.h $(INCDIR)/filenames.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/bfdlink.h libaout.h $(INCDIR)/hashtab.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
+coff-alpha.lo: coff-alpha.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/symconst.h $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h \
+  $(INCDIR)/aout/ar.h libcoff.h libecoff.h coffswap.h \
+  ecoffswap.h
+coff64-rs6000.lo: coff64-rs6000.c $(INCDIR)/filenames.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/ecoff.h \
-  $(INCDIR)/coff/alpha.h $(INCDIR)/aout/ar.h libcoff.h \
-  libecoff.h coffswap.h ecoffswap.h
-coff64-rs6000.lo: coff64-rs6000.c ./bfd.h ./config.h \
-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/xcoff.h $(INCDIR)/coff/rs6k64.h \
-  libcoff.h libxcoff.h coffcode.h coffswap.h
-demo64.lo: demo64.c aoutf1.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/coff/xcoff.h $(INCDIR)/coff/rs6k64.h libcoff.h \
+  libxcoff.h coffcode.h coffswap.h
+demo64.lo: demo64.c aoutf1.h $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/aout/sun4.h libaout.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
   $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h aout-target.h
-efi-app-ia64.lo: efi-app-ia64.c ./bfd.h ./config.h \
-  $(INCDIR)/filenames.h coff-ia64.c $(INCDIR)/hashtab.h \
-  $(INCDIR)/coff/ia64.h $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
+efi-app-ia64.lo: efi-app-ia64.c $(INCDIR)/filenames.h \
+  coff-ia64.c $(INCDIR)/hashtab.h $(INCDIR)/coff/ia64.h \
+  $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h coffcode.h \
   peicode.h libpei.h
-elf64-x86-64.lo: elf64-x86-64.c ./bfd.h ./config.h \
-  $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
-  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
-  ./elf64-target.h
-elf64-alpha.lo: elf64-alpha.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+elf64-x86-64.lo: elf64-x86-64.c $(INCDIR)/filenames.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/x86-64.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-target.h
+elf64-alpha.lo: elf64-alpha.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h $(INCDIR)/aout/ar.h \
-  libcoff.h libecoff.h ecoffswap.h ./elf64-target.h
+  libcoff.h libecoff.h ecoffswap.h elf64-target.h
 elf64-hppa.lo: elf64-hppa.c $(INCDIR)/alloca-conf.h \
-  ./config.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h libhppa.h \
-  elf64-hppa.h elf-hppa.h ./elf64-target.h
-elf64-gen.lo: elf64-gen.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  ./elf64-target.h
-elfn32-mips.lo: elfn32-mips.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/filenames.h $(INCDIR)/hashtab.h elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \
+  libhppa.h elf64-hppa.h elf-hppa.h elf64-target.h
+elf64-gen.lo: elf64-gen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h elf64-target.h
+elfn32-mips.lo: elfn32-mips.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/bfdlink.h genlink.h elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   elfxx-mips.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \
-  ecoffswap.h ./elf32-target.h
-elf64-mips.lo: elf64-mips.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/bfdlink.h \
-  genlink.h elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h elfxx-mips.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h \
-  ecoffswap.h ./elf64-target.h
-elf64-mmix.lo: elf64-mmix.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  ecoffswap.h elf32-target.h
+elf64-mips.lo: elf64-mips.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/aout/ar.h $(INCDIR)/bfdlink.h genlink.h elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  elfxx-mips.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/alpha.h ecoffswap.h \
+  elf64-target.h
+elf64-mmix.lo: elf64-mmix.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mmix.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
+  elf64-target.h
+elf64-ppc.lo: elf64-ppc.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/elf/mmix.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  ./elf64-target.h
-elf64-ppc.lo: elf64-ppc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/ppc64.h \
-  $(INCDIR)/elf/reloc-macros.h elf64-ppc.h ./elf64-target.h
-elf64-s390.lo: elf64-s390.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-ppc.h elf64-target.h
+elf64-s390.lo: elf64-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf64-target.h
-elf64-sh64.lo: elf64-sh64.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-target.h
+elf64-sh64.lo: elf64-sh64.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h ./elf64-target.h
-elf64-sparc.lo: elf64-sparc.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/elf/reloc-macros.h elf64-target.h
+elf64-sparc.lo: elf64-sparc.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/opcode/sparc.h elfxx-sparc.h ./elf64-target.h
-elf64.lo: elf64.c elfcode.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h \
-  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h elfcore.h
-mmo.lo: mmo.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h $(INCDIR)/elf/mmix.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h
-nlm32-alpha.lo: nlm32-alpha.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+  $(INCDIR)/opcode/sparc.h elfxx-sparc.h elf64-target.h
+elf64.lo: elf64.c elfcode.h $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elfcore.h
+mmo.lo: mmo.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/elf/mmix.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/opcode/mmix.h
+nlm32-alpha.lo: nlm32-alpha.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/nlm/alpha-ext.h libnlm.h \
   $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h \
   nlmswap.h nlm-target.h
-nlm64.lo: nlm64.c nlmcode.h ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h libnlm.h $(INCDIR)/nlm/common.h \
-  $(INCDIR)/nlm/internal.h $(INCDIR)/nlm/external.h
-aix386-core.lo: aix386-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
+nlm64.lo: nlm64.c nlmcode.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
+  $(INCDIR)/nlm/external.h
+aix386-core.lo: aix386-core.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/bfdlink.h
-hpux-core.lo: hpux-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-irix-core.lo: irix-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-lynx-core.lo: lynx-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-osf-core.lo: osf-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-sco5-core.lo: sco5-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h
-trad-core.lo: trad-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h libaout.h $(INCDIR)/bfdlink.h
-cisco-core.lo: cisco-core.c ./bfd.h ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h
-elf32-ia64.lo: elf32-ia64.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h \
-  elf32-target.h
-elf64-ia64.lo: elf64-ia64.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ia64.h ./bfd.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h $(INCDIR)/hashtab.h \
-  elf64-target.h
-peigen.lo: peigen.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/pe.h libcoff.h \
-  $(INCDIR)/bfdlink.h libpei.h
-pepigen.lo: pepigen.c ./config.h $(INCDIR)/filenames.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/ia64.h \
-  $(INCDIR)/coff/external.h $(INCDIR)/coff/pe.h libcoff.h \
-  $(INCDIR)/bfdlink.h libpei.h
+hpux-core.lo: hpux-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+irix-core.lo: irix-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+lynx-core.lo: lynx-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+osf-core.lo: osf-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+sco5-core.lo: sco5-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libaout.h $(INCDIR)/bfdlink.h
+trad-core.lo: trad-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  libaout.h $(INCDIR)/bfdlink.h
+cisco-core.lo: cisco-core.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+elf32-ia64.lo: elf32-ia64.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h \
+  $(INCDIR)/hashtab.h elf32-target.h
+elf64-ia64.lo: elf64-ia64.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/objalloc.h \
+  $(INCDIR)/hashtab.h elf64-target.h
+peigen.lo: peigen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h libpei.h
+pepigen.lo: pepigen.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/ia64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/pe.h libcoff.h $(INCDIR)/bfdlink.h libpei.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
 # Otherwise a system limit (for SysV at least) may be exceeded.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index 4079147d30e..9c446056218 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -706,7 +706,12 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
 	  || machine == bfd_mach_sparc
 	  || machine == bfd_mach_sparc_sparclite
 	  || machine == bfd_mach_sparc_sparclite_le
-	  || machine == bfd_mach_sparc_v9)
+	  || machine == bfd_mach_sparc_v8plus
+	  || machine == bfd_mach_sparc_v8plusa
+	  || machine == bfd_mach_sparc_v8plusb
+	  || machine == bfd_mach_sparc_v9
+	  || machine == bfd_mach_sparc_v9a
+	  || machine == bfd_mach_sparc_v9b)
 	arch_flags = M_SPARC;
       else if (machine == bfd_mach_sparc_sparclet)
 	arch_flags = M_SPARCLET;
diff --git a/bfd/archures.c b/bfd/archures.c
index 74d2b712ed5..a96771cf8da 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -365,6 +365,11 @@ DESCRIPTION
 .   bfd_arch_maxq,     {* Dallas MAXQ 10/20 *}
 .#define bfd_mach_maxq10    10
 .#define bfd_mach_maxq20    20
+.  bfd_arch_z80,
+.#define bfd_mach_z80strict      1 {* No undocumented opcodes.  *}
+.#define bfd_mach_z80            3 {* With ixl, ixh, iyl, and iyh.  *}
+.#define bfd_mach_z80full        7 {* All undocumented instructions.  *}
+.#define bfd_mach_r800           11 {* R800: successor with multiplication.  *}
 .  bfd_arch_last
 .  };
 */
@@ -461,6 +466,7 @@ extern const bfd_arch_info_type bfd_we32k_arch;
 extern const bfd_arch_info_type bfd_w65_arch;
 extern const bfd_arch_info_type bfd_xstormy16_arch;
 extern const bfd_arch_info_type bfd_xtensa_arch;
+extern const bfd_arch_info_type bfd_z80_arch;
 extern const bfd_arch_info_type bfd_z8k_arch;
 
 static const bfd_arch_info_type * const bfd_archures_list[] =
@@ -524,6 +530,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_we32k_arch,
     &bfd_xstormy16_arch,
     &bfd_xtensa_arch,
+    &bfd_z80_arch,
     &bfd_z8k_arch,
 #endif
   0
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 1d93b0f3050..7afe43725a7 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1953,6 +1953,11 @@ enum bfd_architecture
    bfd_arch_maxq,     /* Dallas MAXQ 10/20 */
 #define bfd_mach_maxq10    10
 #define bfd_mach_maxq20    20
+  bfd_arch_z80,
+#define bfd_mach_z80strict      1 /* No undocumented opcodes.  */
+#define bfd_mach_z80            3 /* With ixl, ixh, iyl, and iyh.  */
+#define bfd_mach_z80full        7 /* All undocumented instructions.  */
+#define bfd_mach_r800           11 /* R800: successor with multiplication.  */
   bfd_arch_last
   };
 
@@ -4058,6 +4063,9 @@ internally by the linker after analysis of a
 BFD_RELOC_XTENSA_ASM_EXPAND.  */
   BFD_RELOC_XTENSA_ASM_SIMPLIFY,
 
+/* 8 bit signed offset in (ix+d) or (iy+d).  */
+  BFD_RELOC_Z80_DISP8,
+
 /* DJNZ offset.  */
   BFD_RELOC_Z8K_DISP7,
 
@@ -4770,6 +4778,7 @@ typedef struct bfd_target
 #define BFD_JUMP_TABLE_COPY(NAME) \
   NAME##_bfd_copy_private_bfd_data, \
   NAME##_bfd_merge_private_bfd_data, \
+  _bfd_generic_init_private_section_data, \
   NAME##_bfd_copy_private_section_data, \
   NAME##_bfd_copy_private_symbol_data, \
   NAME##_bfd_copy_private_header_data, \
@@ -4782,6 +4791,12 @@ typedef struct bfd_target
   /* Called to merge BFD general private data from one object file
      to a common output file when linking.  */
   bfd_boolean (*_bfd_merge_private_bfd_data) (bfd *, bfd *);
+  /* Called to initialize BFD private section data from one object file
+     to another.  */
+#define bfd_init_private_section_data(ibfd, isec, obfd, osec, link_info) \
+  BFD_SEND (obfd, _bfd_init_private_section_data, (ibfd, isec, obfd, osec, link_info))
+  bfd_boolean (*_bfd_init_private_section_data)
+    (bfd *, sec_ptr, bfd *, sec_ptr, struct bfd_link_info *);
   /* Called to copy BFD private section data from one object file
      to another.  */
   bfd_boolean (*_bfd_copy_private_section_data)
diff --git a/bfd/bfdwin.c b/bfd/bfdwin.c
index d3e4ba83d1e..7236906e28b 100644
--- a/bfd/bfdwin.c
+++ b/bfd/bfdwin.c
@@ -1,5 +1,6 @@
 /* Support for memory-mapped windows into a BFD.
-   Copyright 1995, 1996, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 1995, 1996, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
    Written by Cygnus Support.
 
 This file is part of BFD, the Binary File Descriptor library.
@@ -144,7 +145,6 @@ bfd_get_file_window (bfd *abfd,
       file_ptr file_offset, offset2;
       size_t real_size;
       int fd;
-      FILE *f;
 
       /* Find the real file and the real offset into it.  */
       while (abfd->my_archive != NULL)
@@ -152,8 +152,13 @@ bfd_get_file_window (bfd *abfd,
 	  offset += abfd->origin;
 	  abfd = abfd->my_archive;
 	}
-      f = bfd_cache_lookup (abfd);
-      fd = fileno (f);
+
+      /* Seek into the file, to ensure it is open if cacheable.  */
+      if (abfd->iostream == NULL
+	  && (abfd->iovec == NULL
+	      || abfd->iovec->bseek (abfd, offset, SEEK_SET) != 0))
+	return FALSE;
+      fd = fileno ((FILE *) abfd->iostream);
 
       /* Compute offsets and size for mmap and for the user's data.  */
       offset2 = offset % pagesize;
diff --git a/bfd/cache.c b/bfd/cache.c
index e2524fbf15f..ef4a006b40e 100644
--- a/bfd/cache.c
+++ b/bfd/cache.c
@@ -1,7 +1,7 @@
 /* BFD library -- caching of file descriptors.
 
    Copyright 1990, 1991, 1992, 1993, 1994, 1996, 2000, 2001, 2002,
-   2003, 2004 Free Software Foundation, Inc.
+   2003, 2004, 2005 Free Software Foundation, Inc.
 
    Hacked by Steve Chamberlain of Cygnus Support (steve@cygnus.com).
 
@@ -45,19 +45,216 @@ SUBSECTION
 #include "libbfd.h"
 #include "libiberty.h"
 
-static bfd_boolean bfd_cache_delete (bfd *);
+/* In some cases we can optimize cache operation when reopening files.
+   For instance, a flush is entirely unnecessary if the file is already
+   closed, so a flush would use CACHE_NO_OPEN.  Similarly, a seek using
+   SEEK_SET or SEEK_END need not first seek to the current position.
+   For stat we ignore seek errors, just in case the file has changed
+   while we weren't looking.  If it has, then it's possible that the
+   file is shorter and we don't want a seek error to prevent us doing
+   the stat.  */
+enum cache_flag {
+  CACHE_NORMAL = 0,
+  CACHE_NO_OPEN = 1,
+  CACHE_NO_SEEK = 2,
+  CACHE_NO_SEEK_ERROR = 4
+};
+
+/* The maximum number of files which the cache will keep open at
+   one time.  */
+
+#define BFD_CACHE_MAX_OPEN 10
+
+/* The number of BFD files we have open.  */
+
+static int open_files;
+
+/* Zero, or a pointer to the topmost BFD on the chain.  This is
+   used by the <<bfd_cache_lookup>> macro in @file{libbfd.h} to
+   determine when it can avoid a function call.  */
+
+static bfd *bfd_last_cache = NULL;
+
+/* Insert a BFD into the cache.  */
+
+static void
+insert (bfd *abfd)
+{
+  if (bfd_last_cache == NULL)
+    {
+      abfd->lru_next = abfd;
+      abfd->lru_prev = abfd;
+    }
+  else
+    {
+      abfd->lru_next = bfd_last_cache;
+      abfd->lru_prev = bfd_last_cache->lru_prev;
+      abfd->lru_prev->lru_next = abfd;
+      abfd->lru_next->lru_prev = abfd;
+    }
+  bfd_last_cache = abfd;
+}
+
+/* Remove a BFD from the cache.  */
+
+static void
+snip (bfd *abfd)
+{
+  abfd->lru_prev->lru_next = abfd->lru_next;
+  abfd->lru_next->lru_prev = abfd->lru_prev;
+  if (abfd == bfd_last_cache)
+    {
+      bfd_last_cache = abfd->lru_next;
+      if (abfd == bfd_last_cache)
+	bfd_last_cache = NULL;
+    }
+}
+
+/* Close a BFD and remove it from the cache.  */
+
+static bfd_boolean
+bfd_cache_delete (bfd *abfd)
+{
+  bfd_boolean ret;
+
+  if (fclose ((FILE *) abfd->iostream) == 0)
+    ret = TRUE;
+  else
+    {
+      ret = FALSE;
+      bfd_set_error (bfd_error_system_call);
+    }
+
+  snip (abfd);
+
+  abfd->iostream = NULL;
+  --open_files;
 
+  return ret;
+}
+
+/* We need to open a new file, and the cache is full.  Find the least
+   recently used cacheable BFD and close it.  */
+
+static bfd_boolean
+close_one (void)
+{
+  register bfd *kill;
+
+  if (bfd_last_cache == NULL)
+    kill = NULL;
+  else
+    {
+      for (kill = bfd_last_cache->lru_prev;
+	   ! kill->cacheable;
+	   kill = kill->lru_prev)
+	{
+	  if (kill == bfd_last_cache)
+	    {
+	      kill = NULL;
+	      break;
+	    }
+	}
+    }
+
+  if (kill == NULL)
+    {
+      /* There are no open cacheable BFD's.  */
+      return TRUE;
+    }
+
+  kill->where = real_ftell ((FILE *) kill->iostream);
+
+  /* Save the file st_mtime.  This is a hack so that gdb can detect when
+     an executable has been deleted and recreated.  The only thing that
+     makes this reasonable is that st_mtime doesn't change when a file
+     is unlinked, so saving st_mtime makes BFD's file cache operation
+     a little more transparent for this particular usage pattern.  If we
+     hadn't closed the file then we would not have lost the original
+     contents, st_mtime etc.  Of course, if something is writing to an
+     existing file, then this is the wrong thing to do.
+     FIXME: gdb should save these times itself on first opening a file,
+     and this hack be removed.  */
+  if (kill->direction == no_direction || kill->direction == read_direction)
+    {
+      bfd_get_mtime (kill);
+      kill->mtime_set = TRUE;
+    }
+
+  return bfd_cache_delete (kill);
+}
+
+/* Check to see if the required BFD is the same as the last one
+   looked up. If so, then it can use the stream in the BFD with
+   impunity, since it can't have changed since the last lookup;
+   otherwise, it has to perform the complicated lookup function.  */
+
+#define bfd_cache_lookup(x, flag) \
+  ((x) == bfd_last_cache			\
+   ? (FILE *) (bfd_last_cache->iostream)	\
+   : bfd_cache_lookup_worker (x, flag))
+
+/* Called when the macro <<bfd_cache_lookup>> fails to find a
+   quick answer.  Find a file descriptor for @var{abfd}.  If
+   necessary, it open it.  If there are already more than
+   <<BFD_CACHE_MAX_OPEN>> files open, it tries to close one first, to
+   avoid running out of file descriptors.  It will return NULL
+   if it is unable to (re)open the @var{abfd}.  */
+
+static FILE *
+bfd_cache_lookup_worker (bfd *abfd, enum cache_flag flag)
+{
+  bfd *orig_bfd = abfd;
+  if ((abfd->flags & BFD_IN_MEMORY) != 0)
+    abort ();
+
+  if (abfd->my_archive)
+    abfd = abfd->my_archive;
+
+  if (abfd->iostream != NULL)
+    {
+      /* Move the file to the start of the cache.  */
+      if (abfd != bfd_last_cache)
+	{
+	  snip (abfd);
+	  insert (abfd);
+	}
+      return (FILE *) abfd->iostream;
+    }
+
+  if (flag & CACHE_NO_OPEN)
+    return NULL;
+
+  if (bfd_open_file (abfd) == NULL)
+    ;
+  else if (!(flag & CACHE_NO_SEEK)
+	   && real_fseek ((FILE *) abfd->iostream, abfd->where, SEEK_SET) != 0
+	   && !(flag & CACHE_NO_SEEK_ERROR))
+    bfd_set_error (bfd_error_system_call);
+  else
+    return (FILE *) abfd->iostream;
+
+  (*_bfd_error_handler) (_("reopening %B: %s\n"),
+			 orig_bfd, bfd_errmsg (bfd_get_error ()));
+  return NULL;
+}
 
 static file_ptr
 cache_btell (struct bfd *abfd)
 {
-  return real_ftell (bfd_cache_lookup (abfd));
+  FILE *f = bfd_cache_lookup (abfd, CACHE_NO_OPEN);
+  if (f == NULL)
+    return abfd->where;
+  return real_ftell (f);
 }
 
 static int
 cache_bseek (struct bfd *abfd, file_ptr offset, int whence)
 {
-  return real_fseek (bfd_cache_lookup (abfd), offset, whence);
+  FILE *f = bfd_cache_lookup (abfd, whence != SEEK_CUR ? CACHE_NO_SEEK : 0);
+  if (f == NULL)
+    return -1;
+  return real_fseek (f, offset, whence);
 }
 
 /* Note that archive entries don't have streams; they share their parent's.
@@ -70,6 +267,7 @@ cache_bseek (struct bfd *abfd, file_ptr offset, int whence)
 static file_ptr
 cache_bread (struct bfd *abfd, void *buf, file_ptr nbytes)
 {
+  FILE *f;
   file_ptr nread;
   /* FIXME - this looks like an optimization, but it's really to cover
      up for a feature of some OSs (not solaris - sigh) that
@@ -83,10 +281,14 @@ cache_bread (struct bfd *abfd, void *buf, file_ptr nbytes)
   if (nbytes == 0)
     return 0;
 
+  f = bfd_cache_lookup (abfd, 0);
+  if (f == NULL)
+    return 0;
+
 #if defined (__VAX) && defined (VMS)
   /* Apparently fread on Vax VMS does not keep the record length
      information.  */
-  nread = read (fileno (bfd_cache_lookup (abfd)), buf, nbytes);
+  nread = read (fileno (f), buf, nbytes);
   /* Set bfd_error if we did not read as much data as we expected.  If
      the read failed due to an error set the bfd_error_system_call,
      else set bfd_error_file_truncated.  */
@@ -96,11 +298,11 @@ cache_bread (struct bfd *abfd, void *buf, file_ptr nbytes)
       return -1;
     }
 #else
-  nread = fread (buf, 1, nbytes, bfd_cache_lookup (abfd));
+  nread = fread (buf, 1, nbytes, f);
   /* Set bfd_error if we did not read as much data as we expected.  If
      the read failed due to an error set the bfd_error_system_call,
      else set bfd_error_file_truncated.  */
-  if (nread < nbytes && ferror (bfd_cache_lookup (abfd)))
+  if (nread < nbytes && ferror (f))
     {
       bfd_set_error (bfd_error_system_call);
       return -1;
@@ -112,8 +314,12 @@ cache_bread (struct bfd *abfd, void *buf, file_ptr nbytes)
 static file_ptr
 cache_bwrite (struct bfd *abfd, const void *where, file_ptr nbytes)
 {
-  file_ptr nwrite = fwrite (where, 1, nbytes, bfd_cache_lookup (abfd));
-  if (nwrite < nbytes && ferror (bfd_cache_lookup (abfd)))
+  file_ptr nwrite;
+  FILE *f = bfd_cache_lookup (abfd, 0);
+  if (f == NULL)
+    return 0;
+  nwrite = fwrite (where, 1, nbytes, f);
+  if (nwrite < nbytes && ferror (f))
     {
       bfd_set_error (bfd_error_system_call);
       return -1;
@@ -130,7 +336,11 @@ cache_bclose (struct bfd *abfd)
 static int
 cache_bflush (struct bfd *abfd)
 {
-  int sts = fflush (bfd_cache_lookup (abfd));
+  int sts;
+  FILE *f = bfd_cache_lookup (abfd, CACHE_NO_OPEN);
+  if (f == NULL)
+    return 0;
+  sts = fflush (f);
   if (sts < 0)
     bfd_set_error (bfd_error_system_call);
   return sts;
@@ -139,7 +349,11 @@ cache_bflush (struct bfd *abfd)
 static int
 cache_bstat (struct bfd *abfd, struct stat *sb)
 {
-  int sts = fstat (fileno (bfd_cache_lookup (abfd)), sb);
+  int sts;
+  FILE *f = bfd_cache_lookup (abfd, CACHE_NO_SEEK_ERROR);
+  if (f == NULL)
+    return -1;
+  sts = fstat (fileno (f), sb);
   if (sts < 0)
     bfd_set_error (bfd_error_system_call);
   return sts;
@@ -152,147 +366,6 @@ static const struct bfd_iovec cache_iovec = {
 
 /*
 INTERNAL_FUNCTION
-	BFD_CACHE_MAX_OPEN macro
-
-DESCRIPTION
-	The maximum number of files which the cache will keep open at
-	one time.
-
-.#define BFD_CACHE_MAX_OPEN 10
-
-*/
-
-/* The number of BFD files we have open.  */
-
-static int open_files;
-
-/*
-INTERNAL_FUNCTION
-	bfd_last_cache
-
-SYNOPSIS
-	extern bfd *bfd_last_cache;
-
-DESCRIPTION
-	Zero, or a pointer to the topmost BFD on the chain.  This is
-	used by the <<bfd_cache_lookup>> macro in @file{libbfd.h} to
-	determine when it can avoid a function call.
-*/
-
-bfd *bfd_last_cache = NULL;
-
-/*
-  INTERNAL_FUNCTION
-  	bfd_cache_lookup
-
-  DESCRIPTION
- 	Check to see if the required BFD is the same as the last one
- 	looked up. If so, then it can use the stream in the BFD with
- 	impunity, since it can't have changed since the last lookup;
- 	otherwise, it has to perform the complicated lookup function.
-
-  .#define bfd_cache_lookup(x) \
-  .    ((x) == bfd_last_cache ? \
-  .      (FILE *) (bfd_last_cache->iostream): \
-  .       bfd_cache_lookup_worker (x))
-
- */
-
-/* Insert a BFD into the cache.  */
-
-static void
-insert (bfd *abfd)
-{
-  if (bfd_last_cache == NULL)
-    {
-      abfd->lru_next = abfd;
-      abfd->lru_prev = abfd;
-    }
-  else
-    {
-      abfd->lru_next = bfd_last_cache;
-      abfd->lru_prev = bfd_last_cache->lru_prev;
-      abfd->lru_prev->lru_next = abfd;
-      abfd->lru_next->lru_prev = abfd;
-    }
-  bfd_last_cache = abfd;
-}
-
-/* Remove a BFD from the cache.  */
-
-static void
-snip (bfd *abfd)
-{
-  abfd->lru_prev->lru_next = abfd->lru_next;
-  abfd->lru_next->lru_prev = abfd->lru_prev;
-  if (abfd == bfd_last_cache)
-    {
-      bfd_last_cache = abfd->lru_next;
-      if (abfd == bfd_last_cache)
-	bfd_last_cache = NULL;
-    }
-}
-
-/* We need to open a new file, and the cache is full.  Find the least
-   recently used cacheable BFD and close it.  */
-
-static bfd_boolean
-close_one (void)
-{
-  register bfd *kill;
-
-  if (bfd_last_cache == NULL)
-    kill = NULL;
-  else
-    {
-      for (kill = bfd_last_cache->lru_prev;
-	   ! kill->cacheable;
-	   kill = kill->lru_prev)
-	{
-	  if (kill == bfd_last_cache)
-	    {
-	      kill = NULL;
-	      break;
-	    }
-	}
-    }
-
-  if (kill == NULL)
-    {
-      /* There are no open cacheable BFD's.  */
-      return TRUE;
-    }
-
-  kill->where = real_ftell ((FILE *) kill->iostream);
-
-  return bfd_cache_delete (kill);
-}
-
-/* Close a BFD and remove it from the cache.  */
-
-static bfd_boolean
-bfd_cache_delete (bfd *abfd)
-{
-  bfd_boolean ret;
-
-  if (fclose ((FILE *) abfd->iostream) == 0)
-    ret = TRUE;
-  else
-    {
-      ret = FALSE;
-      bfd_set_error (bfd_error_system_call);
-    }
-
-  snip (abfd);
-
-  abfd->iostream = NULL;
-  --open_files;
-
-  return ret;
-}
-
-/*
-INTERNAL_FUNCTION
 	bfd_cache_init
 
 SYNOPSIS
@@ -447,7 +520,9 @@ bfd_open_file (bfd *abfd)
       break;
     }
 
-  if (abfd->iostream != NULL)
+  if (abfd->iostream == NULL)
+    bfd_set_error (bfd_error_system_call);
+  else
     {
       if (! bfd_cache_init (abfd))
 	return NULL;
@@ -455,48 +530,3 @@ bfd_open_file (bfd *abfd)
 
   return (FILE *) abfd->iostream;
 }
-
-/*
-INTERNAL_FUNCTION
-	bfd_cache_lookup_worker
-
-SYNOPSIS
-	FILE *bfd_cache_lookup_worker (bfd *abfd);
-
-DESCRIPTION
-	Called when the macro <<bfd_cache_lookup>> fails to find a
-	quick answer.  Find a file descriptor for @var{abfd}.  If
-	necessary, it open it.  If there are already more than
-	<<BFD_CACHE_MAX_OPEN>> files open, it tries to close one first, to
-	avoid running out of file descriptors.  It will abort rather than
-	returning NULL if it is unable to (re)open the @var{abfd}.
-*/
-
-FILE *
-bfd_cache_lookup_worker (bfd *abfd)
-{
-  if ((abfd->flags & BFD_IN_MEMORY) != 0)
-    abort ();
-
-  if (abfd->my_archive)
-    abfd = abfd->my_archive;
-
-  if (abfd->iostream != NULL)
-    {
-      /* Move the file to the start of the cache.  */
-      if (abfd != bfd_last_cache)
-	{
-	  snip (abfd);
-	  insert (abfd);
-	}
-    }
-  else
-    {
-      if (bfd_open_file (abfd) == NULL
-	  || abfd->where != (unsigned long) abfd->where
-	  || real_fseek ((FILE *) abfd->iostream, abfd->where, SEEK_SET) != 0)
-	abort ();
-    }
-
-  return (FILE *) abfd->iostream;
-}
diff --git a/bfd/coff-rs6000.c b/bfd/coff-rs6000.c
index ed7125a5058..8e54c6a135a 100644
--- a/bfd/coff-rs6000.c
+++ b/bfd/coff-rs6000.c
@@ -4135,6 +4135,7 @@ const bfd_target rs6000coff_vec =
     /* Copy */
     _bfd_xcoff_copy_private_bfd_data,
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
+    _bfd_generic_init_private_section_data,
     ((bfd_boolean (*) (bfd *, asection *, bfd *, asection *)) bfd_true),
     ((bfd_boolean (*) (bfd *, asymbol *, bfd *, asymbol *)) bfd_true),
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
@@ -4385,6 +4386,7 @@ const bfd_target pmac_xcoff_vec =
     /* Copy */
     _bfd_xcoff_copy_private_bfd_data,
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
+    _bfd_generic_init_private_section_data,
     ((bfd_boolean (*) (bfd *, asection *, bfd *, asection *)) bfd_true),
     ((bfd_boolean (*) (bfd *, asymbol *, bfd *, asymbol *)) bfd_true),
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
diff --git a/bfd/coff-z80.c b/bfd/coff-z80.c
new file mode 100644
index 00000000000..fe401d77b86
--- /dev/null
+++ b/bfd/coff-z80.c
@@ -0,0 +1,244 @@
+/* BFD back-end for Zilog Z80 COFF binaries.
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify 
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "bfdlink.h"
+#include "coff/z80.h"
+#include "coff/internal.h"
+#include "libcoff.h"
+
+#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 0
+
+static reloc_howto_type r_imm32 =
+HOWTO (R_IMM32, 0, 1, 32, FALSE, 0,
+       complain_overflow_dont, 0, "r_imm32", TRUE, 0xffffffff, 0xffffffff,
+       FALSE);
+
+static reloc_howto_type r_imm16 =
+HOWTO (R_IMM16, 0, 1, 16, FALSE, 0,
+       complain_overflow_dont, 0, "r_imm16", TRUE, 0x0000ffff, 0x0000ffff,
+       FALSE);
+
+static reloc_howto_type r_imm8 =
+HOWTO (R_IMM8, 0, 0, 8, FALSE, 0,
+       complain_overflow_bitfield, 0, "r_imm8", TRUE, 0x000000ff, 0x000000ff,
+       FALSE);
+
+static reloc_howto_type r_jr =
+HOWTO (R_JR, 0, 0, 8, TRUE, 0, 
+       complain_overflow_signed, 0, "r_jr", FALSE, 0, 0xFF,
+       FALSE);
+
+static reloc_howto_type r_off8 =
+HOWTO (R_OFF8, 0, 0, 8, FALSE, 0, 
+       complain_overflow_signed, 0,"r_off8", FALSE, 0, 0xff,
+       FALSE);
+
+
+#define BADMAG(x) Z80BADMAG(x)
+#define Z80 1			/* Customize coffcode.h.  */
+#define __A_MAGIC_SET__
+
+/* Code to swap in the reloc.  */
+
+#define SWAP_IN_RELOC_OFFSET	H_GET_32
+#define SWAP_OUT_RELOC_OFFSET	H_PUT_32
+
+#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
+  dst->r_stuff[0] = 'S'; \
+  dst->r_stuff[1] = 'C';
+
+/* Code to turn a r_type into a howto ptr, uses the above howto table.  */
+
+static void
+rtype2howto (arelent *internal, struct internal_reloc *dst)
+{
+  switch (dst->r_type)
+    {
+    default:
+      abort ();
+      break;
+    case R_IMM8:
+      internal->howto = &r_imm8;
+      break;
+    case R_IMM16:
+      internal->howto = &r_imm16;
+      break;
+    case R_IMM32:
+      internal->howto = &r_imm32;
+      break;
+    case R_JR:
+      internal->howto = &r_jr;
+      break;
+    case R_OFF8:
+      internal->howto = &r_off8;
+      break;
+    }
+}
+
+#define RTYPE2HOWTO(internal, relocentry) rtype2howto (internal, relocentry)
+
+static reloc_howto_type *
+coff_z80_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+			    bfd_reloc_code_real_type code)
+{
+  switch (code)
+    {
+    case BFD_RELOC_8:		return & r_imm8;
+    case BFD_RELOC_16:		return & r_imm16;
+    case BFD_RELOC_32:		return & r_imm32;
+    case BFD_RELOC_8_PCREL:	return & r_jr;
+    case BFD_RELOC_Z80_DISP8:	return & r_off8;
+    default:			BFD_FAIL ();
+      return NULL;
+    }
+}
+
+/* Perform any necessary magic to the addend in a reloc entry.  */
+
+#define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \
+ cache_ptr->addend =  ext_reloc.r_offset;
+
+#define RELOC_PROCESSING(relent,reloc,symbols,abfd,section) \
+ reloc_processing(relent, reloc, symbols, abfd, section)
+
+static void
+reloc_processing (arelent *relent,
+                  struct internal_reloc *reloc,
+                  asymbol **symbols,
+                  bfd *abfd,
+                  asection *section)
+{
+  relent->address = reloc->r_vaddr;
+  rtype2howto (relent, reloc);
+
+  if (reloc->r_symndx > 0)
+    relent->sym_ptr_ptr = symbols + obj_convert (abfd)[reloc->r_symndx];
+  else
+    relent->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
+
+  relent->addend = reloc->r_offset;
+  relent->address -= section->vma;
+}
+
+static void
+extra_case (bfd *in_abfd,
+            struct bfd_link_info *link_info,
+            struct bfd_link_order *link_order,
+            arelent *reloc,
+            bfd_byte *data,
+            unsigned int *src_ptr,
+            unsigned int *dst_ptr)
+{
+  asection * input_section = link_order->u.indirect.section;
+  int val;
+
+  switch (reloc->howto->type)
+    {
+    case R_OFF8:
+	val = bfd_coff_reloc16_get_value (reloc, link_info,
+					   input_section);
+	if (val>127 || val<-128) /* Test for overflow.  */
+	  {
+	    if (! ((*link_info->callbacks->reloc_overflow)
+		   (link_info, NULL,
+		    bfd_asymbol_name (*reloc->sym_ptr_ptr),
+		    reloc->howto->name, reloc->addend, input_section->owner,
+		    input_section, reloc->address)))
+	      abort ();
+	  }
+	bfd_put_8 (in_abfd, val, data + *dst_ptr);
+	(*dst_ptr) += 1;
+	(*src_ptr) += 1;
+      break;
+
+    case R_IMM8:
+      val = bfd_get_16 ( in_abfd, data+*src_ptr)
+	+ bfd_coff_reloc16_get_value (reloc, link_info, input_section);
+      bfd_put_8 (in_abfd, val, data + *dst_ptr);
+      (*dst_ptr) += 1;
+      (*src_ptr) += 1;
+      break;
+
+    case R_IMM16:
+      val = bfd_get_16 ( in_abfd, data+*src_ptr)
+	+ bfd_coff_reloc16_get_value (reloc, link_info, input_section);
+      bfd_put_16 (in_abfd, val, data + *dst_ptr);
+      (*dst_ptr) += 2;
+      (*src_ptr) += 2;
+      break;
+
+    case R_IMM32:
+      val = bfd_get_32 ( in_abfd, data+*src_ptr)
+	+ bfd_coff_reloc16_get_value (reloc, link_info, input_section);
+      bfd_put_32 (in_abfd, val, data + *dst_ptr);
+      (*dst_ptr) += 4;
+      (*src_ptr) += 4;
+      break;
+
+    case R_JR:
+      {
+	bfd_vma dst = bfd_coff_reloc16_get_value (reloc, link_info,
+						  input_section);
+	bfd_vma dot = (link_order->offset
+		       + *dst_ptr
+		       + input_section->output_section->vma);
+	int gap = dst - dot - 1;  /* -1, Since the offset is relative
+				     to the value of PC after reading
+				     the offset.  */
+
+	if (gap >= 128 || gap < -128)
+	  {
+	    if (! ((*link_info->callbacks->reloc_overflow)
+		   (link_info, NULL,
+		    bfd_asymbol_name (*reloc->sym_ptr_ptr),
+		    reloc->howto->name, reloc->addend, input_section->owner,
+		    input_section, reloc->address)))
+	      abort ();
+	  }
+	bfd_put_8 (in_abfd, gap, data + *dst_ptr);
+	(*dst_ptr)++;
+	(*src_ptr)++;
+	break;
+      }
+
+    default:
+      abort ();
+    }
+}
+
+#define coff_reloc16_extra_cases    extra_case
+#define coff_bfd_reloc_type_lookup  coff_z80_reloc_type_lookup
+
+#include "coffcode.h"
+
+#undef  coff_bfd_get_relocated_section_contents
+#define coff_bfd_get_relocated_section_contents \
+  bfd_coff_reloc16_get_relocated_section_contents
+
+#undef  coff_bfd_relax_section
+#define coff_bfd_relax_section bfd_coff_reloc16_relax_section
+
+CREATE_LITTLE_COFF_TARGET_VEC (z80coff_vec, "coff-z80", 0, 0, '\0', NULL, 
+			       COFF_SWAP_TABLE)
+
diff --git a/bfd/coff64-rs6000.c b/bfd/coff64-rs6000.c
index a3d3699c27b..77a6eecbc20 100644
--- a/bfd/coff64-rs6000.c
+++ b/bfd/coff64-rs6000.c
@@ -2682,6 +2682,7 @@ const bfd_target rs6000coff64_vec =
     /* Copy */
     _bfd_xcoff_copy_private_bfd_data,
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
+    _bfd_generic_init_private_section_data,
     ((bfd_boolean (*) (bfd *, asection *, bfd *, asection *)) bfd_true),
     ((bfd_boolean (*) (bfd *, asymbol *, bfd *, asymbol *)) bfd_true),
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
@@ -2933,6 +2934,7 @@ const bfd_target aix5coff64_vec =
     /* Copy */
     _bfd_xcoff_copy_private_bfd_data,
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
+    _bfd_generic_init_private_section_data,
     ((bfd_boolean (*) (bfd *, asection *, bfd *, asection *)) bfd_true),
     ((bfd_boolean (*) (bfd *, asymbol *, bfd *, asymbol *)) bfd_true),
     ((bfd_boolean (*) (bfd *, bfd *)) bfd_true),
diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 3b94dff431a..aaf79c10325 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -1955,6 +1955,23 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
       machine = 88100;
       break;
 #endif
+#ifdef Z80MAGIC
+    case Z80MAGIC:
+      arch = bfd_arch_z80;
+      switch (internal_f->f_flags & F_MACHMASK)
+	{
+	case 0:
+	case bfd_mach_z80strict << 12:
+	case bfd_mach_z80 << 12:
+	case bfd_mach_z80full << 12:
+	case bfd_mach_r800 << 12:
+	  machine = ((unsigned)internal_f->f_flags & F_MACHMASK) >> 12;
+	  break;
+	default:
+	  return FALSE;
+	}
+      break;
+#endif
 #ifdef Z8KMAGIC
     case Z8KMAGIC:
       arch = bfd_arch_z8k;
@@ -2555,6 +2572,24 @@ coff_set_flags (bfd * abfd,
 {
   switch (bfd_get_arch (abfd))
     {
+#ifdef Z80MAGIC
+    case bfd_arch_z80:
+      *magicp = Z80MAGIC;
+      switch (bfd_get_mach (abfd))
+	{
+	case 0:
+	case bfd_mach_z80strict:
+	case bfd_mach_z80:
+	case bfd_mach_z80full:
+	case bfd_mach_r800:
+	  *flagsp = bfd_get_mach (abfd) << 12;
+	  break;
+	default:
+	  return FALSE;
+	}
+      return TRUE;
+#endif
+
 #ifdef Z8KMAGIC
     case bfd_arch_z8k:
       *magicp = Z8KMAGIC;
diff --git a/bfd/config.bfd b/bfd/config.bfd
index aec10e18233..ab47fa3cc25 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -101,6 +101,7 @@ v850*)		 targ_archs=bfd_v850_arch ;;
 x86_64)		 targ_archs=bfd_i386_arch ;;
 xscale*)	 targ_archs=bfd_arm_arch ;;
 xtensa*)	 targ_archs=bfd_xtensa_arch ;;
+z80|r800)	 targ_archs=bfd_z80_arch ;;
 z8k*)		 targ_archs=bfd_z8k_arch ;;
 am33_2.0)	 targ_archs=bfd_mn10300_arch ;;
 *)		 targ_archs=bfd_${targ_cpu}_arch ;;
@@ -1366,6 +1367,11 @@ case "${targ}" in
     targ_selvecs=bfd_elf32_xtensa_be_vec
     ;;
 
+  z80-*-*)
+    targ_defvec=z80coff_vec
+    targ_underscore=no
+    ;;
+
   z8k*-*-*)
     targ_defvec=z8kcoff_vec
     targ_underscore=yes
diff --git a/bfd/configure b/bfd/configure
index 179967607f6..d7f01e6c440 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -13190,6 +13190,7 @@ do
     vms_vax_vec)		tb="$tb vms.lo vms-hdr.lo vms-gsd.lo vms-tir.lo vms-misc.lo" ;;
     w65_vec)			tb="$tb coff-w65.lo reloc16.lo" ;;
     we32kcoff_vec)		tb="$tb coff-we32k.lo" ;;
+    z80coff_vec)		tb="$tb coff-z80.lo reloc16.lo" ;;
     z8kcoff_vec)		tb="$tb coff-z8k.lo reloc16.lo cofflink.lo" ;;
 
     # These appear out of order in targets.c
diff --git a/bfd/configure.in b/bfd/configure.in
index 7ace2196d06..1a7dc84de5b 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -811,6 +811,7 @@ do
     vms_vax_vec)		tb="$tb vms.lo vms-hdr.lo vms-gsd.lo vms-tir.lo vms-misc.lo" ;;
     w65_vec)			tb="$tb coff-w65.lo reloc16.lo" ;;
     we32kcoff_vec)		tb="$tb coff-we32k.lo" ;;
+    z80coff_vec)		tb="$tb coff-z80.lo reloc16.lo" ;;
     z8kcoff_vec)		tb="$tb coff-z8k.lo reloc16.lo cofflink.lo" ;;
 
     # These appear out of order in targets.c
diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
index cbd6a58eb9e..360ee9bf063 100644
--- a/bfd/cpu-ia64-opc.c
+++ b/bfd/cpu-ia64-opc.c
@@ -457,6 +457,10 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
     { REG, ins_reg,   ext_reg,	 "r", {{ 2, 20}}, 0,		/* R3_2 */
       "a general register r0-r3" },
 
+    /* memory operands: */
+    { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */
+      "a memory address" },
+
     /* indirect operands: */
     { IND, ins_reg,   ext_reg,	"cpuid", {{7, 20}}, 0,		/* CPUID_R3 */
       "a cpuid register" },
@@ -468,8 +472,6 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "an itr register" },
     { IND, ins_reg,   ext_reg,	"ibr",   {{7, 20}}, 0,		/* IBR_R3 */
       "an ibr register" },
-    { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */
-      "an indirect memory address" },
     { IND, ins_reg,   ext_reg,	"msr",   {{7, 20}}, 0,		/* MSR_R3 */
       "an msr register" },
     { IND, ins_reg,   ext_reg,	"pkr",   {{7, 20}}, 0,		/* PKR_R3 */
diff --git a/bfd/cpu-z80.c b/bfd/cpu-z80.c
new file mode 100644
index 00000000000..3fd6fd48176
--- /dev/null
+++ b/bfd/cpu-z80.c
@@ -0,0 +1,57 @@
+/* BFD library support routines for the Z80 architecture.
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_z80_arch;
+
+/* This routine is provided two arch_infos and
+   returns whether they'd be compatible.  */
+
+static const bfd_arch_info_type *
+compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+{
+  if (a->arch != b->arch)
+    return NULL;
+
+  if (a->mach == b->mach)
+    return a;
+
+  return (a->arch == bfd_arch_z80) ? & bfd_z80_arch : NULL;
+}
+
+#define N(name,print,default,next)  \
+{ 16, 16, 8, bfd_arch_z80, name, "z80", print, 0, default, \
+    compatible, bfd_default_scan, next }
+
+#define M(n) &arch_info_struct[n]
+
+static const bfd_arch_info_type arch_info_struct[] =
+{
+  N (bfd_mach_z80strict, "z80-strict", FALSE, M(1)),
+  N (bfd_mach_z80,       "z80",        FALSE, M(2)),
+  N (bfd_mach_z80full,   "z80-full",   FALSE, M(3)),
+  N (bfd_mach_r800,      "r800",       FALSE, NULL)
+};
+
+const bfd_arch_info_type bfd_z80_arch = N (0, "z80-any", TRUE, M(0));
diff --git a/bfd/dep-in.sed b/bfd/dep-in.sed
index 90a2e6a7f06..2732d6b42e3 100644
--- a/bfd/dep-in.sed
+++ b/bfd/dep-in.sed
@@ -4,6 +4,7 @@ s/\\\n */ /g
 t loop
 
 s!\.o:!.lo:!
+s! \./! !g
 s! @BFD_H@!!g
 s!@SRCDIR@/../include!$(INCDIR)!g
 s!@TOPDIR@/include!$(INCDIR)!g
diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index d011a454ee7..be1c65fb54d 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -870,7 +870,7 @@ struct elf_backend_data
      newly created and plt/got refcounts and dynamic indices should not
      be copied.  */
   void (*elf_backend_copy_indirect_symbol)
-    (const struct elf_backend_data *, struct elf_link_hash_entry *,
+    (struct bfd_link_info *, struct elf_link_hash_entry *,
      struct elf_link_hash_entry *);
 
   /* Modify any information related to dynamic linking such that the
@@ -1462,7 +1462,7 @@ extern struct bfd_hash_entry *_bfd_elf_link_hash_newfunc
 extern struct bfd_link_hash_table *_bfd_elf_link_hash_table_create
   (bfd *);
 extern void _bfd_elf_link_hash_copy_indirect
-  (const struct elf_backend_data *, struct elf_link_hash_entry *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *,
    struct elf_link_hash_entry *);
 extern void _bfd_elf_link_hash_hide_symbol
   (struct bfd_link_info *, struct elf_link_hash_entry *, bfd_boolean);
@@ -1492,6 +1492,10 @@ extern bfd_boolean _bfd_elf_copy_private_header_data
   (bfd *, bfd *);
 extern bfd_boolean _bfd_elf_copy_private_symbol_data
   (bfd *, asymbol *, bfd *, asymbol *);
+#define _bfd_generic_init_private_section_data \
+  _bfd_elf_init_private_section_data
+extern bfd_boolean _bfd_elf_init_private_section_data
+  (bfd *, asection *, bfd *, asection *, struct bfd_link_info *);
 extern bfd_boolean _bfd_elf_copy_private_section_data
   (bfd *, asection *, bfd *, asection *);
 extern bfd_boolean _bfd_elf_write_object_contents
diff --git a/bfd/elf.c b/bfd/elf.c
index 3a139a0bcf0..0e72d4ef93f 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -1458,12 +1458,11 @@ _bfd_elf_link_hash_newfunc (struct bfd_hash_entry *entry,
    old indirect symbol.  Also used for copying flags to a weakdef.  */
 
 void
-_bfd_elf_link_hash_copy_indirect (const struct elf_backend_data *bed,
+_bfd_elf_link_hash_copy_indirect (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *dir,
 				  struct elf_link_hash_entry *ind)
 {
-  bfd_signed_vma tmp;
-  bfd_signed_vma lowest_valid = bed->can_refcount;
+  struct elf_link_hash_table *htab;
 
   /* Copy down any references that we may have already seen to the
      symbol which just became indirect.  */
@@ -1480,33 +1479,32 @@ _bfd_elf_link_hash_copy_indirect (const struct elf_backend_data *bed,
 
   /* Copy over the global and procedure linkage table refcount entries.
      These may have been already set up by a check_relocs routine.  */
-  tmp = dir->got.refcount;
-  if (tmp < lowest_valid)
+  htab = elf_hash_table (info);
+  if (ind->got.refcount > htab->init_got_refcount.refcount)
     {
-      dir->got.refcount = ind->got.refcount;
-      ind->got.refcount = tmp;
+      if (dir->got.refcount < 0)
+	dir->got.refcount = 0;
+      dir->got.refcount += ind->got.refcount;
+      ind->got.refcount = htab->init_got_refcount.refcount;
     }
-  else
-    BFD_ASSERT (ind->got.refcount < lowest_valid);
 
-  tmp = dir->plt.refcount;
-  if (tmp < lowest_valid)
+  if (ind->plt.refcount > htab->init_plt_refcount.refcount)
     {
-      dir->plt.refcount = ind->plt.refcount;
-      ind->plt.refcount = tmp;
+      if (dir->plt.refcount < 0)
+	dir->plt.refcount = 0;
+      dir->plt.refcount += ind->plt.refcount;
+      ind->plt.refcount = htab->init_plt_refcount.refcount;
     }
-  else
-    BFD_ASSERT (ind->plt.refcount < lowest_valid);
 
-  if (dir->dynindx == -1)
+  if (ind->dynindx != -1)
     {
+      if (dir->dynindx != -1)
+	_bfd_elf_strtab_delref (htab->dynstr, dir->dynstr_index);
       dir->dynindx = ind->dynindx;
       dir->dynstr_index = ind->dynstr_index;
       ind->dynindx = -1;
       ind->dynstr_index = 0;
     }
-  else
-    BFD_ASSERT (ind->dynindx == -1);
 }
 
 void
@@ -2670,29 +2668,7 @@ elf_fake_sections (bfd *abfd, asection *asect, void *failedptrarg)
   if (this_hdr->sh_type == SHT_NULL)
     {
       if ((asect->flags & SEC_GROUP) != 0)
-	{
-	  /* We also need to mark SHF_GROUP here for relocatable
-	     link.  */
-	  struct bfd_link_order *l;
-	  asection *elt;
-
-	  for (l = asect->map_head.link_order; l != NULL; l = l->next)
-	    if (l->type == bfd_indirect_link_order
-		&& (elt = elf_next_in_group (l->u.indirect.section)) != NULL)
-	      do
-		{
-		  /* The name is not important. Anything will do.  */
-		  elf_group_name (elt->output_section) = "G";
-		  elf_section_flags (elt->output_section) |= SHF_GROUP;
-
-		  elt = elf_next_in_group (elt);
-		  /* During a relocatable link, the lists are
-		     circular.  */
-		}
-	      while (elt != elf_next_in_group (l->u.indirect.section));
-
-	  this_hdr->sh_type = SHT_GROUP;
-	}
+	this_hdr->sh_type = SHT_GROUP;
       else if ((asect->flags & SEC_ALLOC) != 0
 	  && (((asect->flags & (SEC_LOAD | SEC_HAS_CONTENTS)) == 0)
 	      || (asect->flags & SEC_NEVER_LOAD) != 0))
@@ -2827,7 +2803,6 @@ bfd_elf_set_group_contents (bfd *abfd, asection *sec, void *failedptrarg)
   unsigned long symindx;
   asection *elt, *first;
   unsigned char *loc;
-  struct bfd_link_order *l;
   bfd_boolean gas;
 
   /* Ignore linker created group section.  See elfNN_ia64_object_p in
@@ -2896,22 +2871,6 @@ bfd_elf_set_group_contents (bfd *abfd, asection *sec, void *failedptrarg)
 	break;
     }
 
-  /* If this is a relocatable link, then the above did nothing because
-     SEC is the output section.  Look through the input sections
-     instead.  */
-  for (l = sec->map_head.link_order; l != NULL; l = l->next)
-    if (l->type == bfd_indirect_link_order
-	&& (elt = elf_next_in_group (l->u.indirect.section)) != NULL)
-      do
-	{
-	  loc -= 4;
-	  H_PUT_32 (abfd,
-		    elf_section_data (elt->output_section)->this_idx, loc);
-	  elt = elf_next_in_group (elt);
-	  /* During a relocatable link, the lists are circular.  */
-	}
-      while (elt != elf_next_in_group (l->u.indirect.section));
-
   if ((loc -= 4) != sec->contents)
     abort ();
 
@@ -3091,67 +3050,46 @@ assign_section_numbers (bfd *abfd, struct bfd_link_info *link_info)
 	{
 	  s = elf_linked_to_section (sec);
 	  if (s)
-	    d->this_hdr.sh_link = elf_section_data (s)->this_idx;
-	  else
 	    {
-	      struct bfd_link_order *p;
-
-	      /* Find out what the corresponding section in output
-		 is.  */
-	      for (p = sec->map_head.link_order; p != NULL; p = p->next)
+	      if (link_info != NULL)
 		{
-		  s = p->u.indirect.section;
-		  if (p->type == bfd_indirect_link_order
-		      && (bfd_get_flavour (s->owner)
-			  == bfd_target_elf_flavour))
+		  /* For linker, elf_linked_to_section points to the
+		     input section.  */
+		  if (elf_discarded_section (s))
 		    {
-		      Elf_Internal_Shdr ** const elf_shdrp
-			= elf_elfsections (s->owner);
-		      int elfsec
-			= _bfd_elf_section_from_bfd_section (s->owner, s);
-		      elfsec = elf_shdrp[elfsec]->sh_link;
-		      /* PR 290:
-			 The Intel C compiler generates SHT_IA_64_UNWIND with
-			 SHF_LINK_ORDER.  But it doesn't set the sh_link or
-			 sh_info fields.  Hence we could get the situation
-		         where elfsec is 0.  */
-		      if (elfsec == 0)
-			{
-			  const struct elf_backend_data *bed
-			    = get_elf_backend_data (abfd);
-			  if (bed->link_order_error_handler)
-			    bed->link_order_error_handler
-			      (_("%B: warning: sh_link not set for section `%A'"),
-			       abfd, s);
-			}
-		      else
+		      asection *kept;
+		      (*_bfd_error_handler)
+			(_("%B: sh_link of section `%A' points to discarded section `%A' of `%B'"),
+			 abfd, d->this_hdr.bfd_section,
+			 s, s->owner);
+		      /* Point to the kept section if it has the same
+			 size as the discarded one.  */
+		      kept = _bfd_elf_check_kept_section (s);
+		      if (kept == NULL)
 			{
-			  s = elf_shdrp[elfsec]->bfd_section;
-			  if (elf_discarded_section (s))
-			    {
-			      asection *kept;
-			       (*_bfd_error_handler)
-				  (_("%B: sh_link of section `%A' points to discarded section `%A' of `%B'"),
-				   abfd, d->this_hdr.bfd_section,
-				   s, s->owner);
-			       /* Point to the kept section if it has
-				  the same size as the discarded
-				  one.  */
-			       kept = _bfd_elf_check_kept_section (s);
-			       if (kept == NULL)
-				 {
-				   bfd_set_error (bfd_error_bad_value);
-				   return FALSE;
-				 }
-			       s = kept;
-			    }
-			  s = s->output_section;
-			  BFD_ASSERT (s != NULL);
-			  d->this_hdr.sh_link = elf_section_data (s)->this_idx;
+			  bfd_set_error (bfd_error_bad_value);
+			  return FALSE;
 			}
-		      break;
+		      s = kept;
 		    }
+		  s = s->output_section;
+		  BFD_ASSERT (s != NULL);
 		}
+	      d->this_hdr.sh_link = elf_section_data (s)->this_idx;
+	    }
+	  else
+	    {
+	      /* PR 290:
+		 The Intel C compiler generates SHT_IA_64_UNWIND with
+		 SHF_LINK_ORDER.  But it doesn't set the sh_link or
+		 sh_info fields.  Hence we could get the situation
+	         where s is NULL.  */
+	      const struct elf_backend_data *bed
+		= get_elf_backend_data (abfd);
+	      if (bed->link_order_error_handler)
+		bed->link_order_error_handler
+		  (_("%B: warning: sh_link not set for section `%A'"),
+		   abfd, sec);
 	    }
 	}
 
@@ -5665,6 +5603,62 @@ copy_private_bfd_data (bfd *ibfd, bfd *obfd)
   return TRUE;
 }
 
+/* Initialize private output section information from input section.  */
+
+bfd_boolean
+_bfd_elf_init_private_section_data (bfd *ibfd,
+				    asection *isec,
+				    bfd *obfd,
+				    asection *osec,
+				    struct bfd_link_info *link_info)
+
+{
+  Elf_Internal_Shdr *ihdr, *ohdr;
+  bfd_boolean need_group = link_info == NULL || link_info->relocatable;
+
+  if (ibfd->xvec->flavour != bfd_target_elf_flavour
+      || obfd->xvec->flavour != bfd_target_elf_flavour)
+    return TRUE;
+
+  /* FIXME: What if the output ELF section type has been set to
+     something different?  */
+  if (elf_section_type (osec) == SHT_NULL)
+    elf_section_type (osec) = elf_section_type (isec);
+
+  /* Set things up for objcopy and relocatable link.  The output
+     SHT_GROUP section will have its elf_next_in_group pointing back
+     to the input group members.  Ignore linker created group section.
+     See elfNN_ia64_object_p in elfxx-ia64.c.  */
+
+  if (need_group)
+    {
+      if (elf_sec_group (isec) == NULL
+	  || (elf_sec_group (isec)->flags & SEC_LINKER_CREATED) == 0)
+	{
+	  if (elf_section_flags (isec) & SHF_GROUP)
+	    elf_section_flags (osec) |= SHF_GROUP;
+	  elf_next_in_group (osec) = elf_next_in_group (isec);
+	  elf_group_name (osec) = elf_group_name (isec);
+	}
+    }
+
+  ihdr = &elf_section_data (isec)->this_hdr;
+
+  /* We need to handle elf_linked_to_section for SHF_LINK_ORDER. We
+     don't use the output section of the linked-to section since it
+     may be NULL at this point.  */
+  if ((ihdr->sh_flags & SHF_LINK_ORDER) != 0)
+    {
+      ohdr = &elf_section_data (osec)->this_hdr;
+      ohdr->sh_flags |= SHF_LINK_ORDER;
+      elf_linked_to_section (osec) = elf_linked_to_section (isec);
+    }
+
+  osec->use_rela_p = isec->use_rela_p;
+
+  return TRUE;
+}
+
 /* Copy private section information.  This copies over the entsize
    field, and sometimes the info field.  */
 
@@ -5691,27 +5685,8 @@ _bfd_elf_copy_private_section_data (bfd *ibfd,
       || ihdr->sh_type == SHT_GNU_verdef)
     ohdr->sh_info = ihdr->sh_info;
 
-  /* Set things up for objcopy.  The output SHT_GROUP section will
-     have its elf_next_in_group pointing back to the input group
-     members.  Ignore linker created group section.  See
-     elfNN_ia64_object_p in elfxx-ia64.c.  We also need to handle
-     elf_linked_to_section for SHF_LINK_ORDER.  */
-
-  if ((ihdr->sh_flags & SHF_LINK_ORDER) != 0
-      && elf_linked_to_section (isec) != 0)
-    elf_linked_to_section (osec)
-      = elf_linked_to_section (isec)->output_section;
-
-  if (elf_sec_group (isec) == NULL
-      || (elf_sec_group (isec)->flags & SEC_LINKER_CREATED) == 0)
-    {
-      elf_next_in_group (osec) = elf_next_in_group (isec);
-      elf_group_name (osec) = elf_group_name (isec);
-    }
-
-  osec->use_rela_p = isec->use_rela_p;
-
-  return TRUE;
+  return _bfd_elf_init_private_section_data (ibfd, isec, obfd, osec,
+					     NULL);
 }
 
 /* Copy private header information.  */
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index c4bfd3107d1..6f220e9631b 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -1793,7 +1793,7 @@ elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf32_arm_copy_indirect_symbol (const struct elf_backend_data *bed,
+elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *dir,
 				struct elf_link_hash_entry *ind)
 {
@@ -1809,10 +1809,7 @@ elf32_arm_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct elf32_arm_relocs_copied **pp;
 	  struct elf32_arm_relocs_copied *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->relocs_copied; (p = *pp) != NULL; )
 	    {
@@ -1836,16 +1833,9 @@ elf32_arm_copy_indirect_symbol (const struct elf_backend_data *bed,
       eind->relocs_copied = NULL;
     }
 
-  /* If the direct symbol already has an associated PLT entry, the
-     indirect symbol should not.  If it doesn't, swap refcount information
-     from the indirect symbol.  */
-  if (edir->plt_thumb_refcount == 0)
-    {
-      edir->plt_thumb_refcount = eind->plt_thumb_refcount;
-      eind->plt_thumb_refcount = 0;
-    }
-  else
-    BFD_ASSERT (eind->plt_thumb_refcount == 0);
+  /* Copy over PLT info.  */
+  edir->plt_thumb_refcount += eind->plt_thumb_refcount;
+  eind->plt_thumb_refcount = 0;
 
   if (ind->root.type == bfd_link_hash_indirect
       && dir->got.refcount <= 0)
@@ -1854,7 +1844,7 @@ elf32_arm_copy_indirect_symbol (const struct elf_backend_data *bed,
       eind->tls_type = GOT_UNKNOWN;
     }
 
-  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 /* Create an ARM elf linker hash table.  */
diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
index 72f8aee5c96..c1a1b7443a1 100644
--- a/bfd/elf32-bfin.c
+++ b/bfd/elf32-bfin.c
@@ -433,11 +433,8 @@ bfin_imm16_reloc (bfd *abfd,
       if (!relocatable || !strcmp (symbol->name, symbol->section->name))
 	relocation += output_base + symbol->section->output_offset;
 
-      if (symbol->flags & BSF_SECTION_SYM)
-	{
-	  /* Add in supplied addend.  */
-	  relocation += reloc_entry->addend;
-	}
+      /* Add in supplied addend.  */
+      relocation += reloc_entry->addend;
     }
   else
     {
@@ -470,7 +467,6 @@ bfin_imm16_reloc (bfd *abfd,
   /* Here the variable relocation holds the final address of the
      symbol we are relocating against, plus any addend.  */
 
-  x = bfd_get_16 (abfd, (bfd_byte *) data + reloc_addr);
   relocation >>= (bfd_vma) howto->rightshift;
   x = relocation;
   bfd_put_16 (abfd, x, (unsigned char *) data + reloc_addr);
@@ -759,7 +755,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_pcrel5m2",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x0000000F,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x0000000F,		/* dst_mask.  */
 	 FALSE),		/* pcrel_offset.  */
 
@@ -787,7 +783,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_pcrel10",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x000003FF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x000003FF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
  
@@ -805,7 +801,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_pcrel12_jump",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x0FFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x0FFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -819,7 +815,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_imm16_reloc,	/* special_function.  */
 	 "R_rimm16",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x0000FFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x0000FFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -833,7 +829,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_imm16_reloc,	/* special_function.  */
 	 "R_luimm16",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x0000FFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x0000FFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
  
@@ -847,7 +843,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_imm16_reloc,	/* special_function.  */
 	 "R_huimm16",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x0000FFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x0000FFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -861,7 +857,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_pcrel12_jump_s",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x00000FFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x00000FFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -875,7 +871,7 @@ static reloc_howto_type bfin_howto_table [] =
          bfin_pcrel24_reloc,	/* special_function.  */
          "R_pcrel24_jump_x",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x00FFFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x00FFFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -889,7 +885,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_pcrel24_reloc,	/* special_function.  */
 	 "R_pcrel24",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x00FFFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x00FFFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -931,7 +927,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_pcrel24_reloc,	/* special_function.  */
 	 "R_pcrel24_jump_l",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x00FFFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x00FFFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -945,7 +941,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_pcrel24_reloc,	/* special_function.  */
 	 "R_pcrel24_call_x",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x00FFFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x00FFFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -973,7 +969,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_byte_data",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0xFF,			/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0xFF,			/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -987,7 +983,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_byte2_data",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0xFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0xFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -1001,7 +997,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_byte4_reloc,	/* special_function.  */
 	 "R_byte4_data",	/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0xFFFFFFFF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0xFFFFFFFF,		/* dst_mask.  */
 	 TRUE),			/* pcrel_offset.  */
 
@@ -1015,7 +1011,7 @@ static reloc_howto_type bfin_howto_table [] =
 	 bfin_bfd_reloc,	/* special_function.  */
 	 "R_pcrel11",		/* name.  */
 	 FALSE,			/* partial_inplace.  */
-	 0x000003FF,		/* src_mask.  */
+	 0,			/* src_mask.  */
 	 0x000003FF,		/* dst_mask.  */
 	 FALSE),		/* pcrel_offset.  */
 };
@@ -1660,6 +1656,7 @@ elf32_bfin_reloc_type_class (const Elf_Internal_Rela * rela)
       return reloc_class_normal;
     }
 }
+
 static bfd_boolean
 bfin_relocate_section (bfd * output_bfd,
 		       struct bfd_link_info *info,
@@ -1678,7 +1675,6 @@ bfin_relocate_section (bfd * output_bfd,
   asection *sreloc;
   Elf_Internal_Rela *rel;
   Elf_Internal_Rela *relend;
-  char *error_msg = NULL;
   int i = 0;
 
   if (info->relocatable)
@@ -1705,6 +1701,7 @@ bfin_relocate_section (bfd * output_bfd,
       bfd_vma relocation = 0;
       bfd_boolean unresolved_reloc;
       bfd_reloc_status_type r;
+      bfd_vma address;
 
       r_type = ELF32_R_TYPE (rel->r_info);
       if (r_type < 0 || r_type >= 243)
@@ -1735,10 +1732,6 @@ bfin_relocate_section (bfd * output_bfd,
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
 	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
-	  /* Call to bfd_elf_rela_local_sym would have CHANGED the sec
-             as well as updated relocation. The value returned is
-             w.r.t the original section.  */
-	  sec = local_sections[r_symndx];
 	}
       else
 	{
@@ -1762,6 +1755,45 @@ bfin_relocate_section (bfd * output_bfd,
 	    }
 	}
 
+      address = rel->r_offset;
+      /* First, get stack relocs out of the way.  */
+      switch (r_type)
+	{
+	case R_push:
+	  reloc_stack_push (relocation + rel->r_addend);
+	  r = bfd_reloc_ok;
+	  goto done_reloc;
+	case R_const:
+	  reloc_stack_push (rel->r_addend);
+	  r = bfd_reloc_ok;
+	  goto done_reloc;
+	case R_add:
+	case R_sub:
+	case R_mult:
+	case R_div:
+	case R_mod:
+	case R_lshift:
+	case R_rshift:
+	case R_neg:
+	case R_and:
+	case R_or:
+	case R_xor:
+	case R_land:
+	case R_lor:
+	case R_comp:
+	case R_page:
+	case R_hwpage:
+	  reloc_stack_operate (r_type);
+	  r = bfd_reloc_ok;
+	  goto done_reloc;
+
+	default:
+	  if (!is_reloc_stack_empty())
+	    relocation = reloc_stack_pop ();
+	  break;
+	}
+
+      /* Then, process normally.  */
       switch (r_type)
 	{
 	case R_BFIN_GNU_VTINHERIT:
@@ -1773,7 +1805,7 @@ bfin_relocate_section (bfd * output_bfd,
 	     in the global offset table.  */
 	  if (h != NULL
 	      && strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
-	    break;
+	    goto do_default;
 	  /* Fall through.  */
 	  /* Relocation is the offset of the entry for this symbol in
 	     the global offset table.  */
@@ -1793,13 +1825,14 @@ bfin_relocate_section (bfd * output_bfd,
 
 		off = h->got.offset;
 		BFD_ASSERT (off != (bfd_vma) - 1);
-
 		dyn = elf_hash_table (info)->dynamic_sections_created;
+
 		if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
 		    || (info->shared
 			&& (info->symbolic
 			    || h->dynindx == -1
-			    || h->forced_local) && h->def_regular))
+			    || h->forced_local)
+			&& h->def_regular))
 		  {
 		    /* This is actually a static link, or it is a
 		       -Bsymbolic link and the symbol is defined
@@ -1827,10 +1860,9 @@ bfin_relocate_section (bfd * output_bfd,
 	      }
 	    else
 	      {
-		BFD_ASSERT (local_got_offsets != NULL
-			    && local_got_offsets[r_symndx] != (bfd_vma) - 1);
-
+		BFD_ASSERT (local_got_offsets != NULL);
 		off = local_got_offsets[r_symndx];
+		BFD_ASSERT (off != (bfd_vma) - 1);
 
 		/* The offset must always be a multiple of 4.  We use
 		   the least significant bit to record whether we have
@@ -1839,7 +1871,6 @@ bfin_relocate_section (bfd * output_bfd,
 		  off &= ~1;
 		else
 		  {
-
 		    bfd_put_32 (output_bfd, relocation, sgot->contents + off);
 
 		    if (info->shared)
@@ -1871,71 +1902,52 @@ bfin_relocate_section (bfd * output_bfd,
             /* bfin : preg = [preg + 17bitdiv4offset] relocation is div by 4.  */
             relocation /= 4;
 	  }
+	  goto do_default;
+
+	case R_pcrel24:
+	case R_pcrel24_jump_l:
+	  {
+	    bfd_vma x;
+
+	    relocation += rel->r_addend;
+
+	    /* Perform usual pc-relative correction.  */
+	    relocation -= input_section->output_section->vma + input_section->output_offset;
+	    relocation -= address;
+
+	    /* We are getting reloc_entry->address 2 byte off from
+	       the start of instruction. Assuming absolute postion
+	       of the reloc data. But, following code had been written assuming 
+	       reloc address is starting at begining of instruction.
+	       To compensate that I have increased the value of 
+	       relocation by 1 (effectively 2) and used the addr -2 instead of addr.  */ 
+
+	    relocation += 2;
+	    address -= 2;
+
+	    relocation >>= 1;
+
+	    x = bfd_get_16 (input_bfd, contents + address);
+	    x = (x & 0xff00) | ((relocation >> 16) & 0xff);
+	    bfd_put_16 (input_bfd, x, contents + address);
+
+	    x = bfd_get_16 (input_bfd, contents + address + 2);
+	    x = relocation & 0xFFFF;
+	    bfd_put_16 (input_bfd, x, contents + address + 2);
+	    r = bfd_reloc_ok;
+	  }
 	  break;
 
 	default:
-	  if (howto->special_function)
-	    {
-	      bfd_reloc_status_type cont;
-	      arelent reloc_ent;
-	      asymbol symbol;
-	      asymbol *symbol1;
-	      symbol.flags = 0;
-	      symbol.section = bfd_und_section_ptr;
-	      symbol.value = 0;
-
-	      if (h != NULL)
-		{
-		  if (unresolved_reloc)
-		    {
-		      break;
-		    }
-		  if (h->root.type != bfd_link_hash_undefweak
-		      && h->root.type != bfd_link_hash_undefined)
-		    {
-		      symbol.the_bfd = input_bfd;
-		      symbol.section = h->root.u.def.section;
-		      symbol.name = h->root.root.string;
-		      symbol.value = h->root.u.def.value;
-		    }
-		  if (h->root.type == bfd_link_hash_defweak
-                      || h->root.type == bfd_link_hash_undefweak)
-		    {
-		      symbol.name = h->root.root.string;
-		      symbol.flags |= BSF_WEAK;
-		    }
-		}
-	      else
-		{
-		  symbol = *sec->symbol;
-		}
-	      reloc_ent.address = rel->r_offset;
-	      reloc_ent.howto = howto;
-	      reloc_ent.addend = rel->r_addend;
-	      symbol1 = &symbol;
-	      reloc_ent.sym_ptr_ptr = &symbol1;
-
-	      cont =
-		howto->special_function (input_bfd, &reloc_ent, &symbol,
-					 contents, input_section,
-					 info->
-					 relocatable ? output_bfd : NULL,
-					 &error_msg);
-	      if (cont == bfd_reloc_ok)
-		{
-		  continue;
-		}
-	    }
-	  else
-	    {
-	      fprintf (stderr, "%s no special func r_type is %d\n",
-		       input_bfd->filename, r_type);
-	      bfd_set_error (bfd_error_bad_value);
-	      return FALSE;
-	    }
+	do_default:
+	  r = _bfd_final_link_relocate (howto, input_bfd, input_section,
+					contents, address,
+					relocation, rel->r_addend);
+
 	  break;
 	}
 
+    done_reloc:
       /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
          because such sections are not SEC_ALLOC and thus ld.so will
          not process them.  */
@@ -1949,10 +1961,6 @@ bfin_relocate_section (bfd * output_bfd,
 	  return FALSE;
 	}
 
-      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
-				    contents, rel->r_offset,
-				    relocation, rel->r_addend);
-
       if (r != bfd_reloc_ok)
 	{
 	  const char *name;
@@ -2756,7 +2764,7 @@ bfd_bfin_elf32_create_embedded_relocs (
       bfd_put_32 (abfd, irel->r_offset + datasec->output_offset, p);
       memset (p + 4, 0, 8);
       if (targetsec != NULL)
-	strncpy (p + 4, targetsec->output_section->name, 8);
+	strncpy ((char *) p + 4, targetsec->output_section->name, 8);
     }
 
   if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
index 4580beabd90..06865dcc2e2 100644
--- a/bfd/elf32-cris.c
+++ b/bfd/elf32-cris.c
@@ -156,7 +156,12 @@ static reloc_howto_type cris_elf_howto_table [] =
 	 32,			/* bitsize */
 	 FALSE,			/* pc_relative */
 	 0,			/* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
+	 /* We don't want overflow complaints for 64-bit vma builds
+	    for e.g. sym+0x40000000 (or actually sym-0xc0000000 in
+	    32-bit ELF) where sym=0xc0001234.
+	    Don't do this for the PIC relocs, as we don't expect to
+	    see them with large offsets.  */
+	 complain_overflow_dont, /* complain_on_overflow */
 	 bfd_elf_generic_reloc,	/* special_function */
 	 "R_CRIS_32",		/* name */
 	 FALSE,			/* partial_inplace */
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 942b376cf9f..5d34558c361 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -1004,7 +1004,7 @@ elf32_hppa_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf32_hppa_copy_indirect_symbol (const struct elf_backend_data *bed,
+elf32_hppa_copy_indirect_symbol (struct bfd_link_info *info,
 				 struct elf_link_hash_entry *eh_dir,
 				 struct elf_link_hash_entry *eh_ind)
 {
@@ -1020,16 +1020,15 @@ elf32_hppa_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct elf32_hppa_dyn_reloc_entry **hdh_pp;
 	  struct elf32_hppa_dyn_reloc_entry *hdh_p;
 
-	  if (eh_ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (hdh_pp = &hh_ind->dyn_relocs; (hdh_p = *hdh_pp) != NULL; )
 	    {
 	      struct elf32_hppa_dyn_reloc_entry *hdh_q;
 
-	      for (hdh_q = hh_dir->dyn_relocs; hdh_q != NULL; hdh_q = hdh_q->hdh_next)
+	      for (hdh_q = hh_dir->dyn_relocs;
+		   hdh_q != NULL;
+		   hdh_q = hdh_q->hdh_next)
 		if (hdh_q->sec == hdh_p->sec)
 		  {
 #if RELATIVE_DYNRELOCS
@@ -1062,7 +1061,7 @@ elf32_hppa_copy_indirect_symbol (const struct elf_backend_data *bed,
       eh_dir->needs_plt |= eh_ind->needs_plt;
     }
   else
-   _bfd_elf_link_hash_copy_indirect (bed, eh_dir, eh_ind);
+   _bfd_elf_link_hash_copy_indirect (info, eh_dir, eh_ind);
 }
 
 /* Look through the relocs for a section during the first phase, and
diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
index c9c44337805..d9e6fbf5280 100644
--- a/bfd/elf32-i370.c
+++ b/bfd/elf32-i370.c
@@ -379,7 +379,7 @@ i370_elf_fake_sections (bfd *abfd ATTRIBUTE_UNUSED,
 			Elf_Internal_Shdr *shdr,
 			asection *asect)
 {
-  if ((asect->flags & SEC_EXCLUDE) != 0)
+  if ((asect->flags & (SEC_GROUP | SEC_EXCLUDE)) == SEC_EXCLUDE)
     shdr->sh_flags |= SHF_EXCLUDE;
 
   if ((asect->flags & SEC_SORT_ENTRIES) != 0)
diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index acb9f1936ee..061a9cb32d8 100644
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -772,7 +772,7 @@ elf_i386_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf_i386_copy_indirect_symbol (const struct elf_backend_data *bed,
+elf_i386_copy_indirect_symbol (struct bfd_link_info *info,
 			       struct elf_link_hash_entry *dir,
 			       struct elf_link_hash_entry *ind)
 {
@@ -788,10 +788,7 @@ elf_i386_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct elf_i386_dyn_relocs **pp;
 	  struct elf_i386_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -836,7 +833,7 @@ elf_i386_copy_indirect_symbol (const struct elf_backend_data *bed,
       dir->pointer_equality_needed |= ind->pointer_equality_needed;
     }
   else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+    _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static int
diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index c26bebf73c4..82ed13c881d 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -1755,7 +1755,7 @@ m32r_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-m32r_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
+m32r_elf_copy_indirect_symbol (struct bfd_link_info *info,
                                struct elf_link_hash_entry *dir,
                                struct elf_link_hash_entry *ind)
 {
@@ -1772,10 +1772,7 @@ m32r_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
           struct elf_m32r_dyn_relocs **pp;
           struct elf_m32r_dyn_relocs *p;
 
-          if (ind->root.type == bfd_link_hash_indirect)
-            abort ();
-
-          /* Add reloc counts against the weak sym to the strong sym
+          /* Add reloc counts against the indirect sym to the direct sym
              list.  Merge any entries against the same section.  */
           for (pp = &eind->dyn_relocs; (p = *pp) != NULL;)
             {
@@ -1799,7 +1796,7 @@ m32r_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
       eind->dyn_relocs = NULL;
     }
 
-  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 
diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index 589dccfb35d..fec2bbb460a 100644
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -1871,7 +1871,7 @@ elf_m68k_finish_dynamic_symbol (output_bfd, info, h, sym)
 		  + got_offset
 		  - (splt->output_section->vma
 		     + h->plt.offset
-		     + CFV4E_FLAG (output_bfd) ? 8 : 2),
+		     + (CFV4E_FLAG (output_bfd) ? 8 : 2)),
 		  splt->contents + h->plt.offset + plt_off1);
 
       bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
@@ -1884,7 +1884,7 @@ elf_m68k_finish_dynamic_symbol (output_bfd, info, h, sym)
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
-		   + CFV4E_FLAG (output_bfd) ? 12 : 8),
+		   + (CFV4E_FLAG (output_bfd) ? 12 : 8)),
 		  sgot->contents + got_offset);
 
       /* Fill in the entry in the .rela.plt section.  */
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 2134af2c761..70d03a3f996 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -1856,7 +1856,7 @@ ppc_elf_fake_sections (bfd *abfd ATTRIBUTE_UNUSED,
 		       Elf_Internal_Shdr *shdr,
 		       asection *asect)
 {
-  if ((asect->flags & SEC_EXCLUDE) != 0)
+  if ((asect->flags & (SEC_GROUP | SEC_EXCLUDE)) == SEC_EXCLUDE)
     shdr->sh_flags |= SHF_EXCLUDE;
 
   if ((asect->flags & SEC_SORT_ENTRIES) != 0)
@@ -2565,12 +2565,11 @@ ppc_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-ppc_elf_copy_indirect_symbol (const struct elf_backend_data *bed ATTRIBUTE_UNUSED,
+ppc_elf_copy_indirect_symbol (struct bfd_link_info *info,
 			      struct elf_link_hash_entry *dir,
 			      struct elf_link_hash_entry *ind)
 {
   struct ppc_elf_link_hash_entry *edir, *eind;
-  bfd_signed_vma tmp;
 
   edir = (struct ppc_elf_link_hash_entry *) dir;
   eind = (struct ppc_elf_link_hash_entry *) ind;
@@ -2582,10 +2581,7 @@ ppc_elf_copy_indirect_symbol (const struct elf_backend_data *bed ATTRIBUTE_UNUSE
 	  struct ppc_elf_dyn_relocs **pp;
 	  struct ppc_elf_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -2631,14 +2627,8 @@ ppc_elf_copy_indirect_symbol (const struct elf_backend_data *bed ATTRIBUTE_UNUSE
 
   /* Copy over the GOT refcount entries that we may have already seen to
      the symbol which just became indirect.  */
-  tmp = edir->elf.got.refcount;
-  if (tmp < 1)
-    {
-      edir->elf.got.refcount = eind->elf.got.refcount;
-      eind->elf.got.refcount = tmp;
-    }
-  else
-    BFD_ASSERT (eind->elf.got.refcount < 1);
+  edir->elf.got.refcount += eind->elf.got.refcount;
+  eind->elf.got.refcount = 0;
 
   /* And plt entries.  */
   if (eind->elf.plt.plist != NULL)
@@ -2669,15 +2659,16 @@ ppc_elf_copy_indirect_symbol (const struct elf_backend_data *bed ATTRIBUTE_UNUSE
       eind->elf.plt.plist = NULL;
     }
 
-  if (edir->elf.dynindx == -1)
+  if (eind->elf.dynindx != -1)
     {
+      if (edir->elf.dynindx != -1)
+	_bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
+				edir->elf.dynstr_index);
       edir->elf.dynindx = eind->elf.dynindx;
       edir->elf.dynstr_index = eind->elf.dynstr_index;
       eind->elf.dynindx = -1;
       eind->elf.dynstr_index = 0;
     }
-  else
-    BFD_ASSERT (eind->elf.dynindx == -1);
 }
 
 /* Return 1 if target is one of ours.  */
diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
index 55090c6a0c0..14a3191b596 100644
--- a/bfd/elf32-s390.c
+++ b/bfd/elf32-s390.c
@@ -41,7 +41,7 @@ static bfd_boolean create_got_section
 static bfd_boolean elf_s390_create_dynamic_sections
   PARAMS((bfd *, struct bfd_link_info *));
 static void elf_s390_copy_indirect_symbol
-  PARAMS ((const struct elf_backend_data *, struct elf_link_hash_entry *,
+  PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *,
 	   struct elf_link_hash_entry *));
 static bfd_boolean elf_s390_check_relocs
   PARAMS ((bfd *, struct bfd_link_info *, asection *,
@@ -855,8 +855,8 @@ elf_s390_create_dynamic_sections (dynobj, info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf_s390_copy_indirect_symbol (bed, dir, ind)
-     const struct elf_backend_data *bed;
+elf_s390_copy_indirect_symbol (info, dir, ind)
+     struct bfd_link_info *info;
      struct elf_link_hash_entry *dir, *ind;
 {
   struct elf_s390_link_hash_entry *edir, *eind;
@@ -871,10 +871,7 @@ elf_s390_copy_indirect_symbol (bed, dir, ind)
 	  struct elf_s390_dyn_relocs **pp;
 	  struct elf_s390_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -918,7 +915,7 @@ elf_s390_copy_indirect_symbol (bed, dir, ind)
       dir->needs_plt |= ind->needs_plt;
     }
   else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+    _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static int
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index abbee05c51c..4d1e280881f 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -6063,14 +6063,11 @@ sh_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info,
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-sh_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
+sh_elf_copy_indirect_symbol (struct bfd_link_info *info,
 			     struct elf_link_hash_entry *dir,
 			     struct elf_link_hash_entry *ind)
 {
   struct elf_sh_link_hash_entry *edir, *eind;
-#ifdef INCLUDE_SHMEDIA
-  bfd_signed_vma tmp;
-#endif
 
   edir = (struct elf_sh_link_hash_entry *) dir;
   eind = (struct elf_sh_link_hash_entry *) ind;
@@ -6082,9 +6079,7 @@ sh_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct elf_sh_dyn_relocs **pp;
 	  struct elf_sh_dyn_relocs *p;
 
-	  BFD_ASSERT (ind->root.type != bfd_link_hash_indirect);
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -6110,14 +6105,8 @@ sh_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
   edir->gotplt_refcount = eind->gotplt_refcount;
   eind->gotplt_refcount = 0;
 #ifdef INCLUDE_SHMEDIA
-  tmp = edir->datalabel_got.refcount;
-  if (tmp < 1)
-    {
-      edir->datalabel_got.refcount = eind->datalabel_got.refcount;
-      eind->datalabel_got.refcount = tmp;
-    }
-  else
-    BFD_ASSERT (eind->datalabel_got.refcount < 1);
+  edir->datalabel_got.refcount += eind->datalabel_got.refcount;
+  eind->datalabel_got.refcount = 0;
 #endif
 
   if (ind->root.type == bfd_link_hash_indirect
@@ -6139,7 +6128,7 @@ sh_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
       dir->needs_plt |= ind->needs_plt;
     }
   else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+    _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static int
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 9bc2fcfbcf9..d15c77230d7 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -95,6 +95,7 @@ static bfd_vma opd_entry_value
 #define elf_backend_hide_symbol		      ppc64_elf_hide_symbol
 #define elf_backend_always_size_sections      ppc64_elf_func_desc_adjust
 #define elf_backend_size_dynamic_sections     ppc64_elf_size_dynamic_sections
+#define elf_backend_action_discarded	      ppc64_elf_action_discarded
 #define elf_backend_relocate_section	      ppc64_elf_relocate_section
 #define elf_backend_finish_dynamic_symbol     ppc64_elf_finish_dynamic_symbol
 #define elf_backend_reloc_type_class	      ppc64_elf_reloc_type_class
@@ -3843,10 +3844,9 @@ move_plt_plist (struct ppc_link_hash_entry *from,
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-ppc64_elf_copy_indirect_symbol
-  (const struct elf_backend_data *bed ATTRIBUTE_UNUSED,
-   struct elf_link_hash_entry *dir,
-   struct elf_link_hash_entry *ind)
+ppc64_elf_copy_indirect_symbol (struct bfd_link_info *info,
+				struct elf_link_hash_entry *dir,
+				struct elf_link_hash_entry *ind)
 {
   struct ppc_link_hash_entry *edir, *eind;
 
@@ -3861,10 +3861,7 @@ ppc64_elf_copy_indirect_symbol
 	  struct ppc_dyn_relocs **pp;
 	  struct ppc_dyn_relocs *p;
 
-	  if (eind->elf.root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -3944,15 +3941,16 @@ ppc64_elf_copy_indirect_symbol
   /* And plt entries.  */
   move_plt_plist (eind, edir);
 
-  if (edir->elf.dynindx == -1)
+  if (eind->elf.dynindx != -1)
     {
+      if (edir->elf.dynindx != -1)
+	_bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
+				edir->elf.dynstr_index);
       edir->elf.dynindx = eind->elf.dynindx;
       edir->elf.dynstr_index = eind->elf.dynstr_index;
       eind->elf.dynindx = -1;
       eind->elf.dynstr_index = 0;
     }
-  else
-    BFD_ASSERT (eind->elf.dynindx == -1);
 }
 
 /* Find the function descriptor hash entry from the given function code
@@ -6120,15 +6118,24 @@ dec_dynrel_count (bfd_vma r_info,
 
   if (h != NULL)
     pp = &((struct ppc_link_hash_entry *) h)->dyn_relocs;
-  else if (sym_sec != NULL)
-    {
-      void *vpp = &elf_section_data (sym_sec)->local_dynrel;
-      pp = (struct ppc_dyn_relocs **) vpp;
-    }
   else
     {
-      void *vpp = &elf_section_data (sec)->local_dynrel;
-      pp = (struct ppc_dyn_relocs **) vpp;
+      if (sym_sec != NULL)
+	{
+	  void *vpp = &elf_section_data (sym_sec)->local_dynrel;
+	  pp = (struct ppc_dyn_relocs **) vpp;
+	}
+      else
+	{
+	  void *vpp = &elf_section_data (sec)->local_dynrel;
+	  pp = (struct ppc_dyn_relocs **) vpp;
+	}
+
+      /* elf_gc_sweep may have already removed all dyn relocs associated
+	 with local syms for a given section.  Don't report a dynreloc
+	 miscount.  */
+      if (*pp == NULL)
+	return TRUE;
     }
 
   while ((p = *pp) != NULL)
@@ -6476,7 +6483,8 @@ ppc64_elf_edit_opd (bfd *obfd, struct bfd_link_info *info,
 
 	      if (skip)
 		{
-		  if (!info->relocatable
+		  if (!NO_OPD_RELOCS
+		      && !info->relocatable
 		      && !dec_dynrel_count (rel->r_info, sec, info,
 					    NULL, h, sym_sec))
 		    goto error_ret;
@@ -9454,6 +9462,21 @@ ppc64_elf_restore_symbols (struct bfd_link_info *info)
   elf_link_hash_traverse (&htab->elf, undo_symbol_twiddle, info);
 }
 
+/* What to do when ld finds relocations against symbols defined in
+   discarded sections.  */
+
+static unsigned int
+ppc64_elf_action_discarded (asection *sec)
+{
+  if (strcmp (".opd", sec->name) == 0)
+    return 0;
+
+  if (strcmp (".toc", sec->name) == 0)
+    return 0;
+
+  return _bfd_elf_default_action_discarded (sec);
+}
+
 /* The RELOCATE_SECTION function is called by the ELF backend linker
    to handle the relocations for a section.
 
diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
index 7808c3fd1a3..f93c6130255 100644
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c
@@ -41,7 +41,7 @@ static bfd_boolean create_got_section
 static bfd_boolean elf_s390_create_dynamic_sections
   PARAMS((bfd *, struct bfd_link_info *));
 static void elf_s390_copy_indirect_symbol
-  PARAMS ((const struct elf_backend_data *, struct elf_link_hash_entry *,
+  PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *,
 	   struct elf_link_hash_entry *));
 static bfd_boolean elf_s390_check_relocs
   PARAMS ((bfd *, struct bfd_link_info *, asection *,
@@ -808,8 +808,8 @@ elf_s390_create_dynamic_sections (dynobj, info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf_s390_copy_indirect_symbol (bed, dir, ind)
-     const struct elf_backend_data *bed;
+elf_s390_copy_indirect_symbol (info, dir, ind)
+     struct bfd_link_info *info;
      struct elf_link_hash_entry *dir, *ind;
 {
   struct elf_s390_link_hash_entry *edir, *eind;
@@ -824,10 +824,7 @@ elf_s390_copy_indirect_symbol (bed, dir, ind)
 	  struct elf_s390_dyn_relocs **pp;
 	  struct elf_s390_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -871,7 +868,7 @@ elf_s390_copy_indirect_symbol (bed, dir, ind)
       dir->needs_plt |= ind->needs_plt;
     }
   else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+    _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static int
diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index 0520906b227..54914ba2d3d 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -525,7 +525,7 @@ elf64_x86_64_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 static void
-elf64_x86_64_copy_indirect_symbol (const struct elf_backend_data *bed,
+elf64_x86_64_copy_indirect_symbol (struct bfd_link_info *info,
 				   struct elf_link_hash_entry *dir,
 				   struct elf_link_hash_entry *ind)
 {
@@ -541,10 +541,7 @@ elf64_x86_64_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct elf64_x86_64_dyn_relocs **pp;
 	  struct elf64_x86_64_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -589,7 +586,7 @@ elf64_x86_64_copy_indirect_symbol (const struct elf_backend_data *bed,
       dir->pointer_equality_needed |= ind->pointer_equality_needed;
     }
   else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+    _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static bfd_boolean
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 61676d619f6..899c48db8e9 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -1283,7 +1283,7 @@ _bfd_elf_merge_symbol (bfd *abfd,
       flip->root.type = h->root.type;
       h->root.type = bfd_link_hash_indirect;
       h->root.u.i.link = (struct bfd_link_hash_entry *) flip;
-      (*bed->elf_backend_copy_indirect_symbol) (bed, flip, h);
+      (*bed->elf_backend_copy_indirect_symbol) (info, flip, h);
       flip->root.u.undef.abfd = h->root.u.undef.abfd;
       if (h->def_dynamic)
 	{
@@ -1437,7 +1437,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
       struct elf_link_hash_entry *ht;
 
       ht = (struct elf_link_hash_entry *) hi->root.u.i.link;
-      (*bed->elf_backend_copy_indirect_symbol) (bed, ht, hi);
+      (*bed->elf_backend_copy_indirect_symbol) (info, ht, hi);
 
       /* See if the new flags lead us to realize that the symbol must
 	 be dynamic.  */
@@ -1506,7 +1506,7 @@ nondefault:
 
       if (hi->root.type == bfd_link_hash_indirect)
 	{
-	  (*bed->elf_backend_copy_indirect_symbol) (bed, h, hi);
+	  (*bed->elf_backend_copy_indirect_symbol) (info, h, hi);
 
 	  /* See if the new flags lead us to realize that the symbol
 	     must be dynamic.  */
@@ -2317,7 +2317,7 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 	  const struct elf_backend_data *bed;
 
 	  bed = get_elf_backend_data (elf_hash_table (eif->info)->dynobj);
-	  (*bed->elf_backend_copy_indirect_symbol) (bed, weakdef, h);
+	  (*bed->elf_backend_copy_indirect_symbol) (eif->info, weakdef, h);
 	}
     }
 
@@ -4139,7 +4139,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 	      (*bed->elf_backend_hide_symbol) (info, hi, TRUE);
 	      hi->root.type = bfd_link_hash_indirect;
 	      hi->root.u.i.link = (struct bfd_link_hash_entry *) h;
-	      (*bed->elf_backend_copy_indirect_symbol) (bed, h, hi);
+	      (*bed->elf_backend_copy_indirect_symbol) (info, h, hi);
 	      sym_hash = elf_sym_hashes (abfd);
 	      if (sym_hash)
 		for (symidx = 0; symidx < extsymcount; ++symidx)
@@ -6827,8 +6827,10 @@ elf_link_input_bfd (struct elf_final_link_info *finfo, bfd *input_bfd)
 	isec = bfd_com_section_ptr;
       else
 	{
-	  /* Who knows?  */
-	  isec = NULL;
+	  /* Don't attempt to output symbols with st_shnx in the
+	     reserved range other than SHN_ABS and SHN_COMMON.  */
+	  *ppsection = NULL;
+	  continue;
 	}
 
       *ppsection = isec;
@@ -6859,20 +6861,12 @@ elf_link_input_bfd (struct elf_final_link_info *finfo, bfd *input_bfd)
 	continue;
 
       /* If this symbol is defined in a section which we are
-	 discarding, we don't need to keep it, but note that
-	 linker_mark is only reliable for sections that have contents.
-	 For the benefit of the MIPS ELF linker, we check SEC_EXCLUDE
-	 as well as linker_mark.  */
-      if ((isym->st_shndx < SHN_LORESERVE || isym->st_shndx > SHN_HIRESERVE)
+	 discarding, we don't need to keep it.  */
+      if (isym->st_shndx != SHN_UNDEF
+	  && (isym->st_shndx < SHN_LORESERVE || isym->st_shndx > SHN_HIRESERVE)
 	  && (isec == NULL
-	      || (! isec->linker_mark && (isec->flags & SEC_HAS_CONTENTS) != 0)
-	      || (! finfo->info->relocatable
-		  && (isec->flags & SEC_EXCLUDE) != 0)))
-	continue;
-
-      /* If the section is not in the output BFD's section list, it is not
-	 being output.  */
-      if (bfd_section_removed_from_list (output_bfd, isec->output_section))
+	      || bfd_section_removed_from_list (output_bfd,
+						isec->output_section)))
 	continue;
 
       /* Get the name of the symbol.  */
diff --git a/bfd/elfxx-ia64.c b/bfd/elfxx-ia64.c
index dc2c2e15a86..5dfdaaa7406 100644
--- a/bfd/elfxx-ia64.c
+++ b/bfd/elfxx-ia64.c
@@ -216,7 +216,7 @@ static struct bfd_hash_entry *elfNN_ia64_new_elf_hash_entry
   PARAMS ((struct bfd_hash_entry *entry, struct bfd_hash_table *table,
 	   const char *string));
 static void elfNN_ia64_hash_copy_indirect
-  PARAMS ((const struct elf_backend_data *, struct elf_link_hash_entry *,
+  PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *,
 	   struct elf_link_hash_entry *));
 static void elfNN_ia64_hash_hide_symbol
   PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *, bfd_boolean));
@@ -1798,8 +1798,8 @@ elfNN_ia64_new_elf_hash_entry (entry, table, string)
 }
 
 static void
-elfNN_ia64_hash_copy_indirect (bed, xdir, xind)
-     const struct elf_backend_data *bed ATTRIBUTE_UNUSED;
+elfNN_ia64_hash_copy_indirect (info, xdir, xind)
+     struct bfd_link_info *info;
      struct elf_link_hash_entry *xdir, *xind;
 {
   struct elfNN_ia64_link_hash_entry *dir, *ind;
@@ -1821,29 +1821,34 @@ elfNN_ia64_hash_copy_indirect (bed, xdir, xind)
   /* Copy over the got and plt data.  This would have been done
      by check_relocs.  */
 
-  if (dir->info == NULL)
+  if (ind->info != NULL)
     {
       struct elfNN_ia64_dyn_sym_info *dyn_i;
+      struct elfNN_ia64_dyn_sym_info **pdyn;
 
-      dir->info = dyn_i = ind->info;
+      pdyn = &dir->info;
+      while ((dyn_i = *pdyn) != NULL)
+	pdyn = &dyn_i->next;
+      *pdyn = dyn_i = ind->info;
       ind->info = NULL;
 
       /* Fix up the dyn_sym_info pointers to the global symbol.  */
       for (; dyn_i; dyn_i = dyn_i->next)
 	dyn_i->h = &dir->root;
     }
-  BFD_ASSERT (ind->info == NULL);
 
   /* Copy over the dynindx.  */
 
-  if (dir->root.dynindx == -1)
+  if (ind->root.dynindx != -1)
     {
+      if (dir->root.dynindx != -1)
+	_bfd_elf_strtab_delref (elf_hash_table (info)->dynstr,
+				dir->root.dynstr_index);
       dir->root.dynindx = ind->root.dynindx;
       dir->root.dynstr_index = ind->root.dynstr_index;
       ind->root.dynindx = -1;
       ind->root.dynstr_index = 0;
     }
-  BFD_ASSERT (ind->root.dynindx == -1);
 }
 
 static void
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 27d2dc3854b..685f1d22e3f 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -8387,13 +8387,13 @@ _bfd_mips_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED,
    _bfd_elf_link_hash_copy_indirect copy the flags for us.  */
 
 void
-_bfd_mips_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
+_bfd_mips_elf_copy_indirect_symbol (struct bfd_link_info *info,
 				    struct elf_link_hash_entry *dir,
 				    struct elf_link_hash_entry *ind)
 {
   struct mips_elf_link_hash_entry *dirmips, *indmips;
 
-  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 
   if (ind->root.type != bfd_link_hash_indirect)
     return;
@@ -8408,8 +8408,6 @@ _bfd_mips_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
 
   if (dirmips->tls_type == 0)
     dirmips->tls_type = indmips->tls_type;
-  else
-    BFD_ASSERT (indmips->tls_type == 0);
 }
 
 void
diff --git a/bfd/elfxx-mips.h b/bfd/elfxx-mips.h
index ff53b0d8c53..d419435c110 100644
--- a/bfd/elfxx-mips.h
+++ b/bfd/elfxx-mips.h
@@ -72,7 +72,7 @@ extern asection * _bfd_mips_elf_gc_mark_hook
 extern bfd_boolean _bfd_mips_elf_gc_sweep_hook
   (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *);
 extern void _bfd_mips_elf_copy_indirect_symbol
-  (const struct elf_backend_data *, struct elf_link_hash_entry *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *,
    struct elf_link_hash_entry *);
 extern void _bfd_mips_elf_hide_symbol
   (struct bfd_link_info *, struct elf_link_hash_entry *, bfd_boolean);
diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index eff34eadf04..e587a675d80 100644
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -881,7 +881,7 @@ _bfd_sparc_elf_create_dynamic_sections (bfd *dynobj,
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
 
 void
-_bfd_sparc_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
+_bfd_sparc_elf_copy_indirect_symbol (struct bfd_link_info *info,
 				     struct elf_link_hash_entry *dir,
 				     struct elf_link_hash_entry *ind)
 {
@@ -897,10 +897,7 @@ _bfd_sparc_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
 	  struct _bfd_sparc_elf_dyn_relocs **pp;
 	  struct _bfd_sparc_elf_dyn_relocs *p;
 
-	  if (ind->root.type == bfd_link_hash_indirect)
-	    abort ();
-
-	  /* Add reloc counts against the weak sym to the strong sym
+	  /* Add reloc counts against the indirect sym to the direct sym
 	     list.  Merge any entries against the same section.  */
 	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
 	    {
@@ -930,7 +927,7 @@ _bfd_sparc_elf_copy_indirect_symbol (const struct elf_backend_data *bed,
       edir->tls_type = eind->tls_type;
       eind->tls_type = GOT_UNKNOWN;
     }
-  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 }
 
 static int
diff --git a/bfd/elfxx-sparc.h b/bfd/elfxx-sparc.h
index 1bfaaa6cfcf..624aea52787 100644
--- a/bfd/elfxx-sparc.h
+++ b/bfd/elfxx-sparc.h
@@ -97,7 +97,7 @@ extern struct bfd_link_hash_table *_bfd_sparc_elf_link_hash_table_create
 extern bfd_boolean _bfd_sparc_elf_create_dynamic_sections
   (bfd *, struct bfd_link_info *);
 extern void _bfd_sparc_elf_copy_indirect_symbol
-  (const struct elf_backend_data *,
+  (struct bfd_link_info *,
    struct elf_link_hash_entry *,
    struct elf_link_hash_entry *);
 extern bfd_boolean _bfd_sparc_elf_check_relocs
diff --git a/bfd/hppabsd-core.c b/bfd/hppabsd-core.c
index 2ad27351b8a..894d244bbc3 100644
--- a/bfd/hppabsd-core.c
+++ b/bfd/hppabsd-core.c
@@ -1,5 +1,5 @@
 /* BFD back-end for HPPA BSD core files.
-   Copyright 1993, 1994, 1995, 1998, 1999, 2001, 2002, 2003, 2004
+   Copyright 1993, 1994, 1995, 1998, 1999, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -137,14 +137,11 @@ hppabsd_core_core_file_p (abfd)
   /* Sanity checks.  Make sure the size of the core file matches the
      the size computed from information within the core itself.  */
   {
-    FILE *stream = bfd_cache_lookup (abfd);
     struct stat statbuf;
 
-    if (fstat (fileno (stream), &statbuf) < 0)
-      {
-	bfd_set_error (bfd_error_system_call);
-	return NULL;
-      }
+    if (bfd_stat (abfd, &statbuf) < 0)
+      return NULL;
+
     if (NBPG * (UPAGES + u.u_dsize + u.u_ssize) > statbuf.st_size)
       {
 	bfd_set_error (bfd_error_file_truncated);
diff --git a/bfd/hpux-core.c b/bfd/hpux-core.c
index e68a715b588..9a97531eb93 100644
--- a/bfd/hpux-core.c
+++ b/bfd/hpux-core.c
@@ -61,7 +61,9 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 # endif
 #endif
 #include <signal.h>
+#ifdef HPUX_CORE
 #include <machine/reg.h>
+#endif
 #include <sys/user.h>		/* After a.out.h  */
 #include <sys/file.h>
 
diff --git a/bfd/libbfd-in.h b/bfd/libbfd-in.h
index 0290c84eda3..df46ae1273c 100644
--- a/bfd/libbfd-in.h
+++ b/bfd/libbfd-in.h
@@ -234,6 +234,9 @@ extern bfd_boolean _bfd_generic_get_section_contents_in_window
 #define _bfd_generic_bfd_print_private_bfd_data \
   ((bfd_boolean (*) (bfd *, void *)) bfd_true)
 
+extern bfd_boolean _bfd_generic_init_private_section_data
+  (bfd *, asection *, bfd *, asection *, struct bfd_link_info *);
+
 /* Routines to use for BFD_JUMP_TABLE_CORE when there is no core file
    support.  Use BFD_JUMP_TABLE_CORE (_bfd_nocore).  */
 
@@ -649,11 +652,6 @@ extern void _bfd_abort
 extern file_ptr real_ftell (FILE *file);
 extern int real_fseek (FILE *file, file_ptr offset, int whence);
 
-FILE *	bfd_cache_lookup_worker
-  (bfd *);
-
-extern bfd *bfd_last_cache;
-
 /* List of supported target vectors, and the default vector (if
    bfd_default_vector[0] is NULL, there is no default).  */
 extern const bfd_target * const *bfd_target_vector;
diff --git a/bfd/libbfd.c b/bfd/libbfd.c
index 3b27e08a8f3..34e32ac1112 100644
--- a/bfd/libbfd.c
+++ b/bfd/libbfd.c
@@ -1042,3 +1042,13 @@ _bfd_generic_match_sections_by_type (bfd *abfd ATTRIBUTE_UNUSED,
 {
   return TRUE;
 }
+
+bfd_boolean
+_bfd_generic_init_private_section_data (bfd *ibfd ATTRIBUTE_UNUSED,
+					asection *isec ATTRIBUTE_UNUSED,
+					bfd *obfd ATTRIBUTE_UNUSED,
+					asection *osec ATTRIBUTE_UNUSED,
+					struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
+{
+  return TRUE;
+}
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 56ad092983f..ff1fde7a108 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -239,6 +239,9 @@ extern bfd_boolean _bfd_generic_get_section_contents_in_window
 #define _bfd_generic_bfd_print_private_bfd_data \
   ((bfd_boolean (*) (bfd *, void *)) bfd_true)
 
+extern bfd_boolean _bfd_generic_init_private_section_data
+  (bfd *, asection *, bfd *, asection *, struct bfd_link_info *);
+
 /* Routines to use for BFD_JUMP_TABLE_CORE when there is no core file
    support.  Use BFD_JUMP_TABLE_CORE (_bfd_nocore).  */
 
@@ -654,11 +657,6 @@ extern void _bfd_abort
 extern file_ptr real_ftell (FILE *file);
 extern int real_fseek (FILE *file, file_ptr offset, int whence);
 
-FILE *	bfd_cache_lookup_worker
-  (bfd *);
-
-extern bfd *bfd_last_cache;
-
 /* List of supported target vectors, and the default vector (if
    bfd_default_vector[0] is NULL, there is no default).  */
 extern const bfd_target * const *bfd_target_vector;
@@ -764,21 +762,12 @@ struct _bfd_window_internal {
   unsigned mapped : 1;         /* 1 = mmap, 0 = malloc */
 };
 /* Extracted from cache.c.  */
-#define BFD_CACHE_MAX_OPEN 10
-extern bfd *bfd_last_cache;
-
-#define bfd_cache_lookup(x) \
-    ((x) == bfd_last_cache ? \
-      (FILE *) (bfd_last_cache->iostream): \
-       bfd_cache_lookup_worker (x))
 bfd_boolean bfd_cache_init (bfd *abfd);
 
 bfd_boolean bfd_cache_close (bfd *abfd);
 
 FILE* bfd_open_file (bfd *abfd);
 
-FILE *bfd_cache_lookup_worker (bfd *abfd);
-
 /* Extracted from reloc.c.  */
 #ifdef _BFD_MAKE_TABLE_bfd_reloc_code_real
 
@@ -1827,6 +1816,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_XTENSA_OP2",
   "BFD_RELOC_XTENSA_ASM_EXPAND",
   "BFD_RELOC_XTENSA_ASM_SIMPLIFY",
+  "BFD_RELOC_Z80_DISP8",
   "BFD_RELOC_Z8K_DISP7",
   "BFD_RELOC_Z8K_CALLR",
   "BFD_RELOC_Z8K_IMM4L",
diff --git a/bfd/linker.c b/bfd/linker.c
index 0bfdfb23706..9e6199b835a 100644
--- a/bfd/linker.c
+++ b/bfd/linker.c
@@ -2364,12 +2364,9 @@ _bfd_generic_link_output_symbols (bfd *output_bfd,
 
       /* If this symbol is in a section which is not being included
 	 in the output file, then we don't want to output the
-	 symbol.  .bss and similar sections won't have the linker_mark
-	 field set.  We also check if its output section has been
-	 removed from the output file.  */
-      if (((sym->section->flags & SEC_HAS_CONTENTS) != 0
-	   && ! sym->section->linker_mark)
-	  || bfd_section_removed_from_list (output_bfd,
+	 symbol.  */
+      if (!bfd_is_abs_section (sym->section)
+	  && bfd_section_removed_from_list (output_bfd,
 					    sym->section->output_section))
 	output = FALSE;
 
diff --git a/bfd/osf-core.c b/bfd/osf-core.c
index 1ad0a362f5b..35aa82df43e 100644
--- a/bfd/osf-core.c
+++ b/bfd/osf-core.c
@@ -26,7 +26,9 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include "libbfd.h"
 
 #include <sys/user.h>
+#ifdef OSF_CORE
 #include <sys/core.h>
+#endif
 
 /* forward declarations */
 
diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in
index 332782d7c7d..13d0104aba8 100644
--- a/bfd/po/SRC-POTFILES.in
+++ b/bfd/po/SRC-POTFILES.in
@@ -63,6 +63,7 @@ cpu-alpha.c
 cpu-arc.c
 cpu-arm.c
 cpu-avr.c
+cpu-bfin.c
 cpu-cr16c.c
 cpu-cris.c
 cpu-crx.c
@@ -128,6 +129,7 @@ elf32-am33lin.c
 elf32-arc.c
 elf32-arm.c
 elf32-avr.c
+elf32-bfin.c
 elf32.c
 elf32-cr16c.c
 elf32-cris.c
diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot
index 83367cb7156..37c57290aee 100644
--- a/bfd/po/bfd.pot
+++ b/bfd/po/bfd.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2005-07-14 17:27-0500\n"
+"POT-Creation-Date: 2005-10-25 22:24+0930\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -33,35 +33,35 @@ msgstr ""
 msgid "%B: Bad relocation record imported: %d"
 msgstr ""
 
-#: aoutx.h:1250 aoutx.h:1584
+#: aoutx.h:1244 aoutx.h:1578
 #, c-format
 msgid "%s: can not represent section `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1550
+#: aoutx.h:1544
 #, c-format
 msgid ""
 "%s: can not represent section for symbol `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1552
+#: aoutx.h:1546
 msgid "*unknown*"
 msgstr ""
 
-#: aoutx.h:5287
+#: aoutx.h:5281
 #, c-format
 msgid "%s: relocatable link from %s to %s not supported"
 msgstr ""
 
-#: archive.c:1758
+#: archive.c:1760
 msgid "Warning: writing archive was slow: rewriting timestamp\n"
 msgstr ""
 
-#: archive.c:2017
+#: archive.c:2019
 msgid "Reading archive file mod timestamp"
 msgstr ""
 
-#: archive.c:2041
+#: archive.c:2043
 msgid "Writing updated armap timestamp"
 msgstr ""
 
@@ -145,22 +145,22 @@ msgstr ""
 msgid "#<Invalid error code>"
 msgstr ""
 
-#: bfd.c:768
+#: bfd.c:771
 #, c-format
 msgid "BFD %s assertion fail %s:%d"
 msgstr ""
 
-#: bfd.c:784
+#: bfd.c:787
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d in %s\n"
 msgstr ""
 
-#: bfd.c:788
+#: bfd.c:791
 #, c-format
 msgid "BFD %s internal error, aborting at %s line %d\n"
 msgstr ""
 
-#: bfd.c:790
+#: bfd.c:793
 msgid "Please report this bug.\n"
 msgstr ""
 
@@ -183,26 +183,6 @@ msgstr ""
 msgid "%B: symbol `%s' has unrecognized smclas %d"
 msgstr ""
 
-#: coff-a29k.c:120
-msgid "Missing IHCONST"
-msgstr ""
-
-#: coff-a29k.c:181
-msgid "Missing IHIHALF"
-msgstr ""
-
-#: coff-a29k.c:213 coff-or32.c:227
-msgid "Unrecognized reloc"
-msgstr ""
-
-#: coff-a29k.c:409
-msgid "missing IHCONST reloc"
-msgstr ""
-
-#: coff-a29k.c:499
-msgid "missing IHIHALF reloc"
-msgstr ""
-
 #: coff-alpha.c:489
 msgid ""
 "%B: Cannot handle compressed Alpha binaries.\n"
@@ -229,22 +209,22 @@ msgstr ""
 msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW"
 msgstr ""
 
-#: coff-alpha.c:1557 elf32-m32r.c:2452 elf64-alpha.c:3932 elf64-alpha.c:4058
-#: elf32-ia64.c:4085 elf64-ia64.c:4085
+#: coff-alpha.c:1557 elf32-m32r.c:2471 elf64-alpha.c:3912 elf64-alpha.c:4038
+#: elf32-ia64.c:4108 elf64-ia64.c:4108
 msgid "%B: unknown relocation type %d"
 msgstr ""
 
-#: coff-arm.c:990 elf32-arm.c:1916
+#: coff-arm.c:990 elf32-arm.c:1926
 #, c-format
 msgid "%B: unable to find THUMB glue '%s' for `%s'"
 msgstr ""
 
-#: coff-arm.c:1019 elf32-arm.c:1950
+#: coff-arm.c:1019 elf32-arm.c:1960
 #, c-format
 msgid "%B: unable to find ARM glue '%s' for `%s'"
 msgstr ""
 
-#: coff-arm.c:1319 elf32-arm.c:2673
+#: coff-arm.c:1319 elf32-arm.c:2683
 #, c-format
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
@@ -259,7 +239,7 @@ msgid ""
 "  consider relinking with --support-old-code enabled"
 msgstr ""
 
-#: coff-arm.c:1702 cofflink.c:3013 coff-tic80.c:695
+#: coff-arm.c:1702 cofflink.c:3015 coff-tic80.c:695
 msgid "%B: bad reloc address 0x%lx in section `%A'"
 msgstr ""
 
@@ -272,14 +252,14 @@ msgstr ""
 msgid "ERROR: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d"
 msgstr ""
 
-#: coff-arm.c:2174 elf32-arm.c:4464
+#: coff-arm.c:2174 elf32-arm.c:5093
 #, c-format
 msgid ""
 "ERROR: %B passes floats in float registers, whereas %B passes them in "
 "integer registers"
 msgstr ""
 
-#: coff-arm.c:2177 elf32-arm.c:4468
+#: coff-arm.c:2177 elf32-arm.c:5097
 #, c-format
 msgid ""
 "ERROR: %B passes floats in integer registers, whereas %B passes them in "
@@ -300,12 +280,12 @@ msgid ""
 "position independent"
 msgstr ""
 
-#: coff-arm.c:2222 elf32-arm.c:4533
+#: coff-arm.c:2222 elf32-arm.c:5162
 #, c-format
 msgid "Warning: %B supports interworking, whereas %B does not"
 msgstr ""
 
-#: coff-arm.c:2225 elf32-arm.c:4539
+#: coff-arm.c:2225 elf32-arm.c:5168
 #, c-format
 msgid "Warning: %B does not support interworking, whereas %B does"
 msgstr ""
@@ -315,7 +295,7 @@ msgstr ""
 msgid "private flags = %x:"
 msgstr ""
 
-#: coff-arm.c:2257 elf32-arm.c:4590
+#: coff-arm.c:2257 elf32-arm.c:5219
 #, c-format
 msgid " [floats passed in float registers]"
 msgstr ""
@@ -325,7 +305,7 @@ msgstr ""
 msgid " [floats passed in integer registers]"
 msgstr ""
 
-#: coff-arm.c:2262 elf32-arm.c:4593
+#: coff-arm.c:2262 elf32-arm.c:5222
 #, c-format
 msgid " [position independent]"
 msgstr ""
@@ -350,14 +330,14 @@ msgstr ""
 msgid " [interworking not supported]"
 msgstr ""
 
-#: coff-arm.c:2318 elf32-arm.c:4271
+#: coff-arm.c:2318 elf32-arm.c:4571
 #, c-format
 msgid ""
 "Warning: Not setting interworking flag of %B since it has already been "
 "specified as non-interworking"
 msgstr ""
 
-#: coff-arm.c:2322 elf32-arm.c:4275
+#: coff-arm.c:2322 elf32-arm.c:4575
 #, c-format
 msgid "Warning: Clearing the interworking flag of %B due to outside request"
 msgstr ""
@@ -378,36 +358,36 @@ msgstr ""
 msgid "%B (%s): Section flag %s (0x%x) ignored"
 msgstr ""
 
-#: coffcode.h:2210
+#: coffcode.h:2204
 #, c-format
 msgid "Unrecognized TI COFF target id '0x%x'"
 msgstr ""
 
-#: coffcode.h:4238
+#: coffcode.h:4211
 msgid "%B: warning: line number table read failed"
 msgstr ""
 
-#: coffcode.h:4270
+#: coffcode.h:4243
 msgid "%B: warning: illegal symbol index %ld in line numbers"
 msgstr ""
 
-#: coffcode.h:4284
+#: coffcode.h:4257
 msgid "%B: warning: duplicate line number information for `%s'"
 msgstr ""
 
-#: coffcode.h:4629
+#: coffcode.h:4597
 msgid "%B: Unrecognized storage class %d for %s symbol `%s'"
 msgstr ""
 
-#: coffcode.h:4755
+#: coffcode.h:4723
 msgid "warning: %B: local symbol `%s' has no section"
 msgstr ""
 
-#: coffcode.h:4859 coff-i860.c:586 coff-tic54x.c:376
+#: coffcode.h:4827 coff-i860.c:586 coff-tic54x.c:376
 msgid "%B: warning: illegal symbol index %ld in relocs"
 msgstr ""
 
-#: coffcode.h:4897
+#: coffcode.h:4865
 msgid "%B: illegal relocation type %d at address 0x%lx"
 msgstr ""
 
@@ -429,7 +409,7 @@ msgstr ""
 msgid "uncertain calling convention for non-COFF symbol"
 msgstr ""
 
-#: cofflink.c:507 elflink.c:3967
+#: cofflink.c:507 elflink.c:3948
 msgid "Warning: type of symbol `%s' changed from %d to %d in %B"
 msgstr ""
 
@@ -447,7 +427,7 @@ msgstr ""
 msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff"
 msgstr ""
 
-#: coff-m68k.c:482 elf32-m68k.c:2183
+#: coff-m68k.c:482 elf32-bfin.c:2722 elf32-m68k.c:2193
 msgid "unsupported reloc type"
 msgstr ""
 
@@ -475,6 +455,10 @@ msgstr ""
 msgid "GP relative relocation when _gp not defined"
 msgstr ""
 
+#: coff-or32.c:227
+msgid "Unrecognized reloc"
+msgstr ""
+
 #: coff-rs6000.c:2785
 #, c-format
 msgid "%s: unsupported relocation type 0x%02x"
@@ -536,49 +520,49 @@ msgstr ""
 msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
 msgstr ""
 
-#: dwarf2.c:857
+#: dwarf2.c:856
 msgid "Dwarf Error: mangled line number section (bad file number)."
 msgstr ""
 
-#: dwarf2.c:948
+#: dwarf2.c:947
 msgid "Dwarf Error: Can't find .debug_line section."
 msgstr ""
 
-#: dwarf2.c:965
+#: dwarf2.c:964
 #, c-format
 msgid ""
 "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%"
 "lu)."
 msgstr ""
 
-#: dwarf2.c:1193
+#: dwarf2.c:1192
 msgid "Dwarf Error: mangled line number section."
 msgstr ""
 
-#: dwarf2.c:1383
+#: dwarf2.c:1382
 msgid "Dwarf Error: Can't find .debug_ranges section."
 msgstr ""
 
-#: dwarf2.c:1565 dwarf2.c:1666 dwarf2.c:1896
+#: dwarf2.c:1544 dwarf2.c:1660 dwarf2.c:1930
 #, c-format
 msgid "Dwarf Error: Could not find abbrev number %u."
 msgstr ""
 
-#: dwarf2.c:1857
+#: dwarf2.c:1891
 #, c-format
 msgid ""
 "Dwarf Error: found dwarf version '%u', this reader only handles version 2 "
 "information."
 msgstr ""
 
-#: dwarf2.c:1864
+#: dwarf2.c:1898
 #, c-format
 msgid ""
 "Dwarf Error: found address size '%u', this reader can not handle sizes "
 "greater than '%u'."
 msgstr ""
 
-#: dwarf2.c:1887
+#: dwarf2.c:1921
 #, c-format
 msgid "Dwarf Error: Bad abbrev number: %u."
 msgstr ""
@@ -644,248 +628,317 @@ msgid ""
 "      Type: %s"
 msgstr ""
 
-#: elf32-arm.c:2305
+#: elf32-arm.c:2315
 msgid "%B: BE8 images only valid in big-endian mode."
 msgstr ""
 
-#: elf32-arm.c:2461
+#: elf32-arm.c:2471
 #, c-format
 msgid "Invalid TARGET2 relocation type '%s'."
 msgstr ""
 
-#: elf32-arm.c:2568
+#: elf32-arm.c:2578
 msgid ""
 "%B(%s): warning: interworking not enabled.\n"
 "  first occurrence: %B: thumb call to arm"
 msgstr ""
 
-#: elf32-arm.c:3034
+#: elf32-arm.c:3044
 msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'."
 msgstr ""
 
-#: elf32-arm.c:3217
+#: elf32-arm.c:3227
 msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'."
 msgstr ""
 
-#: elf32-arm.c:3879
+#: elf32-arm.c:3889
 msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"
 msgstr ""
 
-#: elf32-arm.c:4092 elf32-sh.c:4611 elf64-sh64.c:1537
+#: elf32-arm.c:4290 elf32-sh.c:4618 elf64-sh64.c:1537
 msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section"
 msgstr ""
 
-#: elf32-arm.c:4153 elf64-ppc.c:9615
+#: elf32-arm.c:4351 elf64-ppc.c:9672
 msgid "%B(%A+0x%lx): %s used with TLS symbol %s"
 msgstr ""
 
-#: elf32-arm.c:4154 elf64-ppc.c:9616
+#: elf32-arm.c:4352 elf64-ppc.c:9673
 msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s"
 msgstr ""
 
-#: elf32-arm.c:4177
-msgid "%B(%A+0x%lx): warning: unresolvable relocation %d against symbol `%s'"
+#: elf32-arm.c:4375 elf32-i386.c:3038 elf32-m32r.c:2653 elf32-m68k.c:1737
+#: elf32-ppc.c:6561 elf32-s390.c:3012 elf32-sh.c:4717 elf32-xtensa.c:2311
+#: elf64-ppc.c:10825 elf64-s390.c:3010 elf64-sh64.c:1626 elf64-x86-64.c:2522
+#: elf-hppa.h:1413 elf-m10300.c:1460 elfxx-sparc.c:3137
+msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
 msgstr ""
 
-#: elf32-arm.c:4210 elf32-avr.c:880 elf32-cr16c.c:773 elf32-cris.c:1502
+#: elf32-arm.c:4411 elf32-avr.c:880 elf32-cr16c.c:773 elf32-cris.c:1502
 #: elf32-crx.c:911 elf32-d10v.c:536 elf32-fr30.c:595 elf32-frv.c:4107
 #: elf32-h8300.c:494 elf32-i860.c:1189 elf32-ip2k.c:1474 elf32-iq2000.c:616
-#: elf32-m32c.c:400 elf32-m32r.c:3085 elf32-m68hc1x.c:1194 elf32-ms1.c:373
+#: elf32-m32c.c:465 elf32-m32r.c:3111 elf32-m68hc1x.c:1194 elf32-ms1.c:373
 #: elf32-msp430.c:508 elf32-openrisc.c:383 elf32-v850.c:1672
-#: elf32-xstormy16.c:909 elf64-mmix.c:1517 elf-m10200.c:427 elf-m10300.c:1529
+#: elf32-xstormy16.c:909 elf64-mmix.c:1517 elf-m10200.c:427 elf-m10300.c:1509
 msgid "internal error: out of range error"
 msgstr ""
 
-#: elf32-arm.c:4214 elf32-avr.c:884 elf32-cr16c.c:777 elf32-cris.c:1506
+#: elf32-arm.c:4415 elf32-avr.c:884 elf32-cr16c.c:777 elf32-cris.c:1506
 #: elf32-crx.c:915 elf32-d10v.c:540 elf32-fr30.c:599 elf32-frv.c:4111
-#: elf32-h8300.c:498 elf32-i860.c:1193 elf32-iq2000.c:620 elf32-m32c.c:404
-#: elf32-m32r.c:3089 elf32-m68hc1x.c:1198 elf32-msp430.c:512
+#: elf32-h8300.c:498 elf32-i860.c:1193 elf32-iq2000.c:620 elf32-m32c.c:469
+#: elf32-m32r.c:3115 elf32-m68hc1x.c:1198 elf32-msp430.c:512
 #: elf32-openrisc.c:387 elf32-v850.c:1676 elf32-xstormy16.c:913
-#: elf64-mmix.c:1521 elf-m10200.c:431 elf-m10300.c:1533 elfxx-mips.c:7198
+#: elf64-mmix.c:1521 elf-m10200.c:431 elf-m10300.c:1513 elfxx-mips.c:7212
 msgid "internal error: unsupported relocation error"
 msgstr ""
 
-#: elf32-arm.c:4218 elf32-cr16c.c:781 elf32-crx.c:919 elf32-d10v.c:544
-#: elf32-h8300.c:502 elf32-m32r.c:3093 elf32-m68hc1x.c:1202 elf-m10200.c:435
-#: elf-m10300.c:1537
+#: elf32-arm.c:4419 elf32-cr16c.c:781 elf32-crx.c:919 elf32-d10v.c:544
+#: elf32-h8300.c:502 elf32-m32r.c:3119 elf32-m68hc1x.c:1202 elf-m10200.c:435
+#: elf-m10300.c:1517
 msgid "internal error: dangerous error"
 msgstr ""
 
-#: elf32-arm.c:4222 elf32-avr.c:892 elf32-cr16c.c:785 elf32-cris.c:1514
+#: elf32-arm.c:4423 elf32-avr.c:892 elf32-cr16c.c:785 elf32-cris.c:1514
 #: elf32-crx.c:923 elf32-d10v.c:548 elf32-fr30.c:607 elf32-frv.c:4119
 #: elf32-h8300.c:506 elf32-i860.c:1201 elf32-ip2k.c:1489 elf32-iq2000.c:628
-#: elf32-m32c.c:412 elf32-m32r.c:3097 elf32-m68hc1x.c:1206 elf32-ms1.c:381
+#: elf32-m32c.c:477 elf32-m32r.c:3123 elf32-m68hc1x.c:1206 elf32-ms1.c:381
 #: elf32-msp430.c:520 elf32-openrisc.c:395 elf32-v850.c:1696
-#: elf32-xstormy16.c:921 elf64-mmix.c:1529 elf-m10200.c:439 elf-m10300.c:1541
+#: elf32-xstormy16.c:921 elf64-mmix.c:1529 elf-m10200.c:439 elf-m10300.c:1521
 msgid "internal error: unknown error"
 msgstr ""
 
-#: elf32-arm.c:4321
+#: elf32-arm.c:4664
 msgid ""
 "Warning: Clearing the interworking flag of %B because non-interworking code "
 "in %B has been linked with it"
 msgstr ""
 
-#: elf32-arm.c:4440
+#: elf32-arm.c:4751
+msgid "ERROR: %B uses VFP register arguments, %B does not"
+msgstr ""
+
+#: elf32-arm.c:4798
+msgid "ERROR: %B: Conflicting architecture profiles %c/%c"
+msgstr ""
+
+#: elf32-arm.c:4813
+msgid "Warning: %B: Conflicting platform configuration"
+msgstr ""
+
+#: elf32-arm.c:4821
+msgid "ERROR: %B: Conflicting use of R9"
+msgstr ""
+
+#: elf32-arm.c:4833
+msgid "ERROR: %B: SB relative addressing conflicts with use of R9"
+msgstr ""
+
+#: elf32-arm.c:4855
+msgid "ERROR: %B: Conflicting definitions of wchar_t"
+msgstr ""
+
+#: elf32-arm.c:4881
+msgid "ERROR: %B: Conflicting enum sizes"
+msgstr ""
+
+#: elf32-arm.c:4892
+msgid "ERROR: %B uses iWMMXt register arguments, %B does not"
+msgstr ""
+
+#: elf32-arm.c:4912
+msgid "ERROR: %B: Must be processed by '%s' toolchain"
+msgstr ""
+
+#: elf32-arm.c:4932 elf32-arm.c:4951
+msgid "ERROR: %B: Incompatible object tag '%s':%d"
+msgstr ""
+
+#: elf32-arm.c:4961
+msgid "Warning: %B: Unknown EABI object attribute %d"
+msgstr ""
+
+#: elf32-arm.c:5069
 msgid ""
 "ERROR: Source object %B has EABI version %d, but target %B has EABI version %"
 "d"
 msgstr ""
 
-#: elf32-arm.c:4453
+#: elf32-arm.c:5082
 msgid "ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"
 msgstr ""
 
-#: elf32-arm.c:4478
+#: elf32-arm.c:5107
 msgid "ERROR: %B uses VFP instructions, whereas %B does not"
 msgstr ""
 
-#: elf32-arm.c:4482
+#: elf32-arm.c:5111
 msgid "ERROR: %B uses FPA instructions, whereas %B does not"
 msgstr ""
 
-#: elf32-arm.c:4492
+#: elf32-arm.c:5121
 msgid "ERROR: %B uses Maverick instructions, whereas %B does not"
 msgstr ""
 
-#: elf32-arm.c:4496
+#: elf32-arm.c:5125
 msgid "ERROR: %B does not use Maverick instructions, whereas %B does"
 msgstr ""
 
-#: elf32-arm.c:4515
+#: elf32-arm.c:5144
 msgid "ERROR: %B uses software FP, whereas %B uses hardware FP"
 msgstr ""
 
-#: elf32-arm.c:4519
+#: elf32-arm.c:5148
 msgid "ERROR: %B uses hardware FP, whereas %B uses software FP"
 msgstr ""
 
 #. Ignore init flag - it may not be set, despite the flags field
 #. containing valid data.
 #. Ignore init flag - it may not be set, despite the flags field containing valid data.
-#: elf32-arm.c:4566 elf32-cris.c:3235 elf32-m68hc1x.c:1338 elf32-m68k.c:428
-#: elf32-vax.c:528 elfxx-mips.c:9903
+#: elf32-arm.c:5195 elf32-bfin.c:2164 elf32-cris.c:3243 elf32-m68hc1x.c:1338
+#: elf32-m68k.c:428 elf32-vax.c:528 elfxx-mips.c:9933
 #, c-format
 msgid "private flags = %lx:"
 msgstr ""
 
-#: elf32-arm.c:4575
+#: elf32-arm.c:5204
 #, c-format
 msgid " [interworking enabled]"
 msgstr ""
 
-#: elf32-arm.c:4583
+#: elf32-arm.c:5212
 #, c-format
 msgid " [VFP float format]"
 msgstr ""
 
-#: elf32-arm.c:4585
+#: elf32-arm.c:5214
 #, c-format
 msgid " [Maverick float format]"
 msgstr ""
 
-#: elf32-arm.c:4587
+#: elf32-arm.c:5216
 #, c-format
 msgid " [FPA float format]"
 msgstr ""
 
-#: elf32-arm.c:4596
+#: elf32-arm.c:5225
 #, c-format
 msgid " [new ABI]"
 msgstr ""
 
-#: elf32-arm.c:4599
+#: elf32-arm.c:5228
 #, c-format
 msgid " [old ABI]"
 msgstr ""
 
-#: elf32-arm.c:4602
+#: elf32-arm.c:5231
 #, c-format
 msgid " [software FP]"
 msgstr ""
 
-#: elf32-arm.c:4611
+#: elf32-arm.c:5240
 #, c-format
 msgid " [Version1 EABI]"
 msgstr ""
 
-#: elf32-arm.c:4614 elf32-arm.c:4625
+#: elf32-arm.c:5243 elf32-arm.c:5254
 #, c-format
 msgid " [sorted symbol table]"
 msgstr ""
 
-#: elf32-arm.c:4616 elf32-arm.c:4627
+#: elf32-arm.c:5245 elf32-arm.c:5256
 #, c-format
 msgid " [unsorted symbol table]"
 msgstr ""
 
-#: elf32-arm.c:4622
+#: elf32-arm.c:5251
 #, c-format
 msgid " [Version2 EABI]"
 msgstr ""
 
-#: elf32-arm.c:4630
+#: elf32-arm.c:5259
 #, c-format
 msgid " [dynamic symbols use segment index]"
 msgstr ""
 
-#: elf32-arm.c:4633
+#: elf32-arm.c:5262
 #, c-format
 msgid " [mapping symbols precede others]"
 msgstr ""
 
-#: elf32-arm.c:4640
+#: elf32-arm.c:5269
 #, c-format
 msgid " [Version3 EABI]"
 msgstr ""
 
-#: elf32-arm.c:4644
+#: elf32-arm.c:5273
 #, c-format
 msgid " [Version4 EABI]"
 msgstr ""
 
-#: elf32-arm.c:4647
+#: elf32-arm.c:5276
 #, c-format
 msgid " [BE8]"
 msgstr ""
 
-#: elf32-arm.c:4650
+#: elf32-arm.c:5279
 #, c-format
 msgid " [LE8]"
 msgstr ""
 
-#: elf32-arm.c:4656
+#: elf32-arm.c:5285
 #, c-format
 msgid " <EABI version unrecognised>"
 msgstr ""
 
-#: elf32-arm.c:4663
+#: elf32-arm.c:5292
 #, c-format
 msgid " [relocatable executable]"
 msgstr ""
 
-#: elf32-arm.c:4666
+#: elf32-arm.c:5295
 #, c-format
 msgid " [has entry point]"
 msgstr ""
 
-#: elf32-arm.c:4671
+#: elf32-arm.c:5300
 #, c-format
 msgid "<Unrecognised flag bits set>"
 msgstr ""
 
-#: elf32-arm.c:4907 elf32-i386.c:905 elf32-s390.c:992 elf32-xtensa.c:784
-#: elf64-s390.c:945 elf64-x86-64.c:662 elfxx-sparc.c:1019
+#: elf32-arm.c:5536 elf32-i386.c:902 elf32-s390.c:989 elf32-xtensa.c:784
+#: elf64-s390.c:942 elf64-x86-64.c:666 elfxx-sparc.c:1016
 msgid "%B: bad symbol index: %d"
 msgstr ""
 
+#: elf32-arm.c:6023 elf32-cris.c:2385 elf32-hppa.c:1813 elf32-i370.c:491
+#: elf32-i386.c:1465 elf32-m32r.c:1913 elf32-m68k.c:1088 elf32-ppc.c:4145
+#: elf32-s390.c:1686 elf32-sh.c:3920 elf32-vax.c:1059 elf64-ppc.c:5717
+#: elf64-s390.c:1659 elf64-sh64.c:3442 elf64-x86-64.c:1252 elf-m10300.c:4107
+#: elfxx-sparc.c:1720
+#, c-format
+msgid "dynamic variable `%s' is zero size"
+msgstr ""
+
 #: elf32-avr.c:888 elf32-cris.c:1510 elf32-fr30.c:603 elf32-frv.c:4115
-#: elf32-i860.c:1197 elf32-ip2k.c:1485 elf32-iq2000.c:624 elf32-m32c.c:408
+#: elf32-i860.c:1197 elf32-ip2k.c:1485 elf32-iq2000.c:624 elf32-m32c.c:473
 #: elf32-ms1.c:377 elf32-msp430.c:516 elf32-openrisc.c:391 elf32-v850.c:1680
 #: elf32-xstormy16.c:917 elf64-mmix.c:1525
 msgid "internal error: dangerous relocation"
 msgstr ""
 
+#: elf32-bfin.c:96
+msgid "Division by zero. "
+msgstr ""
+
+#: elf32-bfin.c:1958
+msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'"
+msgstr ""
+
+#: elf32-bfin.c:1991 elf32-i386.c:3079 elf32-m68k.c:1778 elf32-s390.c:3064
+#: elf64-s390.c:3062 elf64-x86-64.c:2567
+msgid "%B(%A+0x%lx): reloc against `%s': error %d"
+msgstr ""
+
 #: elf32-cris.c:1050
 msgid "%B, section %A: unresolvable relocation %s against symbol `%s'"
 msgstr ""
@@ -924,50 +977,50 @@ msgstr ""
 msgid "%B: Internal inconsistency; no relocation section %s"
 msgstr ""
 
-#: elf32-cris.c:2512
+#: elf32-cris.c:2520
 msgid ""
 "%B, section %A:\n"
 "  v10/v32 compatible object %s must not contain a PIC relocation"
 msgstr ""
 
-#: elf32-cris.c:2699 elf32-cris.c:2767
+#: elf32-cris.c:2707 elf32-cris.c:2775
 msgid ""
 "%B, section %A:\n"
 "  relocation %s should not be used in a shared object; recompile with -fPIC"
 msgstr ""
 
-#: elf32-cris.c:3184
+#: elf32-cris.c:3192
 msgid "Unexpected machine number"
 msgstr ""
 
-#: elf32-cris.c:3238
+#: elf32-cris.c:3246
 #, c-format
 msgid " [symbols have a _ prefix]"
 msgstr ""
 
-#: elf32-cris.c:3241
+#: elf32-cris.c:3249
 #, c-format
 msgid " [v10 and v32]"
 msgstr ""
 
-#: elf32-cris.c:3244
+#: elf32-cris.c:3252
 #, c-format
 msgid " [v32]"
 msgstr ""
 
-#: elf32-cris.c:3289
+#: elf32-cris.c:3297
 msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols"
 msgstr ""
 
-#: elf32-cris.c:3290
+#: elf32-cris.c:3298
 msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols"
 msgstr ""
 
-#: elf32-cris.c:3309
+#: elf32-cris.c:3317
 msgid "%B contains CRIS v32 code, incompatible with previous objects"
 msgstr ""
 
-#: elf32-cris.c:3311
+#: elf32-cris.c:3319
 msgid "%B contains non-CRIS-v32 code, incompatible with previous objects"
 msgstr ""
 
@@ -1055,39 +1108,39 @@ msgstr ""
 msgid "relocation references a different segment"
 msgstr ""
 
-#: elf32-frv.c:6345
+#: elf32-frv.c:6324
 msgid "%B: unsupported relocation type %i"
 msgstr ""
 
-#: elf32-frv.c:6663
+#: elf32-frv.c:6642
 #, c-format
 msgid ""
 "%s: compiled with %s and linked with modules that use non-pic relocations"
 msgstr ""
 
-#: elf32-frv.c:6716 elf32-iq2000.c:801 elf32-m32c.c:720
+#: elf32-frv.c:6695 elf32-iq2000.c:801 elf32-m32c.c:785
 #, c-format
 msgid "%s: compiled with %s and linked with modules compiled with %s"
 msgstr ""
 
-#: elf32-frv.c:6728
+#: elf32-frv.c:6707
 #, c-format
 msgid ""
 "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%"
 "lx)"
 msgstr ""
 
-#: elf32-frv.c:6749
+#: elf32-frv.c:6728
 #, c-format
 msgid "%s: cannot link non-fdpic object file into fdpic executable"
 msgstr ""
 
-#: elf32-frv.c:6753
+#: elf32-frv.c:6732
 #, c-format
 msgid "%s: cannot link fdpic object file into non-fdpic executable"
 msgstr ""
 
-#: elf32-frv.c:6778 elf32-iq2000.c:838 elf32-m32c.c:756 elf32-ms1.c:596
+#: elf32-frv.c:6757 elf32-iq2000.c:838 elf32-m32c.c:821 elf32-ms1.c:596
 #, c-format
 msgid "private flags = 0x%lx:"
 msgstr ""
@@ -1096,77 +1149,67 @@ msgstr ""
 msgid "%B: Relocations in generic ELF (EM: %d)"
 msgstr ""
 
-#: elf32-hppa.c:569 elf32-m68hc1x.c:161 elf64-ppc.c:3659
+#: elf32-hppa.c:569 elf32-m68hc1x.c:161 elf64-ppc.c:3660
 msgid "%B: cannot create stub entry %s"
 msgstr ""
 
-#: elf32-hppa.c:822 elf32-hppa.c:3403
+#: elf32-hppa.c:822 elf32-hppa.c:3411
 msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections"
 msgstr ""
 
-#: elf32-hppa.c:1213
+#: elf32-hppa.c:1212
 msgid ""
 "%B: relocation %s can not be used when making a shared object; recompile "
 "with -fPIC"
 msgstr ""
 
-#: elf32-hppa.c:1406
+#: elf32-hppa.c:1405
 #, c-format
 msgid "Could not find relocation section for %s"
 msgstr ""
 
-#: elf32-hppa.c:2669
+#: elf32-hppa.c:2677
 msgid "%B: duplicate export stub %s"
 msgstr ""
 
-#: elf32-hppa.c:3258
+#: elf32-hppa.c:3266
 msgid ""
 "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link"
 msgstr ""
 
-#: elf32-hppa.c:3887
+#: elf32-hppa.c:3895
 msgid "%B(%A+0x%lx): cannot handle %s for %s"
 msgstr ""
 
-#: elf32-hppa.c:4181
+#: elf32-hppa.c:4189
 msgid ".got section not immediately after .plt section"
 msgstr ""
 
-#: elf32-i386.c:327 elf32-s390.c:368 elf64-ppc.c:2123 elf64-s390.c:390
-#: elf64-x86-64.c:197
+#: elf32-i386.c:327 elf32-s390.c:368 elf64-ppc.c:2124 elf64-s390.c:390
+#: elf64-x86-64.c:204
 msgid "%B: invalid relocation type %d"
 msgstr ""
 
-#: elf32-i386.c:1018 elf32-s390.c:1174 elf32-sh.c:6389 elf64-s390.c:1136
-#: elfxx-sparc.c:1147
+#: elf32-i386.c:1015 elf32-s390.c:1171 elf32-sh.c:6389 elf64-s390.c:1133
+#: elfxx-sparc.c:1144
 msgid "%B: `%s' accessed both as normal and thread local symbol"
 msgstr ""
 
-#: elf32-i386.c:1133 elf32-s390.c:1283 elf64-ppc.c:4733 elf64-s390.c:1248
-#: elf64-x86-64.c:906
+#: elf32-i386.c:1130 elf32-s390.c:1280 elf64-ppc.c:4731 elf64-s390.c:1245
+#: elf64-x86-64.c:910
 msgid "%B: bad relocation section name `%s'"
 msgstr ""
 
-#: elf32-i386.c:2144
+#: elf32-i386.c:2149
 msgid "%B: unrecognized relocation (0x%x) in section `%A'"
 msgstr ""
 
-#: elf32-i386.c:2404
+#: elf32-i386.c:2409
 msgid ""
 "%B: relocation R_386_GOTOFF against protected function `%s' can not be used "
 "when making a shared object"
 msgstr ""
 
-#: elf32-i386.c:3033 elf32-m68k.c:1728 elf32-s390.c:3010 elf32-xtensa.c:2314
-#: elf64-s390.c:3007 elf64-x86-64.c:2508 elfxx-sparc.c:3134
-msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'"
-msgstr ""
-
-#: elf32-i386.c:3073 elf32-m68k.c:1768 elf32-s390.c:3061 elf64-s390.c:3058
-#: elf64-x86-64.c:2552
-msgid "%B(%A+0x%lx): reloc against `%s': error %d"
-msgstr ""
-
 #: elf32-ip2k.c:853 elf32-ip2k.c:859 elf32-ip2k.c:926 elf32-ip2k.c:932
 msgid ""
 "ip2k relaxer: switch table without complete matching relocation information."
@@ -1191,45 +1234,39 @@ msgstr ""
 msgid "unsupported relocation between data/insn address spaces"
 msgstr ""
 
-#: elf32-iq2000.c:814 elf32-m32c.c:732
+#: elf32-iq2000.c:814 elf32-m32c.c:797
 #, c-format
 msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr ""
 
-#: elf32-m32r.c:1421
+#: elf32-m32r.c:1436
 msgid "SDA relocation when _SDA_BASE_ not defined"
 msgstr ""
 
-#: elf32-m32r.c:2633 elf64-sh64.c:1626 elf-m10300.c:1483
-#, c-format
-msgid ""
-"%s: warning: unresolvable relocation against symbol `%s' from %s section"
-msgstr ""
-
-#: elf32-m32r.c:3022
+#: elf32-m32r.c:3048
 msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)"
 msgstr ""
 
-#: elf32-m32r.c:3550
+#: elf32-m32r.c:3576
 msgid "%B: Instruction set mismatch with previous modules"
 msgstr ""
 
-#: elf32-m32r.c:3571
+#: elf32-m32r.c:3597
 #, c-format
 msgid "private flags = %lx"
 msgstr ""
 
-#: elf32-m32r.c:3576
+#: elf32-m32r.c:3602
 #, c-format
 msgid ": m32r instructions"
 msgstr ""
 
-#: elf32-m32r.c:3577
+#: elf32-m32r.c:3603
 #, c-format
 msgid ": m32rx instructions"
 msgstr ""
 
-#: elf32-m32r.c:3578
+#: elf32-m32r.c:3604
 #, c-format
 msgid ": m32r2 instructions"
 msgstr ""
@@ -1271,7 +1308,7 @@ msgstr ""
 msgid "%B: linking files compiled for HCS12 with others compiled for HC12"
 msgstr ""
 
-#: elf32-m68hc1x.c:1313 elf32-ppc.c:3515 elf64-sparc.c:696 elfxx-mips.c:9864
+#: elf32-m68hc1x.c:1313 elf32-ppc.c:3576 elf64-sparc.c:696 elfxx-mips.c:9894
 msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr ""
 
@@ -1384,71 +1421,67 @@ msgstr ""
 msgid "failed to install new APUinfo section."
 msgstr ""
 
-#: elf32-ppc.c:2936
+#: elf32-ppc.c:2941
 msgid "%B: relocation %s cannot be used when making a shared object"
 msgstr ""
 
 #. It does not make sense to have a procedure linkage
 #. table entry for a local symbol.
-#: elf32-ppc.c:3152
+#: elf32-ppc.c:3211
 msgid "%B(%A+0x%lx): %s reloc against local symbol"
 msgstr ""
 
-#: elf32-ppc.c:3480
+#: elf32-ppc.c:3541
 msgid ""
 "%B: compiled with -mrelocatable and linked with modules compiled normally"
 msgstr ""
 
-#: elf32-ppc.c:3488
+#: elf32-ppc.c:3549
 msgid ""
 "%B: compiled normally and linked with modules compiled with -mrelocatable"
 msgstr ""
 
-#: elf32-ppc.c:5758 elf64-ppc.c:10129
+#: elf32-ppc.c:5768 elf64-ppc.c:10186
 msgid "%B: unknown relocation type %d for symbol %s"
 msgstr ""
 
-#: elf32-ppc.c:6008
+#: elf32-ppc.c:6018
 msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'"
 msgstr ""
 
-#: elf32-ppc.c:6354 elf32-ppc.c:6376 elf32-ppc.c:6425
+#: elf32-ppc.c:6365 elf32-ppc.c:6391 elf32-ppc.c:6450
 msgid ""
 "%B: the target (%s) of a %s relocation is in the wrong output section (%s)"
 msgstr ""
 
-#: elf32-ppc.c:6480
+#: elf32-ppc.c:6505
 msgid "%B: relocation %s is not yet supported for symbol %s."
 msgstr ""
 
-#: elf32-ppc.c:6536 elf64-ppc.c:10768
-msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"
-msgstr ""
-
-#: elf32-ppc.c:6585 elf64-ppc.c:10815
+#: elf32-ppc.c:6610 elf64-ppc.c:10872
 msgid "%B(%A+0x%lx): %s reloc against `%s': error %d"
 msgstr ""
 
-#: elf32-s390.c:2251 elf64-s390.c:2222
+#: elf32-s390.c:2253 elf64-s390.c:2225
 msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s"
 msgstr ""
 
-#: elf32-sh64.c:218 elf64-sh64.c:2319
+#: elf32-sh64.c:218 elf64-sh64.c:2322
 #, c-format
 msgid "%s: compiled as 32-bit object and %s is 64-bit"
 msgstr ""
 
-#: elf32-sh64.c:221 elf64-sh64.c:2322
+#: elf32-sh64.c:221 elf64-sh64.c:2325
 #, c-format
 msgid "%s: compiled as 64-bit object and %s is 32-bit"
 msgstr ""
 
-#: elf32-sh64.c:223 elf64-sh64.c:2324
+#: elf32-sh64.c:223 elf64-sh64.c:2327
 #, c-format
 msgid "%s: object size does not match that of target %s"
 msgstr ""
 
-#: elf32-sh64.c:446 elf64-sh64.c:2896
+#: elf32-sh64.c:446 elf64-sh64.c:2899
 #, c-format
 msgid "%s: encountered datalabel symbol in input"
 msgstr ""
@@ -1512,31 +1545,27 @@ msgstr ""
 msgid "%B: 0x%lx: fatal: reloc overflow while relaxing"
 msgstr ""
 
-#: elf32-sh.c:4559 elf64-sh64.c:1509
+#: elf32-sh.c:4566 elf64-sh64.c:1509
 msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
 msgstr ""
 
-#: elf32-sh.c:4710
-msgid "%B(%A): unresolvable relocation against symbol `%s'"
-msgstr ""
-
-#: elf32-sh.c:4780
+#: elf32-sh.c:4791
 msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation"
 msgstr ""
 
-#: elf32-sh.c:4813 elf32-sh.c:4828
+#: elf32-sh.c:4824 elf32-sh.c:4839
 msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx"
 msgstr ""
 
-#: elf32-sh.c:4842
+#: elf32-sh.c:4853
 msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32"
 msgstr ""
 
-#: elf32-sh.c:4856
+#: elf32-sh.c:4867
 msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32"
 msgstr ""
 
-#: elf32-sh.c:6600 elf64-alpha.c:4486
+#: elf32-sh.c:6601 elf64-alpha.c:4466
 msgid "%B: TLS local exec code cannot be linked into shared objects"
 msgstr ""
 
@@ -1652,22 +1681,22 @@ msgid ""
 "%ld"
 msgstr ""
 
-#: elf32-vax.c:1597
+#: elf32-vax.c:1604
 #, c-format
 msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
 msgstr ""
 
-#: elf32-vax.c:1721
+#: elf32-vax.c:1728
 #, c-format
 msgid "%s: warning: %s relocation against symbol `%s' from %s section"
 msgstr ""
 
-#: elf32-vax.c:1727
+#: elf32-vax.c:1734
 #, c-format
 msgid "%s: warning: %s relocation to 0x%x from %s section"
 msgstr ""
 
-#: elf32-xstormy16.c:425 elf32-ia64.c:2546 elf64-ia64.c:2546
+#: elf32-xstormy16.c:425 elf32-ia64.c:2563 elf64-ia64.c:2563
 msgid "non-zero addend in @fptr reloc"
 msgstr ""
 
@@ -1675,47 +1704,47 @@ msgstr ""
 msgid "%B(%A): invalid property table"
 msgstr ""
 
-#: elf32-xtensa.c:2202
+#: elf32-xtensa.c:2199
 msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)"
 msgstr ""
 
-#: elf32-xtensa.c:2259
+#: elf32-xtensa.c:2256
 msgid "dynamic relocation in read-only section"
 msgstr ""
 
-#: elf32-xtensa.c:2423
+#: elf32-xtensa.c:2421
 msgid "internal inconsistency in size of .got.loc section"
 msgstr ""
 
-#: elf32-xtensa.c:2737
+#: elf32-xtensa.c:2735
 msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x"
 msgstr ""
 
-#: elf32-xtensa.c:3883 elf32-xtensa.c:3891
+#: elf32-xtensa.c:3881 elf32-xtensa.c:3889
 msgid "Attempt to convert L32R/CALLX to CALL failed"
 msgstr ""
 
-#: elf32-xtensa.c:5469 elf32-xtensa.c:5545 elf32-xtensa.c:6498
-#: elf32-xtensa.c:6552
+#: elf32-xtensa.c:5467 elf32-xtensa.c:5543 elf32-xtensa.c:6496
+#: elf32-xtensa.c:6550
 msgid ""
 "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch"
 msgstr ""
 
-#: elf32-xtensa.c:6371 elf32-xtensa.c:6534
+#: elf32-xtensa.c:6369 elf32-xtensa.c:6532
 msgid ""
 "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY "
 "relocation; possible configuration mismatch"
 msgstr ""
 
-#: elf32-xtensa.c:7852
+#: elf32-xtensa.c:7855
 msgid "invalid relocation address"
 msgstr ""
 
-#: elf32-xtensa.c:7901
+#: elf32-xtensa.c:7904
 msgid "overflow after relaxation"
 msgstr ""
 
-#: elf32-xtensa.c:9029
+#: elf32-xtensa.c:9032
 msgid "%B(%A+0x%lx): unexpected fix for %s relocation"
 msgstr ""
 
@@ -1723,43 +1752,43 @@ msgstr ""
 msgid "GPDISP relocation did not find ldah and lda instructions"
 msgstr ""
 
-#: elf64-alpha.c:2383
+#: elf64-alpha.c:2363
 msgid "%B: .got subsegment exceeds 64K (size %d)"
 msgstr ""
 
-#: elf64-alpha.c:4230 elf64-alpha.c:4242
+#: elf64-alpha.c:4210 elf64-alpha.c:4222
 msgid "%B: gp-relative relocation against dynamic symbol %s"
 msgstr ""
 
-#: elf64-alpha.c:4268 elf64-alpha.c:4403
+#: elf64-alpha.c:4248 elf64-alpha.c:4383
 msgid "%B: pc-relative relocation against dynamic symbol %s"
 msgstr ""
 
-#: elf64-alpha.c:4296
+#: elf64-alpha.c:4276
 msgid "%B: change in gp: BRSGP %s"
 msgstr ""
 
-#: elf64-alpha.c:4321
+#: elf64-alpha.c:4301
 msgid "<unknown>"
 msgstr ""
 
-#: elf64-alpha.c:4326
+#: elf64-alpha.c:4306
 msgid "%B: !samegp reloc against symbol without .prologue: %s"
 msgstr ""
 
-#: elf64-alpha.c:4378
+#: elf64-alpha.c:4358
 msgid "%B: unhandled dynamic relocation against %s"
 msgstr ""
 
-#: elf64-alpha.c:4410
+#: elf64-alpha.c:4390
 msgid "%B: pc-relative relocation against undefined weak symbol %s"
 msgstr ""
 
-#: elf64-alpha.c:4470
+#: elf64-alpha.c:4450
 msgid "%B: dtp-relative relocation against dynamic symbol %s"
 msgstr ""
 
-#: elf64-alpha.c:4493
+#: elf64-alpha.c:4473
 msgid "%B: tp-relative relocation against dynamic symbol %s"
 msgstr ""
 
@@ -1809,29 +1838,29 @@ msgid ""
 "register is $%ld."
 msgstr ""
 
-#: elf64-mmix.c:2204
+#: elf64-mmix.c:2207
 #, c-format
 msgid ""
 "%s: Error: multiple definition of `%s'; start of %s is set in a earlier "
 "linked file\n"
 msgstr ""
 
-#: elf64-mmix.c:2262
+#: elf64-mmix.c:2265
 msgid "Register section has contents\n"
 msgstr ""
 
-#: elf64-mmix.c:2451
+#: elf64-mmix.c:2457
 #, c-format
 msgid ""
 "Internal inconsistency: remaining %u != max %u.\n"
 "  Please report this bug."
 msgstr ""
 
-#: elf64-ppc.c:2499 libbfd.c:928
+#: elf64-ppc.c:2500 libbfd.c:931
 msgid "%B: compiled for a big endian system and target is little endian"
 msgstr ""
 
-#: elf64-ppc.c:2502 libbfd.c:930
+#: elf64-ppc.c:2503 libbfd.c:933
 msgid "%B: compiled for a little endian system and target is big endian"
 msgstr ""
 
@@ -1842,51 +1871,60 @@ msgid ""
 "LD_BIND_NOW=1 or upgrade gcc"
 msgstr ""
 
-#: elf64-ppc.c:6133
+#: elf64-ppc.c:6155
 msgid "dynreloc miscount for %B, section %A"
 msgstr ""
 
-#: elf64-ppc.c:6235
+#: elf64-ppc.c:6257
 msgid "%B: .opd is not a regular array of opd entries"
 msgstr ""
 
-#: elf64-ppc.c:6244
+#: elf64-ppc.c:6266
 msgid "%B: unexpected reloc type %u in .opd section"
 msgstr ""
 
-#: elf64-ppc.c:6265
+#: elf64-ppc.c:6287
 msgid "%B: undefined sym `%s' in .opd section"
 msgstr ""
 
-#: elf64-ppc.c:6915 elf64-ppc.c:7294
+#: elf64-ppc.c:6939 elf64-ppc.c:7318
 #, c-format
 msgid "%s defined in removed toc entry"
 msgstr ""
 
-#: elf64-ppc.c:8081
+#: elf64-ppc.c:8041
+#, c-format
+msgid "long branch stub `%s' offset overflow"
+msgstr ""
+
+#: elf64-ppc.c:8116
 #, c-format
 msgid "can't find branch stub `%s'"
 msgstr ""
 
-#: elf64-ppc.c:8120 elf64-ppc.c:8196
+#: elf64-ppc.c:8155 elf64-ppc.c:8231
 #, c-format
 msgid "linkage table error against `%s'"
 msgstr ""
 
-#: elf64-ppc.c:8325
+#: elf64-ppc.c:8360
 #, c-format
 msgid "can't build branch stub `%s'"
 msgstr ""
 
-#: elf64-ppc.c:9253
+#: elf64-ppc.c:8784
+msgid "%B section %A exceeds stub group size"
+msgstr ""
+
+#: elf64-ppc.c:9295
 msgid ".glink and .plt too far apart"
 msgstr ""
 
-#: elf64-ppc.c:9366
+#: elf64-ppc.c:9408
 msgid "stubs don't match calculated size"
 msgstr ""
 
-#: elf64-ppc.c:9378
+#: elf64-ppc.c:9420
 #, c-format
 msgid ""
 "linker stubs in %u group%s\n"
@@ -1897,28 +1935,28 @@ msgid ""
 "  plt call     %lu"
 msgstr ""
 
-#: elf64-ppc.c:10018
+#: elf64-ppc.c:10075
 msgid ""
 "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; "
 "recompile with -mminimal-toc or upgrade gcc"
 msgstr ""
 
-#: elf64-ppc.c:10026
+#: elf64-ppc.c:10083
 msgid ""
 "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic "
 "multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, "
 "or make `%s' extern"
 msgstr ""
 
-#: elf64-ppc.c:10670
+#: elf64-ppc.c:10727
 msgid "%B: relocation %s is not supported for symbol %s."
 msgstr ""
 
-#: elf64-ppc.c:10749
+#: elf64-ppc.c:10806
 msgid "%B: error: relocation %s not a multiple of %d"
 msgstr ""
 
-#: elf64-sh64.c:1673
+#: elf64-sh64.c:1676
 #, c-format
 msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n"
 msgstr ""
@@ -1943,23 +1981,23 @@ msgstr ""
 msgid "%B: linking UltraSPARC specific with HAL specific code"
 msgstr ""
 
-#: elf64-x86-64.c:688 elf64-x86-64.c:814 elf64-x86-64.c:2055
+#: elf64-x86-64.c:692 elf64-x86-64.c:818 elf64-x86-64.c:2069
 msgid ""
 "%B: relocation %s against `%s' can not be used when making a shared object; "
 "recompile with -fPIC"
 msgstr ""
 
-#: elf64-x86-64.c:756
+#: elf64-x86-64.c:760
 msgid "%B: %s' accessed both as normal and thread local symbol"
 msgstr ""
 
-#: elf64-x86-64.c:1986
+#: elf64-x86-64.c:2000
 msgid ""
 "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be "
 "used when making a shared object"
 msgstr ""
 
-#: elf64-x86-64.c:2051
+#: elf64-x86-64.c:2065
 msgid ""
 "%B: relocation R_X86_64_PC32 against protected function `%s' can not be used "
 "when making a shared object"
@@ -1977,91 +2015,91 @@ msgstr ""
 msgid "%B: no group info for section %A"
 msgstr ""
 
-#: elf.c:659
+#: elf.c:652 elf.c:3091 elflink.c:7588
+msgid "%B: warning: sh_link not set for section `%A'"
+msgstr ""
+
+#: elf.c:688
 msgid "%B: unknown [%d] section `%s' in group [%s]"
 msgstr ""
 
-#: elf.c:1042
+#: elf.c:1071
 #, c-format
 msgid ""
 "\n"
 "Program Header:\n"
 msgstr ""
 
-#: elf.c:1094
+#: elf.c:1123
 #, c-format
 msgid ""
 "\n"
 "Dynamic Section:\n"
 msgstr ""
 
-#: elf.c:1219
+#: elf.c:1248
 #, c-format
 msgid ""
 "\n"
 "Version definitions:\n"
 msgstr ""
 
-#: elf.c:1244
+#: elf.c:1273
 #, c-format
 msgid ""
 "\n"
 "Version References:\n"
 msgstr ""
 
-#: elf.c:1249
+#: elf.c:1278
 #, c-format
 msgid "  required from %s:\n"
 msgstr ""
 
-#: elf.c:1958
+#: elf.c:1985
 msgid "%B: invalid link %lu for reloc section %s (index %u)"
 msgstr ""
 
-#: elf.c:3095 elflink.c:7621
-msgid "%B: warning: sh_link not set for section `%A'"
-msgstr ""
-
-#: elf.c:3105
+#: elf.c:3062
 msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'"
 msgstr ""
 
-#: elf.c:4103
+#: elf.c:4070
 msgid "%B: Not enough room for program headers (allocated %u, need %u)"
 msgstr ""
 
-#: elf.c:4206
+#: elf.c:4173
 msgid ""
 "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section"
 msgstr ""
 
-#: elf.c:4250
+#: elf.c:4217
 msgid "%B: Not enough room for program headers, try linking with -N"
 msgstr ""
 
-#: elf.c:4341
+#: elf.c:4308
 msgid "%B: section %A lma 0x%lx overlaps previous sections"
 msgstr ""
 
-#: elf.c:4742
+#: elf.c:4709
 msgid "%B: warning: allocated section `%s' not in segment"
 msgstr ""
 
-#: elf.c:5035
+#: elf.c:5002
 msgid "%B: symbol `%s' required but not present"
 msgstr ""
 
-#: elf.c:5332
+#: elf.c:5299
 msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n"
 msgstr ""
 
-#: elf.c:5950
+#: elf.c:5961
 #, c-format
 msgid ""
 "Unable to find equivalent output section for symbol '%s' from section '%s'"
 msgstr ""
 
-#: elf.c:6906
+#: elf.c:6917
 msgid "%B: unsupported relocation type %s"
 msgstr ""
 
@@ -2075,143 +2113,147 @@ msgstr ""
 msgid "%s(%s): relocation %d has invalid symbol index %ld"
 msgstr ""
 
-#: elf-hppa.h:1401 elf-hppa.h:1427 elf-hppa.h:1442
+#: elf-hppa.h:1443 elf-hppa.h:1458
 msgid "%B(%A): warning: unresolvable relocation against symbol `%s'"
 msgstr ""
 
-#: elflink.c:942
+#: elflink.c:907
 msgid ""
 "%s: TLS definition in %B section %A mismatches non-TLS definition in %B "
 "section %A"
 msgstr ""
 
-#: elflink.c:946
+#: elflink.c:911
 msgid "%s: TLS reference in %B mismatches non-TLS reference in %B"
 msgstr ""
 
-#: elflink.c:950
+#: elflink.c:915
 msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B"
 msgstr ""
 
-#: elflink.c:954
+#: elflink.c:919
 msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A"
 msgstr ""
 
-#: elflink.c:1513
+#: elflink.c:1491
 msgid "%B: unexpected redefinition of indirect versioned symbol `%s'"
 msgstr ""
 
-#: elflink.c:1829
+#: elflink.c:1807
 msgid "%B: undefined versioned symbol name %s"
 msgstr ""
 
-#: elflink.c:1977
+#: elflink.c:1955
 msgid ""
 "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'"
 msgstr ""
 
-#: elflink.c:2169
+#: elflink.c:2147
 msgid "%B: relocation size mismatch in %B section %A"
 msgstr ""
 
-#: elflink.c:2459
+#: elflink.c:2437
 #, c-format
 msgid "warning: type and size of dynamic symbol `%s' are not defined"
 msgstr ""
 
-#: elflink.c:2780
+#: elflink.c:2761
 msgid "warning: creating a DT_TEXTREL in a shared object."
 msgstr ""
 
-#: elflink.c:3714
+#: elflink.c:3696
 msgid "%B: %s: invalid version %u (max %d)"
 msgstr ""
 
-#: elflink.c:3750
+#: elflink.c:3732
 msgid "%B: %s: invalid needed version %d"
 msgstr ""
 
-#: elflink.c:3931
+#: elflink.c:3912
 msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B"
 msgstr ""
 
-#: elflink.c:3943
+#: elflink.c:3924
 msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B"
 msgstr ""
 
-#: elflink.c:4110
+#: elflink.c:4091
 #, c-format
 msgid "%s: invalid DSO for symbol `%s' definition"
 msgstr ""
 
-#: elflink.c:5170
+#: elflink.c:5152
 #, c-format
 msgid "%s: undefined version: %s"
 msgstr ""
 
-#: elflink.c:5236
+#: elflink.c:5219
 msgid "%B: .preinit_array section is not allowed in DSO"
 msgstr ""
 
-#: elflink.c:5993
+#: elflink.c:5978
 msgid "Not enough memory to sort relocations"
 msgstr ""
 
-#: elflink.c:6384
+#: elflink.c:6369
 msgid "%B: %s symbol `%s' in %B is referenced by DSO"
 msgstr ""
 
-#: elflink.c:6467
+#: elflink.c:6452
 msgid "%B: could not find output section %A for input section %A"
 msgstr ""
 
-#: elflink.c:6564
+#: elflink.c:6549
 msgid "%B: %s symbol `%s' isn't defined"
 msgstr ""
 
-#: elflink.c:7057
+#: elflink.c:7024
 msgid ""
 "error: %B contains a reloc (0x%s) for section %A that references a non-"
 "existent global symbol"
 msgstr ""
 
-#: elflink.c:7091
+#: elflink.c:7058
 msgid ""
 "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' "
-"of %B"
+"of %B\n"
+msgstr ""
+
+#: elflink.c:7665
+msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections"
 msgstr ""
 
-#: elflink.c:7694
+#: elflink.c:7670
 #, c-format
 msgid "%A has both ordered and unordered sections"
 msgstr ""
 
-#: elflink.c:8507 elflink.c:8548
+#: elflink.c:8487 elflink.c:8528
 msgid "%B: could not find output section %s"
 msgstr ""
 
-#: elflink.c:8512
+#: elflink.c:8492
 #, c-format
 msgid "warning: %s section has zero size"
 msgstr ""
 
-#: elflink.c:9128
+#: elflink.c:9087
 msgid "Warning: gc-sections option ignored"
 msgstr ""
 
-#: elflink.c:9708
+#: elflink.c:9704
 msgid "%B: ignoring duplicate section `%A'"
 msgstr ""
 
-#: elflink.c:9715 elflink.c:9722
+#: elflink.c:9711 elflink.c:9718
 msgid "%B: duplicate section `%A' has different size"
 msgstr ""
 
-#: elflink.c:9730 elflink.c:9735
+#: elflink.c:9726 elflink.c:9731
 msgid "%B: warning: could not read contents of section `%A'"
 msgstr ""
 
-#: elflink.c:9739
+#: elflink.c:9735
 msgid "%B: warning: duplicate section `%A' has different contents"
 msgstr ""
 
@@ -2231,149 +2273,149 @@ msgstr ""
 msgid "%B: Warning: bad `%s' option size %u smaller than its header"
 msgstr ""
 
-#: elfxx-mips.c:5951
+#: elfxx-mips.c:5965
 msgid "%B: Malformed reloc detected for section %s"
 msgstr ""
 
-#: elfxx-mips.c:6027
+#: elfxx-mips.c:6041
 msgid "%B: CALL16 reloc at 0x%lx not against global symbol"
 msgstr ""
 
-#: elfxx-mips.c:9365
+#: elfxx-mips.c:9380
 #, c-format
 msgid "%s: illegal section name `%s'"
 msgstr ""
 
-#: elfxx-mips.c:9689
+#: elfxx-mips.c:9719
 msgid "%B: endianness incompatible with that of the selected emulation"
 msgstr ""
 
-#: elfxx-mips.c:9701
+#: elfxx-mips.c:9731
 msgid "%B: ABI is incompatible with that of the selected emulation"
 msgstr ""
 
-#: elfxx-mips.c:9773
+#: elfxx-mips.c:9803
 msgid "%B: warning: linking PIC files with non-PIC files"
 msgstr ""
 
-#: elfxx-mips.c:9790
+#: elfxx-mips.c:9820
 msgid "%B: linking 32-bit code with 64-bit code"
 msgstr ""
 
-#: elfxx-mips.c:9818
+#: elfxx-mips.c:9848
 msgid "%B: linking %s module with previous %s modules"
 msgstr ""
 
-#: elfxx-mips.c:9841
+#: elfxx-mips.c:9871
 msgid "%B: ABI mismatch: linking %s module with previous %s modules"
 msgstr ""
 
-#: elfxx-mips.c:9906
+#: elfxx-mips.c:9936
 #, c-format
 msgid " [abi=O32]"
 msgstr ""
 
-#: elfxx-mips.c:9908
+#: elfxx-mips.c:9938
 #, c-format
 msgid " [abi=O64]"
 msgstr ""
 
-#: elfxx-mips.c:9910
+#: elfxx-mips.c:9940
 #, c-format
 msgid " [abi=EABI32]"
 msgstr ""
 
-#: elfxx-mips.c:9912
+#: elfxx-mips.c:9942
 #, c-format
 msgid " [abi=EABI64]"
 msgstr ""
 
-#: elfxx-mips.c:9914
+#: elfxx-mips.c:9944
 #, c-format
 msgid " [abi unknown]"
 msgstr ""
 
-#: elfxx-mips.c:9916
+#: elfxx-mips.c:9946
 #, c-format
 msgid " [abi=N32]"
 msgstr ""
 
-#: elfxx-mips.c:9918
+#: elfxx-mips.c:9948
 #, c-format
 msgid " [abi=64]"
 msgstr ""
 
-#: elfxx-mips.c:9920
+#: elfxx-mips.c:9950
 #, c-format
 msgid " [no abi set]"
 msgstr ""
 
-#: elfxx-mips.c:9923
+#: elfxx-mips.c:9953
 #, c-format
 msgid " [mips1]"
 msgstr ""
 
-#: elfxx-mips.c:9925
+#: elfxx-mips.c:9955
 #, c-format
 msgid " [mips2]"
 msgstr ""
 
-#: elfxx-mips.c:9927
+#: elfxx-mips.c:9957
 #, c-format
 msgid " [mips3]"
 msgstr ""
 
-#: elfxx-mips.c:9929
+#: elfxx-mips.c:9959
 #, c-format
 msgid " [mips4]"
 msgstr ""
 
-#: elfxx-mips.c:9931
+#: elfxx-mips.c:9961
 #, c-format
 msgid " [mips5]"
 msgstr ""
 
-#: elfxx-mips.c:9933
+#: elfxx-mips.c:9963
 #, c-format
 msgid " [mips32]"
 msgstr ""
 
-#: elfxx-mips.c:9935
+#: elfxx-mips.c:9965
 #, c-format
 msgid " [mips64]"
 msgstr ""
 
-#: elfxx-mips.c:9937
+#: elfxx-mips.c:9967
 #, c-format
 msgid " [mips32r2]"
 msgstr ""
 
-#: elfxx-mips.c:9939
+#: elfxx-mips.c:9969
 #, c-format
 msgid " [mips64r2]"
 msgstr ""
 
-#: elfxx-mips.c:9941
+#: elfxx-mips.c:9971
 #, c-format
 msgid " [unknown ISA]"
 msgstr ""
 
-#: elfxx-mips.c:9944
+#: elfxx-mips.c:9974
 #, c-format
 msgid " [mdmx]"
 msgstr ""
 
-#: elfxx-mips.c:9947
+#: elfxx-mips.c:9977
 #, c-format
 msgid " [mips16]"
 msgstr ""
 
-#: elfxx-mips.c:9950
+#: elfxx-mips.c:9980
 #, c-format
 msgid " [32bitmode]"
 msgstr ""
 
-#: elfxx-mips.c:9952
+#: elfxx-mips.c:9982
 #, c-format
 msgid " [not 32bitmode]"
 msgstr ""
@@ -2383,7 +2425,7 @@ msgstr ""
 msgid "invalid relocation type %d"
 msgstr ""
 
-#: elfxx-sparc.c:2780
+#: elfxx-sparc.c:2783
 msgid "%B: probably compiled without -fPIC?"
 msgstr ""
 
@@ -2470,12 +2512,12 @@ msgstr ""
 msgid "%s: address 0x%s out of range for Intel Hex file"
 msgstr ""
 
-#: libbfd.c:958
+#: libbfd.c:961
 #, c-format
 msgid "Deprecated %s called at %s line %d in %s\n"
 msgstr ""
 
-#: libbfd.c:961
+#: libbfd.c:964
 #, c-format
 msgid "Deprecated %s called\n"
 msgstr ""
@@ -2484,16 +2526,16 @@ msgstr ""
 msgid "%B: indirect symbol `%s' to `%s' is a loop"
 msgstr ""
 
-#: linker.c:2743
+#: linker.c:2740
 #, c-format
 msgid "Attempt to do relocatable link with %s input and %s output"
 msgstr ""
 
-#: linker.c:3040
+#: linker.c:3037
 msgid "%B: warning: ignoring duplicate section `%A'\n"
 msgstr ""
 
-#: linker.c:3054
+#: linker.c:3051
 msgid "%B: warning: duplicate section `%A' has different size\n"
 msgstr ""
 
@@ -2580,71 +2622,71 @@ msgid ""
 "%s: invalid mmo file: file name for number %d was not specified before use\n"
 msgstr ""
 
-#: mmo.c:1891
+#: mmo.c:1892
 #, c-format
 msgid ""
 "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n"
 msgstr ""
 
-#: mmo.c:1927
+#: mmo.c:1928
 #, c-format
 msgid "%s: invalid mmo file: lop_end not last item in file\n"
 msgstr ""
 
-#: mmo.c:1940
+#: mmo.c:1941
 #, c-format
 msgid ""
 "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras "
 "to the preceding lop_stab (%ld)\n"
 msgstr ""
 
-#: mmo.c:2647
+#: mmo.c:2649
 #, c-format
 msgid "%s: invalid symbol table: duplicate symbol `%s'\n"
 msgstr ""
 
-#: mmo.c:2890
+#: mmo.c:2892
 #, c-format
 msgid ""
 "%s: Bad symbol definition: `Main' set to %s rather than the start address %"
 "s\n"
 msgstr ""
 
-#: mmo.c:2982
+#: mmo.c:2984
 #, c-format
 msgid ""
 "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: "
 "%d.  Only `Main' will be emitted.\n"
 msgstr ""
 
-#: mmo.c:3027
+#: mmo.c:3029
 #, c-format
 msgid "%s: internal error, symbol table changed size from %d to %d words\n"
 msgstr ""
 
-#: mmo.c:3079
+#: mmo.c:3081
 #, c-format
 msgid "%s: internal error, internal register section %s had contents\n"
 msgstr ""
 
-#: mmo.c:3130
+#: mmo.c:3132
 #, c-format
 msgid "%s: no initialized registers; section length 0\n"
 msgstr ""
 
-#: mmo.c:3136
+#: mmo.c:3138
 #, c-format
 msgid "%s: too many initialized registers; section length %ld\n"
 msgstr ""
 
-#: mmo.c:3141
+#: mmo.c:3143
 #, c-format
 msgid ""
 "%s: invalid start address for initialized registers of length %ld: 0x%lx%"
 "08lx\n"
 msgstr ""
 
-#: oasys.c:874
+#: oasys.c:876
 #, c-format
 msgid "%s: can not represent section `%s' in oasys"
 msgstr ""
@@ -3019,77 +3061,77 @@ msgstr ""
 msgid "%s: `%s' in loader reloc but not loader sym"
 msgstr ""
 
-#: elf32-ia64.c:1138 elf64-ia64.c:1138
+#: elf32-ia64.c:1139 elf64-ia64.c:1139
 msgid ""
 "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect "
 "branch."
 msgstr ""
 
-#: elf32-ia64.c:2491 elf64-ia64.c:2491
+#: elf32-ia64.c:2508 elf64-ia64.c:2508
 msgid "@pltoff reloc against local symbol"
 msgstr ""
 
-#: elf32-ia64.c:3932 elf64-ia64.c:3932
+#: elf32-ia64.c:3955 elf64-ia64.c:3955
 #, c-format
 msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
 msgstr ""
 
-#: elf32-ia64.c:3943 elf64-ia64.c:3943
+#: elf32-ia64.c:3966 elf64-ia64.c:3966
 #, c-format
 msgid "%s: __gp does not cover short data segment"
 msgstr ""
 
-#: elf32-ia64.c:4190 elf64-ia64.c:4190
+#: elf32-ia64.c:4213 elf64-ia64.c:4213
 msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'"
 msgstr ""
 
-#: elf32-ia64.c:4257 elf64-ia64.c:4257
+#: elf32-ia64.c:4280 elf64-ia64.c:4280
 msgid "%B: @gprel relocation against dynamic symbol %s"
 msgstr ""
 
-#: elf32-ia64.c:4320 elf64-ia64.c:4320
+#: elf32-ia64.c:4343 elf64-ia64.c:4343
 msgid "%B: linking non-pic code in a position independent executable"
 msgstr ""
 
-#: elf32-ia64.c:4457 elf64-ia64.c:4457
+#: elf32-ia64.c:4480 elf64-ia64.c:4480
 msgid "%B: @internal branch to dynamic symbol %s"
 msgstr ""
 
-#: elf32-ia64.c:4459 elf64-ia64.c:4459
+#: elf32-ia64.c:4482 elf64-ia64.c:4482
 msgid "%B: speculation fixup to dynamic symbol %s"
 msgstr ""
 
-#: elf32-ia64.c:4461 elf64-ia64.c:4461
+#: elf32-ia64.c:4484 elf64-ia64.c:4484
 msgid "%B: @pcrel relocation against dynamic symbol %s"
 msgstr ""
 
-#: elf32-ia64.c:4668 elf64-ia64.c:4668
+#: elf32-ia64.c:4691 elf64-ia64.c:4691
 msgid "unsupported reloc"
 msgstr ""
 
-#: elf32-ia64.c:4701 elf64-ia64.c:4701
+#: elf32-ia64.c:4724 elf64-ia64.c:4724
 msgid ""
 "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> "
 "0x1000000)."
 msgstr ""
 
-#: elf32-ia64.c:4962 elf64-ia64.c:4962
+#: elf32-ia64.c:4985 elf64-ia64.c:4985
 msgid "%B: linking trap-on-NULL-dereference with non-trapping files"
 msgstr ""
 
-#: elf32-ia64.c:4971 elf64-ia64.c:4971
+#: elf32-ia64.c:4994 elf64-ia64.c:4994
 msgid "%B: linking big-endian files with little-endian files"
 msgstr ""
 
-#: elf32-ia64.c:4980 elf64-ia64.c:4980
+#: elf32-ia64.c:5003 elf64-ia64.c:5003
 msgid "%B: linking 64-bit files with 32-bit files"
 msgstr ""
 
-#: elf32-ia64.c:4989 elf64-ia64.c:4989
+#: elf32-ia64.c:5012 elf64-ia64.c:5012
 msgid "%B: linking constant-gp files with non-constant-gp files"
 msgstr ""
 
-#: elf32-ia64.c:4999 elf64-ia64.c:4999
+#: elf32-ia64.c:5022 elf64-ia64.c:5022
 msgid "%B: linking auto-pic files with non-auto-pic files"
 msgstr ""
 
@@ -3224,21 +3266,28 @@ msgid ""
 "There is a first thunk, but the section containing it could not be found\n"
 msgstr ""
 
-#: peigen.c:1368 pepigen.c:1368
+#: peigen.c:1365 pepigen.c:1365
 #, c-format
 msgid ""
 "\n"
 "There is an export table, but the section containing it could not be found\n"
 msgstr ""
 
-#: peigen.c:1373 pepigen.c:1373
+#: peigen.c:1374 pepigen.c:1374
+#, c-format
+msgid ""
+"\n"
+"There is an export table in %s, but it does not fit into that section\n"
+msgstr ""
+
+#: peigen.c:1380 pepigen.c:1380
 #, c-format
 msgid ""
 "\n"
 "There is an export table in %s at 0x%lx\n"
 msgstr ""
 
-#: peigen.c:1404 pepigen.c:1404
+#: peigen.c:1408 pepigen.c:1408
 #, c-format
 msgid ""
 "\n"
@@ -3246,128 +3295,128 @@ msgid ""
 "\n"
 msgstr ""
 
-#: peigen.c:1408 pepigen.c:1408
+#: peigen.c:1412 pepigen.c:1412
 #, c-format
 msgid "Export Flags \t\t\t%lx\n"
 msgstr ""
 
-#: peigen.c:1411 pepigen.c:1411
+#: peigen.c:1415 pepigen.c:1415
 #, c-format
 msgid "Time/Date stamp \t\t%lx\n"
 msgstr ""
 
-#: peigen.c:1414 pepigen.c:1414
+#: peigen.c:1418 pepigen.c:1418
 #, c-format
 msgid "Major/Minor \t\t\t%d/%d\n"
 msgstr ""
 
-#: peigen.c:1417 pepigen.c:1417
+#: peigen.c:1421 pepigen.c:1421
 #, c-format
 msgid "Name \t\t\t\t"
 msgstr ""
 
-#: peigen.c:1423 pepigen.c:1423
+#: peigen.c:1427 pepigen.c:1427
 #, c-format
 msgid "Ordinal Base \t\t\t%ld\n"
 msgstr ""
 
-#: peigen.c:1426 pepigen.c:1426
+#: peigen.c:1430 pepigen.c:1430
 #, c-format
 msgid "Number in:\n"
 msgstr ""
 
-#: peigen.c:1429 pepigen.c:1429
+#: peigen.c:1433 pepigen.c:1433
 #, c-format
 msgid "\tExport Address Table \t\t%08lx\n"
 msgstr ""
 
-#: peigen.c:1433 pepigen.c:1433
+#: peigen.c:1437 pepigen.c:1437
 #, c-format
 msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n"
 msgstr ""
 
-#: peigen.c:1436 pepigen.c:1436
+#: peigen.c:1440 pepigen.c:1440
 #, c-format
 msgid "Table Addresses\n"
 msgstr ""
 
-#: peigen.c:1439 pepigen.c:1439
+#: peigen.c:1443 pepigen.c:1443
 #, c-format
 msgid "\tExport Address Table \t\t"
 msgstr ""
 
-#: peigen.c:1444 pepigen.c:1444
+#: peigen.c:1448 pepigen.c:1448
 #, c-format
 msgid "\tName Pointer Table \t\t"
 msgstr ""
 
-#: peigen.c:1449 pepigen.c:1449
+#: peigen.c:1453 pepigen.c:1453
 #, c-format
 msgid "\tOrdinal Table \t\t\t"
 msgstr ""
 
-#: peigen.c:1463 pepigen.c:1463
+#: peigen.c:1467 pepigen.c:1467
 #, c-format
 msgid ""
 "\n"
 "Export Address Table -- Ordinal Base %ld\n"
 msgstr ""
 
-#: peigen.c:1482 pepigen.c:1482
+#: peigen.c:1486 pepigen.c:1486
 msgid "Forwarder RVA"
 msgstr ""
 
-#: peigen.c:1493 pepigen.c:1493
+#: peigen.c:1497 pepigen.c:1497
 msgid "Export RVA"
 msgstr ""
 
-#: peigen.c:1500 pepigen.c:1500
+#: peigen.c:1504 pepigen.c:1504
 #, c-format
 msgid ""
 "\n"
 "[Ordinal/Name Pointer] Table\n"
 msgstr ""
 
-#: peigen.c:1553 pepigen.c:1553
+#: peigen.c:1557 pepigen.c:1557
 #, c-format
 msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n"
 msgstr ""
 
-#: peigen.c:1557 pepigen.c:1557
+#: peigen.c:1561 pepigen.c:1561
 #, c-format
 msgid ""
 "\n"
 "The Function Table (interpreted .pdata section contents)\n"
 msgstr ""
 
-#: peigen.c:1560 pepigen.c:1560
+#: peigen.c:1564 pepigen.c:1564
 #, c-format
 msgid " vma:\t\t\tBegin Address    End Address      Unwind Info\n"
 msgstr ""
 
-#: peigen.c:1562 pepigen.c:1562
+#: peigen.c:1566 pepigen.c:1566
 #, c-format
 msgid ""
 " vma:\t\tBegin    End      EH       EH       PrologEnd  Exception\n"
 "     \t\tAddress  Address  Handler  Data     Address    Mask\n"
 msgstr ""
 
-#: peigen.c:1632 pepigen.c:1632
+#: peigen.c:1636 pepigen.c:1636
 #, c-format
 msgid " Register save millicode"
 msgstr ""
 
-#: peigen.c:1635 pepigen.c:1635
+#: peigen.c:1639 pepigen.c:1639
 #, c-format
 msgid " Register restore millicode"
 msgstr ""
 
-#: peigen.c:1638 pepigen.c:1638
+#: peigen.c:1642 pepigen.c:1642
 #, c-format
 msgid " Glue code sequence"
 msgstr ""
 
-#: peigen.c:1688 pepigen.c:1688
+#: peigen.c:1692 pepigen.c:1692
 #, c-format
 msgid ""
 "\n"
@@ -3375,14 +3424,14 @@ msgid ""
 "PE File Base Relocations (interpreted .reloc section contents)\n"
 msgstr ""
 
-#: peigen.c:1718 pepigen.c:1718
+#: peigen.c:1722 pepigen.c:1722
 #, c-format
 msgid ""
 "\n"
 "Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n"
 msgstr ""
 
-#: peigen.c:1731 pepigen.c:1731
+#: peigen.c:1735 pepigen.c:1735
 #, c-format
 msgid "\treloc %4d offset %4x [%4lx] %s"
 msgstr ""
@@ -3390,7 +3439,7 @@ msgstr ""
 #. The MS dumpbin program reportedly ands with 0xff0f before
 #. printing the characteristics field.  Not sure why.  No reason to
 #. emulate it here.
-#: peigen.c:1769 pepigen.c:1769
+#: peigen.c:1773 pepigen.c:1773
 #, c-format
 msgid ""
 "\n"
diff --git a/bfd/reloc.c b/bfd/reloc.c
index ba8e14c7a42..ea73d137372 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -4575,6 +4575,11 @@ ENUMDOC
   BFD_RELOC_XTENSA_ASM_EXPAND.
 
 ENUM
+  BFD_RELOC_Z80_DISP8
+ENUMDOC
+  8 bit signed offset in (ix+d) or (iy+d).
+
+ENUM
   BFD_RELOC_Z8K_DISP7
 ENUMDOC
   DJNZ offset.
diff --git a/bfd/rs6000-core.c b/bfd/rs6000-core.c
index 22e61cc63c4..280a020a754 100644
--- a/bfd/rs6000-core.c
+++ b/bfd/rs6000-core.c
@@ -71,6 +71,9 @@
 #include <sys/core.h>
 #include <sys/systemcfg.h>
 
+/* Borrowed from <sys/inttypes.h> on recent AIX versions.  */
+typedef unsigned long ptr_to_uint;
+
 #define	core_hdr(bfd)		((CoreHdr *) bfd->tdata.any)
 
 /* AIX 4.1 changed the names and locations of a few items in the core file.
@@ -250,6 +253,15 @@ typedef union {
 #define CORE_COMMONSZ	((int) &((struct core_dump *) 0)->c_entries \
 			 + sizeof (((struct core_dump *) 0)->c_entries))
 
+/* Define prototypes for certain functions, to avoid a compiler warning
+   saying that they are missing.  */
+
+const bfd_target * rs6000coff_core_p (bfd *abfd);
+bfd_boolean rs6000coff_core_file_matches_executable_p (bfd *core_bfd,
+                                                       bfd *exec_bfd);
+char * rs6000coff_core_file_failing_command (bfd *abfd);
+int rs6000coff_core_file_failing_signal (bfd *abfd);
+
 /* Try to read into CORE the header from the core file associated with ABFD.
    Return success.  */
 
@@ -277,13 +289,8 @@ read_hdr (bfd *abfd, CoreHdr *core)
 }
 
 static asection *
-make_bfd_asection (abfd, name, flags, size, vma, filepos)
-     bfd *abfd;
-     const char *name;
-     flagword flags;
-     bfd_size_type size;
-     bfd_vma vma;
-     file_ptr filepos;
+make_bfd_asection (bfd *abfd, const char *name, flagword flags,
+		   bfd_size_type size, bfd_vma vma, file_ptr filepos)
 {
   asection *asect;
 
@@ -304,8 +311,7 @@ make_bfd_asection (abfd, name, flags, size, vma, filepos)
    magic number or anything like, in rs6000coff.  */
 
 const bfd_target *
-rs6000coff_core_p (abfd)
-     bfd *abfd;
+rs6000coff_core_p (bfd *abfd)
 {
   CoreHdr core;
   struct stat statbuf;
@@ -341,11 +347,11 @@ rs6000coff_core_p (abfd)
   else
     {
       c_flag = core.old.c_flag;
-      c_stack = (file_ptr) core.old.c_stack;
+      c_stack = (file_ptr) (ptr_to_uint) core.old.c_stack;
       c_size = core.old.c_size;
       c_stackend = COLD_STACKEND;
       c_lsize = 0x7ffffff;
-      c_loader = (file_ptr) COLD_LOADER (core.old);
+      c_loader = (file_ptr) (ptr_to_uint) COLD_LOADER (core.old);
       proc64 = 0;
     }
 
@@ -523,9 +529,9 @@ rs6000coff_core_p (abfd)
     else
       {
 	c_datasize = core.old.c_datasize;
-	c_data = (file_ptr) core.old.c_data;
+	c_data = (file_ptr) (ptr_to_uint) core.old.c_data;
 	c_vmregions = core.old.c_vmregions;
-	c_vmm = (file_ptr) core.old.c_vmm;
+	c_vmm = (file_ptr) (ptr_to_uint) core.old.c_vmm;
       }
 
     /* .data section from executable.  */
@@ -633,9 +639,7 @@ rs6000coff_core_p (abfd)
 /* Return `TRUE' if given core is from the given executable.  */
 
 bfd_boolean
-rs6000coff_core_file_matches_executable_p (core_bfd, exec_bfd)
-     bfd *core_bfd;
-     bfd *exec_bfd;
+rs6000coff_core_file_matches_executable_p (bfd *core_bfd, bfd *exec_bfd)
 {
   CoreHdr core;
   bfd_size_type size;
@@ -651,7 +655,7 @@ rs6000coff_core_file_matches_executable_p (core_bfd, exec_bfd)
   if (CORE_NEW (core))
     c_loader = CNEW_LOADER (core.new);
   else
-    c_loader = (file_ptr) COLD_LOADER (core.old);
+    c_loader = (file_ptr) (ptr_to_uint) COLD_LOADER (core.old);
 
   if (CORE_NEW (core) && CNEW_PROC64 (core.new))
     size = (int) ((LdInfo *) 0)->l64.ldinfo_filename;
@@ -711,8 +715,7 @@ rs6000coff_core_file_matches_executable_p (core_bfd, exec_bfd)
 }
 
 char *
-rs6000coff_core_file_failing_command (abfd)
-     bfd *abfd;
+rs6000coff_core_file_failing_command (bfd *abfd)
 {
   CoreHdr *core = core_hdr (abfd);
   char *com = CORE_NEW (*core) ?
@@ -725,8 +728,7 @@ rs6000coff_core_file_failing_command (abfd)
 }
 
 int
-rs6000coff_core_file_failing_signal (abfd)
-     bfd *abfd;
+rs6000coff_core_file_failing_signal (bfd *abfd)
 {
   CoreHdr *core = core_hdr (abfd);
   return CORE_NEW (*core) ? core->new.c_signo : core->old.c_signo;
diff --git a/bfd/sco5-core.c b/bfd/sco5-core.c
index e9b5159e6b3..d10dbfa9d3d 100644
--- a/bfd/sco5-core.c
+++ b/bfd/sco5-core.c
@@ -1,5 +1,5 @@
 /* BFD back end for SCO5 core files (U-area and raw sections)
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
    Written by Jouke Numan <jnuman@hiscom.nl>
 
@@ -31,8 +31,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 #include <signal.h>
 
 #include <sys/user.h>		/* After a.out.h  */
+#ifdef SCO5_CORE
 #include <sys/paccess.h>
 #include <sys/region.h>
+#endif
 
 struct sco5_core_struct
 {
@@ -126,14 +128,11 @@ sco5_core_file_p (abfd)
   /* Read coreoffsets region at end of core (see core(FP)).  */
 
   {
-    FILE *stream = bfd_cache_lookup (abfd);
     struct stat statbuf;
 
-    if (fstat (fileno (stream), &statbuf) < 0)
-      {
-	bfd_set_error (bfd_error_system_call);
-	return NULL;
-      }
+    if (bfd_stat (abfd, &statbuf) < 0)
+      return NULL;
+
     coresize = statbuf.st_size;
   }
   /* Last long in core is sizeof struct coreoffsets, read it */
diff --git a/bfd/targets.c b/bfd/targets.c
index 271954fd9c0..8f5795c24a4 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -271,6 +271,7 @@ BFD_JUMP_TABLE macros.
 .#define BFD_JUMP_TABLE_COPY(NAME) \
 .  NAME##_bfd_copy_private_bfd_data, \
 .  NAME##_bfd_merge_private_bfd_data, \
+.  _bfd_generic_init_private_section_data, \
 .  NAME##_bfd_copy_private_section_data, \
 .  NAME##_bfd_copy_private_symbol_data, \
 .  NAME##_bfd_copy_private_header_data, \
@@ -283,6 +284,12 @@ BFD_JUMP_TABLE macros.
 .  {* Called to merge BFD general private data from one object file
 .     to a common output file when linking.  *}
 .  bfd_boolean (*_bfd_merge_private_bfd_data) (bfd *, bfd *);
+.  {* Called to initialize BFD private section data from one object file
+.     to another.  *}
+.#define bfd_init_private_section_data(ibfd, isec, obfd, osec, link_info) \
+.  BFD_SEND (obfd, _bfd_init_private_section_data, (ibfd, isec, obfd, osec, link_info))
+.  bfd_boolean (*_bfd_init_private_section_data)
+.    (bfd *, sec_ptr, bfd *, sec_ptr, struct bfd_link_info *);
 .  {* Called to copy BFD private section data from one object file
 .     to another.  *}
 .  bfd_boolean (*_bfd_copy_private_section_data)
@@ -775,6 +782,7 @@ extern const bfd_target vms_alpha_vec;
 extern const bfd_target vms_vax_vec;
 extern const bfd_target w65_vec;
 extern const bfd_target we32kcoff_vec;
+extern const bfd_target z80coff_vec;
 extern const bfd_target z8kcoff_vec;
 
 /* These are always included.  */
@@ -1127,6 +1135,7 @@ static const bfd_target * const _bfd_target_vector[] = {
 	&vms_vax_vec,
 	&w65_vec,
 	&we32kcoff_vec,
+	&z80coff_vec,
 	&z8kcoff_vec,
 	&bfd_elf32_am33lin_vec,
 #endif /* not SELECT_VECS */
diff --git a/bfd/trad-core.c b/bfd/trad-core.c
index defad69f467..2f8c9f9ca5f 100644
--- a/bfd/trad-core.c
+++ b/bfd/trad-core.c
@@ -1,6 +1,6 @@
 /* BFD back end for traditional Unix core files (U-area and raw sections)
    Copyright 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004
+   2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
    Written by John Gilmore of Cygnus Support.
 
@@ -109,14 +109,11 @@ trad_unix_core_file_p (abfd)
 
   /* Check that the size claimed is no greater than the file size.  */
   {
-    FILE *stream = bfd_cache_lookup (abfd);
     struct stat statbuf;
 
-    if (fstat (fileno (stream), &statbuf) < 0)
-      {
-	bfd_set_error (bfd_error_system_call);
-	return 0;
-      }
+    if (bfd_stat (abfd, &statbuf) < 0)
+      return 0;
+
     if ((unsigned long) (NBPG * (UPAGES + u.u_dsize
 #ifdef TRAD_CORE_DSIZE_INCLUDES_TSIZE
 				 - u.u_tsize
diff --git a/bfd/version.h b/bfd/version.h
index 946a15362ba..c9200e1dede 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -1,3 +1,3 @@
-#define BFD_VERSION_DATE 20051020
+#define BFD_VERSION_DATE 20051101
 #define BFD_VERSION @bfd_version@
 #define BFD_VERSION_STRING @bfd_version_string@
diff --git a/bfd/xcoff-target.h b/bfd/xcoff-target.h
index 04bafd02413..7e73cf26a59 100644
--- a/bfd/xcoff-target.h
+++ b/bfd/xcoff-target.h
@@ -63,8 +63,8 @@
 
 #undef  CORE_FILE_P
 #define CORE_FILE_P rs6000coff_core_p
-extern const bfd_target * rs6000coff_core_p (void);
-extern bfd_boolean rs6000coff_core_file_matches_executable_p (void);
+extern const bfd_target * rs6000coff_core_p (bfd *);
+extern bfd_boolean rs6000coff_core_file_matches_executable_p (bfd *, bfd*);
 
 #undef	coff_core_file_matches_executable_p
 #define coff_core_file_matches_executable_p  \
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 0d8f21d9136..1fc6255def0 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,57 @@
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following change:
+	2003-09-24  Dave Brolley  <brolley@redhat.com>
+
+	* frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
+	CGEN_ATTR_VALUE_TYPE.
+	* m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
+	Use cgen_bitset_intersect_p.
+
+2005-10-27  DJ Delorie  <dj@redhat.com>
+
+	* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
+	(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
+	arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
+	imm operand is needed.
+	(adjnz, sbjnz): Pass the right operands.
+	(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
+	unary-insn): Add -g variants for opcodes that need to support :G.
+	(not.BW:G, push.BW:G): Call it.
+	(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
+	stzx16-imm8-imm8-abs16): Fix operand typos.
+	* m32c.opc (m32c_asm_hash): Support bnCND.
+	(parse_signed4n, print_signed4n): New.
+	
+2005-10-26  DJ Delorie  <dj@redhat.com>
+
+	* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
+	(mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
+	mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
+	dsp8[sp] is signed.
+	(mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
+	(mov.BW:S r0,r1): Fix typo r1l->r1.
+	(tst): Allow :G suffix.
+	* m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
+
+2005-10-26  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
+
+2005-10-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
+	making one a macro of the other.
+
+2005-10-21  DJ Delorie  <dj@redhat.com>
+
+	* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
+	(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
+	indexld, indexls): .w variants have `1' bit.
+	(rot32.b): QI, not SI.
+	(rot32.w): HI, not SI.
+	(xchg16): HI for .w variant.
+
 2005-10-19  Nick Clifton  <nickc@redhat.com>
 
 	* m32r.opc (parse_slo16): Fix bad application of previous patch.
diff --git a/cpu/frv.opc b/cpu/frv.opc
index c3e8405b49a..5d2dc896039 100644
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -50,7 +50,7 @@
 #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
 #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
 
-typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
+typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
 typedef struct
 {
@@ -58,15 +58,15 @@ typedef struct
   int                    constraint_violation;
   unsigned long          mach;
   unsigned long          elf_flags;
-  CGEN_ATTR_VALUE_TYPE * unit_mapping;
+  CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping;
   VLIW_COMBO *           current_vliw;
-  CGEN_ATTR_VALUE_TYPE   major[FRV_VLIW_SIZE];
+  CGEN_ATTR_VALUE_ENUM_TYPE   major[FRV_VLIW_SIZE];
   const CGEN_INSN *      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
-int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
-int frv_is_float_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
-int frv_is_media_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
+int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
 int frv_is_branch_insn  (const CGEN_INSN *);
 int frv_is_float_insn   (const CGEN_INSN *);
 int frv_is_media_insn   (const CGEN_INSN *);
@@ -83,7 +83,7 @@ int spr_valid           (long);
    development tree.  */
 
 bfd_boolean
-frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -107,7 +107,7 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 /* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
 
 bfd_boolean
-frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -126,7 +126,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 /* Returns TRUE if {MAJOR,MACH} supports media insns.  */
 
 bfd_boolean
-frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -270,7 +270,7 @@ static VLIW_COMBO fr550_allowed_vliw[] =
 /* Some insns are assigned specialized implementation units which map to
    different actual implementation units on different machines.  These
    tables perform that mapping.  */
-static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -305,7 +305,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
 /* Some insns are assigned specialized implementation units which map to
    different actual implementation units on different machines.  These
    tables perform that mapping.  */
-static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -337,7 +337,7 @@ static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
 /* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
 };
 
-static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -369,7 +369,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
 /* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
 };
 
-static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -435,7 +435,7 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
    *_allowed_vliw tables above.  */
 static bfd_boolean
 match_unit (FRV_VLIW *vliw,
-	    CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
+	    CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
 {
   /* Map any specialized implementation units to actual ones.  */
   unit1 = vliw->unit_mapping[unit1];
@@ -487,7 +487,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
    If one is found then return it. Otherwise return NULL.  */
 
 static VLIW_COMBO *
-add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
+add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
 {
   int           next    = vliw->next_slot;
   VLIW_COMBO    *current = vliw->current_vliw;
@@ -518,7 +518,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
    Returns TRUE if found, FALSE otherwise.  */
 
 static bfd_boolean
-find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   int i;
 
@@ -533,7 +533,7 @@ find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
    types.  */
 
 static bfd_boolean
-fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   /* In the cpu file, all media insns are represented as being allowed in
      both media units. This makes it easier since this is the case for fr500.
@@ -553,9 +553,9 @@ fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 }
 
 static bfd_boolean
-fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
-  CGEN_ATTR_VALUE_TYPE other_major;
+  CGEN_ATTR_VALUE_ENUM_TYPE other_major;
 
   /* Our caller guarantees there's at least one other instruction.  */
   other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
@@ -588,7 +588,7 @@ fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 }
 
 static bfd_boolean
-find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
+find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
 {
   int i;
 
@@ -601,8 +601,8 @@ find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
 
 static bfd_boolean
 find_major_in_slot (FRV_VLIW *vliw,
-		    CGEN_ATTR_VALUE_TYPE major,
-		    CGEN_ATTR_VALUE_TYPE slot)
+		    CGEN_ATTR_VALUE_ENUM_TYPE major,
+		    CGEN_ATTR_VALUE_ENUM_TYPE slot)
 {
   int i;
 
@@ -657,11 +657,11 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw)
 
 static bfd_boolean
 fr550_check_insn_major_constraints (FRV_VLIW *vliw,
-				    CGEN_ATTR_VALUE_TYPE major,
+				    CGEN_ATTR_VALUE_ENUM_TYPE major,
 				    const CGEN_INSN *insn)
 {
-  CGEN_ATTR_VALUE_TYPE unit;
-  CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
+  CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
   switch (slot)
     {
     case UNIT_I2:
@@ -707,7 +707,7 @@ fr550_check_insn_major_constraints (FRV_VLIW *vliw,
 }
 
 static bfd_boolean
-fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   /* TODO: A table might be faster for some of the more complex instances
      here.  */
@@ -815,7 +815,7 @@ fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 
 static bfd_boolean
 check_insn_major_constraints (FRV_VLIW *vliw,
-			      CGEN_ATTR_VALUE_TYPE major,
+			      CGEN_ATTR_VALUE_ENUM_TYPE major,
 			      const CGEN_INSN *insn)
 {
   switch (vliw->mach)
@@ -841,8 +841,8 @@ int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {
   int index;
-  CGEN_ATTR_VALUE_TYPE major;
-  CGEN_ATTR_VALUE_TYPE unit;
+  CGEN_ATTR_VALUE_ENUM_TYPE major;
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
   VLIW_COMBO *new_vliw;
 
   if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index 095e7cd12ae..cb892ffa859 100644
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -557,6 +557,15 @@
 		     (and UHI (srl UHI value 8) #x00ff)
 		     (and UHI (sll UHI value 8) #xff00))) ; extract
 )
+(df  f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
+     ((value pc) (or SI
+		     (or (srl value 16) (and value #xff00))
+		     (sll (ext INT (trunc QI (and value #xff))) 16)))
+     ((value pc) (or SI
+		     (or (srl value 16) (and value #xff00))
+		     (sll (ext INT (trunc QI (and value #xff))) 16)))
+ )
+
 (df  f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
      ((value pc) (or SI
 		     (or (srl value 16) (and value #xff00))
@@ -1756,6 +1765,10 @@
   h-sint DFLT f-dsp-8-s8
   ((parse "signed8")) () ()
 )
+(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
+  h-sint DFLT f-dsp-8-s24
+  ((parse "signed24")) () ()
+)
 (define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
   h-uint DFLT f-dsp-8-u24
   ((parse "unsigned24")) () ()
@@ -1881,6 +1894,10 @@
   h-sint DFLT f-imm-8-s4
   ((parse "signed4")) () ()
 )
+(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
+  h-sint DFLT f-imm-8-s4
+  ((parse "signed4n")) () ()
+)
 (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
   h-shimm DFLT f-imm-8-s4
   () () ()
@@ -1897,6 +1914,10 @@
   h-sint DFLT f-imm-12-s4
   ((parse "signed4")) () ()
 )
+(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
+  h-sint DFLT f-imm-12-s4
+  ((parse "signed4n") (print "signed4n")) () ()
+)
 (define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
   h-shimm DFLT f-imm-12-s4
   () () ()
@@ -5835,24 +5856,31 @@
 ; Unary insn macros
 ;-------------------------------------------------------------
 
-(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
+(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
   (dni (.sym op mach wstr - group)
-       (.str op wstr " dst" mach "-" group "-" mode)
+       (.str op wstr opg " dst" mach "-" group "-" mode)
        ((machine mach))
-       (.str op wstr " ${dst" mach "-" group "-" mode "}")
+       (.str op wstr opg " ${dst" mach "-" group "-" mode "}")
        encoding
        (sem mode (.sym dst mach - group - mode))
        ())
 )
 
+(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
+  (unary-insn-defn-g mach group mode wstr op encoding sem "")
+)
+
 
+(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
+  (unary-insn-defn-g 16 16 mode wstr op
+		     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
+		     sem opg)
+)
 (define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
-  (unary-insn-defn 16 16 mode wstr op
-		   (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
-		   sem)
+  (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
 )
 
-(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
+(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
   (begin
     ; Multi insns are tried for assembly in the reverse order in which they appear here, so
     ; define the absolute-indirect insns first in order to prevent them from being selected
@@ -5860,26 +5888,39 @@
 ;     (unary-insn-defn 32 24-absolute-indirect mode wstr op
 ; 		     (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
 ; 		     sem)
-    (unary-insn-defn 32 16-Unprefixed mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
-		     sem)
+    (unary-insn-defn-g 32 16-Unprefixed mode wstr op
+		       (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
+		       sem opg)
 ;     (unary-insn-defn 32 24-indirect mode wstr op
 ; 		     (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
 ; 		     sem)
   )
 )
+(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
+  (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
+)
 
-(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
+(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
   (begin
-    (.apply (.sym unary mach -defn) (QI .b 0 op opc1 opc2 opc3 sem))
-    (.apply (.sym unary mach -defn) (HI .w 1 op opc1 opc2 opc3 sem))
+    (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
+    (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
   )
 )
+(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
+  (unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
+)
 
 (define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
   (begin
-    (unary-insn-mach 16 op opc16-1 opc16-2 opc16-3 sem)
-    (unary-insn-mach 32 op opc32-1 opc32-2 opc32-3 sem)
+    (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
+    (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
+  )
+)
+
+(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
+  (begin
+    (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
+    (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
   )
 )
 
@@ -5997,10 +6038,10 @@
 ;-------------------------------------------------------------
 
 (define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem)
-  (dni (.sym op 16 -Q-sp)
-       (.str op ":Q #imm4,sp")
+  (dni (.sym op 16 -wQ-sp)
+       (.str op ".w:q #imm4,sp")
        ((machine 16))
-       (.str op "${size}$Q #${Imm-12-s4},sp")
+       (.str op ".w$Q #${Imm-12-s4},sp")
        (+ opc1 opc2 opc3 Imm-12-s4)
        (sem QI Imm-12-s4 sp)
        ())
@@ -6542,49 +6583,49 @@
 )
 
 ; m16c variants
-(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op opc1 opc2 sem)
+(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
   (begin
-    (arith-jnz-imm4-dst-defn 16 Imm-8-s4 basic Lab-16-8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-basic- mode) Lab-16-8)
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
 			     sem)
-    (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-16 Lab-32-8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-16- mode) Lab-16-8)
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
 			     sem)
-    (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-8 Lab-24-8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-8- mode) Lab-16-8)
+    (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
 			     sem)
   )
 )
 
 ; m32c variants
-(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op opc1 opc2 sem)
+(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
   (begin
-    (arith-jnz-imm4-dst-defn 32 Imm-12-s4 basic-Unprefixed Lab-16-8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-16-8)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
 		     sem)
-    (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-24-Unprefixed Lab-40-8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-40-8)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
 		     sem)
-    (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-16-Unprefixed Lab-32-8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-32-8)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
 		     sem)
-    (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-8-Unprefixed Lab-24-8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-24-8)
+    (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
 		     sem)
   )
 )
 
-(define-pmacro (arith-jnz-imm4-dst-mach mach op opc1 opc2 sem)
+(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
   (begin
-    (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op opc1 opc2 sem))
-    (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op opc1 opc2 sem))
+    (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
+    (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
   )
 )
 
-(define-pmacro (arith-jnz-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
+(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
   (begin
-    (arith-jnz-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
-    (arith-jnz-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
+    (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
+    (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
   )
 )
 
@@ -6595,7 +6636,7 @@
   (dni (.sym op mach wstr -dspsp-dst- dstgroup)
        (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
        ((machine mach))
-       (.str op wstr " ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
+       (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
        encoding
        (sem mach mode dsp (.sym dst mach - dstgroup - mode))
        ())
@@ -6604,7 +6645,7 @@
   (dni (.sym op mach wstr -dst-dspsp- dstgroup)
        (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
        ((machine mach))
-       (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
+       (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
        encoding
        (sem mach mode (.sym dst mach - dstgroup - mode) dsp)
        ())
@@ -6613,28 +6654,28 @@
 ; m16c variants
 (define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
   (begin
-    (mov-dspsp-dst-defn 16 basic Dsp-16-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8)
+    (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
 			     sem)
-    (mov-dspsp-dst-defn 16 16-16 Dsp-32-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8)
+    (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
 			     sem)
-    (mov-dspsp-dst-defn 16 16-8 Dsp-24-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8)
+    (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
 			     sem)
   )
 )
 
 (define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
   (begin
-    (mov-src-dspsp-defn 16 basic Dsp-16-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8)
+    (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
 			     sem)
-    (mov-src-dspsp-defn 16 16-16 Dsp-32-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8)
+    (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
 			     sem)
-    (mov-src-dspsp-defn 16 16-8 Dsp-24-u8 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8)
+    (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op
+			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
 			     sem)
   )
 )
@@ -6642,33 +6683,33 @@
 ; m32c variants
 (define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
   (begin
-    (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8)
+    (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
 		     sem)
-    (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8)
+    (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
 		     sem)
-    (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8)
+    (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
 		     sem)
-    (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8)
+    (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
 		     sem)
   )
 )
 (define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
   (begin
-    (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8)
+    (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
 		     sem)
-    (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8)
+    (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
 		     sem)
-    (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8)
+    (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
 		     sem)
-    (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op
-		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8)
+    (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
+		     (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
 		     sem)
   )
 )
@@ -6702,59 +6743,91 @@
 
 ;-------------------------------------------------------------
 ; lde dsp24,dst -- for m16c
-; TODO abs20[a0], [a0a1] for dsp24
 ;-------------------------------------------------------------
 
-(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem)
-  (dni (.sym op mach wstr -dst-dspsp- dstgroup)
-       (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
-       ((machine mach))
-       (.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}")
-       encoding
-       (sem mode (.sym dst mach - dstgroup - mode) dsp)
-       ())
-)
+(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
+  (begin
+
+    (dni (.sym lde wstr - dstgroup -u20)
+	 (.str "lde" wstr "-" dstgroup "-u20")
+	 ((machine 16))
+	 (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
+	  (.sym dst16- dstgroup - mode) srcdisp)
+	 (nop)
+	 ())
 
-(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem)
+    (dni (.sym lde wstr - dstgroup -u20a0)
+	 (.str "lde" wstr "-" dstgroup "-u20a0")
+	 ((machine 16))
+	 (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
+	  (.sym dst16- dstgroup - mode) srcdisp)
+	 (nop)
+	 ())
+
+    (dni (.sym lde wstr - dstgroup -a1a0)
+	 (.str "lde" wstr "-" dstgroup "-a1a0")
+	 ((machine 16))
+	 (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
+	  (.sym dst16- dstgroup - mode))
+	 (nop)
+	 ())
+    )
+  )
+
+(define-pmacro (lde-dst mode wstr wbit)
   (begin
-    (lde-defn 16 basic Dsp-16-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20)
-			     sem)
-    (lde-defn 16 16-16 Dsp-32-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20)
-			     sem)
-    (lde-defn 16 16-8 Dsp-24-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20)
-			     sem)
+    ; like:       QI   .b   0 
+    (lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
+    (lde-dst-dsp mode wstr wbit 16-8  Dsp-24-u20)
+    (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
   )
 )
 
 ;-------------------------------------------------------------
-; ste src,dsp24 -- for m16c
-; TODO abs20[a0], [a0a1] for dsp24
+; ste dst,dsp24 -- for m16c
 ;-------------------------------------------------------------
 
-(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem)
-  (dni (.sym op mach wstr -dst-dspsp- dstgroup)
-       (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
-       ((machine mach))
-       (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}")
-       encoding
-       (sem mode (.sym dst mach - dstgroup - mode) dsp)
-       ())
-)
+(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
+  (begin
+
+    (dni (.sym ste wstr - dstgroup -u20)
+	 (.str "ste" wstr "-" dstgroup "-u20")
+	 ((machine 16))
+	 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
+	  (.sym dst16- dstgroup - mode) srcdisp)
+	 (nop)
+	 ())
+
+    (dni (.sym ste wstr - dstgroup -u20a0)
+	 (.str "ste" wstr "-" dstgroup "-u20a0")
+	 ((machine 16))
+	 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
+	  (.sym dst16- dstgroup - mode) srcdisp)
+	 (nop)
+	 ())
+
+    (dni (.sym ste wstr - dstgroup -a1a0)
+	 (.str "ste" wstr "-" dstgroup "-a1a0")
+	 ((machine 16))
+	 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
+	 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
+	  (.sym dst16- dstgroup - mode))
+	 (nop)
+	 ())
+    )
+  )
 
-(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem)
+(define-pmacro (ste-dst mode wstr wbit)
   (begin
-    (ste-defn 16 basic Dsp-16-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20)
-			     sem)
-    (ste-defn 16 16-16 Dsp-32-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20)
-			     sem)
-    (ste-defn 16 16-8 Dsp-24-u20 mode wstr op
-			     (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20)
-			     sem)
+    ; like:       QI   .b   0 
+    (ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
+    (ste-dst-dsp mode wstr wbit 16-8  Dsp-24-u20)
+    (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
   )
 )
 
@@ -7091,6 +7164,9 @@
 (binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem)
 ; add.BW:Q #imm4,sp (m16 #7)
 (binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem)
+(dnmi add16-bQ-sp "add16-bQ-sp" ()
+      "add.b:q #${Imm-12-s4},sp"
+      (emit add16-wQ-sp Imm-12-s4))
 ; add.BW:G #imm,sp (m16 #6)
 (binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem)
 ; add.BW:G src,dst (m16 #4 m32 #6)
@@ -7246,7 +7322,7 @@
 )
 
 ; adjnz.size #imm4,dst,label
-(arith-jnz-imm4-dst adjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
+(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
 
 ;-------------------------------------------------------------
 ; and - binary and
@@ -7905,31 +7981,31 @@
 
 ; indexb src (index byte)
 (unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
-(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
+(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem)
 ; indexbd src (index byte dest)
 (unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
-(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
+(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem)
 ; indexbs src (index byte src)
 (unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
-(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
+(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem)
 ; indexl src (index long)
 (unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
-(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
+(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem)
 ; indexld src (index long dest)
 (unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
-(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
+(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem)
 ; indexls src (index long src)
 (unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
-(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
+(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem)
 ; indexw src (index word)
 (unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
-(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
+(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem)
 ; indexwd src (index word dest)
 (unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
-(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
+(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem)
 ; indexws (index word src)
 (unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
-(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
+(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem)
 
 ;-------------------------------------------------------------
 ; jcc - jump on condition
@@ -8450,21 +8526,11 @@
 ; ste - store to extra far data area (m16)
 ;-------------------------------------------------------------
 
-; A special variant of mem16 for lde and ste
-(define-pmacro (extra-mem16 mode address)
-  (mem mode (and #xfffff address)))
+(lde-dst QI .b 0)
+(lde-dst HI .w 1)
 
-(define-pmacro (lde-sem mode src1 dst)
-  (set mode src1 (extra-mem16 mode dst))
-)
-(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem)
-(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem)
-
-(define-pmacro (ste-sem mode src1 dst)
-  (set (extra-mem16 mode dst) src1)
-)
-(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem)
-(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem)
+(ste-dst QI .b 0)
+(ste-dst HI .w 1)
 
 ;-------------------------------------------------------------
 ; ldipl - load interrupt permission level
@@ -8575,8 +8641,8 @@
 )
 (mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
 (mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
-(mov32-wl-s-defn SI l #xB Dsp-8-u24 a0 #xC)
-(mov32-wl-s-defn SI l #xB Dsp-8-u24 a1 #xD)
+(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC)
+(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD)
 
 ; mov.size:Q #imm4,dst (m16 #2 m32 #3)
 (binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
@@ -8649,7 +8715,7 @@
 (mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4)
 (mov32-src-r w 1 HI dst32-2-S-8 r0 0 4)
 (mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7)
-(mov32-src-r w 1 HI dst32-2-S-basic r1l 1 7)
+(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7)
 (mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7)
 (mov32-src-r w 1 HI dst32-2-S-16 r1 1 7)
 (mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7)
@@ -8890,7 +8956,15 @@
 )
 
 ; not.BW:G
-(unary-insn not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
+(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
+
+(dni not16.b.s
+     "not.b:s Dst16-3-S-8"
+     ((machine 16))
+     "not.b:s ${Dst16-3-S-8}"
+     (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
+     (not-sem QI Dst16-3-S-8)
+     ())
 
 ;-------------------------------------------------------------
 ; nop
@@ -9279,7 +9353,7 @@
      ())
 
 ; push.BW:G src (m16 #2)
-(unary-insn-mach 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16)
+(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
 ; push.BW:G src (m32 #2)
 (unary-insn-mach 32 push #xC #x0 #xE push-sem32)
 
@@ -9481,9 +9555,9 @@
 ; rot.BW src,dst
 
 (dni rot16.b-dst "rot r1h,dest" ((machine 16))
-     ("rot.b r1h,${dst16-16-HI}")
-     (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI)
-     (rot-2-sem QI dst16-16-HI)
+     ("rot.b r1h,${dst16-16-QI}")
+     (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
+     (rot-2-sem QI dst16-16-QI)
      ())
 (dni rot16.w-dst "rot r1h,dest" ((machine 16))
      ("rot.w r1h,${dst16-16-HI}")
@@ -9492,14 +9566,14 @@
      ())
  
 (dni rot32.b-dst "rot r1h,dest" ((machine 32))
-     ("rot.b r1h,${dst32-16-Unprefixed-SI}")
-     (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
-     (rot-2-sem QI dst32-16-Unprefixed-SI)
+     ("rot.b r1h,${dst32-16-Unprefixed-QI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
+     (rot-2-sem QI dst32-16-Unprefixed-QI)
      ())
 (dni rot32.w-dst "rot r1h,dest" ((machine 32))
-     ("rot.w r1h,${dst32-16-Unprefixed-SI}")
-     (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
-     (rot-2-sem HI dst32-16-Unprefixed-SI)
+     ("rot.w r1h,${dst32-16-Unprefixed-HI}")
+     (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
+     (rot-2-sem HI dst32-16-Unprefixed-HI)
      ())
 
 ;-------------------------------------------------------------
@@ -9575,7 +9649,7 @@
 )
 
 ; sbjnz.size #imm4,dst,label
-(arith-jnz-imm4-dst sbjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
+(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
 
 ;-------------------------------------------------------------
 ; sccnd - store condition on condition (m32)
@@ -10105,17 +10179,17 @@
      (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
      ())
 (dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
-     ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb]")
+     ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
      (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
      (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
      ())
 (dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
-     ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb]")
-     (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u8 Imm-24-QI)
-     (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-fb) Dsp-24-u8)))
+     ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
+     (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
+     (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
      ())
 (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
-     ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16")
+     ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
      (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI)
      (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
      ())
@@ -10149,12 +10223,12 @@
 )
 
 ; tst.BW #imm,dst (m16 #1 m32 #1)
-(binary-arith-imm-dst tst X (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
+(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
 ; tst.BW src,dst (m16 #2 m32 #3)
 (binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
 (binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
-(binary-arith32-src-dst-Prefixed QI QI .b 0 tst X #x1 #x9 tst-sem)
-(binary-arith32-src-dst-Prefixed HI HI .w 1 tst X #x1 #x9 tst-sem)
+(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem)
+(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem)
 ; tst.BW:S #imm,dst2 (m32 #2)
 (binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem)
 (binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem)
@@ -10215,7 +10289,7 @@
 (xchg16-defn QI b 0 1 r0h)
 (xchg16-defn QI b 0 2 r1l)
 (xchg16-defn QI b 0 3 r1h)
-(xchg16-defn QI w 1 0 r0)
+(xchg16-defn HI w 1 0 r0)
 (xchg16-defn HI w 1 1 r1)
 (xchg16-defn HI w 1 2 r2)
 (xchg16-defn HI w 1 3 r3)
diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 19547ae694d..62353267f47 100644
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -69,6 +69,10 @@ m32c_asm_hash (const char *mnem)
   if (mnem[0] == 's' && mnem[1] == 'c')
     return 's';
   
+  /* Don't hash bmCND  */
+  if (mnem[0] == 'b' && mnem[1] == 'm')
+    return 'b';
+  
   for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
     h += *mnem;
   return h % CGEN_ASM_HASH_SIZE;
@@ -218,6 +222,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
 }
 
 static const char *
+parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
+		int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_SIGNED;
+
+  if (value < -7 || value > 8)
+    return _("Immediate is out of range -7 to 8");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("Immediate is out of range -7 to 8");
+
+  *valuep = -value;
+  return 0;
+}
+
+static const char *
 parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
 	       int opindex, signed long *valuep)
 {
@@ -433,6 +462,26 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
   return 0;
 }
 
+/* This should only be used for #imm->reg.  */
+static const char *
+parse_signed24 (CGEN_CPU_DESC cd, const char **strp,
+		 int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  PARSE_SIGNED;
+
+  if (value <= 0xffffff && value > 0x7fffff)
+    value -= 0x1000000;
+
+  if (value > 0xffffff)
+    return _("dsp:24 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
 static const char *
 parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
 		int opindex, signed long *valuep)
@@ -775,14 +824,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
 			  const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
-  int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
   /* If attributes are absent, assume no restriction.  */
   if (machs == 0)
     machs = ~0;
 
   return ((machs & cd->machs)
-	  && (isas & cd->isas));
+          && cgen_bitset_intersect_p (& isas, cd->isas));
 }
 
 /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
@@ -1072,3 +1121,16 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 {
   print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
 }
+
+static void
+print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		void * dis_info,
+		signed long value,
+		unsigned int attrs ATTRIBUTE_UNUSED,
+		bfd_vma pc ATTRIBUTE_UNUSED,
+		int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", -value);
+}
diff --git a/cpu/m32r.opc b/cpu/m32r.opc
index f2351b106a6..ab69d078c86 100644
--- a/cpu/m32r.opc
+++ b/cpu/m32r.opc
@@ -127,7 +127,10 @@ parse_hi16 (CGEN_CPU_DESC cd,
       ++*strp;
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	value >>= 16;
+	{
+	  value >>= 16;
+	  value &= 0xffff;
+	}
       *valuep = value;
       return errmsg;
     }
@@ -142,8 +145,9 @@ parse_hi16 (CGEN_CPU_DESC cd,
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
         {
-          value = value + (value & 0x8000 ? 0x10000 : 0);
+          value += 0x8000;
           value >>= 16;
+	  value &= 0xffff;
         }
       *valuep = value;
       return errmsg;
diff --git a/depcomp b/depcomp
new file mode 100755
index 00000000000..3510ab0ff53
--- /dev/null
+++ b/depcomp
@@ -0,0 +1,553 @@
+#! /bin/sh
+# depcomp - compile a program generating dependencies as side-effects
+
+scriptversion=2005-05-16.16
+
+# Copyright (C) 1999, 2000, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+# 02110-1301, USA.
+
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# Originally written by Alexandre Oliva <oliva@dcc.unicamp.br>.
+
+case $1 in
+  '')
+     echo "$0: No command.  Try \`$0 --help' for more information." 1>&2
+     exit 1;
+     ;;
+  -h | --h*)
+    cat <<\EOF
+Usage: depcomp [--help] [--version] PROGRAM [ARGS]
+
+Run PROGRAMS ARGS to compile a file, generating dependencies
+as side-effects.
+
+Environment variables:
+  depmode     Dependency tracking mode.
+  source      Source file read by `PROGRAMS ARGS'.
+  object      Object file output by `PROGRAMS ARGS'.
+  DEPDIR      directory where to store dependencies.
+  depfile     Dependency file to output.
+  tmpdepfile  Temporary file to use when outputing dependencies.
+  libtool     Whether libtool is used (yes/no).
+
+Report bugs to <bug-automake@gnu.org>.
+EOF
+    exit $?
+    ;;
+  -v | --v*)
+    echo "depcomp $scriptversion"
+    exit $?
+    ;;
+esac
+
+if test -z "$depmode" || test -z "$source" || test -z "$object"; then
+  echo "depcomp: Variables source, object and depmode must be set" 1>&2
+  exit 1
+fi
+
+# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po.
+depfile=${depfile-`echo "$object" |
+  sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`}
+tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`}
+
+rm -f "$tmpdepfile"
+
+# Some modes work just like other modes, but use different flags.  We
+# parameterize here, but still list the modes in the big case below,
+# to make depend.m4 easier to write.  Note that we *cannot* use a case
+# here, because this file can only contain one case statement.
+if test "$depmode" = hp; then
+  # HP compiler uses -M and no extra arg.
+  gccflag=-M
+  depmode=gcc
+fi
+
+if test "$depmode" = dashXmstdout; then
+   # This is just like dashmstdout with a different argument.
+   dashmflag=-xM
+   depmode=dashmstdout
+fi
+
+case "$depmode" in
+gcc3)
+## gcc 3 implements dependency tracking that does exactly what
+## we want.  Yay!  Note: for some reason libtool 1.4 doesn't like
+## it if -MD -MP comes after the -MF stuff.  Hmm.
+  "$@" -MT "$object" -MD -MP -MF "$tmpdepfile"
+  stat=$?
+  if test $stat -eq 0; then :
+  else
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  mv "$tmpdepfile" "$depfile"
+  ;;
+
+gcc)
+## There are various ways to get dependency output from gcc.  Here's
+## why we pick this rather obscure method:
+## - Don't want to use -MD because we'd like the dependencies to end
+##   up in a subdir.  Having to rename by hand is ugly.
+##   (We might end up doing this anyway to support other compilers.)
+## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like
+##   -MM, not -M (despite what the docs say).
+## - Using -M directly means running the compiler twice (even worse
+##   than renaming).
+  if test -z "$gccflag"; then
+    gccflag=-MD,
+  fi
+  "$@" -Wp,"$gccflag$tmpdepfile"
+  stat=$?
+  if test $stat -eq 0; then :
+  else
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz
+## The second -e expression handles DOS-style file names with drive letters.
+  sed -e 's/^[^:]*: / /' \
+      -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile"
+## This next piece of magic avoids the `deleted header file' problem.
+## The problem is that when a header file which appears in a .P file
+## is deleted, the dependency causes make to die (because there is
+## typically no way to rebuild the header).  We avoid this by adding
+## dummy dependencies for each header file.  Too bad gcc doesn't do
+## this for us directly.
+  tr ' ' '
+' < "$tmpdepfile" |
+## Some versions of gcc put a space before the `:'.  On the theory
+## that the space means something, we add a space to the output as
+## well.
+## Some versions of the HPUX 10.20 sed can't process this invocation
+## correctly.  Breaking it into two sed invocations is a workaround.
+    sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+hp)
+  # This case exists only to let depend.m4 do its work.  It works by
+  # looking at the text of this script.  This case will never be run,
+  # since it is checked for above.
+  exit 1
+  ;;
+
+sgi)
+  if test "$libtool" = yes; then
+    "$@" "-Wp,-MDupdate,$tmpdepfile"
+  else
+    "$@" -MDupdate "$tmpdepfile"
+  fi
+  stat=$?
+  if test $stat -eq 0; then :
+  else
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+
+  if test -f "$tmpdepfile"; then  # yes, the sourcefile depend on other files
+    echo "$object : \\" > "$depfile"
+
+    # Clip off the initial element (the dependent).  Don't try to be
+    # clever and replace this with sed code, as IRIX sed won't handle
+    # lines with more than a fixed number of characters (4096 in
+    # IRIX 6.2 sed, 8192 in IRIX 6.5).  We also remove comment lines;
+    # the IRIX cc adds comments like `#:fec' to the end of the
+    # dependency line.
+    tr ' ' '
+' < "$tmpdepfile" \
+    | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \
+    tr '
+' ' ' >> $depfile
+    echo >> $depfile
+
+    # The second pass generates a dummy entry for each header file.
+    tr ' ' '
+' < "$tmpdepfile" \
+   | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \
+   >> $depfile
+  else
+    # The sourcefile does not contain any dependencies, so just
+    # store a dummy comment line, to avoid errors with the Makefile
+    # "include basename.Plo" scheme.
+    echo "#dummy" > "$depfile"
+  fi
+  rm -f "$tmpdepfile"
+  ;;
+
+aix)
+  # The C for AIX Compiler uses -M and outputs the dependencies
+  # in a .u file.  In older versions, this file always lives in the
+  # current directory.  Also, the AIX compiler puts `$object:' at the
+  # start of each line; $object doesn't have directory information.
+  # Version 6 uses the directory in both cases.
+  stripped=`echo "$object" | sed 's/\(.*\)\..*$/\1/'`
+  tmpdepfile="$stripped.u"
+  if test "$libtool" = yes; then
+    "$@" -Wc,-M
+  else
+    "$@" -M
+  fi
+  stat=$?
+
+  if test -f "$tmpdepfile"; then :
+  else
+    stripped=`echo "$stripped" | sed 's,^.*/,,'`
+    tmpdepfile="$stripped.u"
+  fi
+
+  if test $stat -eq 0; then :
+  else
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+
+  if test -f "$tmpdepfile"; then
+    outname="$stripped.o"
+    # Each line is of the form `foo.o: dependent.h'.
+    # Do two passes, one to just change these to
+    # `$object: dependent.h' and one to simply `dependent.h:'.
+    sed -e "s,^$outname:,$object :," < "$tmpdepfile" > "$depfile"
+    sed -e "s,^$outname: \(.*\)$,\1:," < "$tmpdepfile" >> "$depfile"
+  else
+    # The sourcefile does not contain any dependencies, so just
+    # store a dummy comment line, to avoid errors with the Makefile
+    # "include basename.Plo" scheme.
+    echo "#dummy" > "$depfile"
+  fi
+  rm -f "$tmpdepfile"
+  ;;
+
+icc)
+  # Intel's C compiler understands `-MD -MF file'.  However on
+  #    icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c
+  # ICC 7.0 will fill foo.d with something like
+  #    foo.o: sub/foo.c
+  #    foo.o: sub/foo.h
+  # which is wrong.  We want:
+  #    sub/foo.o: sub/foo.c
+  #    sub/foo.o: sub/foo.h
+  #    sub/foo.c:
+  #    sub/foo.h:
+  # ICC 7.1 will output
+  #    foo.o: sub/foo.c sub/foo.h
+  # and will wrap long lines using \ :
+  #    foo.o: sub/foo.c ... \
+  #     sub/foo.h ... \
+  #     ...
+
+  "$@" -MD -MF "$tmpdepfile"
+  stat=$?
+  if test $stat -eq 0; then :
+  else
+    rm -f "$tmpdepfile"
+    exit $stat
+  fi
+  rm -f "$depfile"
+  # Each line is of the form `foo.o: dependent.h',
+  # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'.
+  # Do two passes, one to just change these to
+  # `$object: dependent.h' and one to simply `dependent.h:'.
+  sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile"
+  # Some versions of the HPUX 10.20 sed can't process this invocation
+  # correctly.  Breaking it into two sed invocations is a workaround.
+  sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" |
+    sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+ia64hp)
+  # The "hp" stanza above does not work with HP's ia64 compilers,
+  # which have integrated preprocessors.  The correct option to use
+  # with these is +Maked; it writes dependencies to a file named
+  # 'foo.d', which lands next to the object file, wherever that
+  # happens to be.
+  tmpdepfile=`echo "$object" | sed -e 's/\.o$/.d/'`
+  "$@" +Maked
+  stat=$?
+  if test $stat -eq 0; then :
+  else
+     rm -f "$tmpdepfile"
+     exit $stat
+  fi
+  rm -f "$depfile"
+
+  # The object file name is correct already.
+  cat "$tmpdepfile" > "$depfile"
+  # Add `dependent.h:' lines.
+  sed -ne '2,${; s/^ //; s/ \\*$//; s/$/:/; p; }' "$tmpdepfile" >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+tru64)
+   # The Tru64 compiler uses -MD to generate dependencies as a side
+   # effect.  `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'.
+   # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put
+   # dependencies in `foo.d' instead, so we check for that too.
+   # Subdirectories are respected.
+   dir=`echo "$object" | sed -e 's|/[^/]*$|/|'`
+   test "x$dir" = "x$object" && dir=
+   base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'`
+
+   if test "$libtool" = yes; then
+      # With Tru64 cc, shared objects can also be used to make a
+      # static library.  This mecanism is used in libtool 1.4 series to
+      # handle both shared and static libraries in a single compilation.
+      # With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d.
+      #
+      # With libtool 1.5 this exception was removed, and libtool now
+      # generates 2 separate objects for the 2 libraries.  These two
+      # compilations output dependencies in in $dir.libs/$base.o.d and
+      # in $dir$base.o.d.  We have to check for both files, because
+      # one of the two compilations can be disabled.  We should prefer
+      # $dir$base.o.d over $dir.libs/$base.o.d because the latter is
+      # automatically cleaned when .libs/ is deleted, while ignoring
+      # the former would cause a distcleancheck panic.
+      tmpdepfile1=$dir.libs/$base.lo.d   # libtool 1.4
+      tmpdepfile2=$dir$base.o.d          # libtool 1.5
+      tmpdepfile3=$dir.libs/$base.o.d    # libtool 1.5
+      tmpdepfile4=$dir.libs/$base.d      # Compaq CCC V6.2-504
+      "$@" -Wc,-MD
+   else
+      tmpdepfile1=$dir$base.o.d
+      tmpdepfile2=$dir$base.d
+      tmpdepfile3=$dir$base.d
+      tmpdepfile4=$dir$base.d
+      "$@" -MD
+   fi
+
+   stat=$?
+   if test $stat -eq 0; then :
+   else
+      rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
+      exit $stat
+   fi
+
+   for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
+   do
+     test -f "$tmpdepfile" && break
+   done
+   if test -f "$tmpdepfile"; then
+      sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile"
+      # That's a tab and a space in the [].
+      sed -e 's,^.*\.[a-z]*:[	 ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile"
+   else
+      echo "#dummy" > "$depfile"
+   fi
+   rm -f "$tmpdepfile"
+   ;;
+
+#nosideeffect)
+  # This comment above is used by automake to tell side-effect
+  # dependency tracking mechanisms from slower ones.
+
+dashmstdout)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout, regardless of -o.
+  "$@" || exit $?
+
+  # Remove the call to Libtool.
+  if test "$libtool" = yes; then
+    while test $1 != '--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+
+  # Remove `-o $object'.
+  IFS=" "
+  for arg
+  do
+    case $arg in
+    -o)
+      shift
+      ;;
+    $object)
+      shift
+      ;;
+    *)
+      set fnord "$@" "$arg"
+      shift # fnord
+      shift # $arg
+      ;;
+    esac
+  done
+
+  test -z "$dashmflag" && dashmflag=-M
+  # Require at least two characters before searching for `:'
+  # in the target name.  This is to cope with DOS-style filenames:
+  # a dependency such as `c:/foo/bar' could be seen as target `c' otherwise.
+  "$@" $dashmflag |
+    sed 's:^[  ]*[^: ][^:][^:]*\:[    ]*:'"$object"'\: :' > "$tmpdepfile"
+  rm -f "$depfile"
+  cat < "$tmpdepfile" > "$depfile"
+  tr ' ' '
+' < "$tmpdepfile" | \
+## Some versions of the HPUX 10.20 sed can't process this invocation
+## correctly.  Breaking it into two sed invocations is a workaround.
+    sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+dashXmstdout)
+  # This case only exists to satisfy depend.m4.  It is never actually
+  # run, as this mode is specially recognized in the preamble.
+  exit 1
+  ;;
+
+makedepend)
+  "$@" || exit $?
+  # Remove any Libtool call
+  if test "$libtool" = yes; then
+    while test $1 != '--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+  # X makedepend
+  shift
+  cleared=no
+  for arg in "$@"; do
+    case $cleared in
+    no)
+      set ""; shift
+      cleared=yes ;;
+    esac
+    case "$arg" in
+    -D*|-I*)
+      set fnord "$@" "$arg"; shift ;;
+    # Strip any option that makedepend may not understand.  Remove
+    # the object too, otherwise makedepend will parse it as a source file.
+    -*|$object)
+      ;;
+    *)
+      set fnord "$@" "$arg"; shift ;;
+    esac
+  done
+  obj_suffix="`echo $object | sed 's/^.*\././'`"
+  touch "$tmpdepfile"
+  ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@"
+  rm -f "$depfile"
+  cat < "$tmpdepfile" > "$depfile"
+  sed '1,2d' "$tmpdepfile" | tr ' ' '
+' | \
+## Some versions of the HPUX 10.20 sed can't process this invocation
+## correctly.  Breaking it into two sed invocations is a workaround.
+    sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile" "$tmpdepfile".bak
+  ;;
+
+cpp)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout.
+  "$@" || exit $?
+
+  # Remove the call to Libtool.
+  if test "$libtool" = yes; then
+    while test $1 != '--mode=compile'; do
+      shift
+    done
+    shift
+  fi
+
+  # Remove `-o $object'.
+  IFS=" "
+  for arg
+  do
+    case $arg in
+    -o)
+      shift
+      ;;
+    $object)
+      shift
+      ;;
+    *)
+      set fnord "$@" "$arg"
+      shift # fnord
+      shift # $arg
+      ;;
+    esac
+  done
+
+  "$@" -E |
+    sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \
+       -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' |
+    sed '$ s: \\$::' > "$tmpdepfile"
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  cat < "$tmpdepfile" >> "$depfile"
+  sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+msvisualcpp)
+  # Important note: in order to support this mode, a compiler *must*
+  # always write the preprocessed file to stdout, regardless of -o,
+  # because we must use -o when running libtool.
+  "$@" || exit $?
+  IFS=" "
+  for arg
+  do
+    case "$arg" in
+    "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI")
+	set fnord "$@"
+	shift
+	shift
+	;;
+    *)
+	set fnord "$@" "$arg"
+	shift
+	shift
+	;;
+    esac
+  done
+  "$@" -E |
+  sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::echo "`cygpath -u \\"\1\\"`":p' | sort | uniq > "$tmpdepfile"
+  rm -f "$depfile"
+  echo "$object : \\" > "$depfile"
+  . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::	\1 \\:p' >> "$depfile"
+  echo "	" >> "$depfile"
+  . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile"
+  rm -f "$tmpdepfile"
+  ;;
+
+none)
+  exec "$@"
+  ;;
+
+*)
+  echo "Unknown depmode $depmode" 1>&2
+  exit 1
+  ;;
+esac
+
+exit 0
+
+# Local Variables:
+# mode: shell-script
+# sh-indentation: 2
+# eval: (add-hook 'write-file-hooks 'time-stamp)
+# time-stamp-start: "scriptversion="
+# time-stamp-format: "%:y-%02m-%02d.%02H"
+# time-stamp-end: "$"
+# End:
diff --git a/etc/ChangeLog b/etc/ChangeLog
index 802f6868e8f..35e23bec28a 100644
--- a/etc/ChangeLog
+++ b/etc/ChangeLog
@@ -1,3 +1,11 @@
+2005-10-21  Mark Mitchell  <mark@codesourcery.com>
+
+	* texi2pod.pl: Substitue for @value even when part of @include. 
+
+2005-10-21  Bob Wilson  <bob.wilson@acm.org>
+
+	* texi2pod.pl: Import latest version from GCC.
+
 2005-05-19  Zack Weinberg  <zack@codesourcery.com>
 
 	* Makefile.in: Have 'all' depend on 'info'.
diff --git a/etc/texi2pod.pl b/etc/texi2pod.pl
index bdc20e8118f..9696a12f361 100644
--- a/etc/texi2pod.pl
+++ b/etc/texi2pod.pl
@@ -1,23 +1,23 @@
 #! /usr/bin/perl -w
 
-#   Copyright (C) 1999, 2000, 2001, 200 Free Software Foundation, Inc.
+#   Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
 
-# This file is part of GNU CC.
+# This file is part of GCC.
 
-# GNU CC is free software; you can redistribute it and/or modify
+# GCC is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation; either version 2, or (at your option)
 # any later version.
 
-# GNU CC is distributed in the hope that it will be useful,
+# GCC is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
 # You should have received a copy of the GNU General Public License
-# along with GNU CC; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston MA 02111-1307, USA.
+# along with GCC; see the file COPYING.  If not, write to
+# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+# Boston MA 02110-1301, USA.
 
 # This does trivial (and I mean _trivial_) conversion of Texinfo
 # markup to Perl POD format.  It's intended to be used to extract
@@ -138,7 +138,7 @@ while(<$inf>) {
 	# Ignore @end foo, where foo is not an operation which may
 	# cause us to skip, if we are presently skipping.
 	my $ended = $1;
-	next if $skipping && $ended !~ /^(?:ifset|ifclear|ignore|menu|iftex)$/;
+	next if $skipping && $ended !~ /^(?:ifset|ifclear|ignore|menu|iftex|copying)$/;
 
 	die "\@end $ended without \@$ended at line $.\n" unless defined $endw;
 	die "\@$endw ended by \@end $ended at line $.\n" unless $ended eq $endw;
@@ -178,7 +178,7 @@ while(<$inf>) {
 	next;
     };
 
-    /^\@(ignore|menu|iftex)\b/ and do {
+    /^\@(ignore|menu|iftex|copying)\b/ and do {
 	push @endwstack, $endw;
 	push @skstack, $skipping;
 	$endw = $1;
@@ -227,11 +227,12 @@ while(<$inf>) {
     /^\@include\s+(.+)$/ and do {
 	push @instack, $inf;
 	$inf = gensym();
+	$file = postprocess($1);
 
 	# Try cwd and $ibase.
-	open($inf, "<" . $1) 
-	    or open($inf, "<" . $ibase . "/" . $1)
-		or die "cannot open $1 or $ibase/$1: $!\n";
+	open($inf, "<" . $file) 
+	    or open($inf, "<" . $ibase . "/" . $file)
+		or die "cannot open $file or $ibase/$file: $!\n";
 	next;
     };
 
@@ -241,10 +242,14 @@ while(<$inf>) {
 	and $_ = "\n=head3 $1\n";
 
     # Block command handlers:
-    /^\@itemize\s+(\@[a-z]+|\*|-)/ and do {
+    /^\@itemize(?:\s+(\@[a-z]+|\*|-))?/ and do {
 	push @endwstack, $endw;
 	push @icstack, $ic;
-	$ic = $1;
+	if (defined $1) {
+	    $ic = $1;
+	} else {
+	    $ic = '@bullet';
+	}
 	$_ = "\n=over 4\n";
 	$endw = "itemize";
     };
@@ -345,6 +350,13 @@ sub postprocess
     s/\@w\{([^\}]*)\}/S<$1>/g;
     s/\@(?:dmn|math)\{([^\}]*)\}/$1/g;
 
+    # keep references of the form @ref{...}, print them bold
+    s/\@(?:ref)\{([^\}]*)\}/B<$1>/g;
+
+    # Change double single quotes to double quotes.
+    s/''/"/g;
+    s/``/"/g;
+
     # Cross references are thrown away, as are @noindent and @refill.
     # (@noindent is impossible in .pod, and @refill is unnecessary.)
     # @* is also impossible in .pod; we discard it and any newline that
@@ -365,14 +377,18 @@ sub postprocess
     s/\@uref\{([^\},]*),([^\},]*)\}/$2 (C<$1>)/g;
     s/\@uref\{([^\},]*),([^\},]*),([^\},]*)\}/$3/g;
 
-    # Turn B<blah I<blah> blah> into B<blah> I<blah> B<blah> to
-    # match Texinfo semantics of @emph inside @samp.  Also handle @r
-    # inside bold.
+    # Un-escape <> at this point.
     s/&LT;/</g;
     s/&GT;/>/g;
-    1 while s/B<((?:[^<>]|I<[^<>]*>)*)R<([^>]*)>/B<$1>${2}B</g;
-    1 while (s/B<([^<>]*)I<([^>]+)>/B<$1>I<$2>B</g);
-    1 while (s/I<([^<>]*)B<([^>]+)>/I<$1>B<$2>I</g);
+
+    # Now un-nest all B<>, I<>, R<>.  Theoretically we could have
+    # indefinitely deep nesting; in practice, one level suffices.
+    1 while s/([BIR])<([^<>]*)([BIR])<([^<>]*)>/$1<$2>$3<$4>$1</g;
+
+    # Replace R<...> with bare ...; eliminate empty markup, B<>;
+    # shift white space at the ends of [BI]<...> expressions outside
+    # the expression.
+    s/R<([^<>]*)>/$1/g;
     s/[BI]<>//g;
     s/([BI])<(\s+)([^>]+)>/$2$1<$3>/g;
     s/([BI])<([^>]+?)(\s+)>/$1<$2>$3/g;
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 37bbf05da9d..7433f6259e6 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,177 @@
+2005-11-01  Paul Gilliam  <pgilliam@us.ibm.com>
+
+        * rs6000-tdep.c (rs6000_gdbarch_init): On GNU/Linux, assume that
+	 bfd_mach_ppc64 has altivec unit, just like bfd_mach_ppc.
+
+2005-11-01  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* tui/tui-data.h (tui_line_or_address): Encapsulate the union in a
+	struct with a tag.
+	(tui_source_element, tui_source_info): Update.
+	* tui/tui-disasm.c, tui/tui-source.c: Update to use the tagged union.
+	* tui/tui-source.h, tui/tui-stack.c, tui/tui-win.c: Likewise.
+	* tui/tui-winsource.c, tui/tui-data.c, tui/tui-layout.c: Likewise.
+	* tui/tui-winsource.h: Likewise.
+
+2005-11-01  Christopher Faylor  <cgf@timesys.com>
+
+	* win32-nat.c (CYGWIN_SIGNAL_STRING): Delete.
+	(_CYGWIN_SIGNAL_STRING): Define if not already defined in cygwin.h.
+	(win32_add_thread): Use XZALLOC rather than xmalloc/memset.
+	(register_loaded_dll): Ditto.
+	(handle_load_dll): Call solib_add here.
+	(handle_unload_dll): Ditto.
+	(info_dll_command): Delete.
+	(handle_output_debug_string): Use official _CYGWIN_SIGNAL_STRING.
+	(win32_current_sos): Duplicate table to pass off to caller rather than
+	deleting our version.
+	(set_win32_aliases): New function.
+	(_initialize_win32_nat): Remove local handling of "info shared".  Set
+	deprecated_init_ui_hook to allow late setting of "info dll" alias.
+
+2005-11-01  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* event-top.c (gdb_setup_readline): Don't set gdb_stdout when
+	--batch-silent option was given.
+	* main.c (batch_silent): New variable.
+	(captured_main): Add new option --batch-silent.
+	(print_gdb_help): Likewise.
+
+2005-11-01  Mark Kettenis  <kettenis@gnu.org>
+
+	* NEWS: Mention VAX floating point support.
+
+2005-10-31  Christopher Faylor  <cgf@timesys.com>
+
+	* win32-nat.c (get_relocated_section_addrs): Reinstate.
+	(solib_symbols_add): New function.
+	(lm_info): Remove end_addr field.
+	(register_loaded_dll): Don't try to find end_addr since gdb will do
+	this automatically now.  Make so_original_name == so_name for now.
+	Eliminate strcpy by using so_name directly.  Read in symbols if new
+	paramater "readsyms" is true.
+	(handle_load_dll): Pass auto_solib_add to register_loaded_dll to
+	control when symbols should be read.
+	(win32_free_so): Don't free objfile here.
+	(win32_create_inferior_hook): New function.
+	(handle_unload_dll): Remove left-over cruft.
+	(win32_special_symbol_handling): New (dummy) function.
+	(map_single_dll_code_section): Reinstate.
+	(dll_code_sections_add): Reinstate.
+	(core_section_load_dll_symbols): Reinstate.  Don't issue an error on
+	duplicate attempts to read same dll.  Make sure that UNIX-like name is
+	used to register DLL.
+	(win32_current_sos): Handle core files.  Reset private list before
+	passing start of list pointer to gdb.
+	(init_win32_ops): Fill out (currently unused)
+	solib_create_inferior_hook.  Fill out special_symbol_handling.
+	* config/i386/tm-cygwin.h: Remove most special solib stuff.
+
+2005-10-31  Christopher Faylor  <cgf@timesys.com>
+
+	* win32-nat.c: Remove comment intended only for debugging.
+
+2005-11-01  Mark Kettenis  <kettenis@gnu.org>
+
+	* doublest.c (floatformat_normalize_byteorder): Handle
+	floatformat_vax.
+	(convert_doublest_to_floatformat): Use
+	floatformat_normalize_byteorder to swap bytes if necessary.
+	* vax-tdep.c: Include floatformat.h.
+	(vax_gdbarch_init): Set float_format, double_format,
+	long_double_format and long_double_bit.
+	* Makefile.in (vax-tdep.o): Update dependencies.
+
+2005-10-31  Christopher Faylor  <cgf@timesys.com>
+
+	Change child_ to win32_ throughout.
+	* win32-nat.c (win32_ops): New variable.
+	(win32_so_ops): Ditto.
+	(psapi_get_dll_name): Make function static.
+	(struct so_stuff): Delete.
+	(struct lm_info): New struct.
+	(solib_start, solib_end): Redefine as struct so_list.
+	(safe_symbol_file_add_stub): Use so_list rather than so_stuff.
+	(register_loaded_dll): Ditto.  Special-case ntdll.dll.  Fill in lm_info
+	field of so_list with information previously stored in so_stuff.
+	(get_image_name): Make function static.
+	(max_dll_name_len): Make variable static.
+	(win32_free_so): New function.
+	(win32_current_sos): Ditto.
+	(win32_relocate_section_addresses): Ditto.
+	(handle_unload_dll): Use so_list rather than so_stuff.  Call free_so to
+	delete shared library.
+	(solib_address): Delete function.
+	(child_solib_loaded_library_pathname): Ditto.
+	(win32_clear_solib): Rename from child_clear_solibs.  Use so_list
+	rather than so_stuff.  Just clear win32-specific stuff.
+	(get_relocated_section_addrs): Delete.
+	(solib_symbols_add): Ditto.
+	(info_dll_command): Make static.  Use lm_info field from so_list to
+	retrieve load address.
+	(fake_create_process): Make function static.
+	(win32_xfer_memory): Ditto.
+	(win32_kill_inferior): Ditto.
+	(win32_resume): Ditto.
+	(cygwin_pid_to_str): Ditto.
+	(do_initial_win32_stuff): Use win32_ops rather than
+	deprecated_child_ops.
+	(child_detach): Ditto.
+	(win32_mourn_inferior): Ditto.
+	(_initialize_win32_nat): Ditto.
+	(init_win32_ops): Ditto.  Fill out win32_so_ops and set
+	current_target_so_ops to win32_so_ops.
+	(core_dll_symbols_add): Delete.
+	(map_single_dll_code_section): Ditto.
+	(dll_code_sections_add): Ditto.
+	(core_section_load_dll_symbols): Ditto.
+	(child_solib_add): Ditto.
+
+2005-10-31  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* tui/tui-command.c (tui_dispatch_ctrl_char): Test output of
+	getenv() before using it.
+
+2005-10-29  Mark Kettenis  <kettenis@gnu.org>
+
+	* hppa-tdep.h (HPPA_INSN_SIZE): New define.
+	* hppa-hpux-tdep.c (hppa_hpux_search_pattern)
+	(hppa64_hpux_search_dummy_call_sequence): Rewrite to avoid
+	assumption on sizeof(unsigned).
+
+	* inf-ttrace.c (inf_ttrace_wait): Comment out TARGET_WAITKIND_EXEC
+	code; return TARGET_WAITKIND_STOPPED instead.
+
+2005-10-28  Mark Kettenis  <kettenis@gnu.org>
+
+	* ppc-tdep.h (PPC_INSN_SIZE): Define.
+
+	* inf-ttrace.c (inf_ttrace_mourn_inferior): Remove redundant cast.
+	(inf_ttrace_kill): Renamed from inf_ttrace_kill_inferior.
+	(inf_ttrace_target): Resort assignments.
+
+2005-10-28  Nick Roberts  <nickrob@snap.net.nz>
+
+	* mi/gdb-mi.el: Sync with Emacs 22.0.50.
+
+2005-10-25  Andreas Schwab  <schwab@suse.de>
+
+	* regformats/reg-ia64.dat: Remove NAT registers.
+
+2005-10-20  Mark Kettenis  <kettenis@gnu.org>
+
+	* rs6000-tdep.c (info_powerpc_cmdlist): Remove variable.
+	(rs6000_info_powerpc_command): Remove function.
+
+2005-10-21  Andreas Schwab  <schwab@suse.de>
+
+	* dwarf2read.c (isreg): Removed.
+	(decode_locdesc): Don't set it.
+
+2005-10-20  Joel Brobecker  <brobecker@adacore.com>
+
+	* Makefile.in (YYFILES): Add ada-lex.c
+
 2005-10-17  Jim Blandy  <jimb@redhat.com>
 
 	* dwarf2expr.c (dwarf_expr_fetch): Use correct comparison to
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 02eaa44d4fd..8d113523df4 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -948,6 +948,7 @@ SUBDIRS = @subdirs@
 YYFILES = c-exp.c \
 	cp-name-parser.c \
 	objc-exp.c \
+	ada-lex.c \
 	ada-exp.c \
 	jv-exp.c \
 	f-exp.c m2-exp.c p-exp.c
@@ -2746,10 +2747,10 @@ vaxnbsd-tdep.o: vaxnbsd-tdep.c $(defs_h) $(arch_utils_h) $(osabi_h) \
 vaxobsd-tdep.o: vaxobsd-tdep.c  $(defs_h) $(arch_utils_h) $(frame_h) \
 	$(frame_unwind_h) $(osabi_h) $(symtab_h) $(trad_frame_h) \
 	$(vax_tdep_h) $(gdb_string_h)
-vax-tdep.o: vax-tdep.c $(defs_h) $(arch_utils_h) $(dis_asm_h) $(frame_h) \
-	$(frame_base_h) $(frame_unwind_h) $(gdbcore_h) $(gdbtypes_h) \
-	$(osabi_h) $(regcache_h) $(regset_h) $(trad_frame_h) $(value_h) \
-	$(gdb_string_h) $(vax_tdep_h)
+vax-tdep.o: vax-tdep.c $(defs_h) $(arch_utils_h) $(dis_asm_h) \
+	$(float_format_h)$(frame_h) $(frame_base_h) $(frame_unwind_h) \
+	$(gdbcore_h) $(gdbtypes_h) $(osabi_h) $(regcache_h) $(regset_h) \
+	$(trad_frame_h) $(value_h) $(gdb_string_h) $(vax_tdep_h)
 win32-nat.o: win32-nat.c $(defs_h) $(frame_h) $(inferior_h) $(target_h) \
 	$(exceptions_h) $(gdbcore_h) $(command_h) $(completer_h) \
 	$(regcache_h) $(top_h) $(buildsym_h) $(symfile_h) $(objfiles_h) \
diff --git a/gdb/NEWS b/gdb/NEWS
index eb5af88361a..89099f6138e 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -56,6 +56,10 @@ After turning this setting "on", GDB prints the index of each element
 when displaying arrays.  The default is "off" to preserve the previous
 behavior.
 
+* VAX floating point support
+
+GDB now supports the not-quite-ieee VAX F and D floating point formats.
+
 *** Changes in GDB 6.3:
 
 * New command line option
diff --git a/gdb/config/i386/tm-cygwin.h b/gdb/config/i386/tm-cygwin.h
index 52ec2751261..48748cd0803 100644
--- a/gdb/config/i386/tm-cygwin.h
+++ b/gdb/config/i386/tm-cygwin.h
@@ -21,16 +21,5 @@
    Boston, MA 02111-1307, USA.  */
 
 #define ATTACH_NO_WAIT
-#define SOLIB_ADD(filename, from_tty, targ, readsyms) child_solib_add(filename, from_tty, targ, readsyms)
-#define PC_SOLIB(addr) solib_address (addr)
-#define SOLIB_LOADED_LIBRARY_PATHNAME(pid) child_solib_loaded_library_pathname(pid)
-#define CLEAR_SOLIB child_clear_solibs
 #define ADD_SHARED_SYMBOL_FILES dll_symbol_command
-
-struct target_ops;
-char *cygwin_pid_to_str (ptid_t ptid);
-void child_solib_add (char *, int, struct target_ops *, int);
-char *solib_address (CORE_ADDR);
-char *child_solib_loaded_library_pathname(int);
-void child_clear_solibs (void);
 void dll_symbol_command (char *, int);
diff --git a/gdb/config/iq2000/iq2000.mt b/gdb/config/iq2000/iq2000.mt
new file mode 100644
index 00000000000..8d5dfb815cb
--- /dev/null
+++ b/gdb/config/iq2000/iq2000.mt
@@ -0,0 +1,3 @@
+TDEPFILES= iq2000-tdep.o
+SIM_OBS= remote-sim.o
+SIM= ../sim/iq2000/libsim.a
diff --git a/gdb/config/ms1/ms1.mt b/gdb/config/ms1/ms1.mt
new file mode 100644
index 00000000000..18ce1abdf71
--- /dev/null
+++ b/gdb/config/ms1/ms1.mt
@@ -0,0 +1,2 @@
+# Target: Morpho Technologies ms1 processor
+TDEPFILES= ms1-tdep.o
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index fa60a7446e8..f62c31230cf 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,12 @@
+2005-11-01  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* gdb.texinfo (Choosing modes): Add --batch-silent.
+
+2005-10-28  Eli Zaretskii  <eliz@gnu.org>
+
+	* gdb.texinfo (GDB/MI Variable Objects): Fix @pxref usage under
+	"The -var-update Command".
+
 2005-10-03  Joel Brobecker  <brobecker@adacore.com>
 
 	* gdb.texinfo (Print Settings): Add documentation for set/show
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 2055f1a00bb..75ae4ef7f07 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -994,6 +994,19 @@ Program exited normally.
 @value{GDBN} control terminates) is not issued when running in batch
 mode.
 
+@item -batch-silent
+@cindex @code{--batch-silent}
+Run in batch mode exactly like @samp{-batch}, but totally silently.  All
+@value{GDBN} output to @code{stdout} is prevented (@code{stderr} is
+unaffected).  This is much quieter than @samp{-silent} and would be useless
+for an interactive session.
+
+This is particularly useful when using targets that give @samp{Loading section}
+messages, for example.
+
+Note that targets that give their output via @value{GDBN}, as opposed to
+writing directly to @code{stdout}, will also be made silent.
+
 @item -nowindows
 @itemx -nw
 @cindex @code{--nowindows}
@@ -20636,9 +20649,9 @@ subsequent @code{-var-update} list.
 Update the value of the variable object @var{name} by evaluating its
 expression after fetching all the new values from memory or registers.
 A @samp{*} causes all existing variable objects to be updated.  The
-option @var{print-values} determines whether names and values, or just
-names are printed in the manner described for
-@code{@pxref{-var-list-children}}.
+option @var{print-values} determines whether names both and values, or
+just names are printed in the manner described for
+@code{-var-list-children} (@pxref{-var-list-children}).
 
 @subsubheading Example
 
diff --git a/gdb/doublest.c b/gdb/doublest.c
index 2562ab67238..8045a1ce139 100644
--- a/gdb/doublest.c
+++ b/gdb/doublest.c
@@ -1,8 +1,8 @@
 /* Floating point routines for GDB, the GNU debugger.
 
    Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
-   1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005 Free Software
-   Foundation, Inc.
+   1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -110,9 +110,10 @@ get_field (const bfd_byte *data, enum floatformat_byteorders order,
   return result;
 }
 
-/* Normalize the byte order of FROM into TO.  If no normalization is needed
-   then FMT->byteorder is returned and TO is not changed; otherwise the format
-   of the normalized form in TO is returned.  */
+/* Normalize the byte order of FROM into TO.  If no normalization is
+   needed then FMT->byteorder is returned and TO is not changed;
+   otherwise the format of the normalized form in TO is returned.  */
+
 static enum floatformat_byteorders
 floatformat_normalize_byteorder (const struct floatformat *fmt,
 				 const void *from, void *to)
@@ -125,23 +126,40 @@ floatformat_normalize_byteorder (const struct floatformat *fmt,
       || fmt->byteorder == floatformat_big)
     return fmt->byteorder;
 
-  gdb_assert (fmt->byteorder == floatformat_littlebyte_bigword);
-
   words = fmt->totalsize / FLOATFORMAT_CHAR_BIT;
   words >>= 2;
 
   swapout = (unsigned char *)to;
   swapin = (const unsigned char *)from;
 
-  while (words-- > 0)
+  if (fmt->byteorder == floatformat_vax)
+    {
+      while (words-- > 0)
+	{
+	  *swapout++ = swapin[1];
+	  *swapout++ = swapin[0];
+	  *swapout++ = swapin[3];
+	  *swapout++ = swapin[2];
+	  swapin += 4;
+	}
+      /* This may look weird, since VAX is little-endian, but it is
+	 easier to translate to big-endian than to little-endian.  */
+      return floatformat_big;
+    }
+  else
     {
-      *swapout++ = swapin[3];
-      *swapout++ = swapin[2];
-      *swapout++ = swapin[1];
-      *swapout++ = swapin[0];
-      swapin += 4;
+      gdb_assert (fmt->byteorder == floatformat_littlebyte_bigword);
+
+      while (words-- > 0)
+	{
+	  *swapout++ = swapin[3];
+	  *swapout++ = swapin[2];
+	  *swapout++ = swapin[1];
+	  *swapout++ = swapin[0];
+	  swapin += 4;
+	}
+      return floatformat_big;
     }
-  return floatformat_big;
 }
   
 /* Convert from FMT to a DOUBLEST.
@@ -337,14 +355,13 @@ ldfrexp (long double value, int *eptr)
 #endif /* HAVE_LONG_DOUBLE */
 
 
-/* The converse: convert the DOUBLEST *FROM to an extended float
-   and store where TO points.  Neither FROM nor TO have any alignment
+/* The converse: convert the DOUBLEST *FROM to an extended float and
+   store where TO points.  Neither FROM nor TO have any alignment
    restrictions.  */
 
 static void
 convert_doublest_to_floatformat (CONST struct floatformat *fmt,
-				 const DOUBLEST *from,
-				 void *to)
+				 const DOUBLEST *from, void *to)
 {
   DOUBLEST dfrom;
   int exponent;
@@ -353,10 +370,14 @@ convert_doublest_to_floatformat (CONST struct floatformat *fmt,
   int mant_bits_left;
   unsigned char *uto = (unsigned char *) to;
   enum floatformat_byteorders order = fmt->byteorder;
+  unsigned char newto[FLOATFORMAT_LARGEST_BYTES];
 
-  if (order == floatformat_littlebyte_bigword)
+  if (order != floatformat_little)
     order = floatformat_big;
 
+  if (order != fmt->byteorder)
+    uto = newto;
+
   memcpy (&dfrom, from, sizeof (dfrom));
   memset (uto, 0, (fmt->totalsize + FLOATFORMAT_CHAR_BIT - 1) 
                     / FLOATFORMAT_CHAR_BIT);
@@ -447,24 +468,7 @@ convert_doublest_to_floatformat (CONST struct floatformat *fmt,
  finalize_byteorder:
   /* Do we need to byte-swap the words in the result?  */
   if (order != fmt->byteorder)
-    {
-      int words;
-      unsigned char *curword = uto;
-      unsigned char tmp;
-
-      words = fmt->totalsize / FLOATFORMAT_CHAR_BIT;
-      words >>= 2;
-      while (words-- > 0)
-	{
-	  tmp = curword[0];
-	  curword[0] = curword[3];
-	  curword[3] = tmp;
-	  tmp = curword[1];
-	  curword[1] = curword[2];
-	  curword[2] = tmp;
-	  curword += 4;
-	}
-    }
+    floatformat_normalize_byteorder (fmt, newto, to);
 }
 
 /* Check if VAL (which is assumed to be a floating point number whose
diff --git a/gdb/dwarf2read.c b/gdb/dwarf2read.c
index ae85ef3554b..4b0b6bd8460 100644
--- a/gdb/dwarf2read.c
+++ b/gdb/dwarf2read.c
@@ -580,15 +580,6 @@ struct dwarf_block
 /* A zeroed version of a partial die for initialization purposes.  */
 static struct partial_die_info zeroed_partial_die;
 
-/* FIXME: decode_locdesc sets these variables to describe the location
-   to the caller.  These ought to be a structure or something.   If
-   none of the flags are set, the object lives at the address returned
-   by decode_locdesc.  */
-
-static int isreg;		/* Object lives in register.
-				   decode_locdesc's return value is
-				   the register number.  */
-
 /* FIXME: We might want to set this from BFD via bfd_arch_bits_per_byte,
    but this would require a corresponding change in unpack_field_as_long
    and friends.  */
@@ -8559,9 +8550,6 @@ dwarf2_fundamental_type (struct objfile *objfile, int typeid,
    callers will only want a very basic result and this can become a
    complaint.
 
-   When the result is a register number, the global isreg flag is set,
-   otherwise it is cleared.
-
    Note that stack[0] is unused except as a default error return.
    Note that stack overflow is not yet handled.  */
 
@@ -8581,7 +8569,6 @@ decode_locdesc (struct dwarf_block *blk, struct dwarf2_cu *cu)
   i = 0;
   stacki = 0;
   stack[stacki] = 0;
-  isreg = 0;
 
   while (i < size)
     {
@@ -8655,14 +8642,12 @@ decode_locdesc (struct dwarf_block *blk, struct dwarf2_cu *cu)
 	case DW_OP_reg29:
 	case DW_OP_reg30:
 	case DW_OP_reg31:
-	  isreg = 1;
 	  stack[++stacki] = op - DW_OP_reg0;
 	  if (i < size)
 	    dwarf2_complex_location_expr_complaint ();
 	  break;
 
 	case DW_OP_regx:
-	  isreg = 1;
 	  unsnd = read_unsigned_leb128 (NULL, (data + i), &bytes_read);
 	  i += bytes_read;
 	  stack[++stacki] = unsnd;
diff --git a/gdb/event-top.c b/gdb/event-top.c
index 4614d4d2f4c..bc1fe8ea38c 100644
--- a/gdb/event-top.c
+++ b/gdb/event-top.c
@@ -1110,8 +1110,10 @@ gdb_setup_readline (void)
      that the sync setup is ALL done in gdb_init, and we would only
      mess it up here.  The sync stuff should really go away over
      time.  */
+  extern batch_silent;
 
-  gdb_stdout = stdio_fileopen (stdout);
+  if (!batch_silent)
+    gdb_stdout = stdio_fileopen (stdout);
   gdb_stderr = stdio_fileopen (stderr);
   gdb_stdlog = gdb_stderr;  /* for moment */
   gdb_stdtarg = gdb_stderr; /* for moment */
diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog
index 65cca45dbac..bdf99aeddb3 100644
--- a/gdb/gdbserver/ChangeLog
+++ b/gdb/gdbserver/ChangeLog
@@ -1,3 +1,10 @@
+2005-10-25  Andreas Schwab  <schwab@suse.de>
+
+	* server.c (main): Allocate mem_buf with PBUFSIZ bytes.
+
+	* linux-ia64-low.c (ia64_regmap): Remove NAT registers.
+	(ia64_num_regs): Reduce to 462.
+
 2005-09-17  Daniel Jacobowitz  <dan@codesourcery.com>
 
 	* acinclude.m4: Correct quoting.
diff --git a/gdb/gdbserver/linux-ia64-low.c b/gdb/gdbserver/linux-ia64-low.c
index 9407e6cbcf7..4a32e991cb1 100644
--- a/gdb/gdbserver/linux-ia64-low.c
+++ b/gdb/gdbserver/linux-ia64-low.c
@@ -26,7 +26,7 @@
 #include <sys/reg.h>
 #endif
 
-#define ia64_num_regs 590
+#define ia64_num_regs 462
 
 #include <asm/ptrace_offsets.h>
 
@@ -263,24 +263,6 @@ static int ia64_regmap[] =
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1,
-    /* nat bits - not fetched directly; instead we obtain these bits from
-       either rnat or unat or from memory. */
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
-    -1, -1, -1, -1, -1, -1, -1, -1,
   };
 
 static int
diff --git a/gdb/gdbserver/server.c b/gdb/gdbserver/server.c
index dfefe2b52a9..cde6d4fd6a4 100644
--- a/gdb/gdbserver/server.c
+++ b/gdb/gdbserver/server.c
@@ -322,7 +322,7 @@ int
 main (int argc, char *argv[])
 {
   char ch, status, *own_buf;
-  unsigned char mem_buf[2000];
+  unsigned char *mem_buf;
   int i = 0;
   int signal;
   unsigned int len;
@@ -359,6 +359,7 @@ main (int argc, char *argv[])
   initialize_low ();
 
   own_buf = malloc (PBUFSIZ);
+  mem_buf = malloc (PBUFSIZ);
 
   if (pid == 0)
     {
diff --git a/gdb/hppa-hpux-tdep.c b/gdb/hppa-hpux-tdep.c
index c0f9a3ab1d6..ed0abf9ee9e 100644
--- a/gdb/hppa-hpux-tdep.c
+++ b/gdb/hppa-hpux-tdep.c
@@ -1,6 +1,6 @@
 /* Target-dependent code for HP-UX on PA-RISC.
 
-   Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -1309,32 +1309,31 @@ static CORE_ADDR
 hppa_hpux_search_pattern (CORE_ADDR start, CORE_ADDR end, 
 			  unsigned int *patterns, int count)
 {
-  unsigned int *buf;
+  int num_insns = (end - start + HPPA_INSN_SIZE) / HPPA_INSN_SIZE;
+  unsigned int *insns;
+  gdb_byte *buf;
   int offset, i;
-  int region, insns;
 
-  region = end - start + 4;
-  insns = region / 4;
-  buf = (unsigned int *) alloca (region);
+  buf = alloca (num_insns * HPPA_INSN_SIZE);
+  insns = alloca (num_insns * sizeof (unsigned int));
 
-  read_memory (start, (char *) buf, region);
+  read_memory (start, buf, num_insns * HPPA_INSN_SIZE);
+  for (i = 0; i < num_insns; i++, buf += HPPA_INSN_SIZE)
+    insns[i] = extract_unsigned_integer (buf, HPPA_INSN_SIZE);
 
-  for (i = 0; i < insns; i++)
-    buf[i] = extract_unsigned_integer (&buf[i], 4);
-
-  for (offset = 0; offset <= insns - count; offset++)
+  for (offset = 0; offset <= num_insns - count; offset++)
     {
       for (i = 0; i < count; i++)
         {
-	  if ((buf[offset + i] & patterns[i]) != patterns[i])
+	  if ((insns[offset + i] & patterns[i]) != patterns[i])
 	    break;
 	}
       if (i == count)
         break;
     }
-    
-  if (offset <= insns - count)
-    return start + offset * 4;
+
+  if (offset <= num_insns - count)
+    return start + offset * HPPA_INSN_SIZE;
   else
     return 0;
 }
@@ -1472,7 +1471,7 @@ hppa64_hpux_search_dummy_call_sequence (struct gdbarch *gdbarch, CORE_ADDR pc,
     {
       CORE_ADDR begin, end;
       char *name;
-      unsigned int insns[2];
+      gdb_byte buf[2 * HPPA_INSN_SIZE];
       int offset;
 
       find_pc_partial_function (SYMBOL_VALUE_ADDRESS (msym), &name,
@@ -1481,16 +1480,16 @@ hppa64_hpux_search_dummy_call_sequence (struct gdbarch *gdbarch, CORE_ADDR pc,
       if (name == NULL || begin == 0 || end == 0)
         continue;
 
-      if (target_read_memory (end - sizeof (insns), (char *)insns, sizeof (insns)) == 0)
+      if (target_read_memory (end - sizeof (buf), buf, sizeof (buf)) == 0)
         {
-	  for (offset = 0; offset < ARRAY_SIZE (insns); offset++)
+	  for (offset = 0; offset < sizeof (buf); offset++)
 	    {
 	      unsigned int insn;
 
-	      insn = extract_unsigned_integer (&insns[offset], 4);
+	      insn = extract_unsigned_integer (buf + offset, HPPA_INSN_SIZE);
 	      if (insn == 0xe840d002) /* bve,n (rp) */
 	        {
-		  addr = (end - sizeof (insns)) + (offset * 4);
+		  addr = (end - sizeof (buf)) + offset;
 		  goto found_pattern;
 		}
 	    }
diff --git a/gdb/hppa-tdep.h b/gdb/hppa-tdep.h
index 484a2d50439..2e5227b75ba 100644
--- a/gdb/hppa-tdep.h
+++ b/gdb/hppa-tdep.h
@@ -75,6 +75,9 @@ enum hppa_regnum
   HPPA_ARG3_REGNUM = 23		/* The fourth argument of a callee. */
 };
 
+/* Instruction size.  */
+#define HPPA_INSN_SIZE 4
+
 /* Target-dependent structure in gdbarch.  */
 struct gdbarch_tdep
 {
diff --git a/gdb/inf-ttrace.c b/gdb/inf-ttrace.c
index a9087afa578..fc19e90b0e1 100644
--- a/gdb/inf-ttrace.c
+++ b/gdb/inf-ttrace.c
@@ -645,28 +645,6 @@ inf_ttrace_create_inferior (char *exec_file, char *allargs, char **env,
 }
 
 static void
-inf_ttrace_kill_inferior (void)
-{
-  pid_t pid = ptid_get_pid (inferior_ptid);
-
-  if (pid == 0)
-    return;
-
-  if (ttrace (TT_PROC_EXIT, pid, 0, 0, 0, 0) == -1)
-    perror_with_name (("ttrace"));
-  /* ??? Is it necessary to call ttrace_wait() here?  */
-
-  if (inf_ttrace_vfork_ppid != -1)
-    {
-      if (ttrace (TT_PROC_DETACH, inf_ttrace_vfork_ppid, 0, 0, 0, 0) == -1)
-	perror_with_name (("ttrace"));
-      inf_ttrace_vfork_ppid = -1;
-    }
-
-  target_mourn_inferior ();
-}
-
-static void
 inf_ttrace_mourn_inferior (void)
 {
   const int num_buckets = ARRAY_SIZE (inf_ttrace_page_dict.buckets);
@@ -715,7 +693,7 @@ inf_ttrace_attach (char *args, int from_tty)
 
   if (from_tty)
     {
-      exec_file = (char *) get_exec_file (0);
+      exec_file = get_exec_file (0);
 
       if (exec_file)
 	printf_unfiltered (_("Attaching to program: %s, %s\n"), exec_file,
@@ -792,6 +770,28 @@ inf_ttrace_detach (char *args, int from_tty)
   inferior_ptid = null_ptid;
 }
 
+static void
+inf_ttrace_kill (void)
+{
+  pid_t pid = ptid_get_pid (inferior_ptid);
+
+  if (pid == 0)
+    return;
+
+  if (ttrace (TT_PROC_EXIT, pid, 0, 0, 0, 0) == -1)
+    perror_with_name (("ttrace"));
+  /* ??? Is it necessary to call ttrace_wait() here?  */
+
+  if (inf_ttrace_vfork_ppid != -1)
+    {
+      if (ttrace (TT_PROC_DETACH, inf_ttrace_vfork_ppid, 0, 0, 0, 0) == -1)
+	perror_with_name (("ttrace"));
+      inf_ttrace_vfork_ppid = -1;
+    }
+
+  target_mourn_inferior ();
+}
+
 static int
 inf_ttrace_resume_callback (struct thread_info *info, void *arg)
 {
@@ -894,6 +894,10 @@ inf_ttrace_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
 #endif
 
     case TTEVT_EXEC:
+      /* FIXME: kettenis/20051029: GDB doesn't really know how to deal
+	 with TARGET_WAITKIND_EXECD events yet.  So we make it look
+	 like a SIGTRAP instead.  */
+#if 0
       ourstatus->kind = TARGET_WAITKIND_EXECD;
       ourstatus->value.execd_pathname =
 	xmalloc (tts.tts_u.tts_exec.tts_pathlen + 1);
@@ -902,6 +906,10 @@ inf_ttrace_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
 		  tts.tts_u.tts_exec.tts_pathlen, 0) == -1)
 	perror_with_name (("ttrace"));
       ourstatus->value.execd_pathname[tts.tts_u.tts_exec.tts_pathlen] = 0;
+#else
+      ourstatus->kind = TARGET_WAITKIND_STOPPED;
+      ourstatus->value.sig = TARGET_SIGNAL_TRAP;
+#endif
       break;
 
     case TTEVT_EXIT:
@@ -1081,9 +1089,9 @@ inf_ttrace_xfer_partial (struct target_ops *ops, enum target_object object,
 static void
 inf_ttrace_files_info (struct target_ops *ignore)
 {
-  printf_unfiltered (_("\tUsing the running image of %s %s.\n"),
-		     attach_flag ? "attached" : "child",
-		     target_pid_to_str (inferior_ptid));
+  printf_filtered (_("\tUsing the running image of %s %s.\n"),
+		   attach_flag ? "attached" : "child",
+		   target_pid_to_str (inferior_ptid));
 }
 
 static int
@@ -1115,24 +1123,24 @@ inf_ttrace_target (void)
 {
   struct target_ops *t = inf_child_target ();
 
-  t->to_create_inferior = inf_ttrace_create_inferior;
-  t->to_kill = inf_ttrace_kill_inferior;
-  t->to_mourn_inferior = inf_ttrace_mourn_inferior;
   t->to_attach = inf_ttrace_attach;
   t->to_detach = inf_ttrace_detach;
   t->to_resume = inf_ttrace_resume;
   t->to_wait = inf_ttrace_wait;
-  t->to_xfer_partial = inf_ttrace_xfer_partial;
   t->to_files_info = inf_ttrace_files_info;
-  t->to_thread_alive = inf_ttrace_thread_alive;
-  t->to_pid_to_str = inf_ttrace_pid_to_str;
-  t->to_follow_fork = inf_ttrace_follow_fork;
   t->to_can_use_hw_breakpoint = inf_ttrace_can_use_hw_breakpoint;
-  t->to_region_size_ok_for_hw_watchpoint =
-    inf_ttrace_region_size_ok_for_hw_watchpoint;
   t->to_insert_watchpoint = inf_ttrace_insert_watchpoint;
   t->to_remove_watchpoint = inf_ttrace_remove_watchpoint;
   t->to_stopped_by_watchpoint = inf_ttrace_stopped_by_watchpoint;
+  t->to_region_size_ok_for_hw_watchpoint =
+    inf_ttrace_region_size_ok_for_hw_watchpoint;
+  t->to_kill = inf_ttrace_kill;
+  t->to_create_inferior = inf_ttrace_create_inferior;
+  t->to_follow_fork = inf_ttrace_follow_fork;
+  t->to_mourn_inferior = inf_ttrace_mourn_inferior;
+  t->to_thread_alive = inf_ttrace_thread_alive;
+  t->to_pid_to_str = inf_ttrace_pid_to_str;
+  t->to_xfer_partial = inf_ttrace_xfer_partial;
 
   ttrace_ops_hack = t;
   return t;
diff --git a/gdb/main.c b/gdb/main.c
index f73af20795e..5e912953da3 100644
--- a/gdb/main.c
+++ b/gdb/main.c
@@ -73,6 +73,9 @@ struct ui_file *gdb_stdtargin;
 struct ui_file *gdb_stdtarg;
 struct ui_file *gdb_stdtargerr;
 
+/* Support for the --batch-silent option.  */
+int batch_silent = 0;
+
 /* Whether to enable writing into executable and core files */
 extern int write_files;
 
@@ -254,6 +257,7 @@ captured_main (void *data)
       {"silent", no_argument, &quiet, 1},
       {"nx", no_argument, &inhibit_gdbinit, 1},
       {"n", no_argument, &inhibit_gdbinit, 1},
+      {"batch-silent", no_argument, 0, 'B'},
       {"batch", no_argument, &batch, 1},
       {"epoch", no_argument, &epoch_interface, 1},
 
@@ -379,6 +383,10 @@ captured_main (void *data)
 					     cmdsize * sizeof (*cmdarg));
 	      }
 	    break;
+	  case 'B':
+	    batch = batch_silent = 1;
+	    gdb_stdout = ui_file_new();
+	    break;
 #ifdef GDBTK
 	  case 'z':
 	    {
@@ -829,6 +837,7 @@ Options:\n\n\
   fputs_unfiltered (_("\
   -b BAUDRATE        Set serial port baud rate used for remote debugging.\n\
   --batch            Exit after processing options.\n\
+  --batch-silent     As for --batch, but suppress all gdb stdout output.\n\
   --cd=DIR           Change current directory to DIR.\n\
   --command=FILE     Execute GDB commands from FILE.\n\
   --core=COREFILE    Analyze the core dump COREFILE.\n\
diff --git a/gdb/mi/gdb-mi.el b/gdb/mi/gdb-mi.el
index ce6411ce455..b0d5a03e05c 100644
--- a/gdb/mi/gdb-mi.el
+++ b/gdb/mi/gdb-mi.el
@@ -187,7 +187,8 @@ GUD buffer (I/O of GDB)           | Locals buffer
         gdb-find-file-unhook nil
         gdb-source-file-list nil
         gdb-last-command nil
-	gdb-prompt-name nil)
+	gdb-prompt-name nil
+	gdb-buffer-fringe-width (car (window-fringes)))
   ;;
   (setq gdb-buffer-type 'gdbmi)
   ;;
diff --git a/gdb/po/gdbtext b/gdb/po/gdbtext
new file mode 100755
index 00000000000..1f80cf9eadb
--- /dev/null
+++ b/gdb/po/gdbtext
@@ -0,0 +1,38 @@
+#!/bin/sh -e
+
+if test $# -lt 3
+then
+    echo "Usage: $0 <xgettext> <package>  <directory> ..." 1>&2
+    exit 0
+fi
+
+xgettext=$1 ; shift
+package=$1 ; shift
+
+for d in "$@"
+do
+  __directories="$__directories --directory=$d"
+done
+
+for d in "$@"
+do
+  (
+      cd $d
+      find * \
+	  -name '*-stub.c' -prune -o \
+	  -name 'testsuite' -prune -o \
+	  -name 'init.c' -prune -o \
+	  -name '*.[hc]' -print
+  )
+done | ${xgettext} \
+    --default-domain=${package} \
+    --copyright-holder="Free Software Foundation, Inc." \
+    --add-comments \
+    --files-from=- \
+    --force-po \
+    --debug \
+    --language=c \
+    --keyword=_ \
+    --keyword=N_ \
+    ${__directories} \
+    -o po/${package}.pot
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 5037c11788a..9abbf5c37b6 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -1,7 +1,7 @@
 /* Target-dependent code for GDB, the GNU debugger.
 
-   Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
-   Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -381,4 +381,7 @@ enum
     ppc_spr_pbu2      = 1023
   };
 
-#endif
+/* Instruction size.  */
+#define PPC_INSN_SIZE 4
+
+#endif /* ppc-tdep.h */
diff --git a/gdb/regformats/reg-ia64.dat b/gdb/regformats/reg-ia64.dat
index 125902dfe8d..21d56645d67 100644
--- a/gdb/regformats/reg-ia64.dat
+++ b/gdb/regformats/reg-ia64.dat
@@ -473,131 +473,3 @@ expedite:ip,psr,r12,bsp,cfm
 64:
 64:
 64:
-64:nat0
-64:nat1
-64:nat2
-64:nat3
-64:nat4
-64:nat5
-64:nat6
-64:nat7
-64:nat8
-64:nat9
-64:nat10
-64:nat11
-64:nat12
-64:nat13
-64:nat14
-64:nat15
-64:nat16
-64:nat17
-64:nat18
-64:nat19
-64:nat20
-64:nat21
-64:nat22
-64:nat23
-64:nat24
-64:nat25
-64:nat26
-64:nat27
-64:nat28
-64:nat29
-64:nat30
-64:nat31
-64:nat32
-64:nat33
-64:nat34
-64:nat35
-64:nat36
-64:nat37
-64:nat38
-64:nat39
-64:nat40
-64:nat41
-64:nat42
-64:nat43
-64:nat44
-64:nat45
-64:nat46
-64:nat47
-64:nat48
-64:nat49
-64:nat50
-64:nat51
-64:nat52
-64:nat53
-64:nat54
-64:nat55
-64:nat56
-64:nat57
-64:nat58
-64:nat59
-64:nat60
-64:nat61
-64:nat62
-64:nat63
-64:nat64
-64:nat65
-64:nat66
-64:nat67
-64:nat68
-64:nat69
-64:nat70
-64:nat71
-64:nat72
-64:nat73
-64:nat74
-64:nat75
-64:nat76
-64:nat77
-64:nat78
-64:nat79
-64:nat80
-64:nat81
-64:nat82
-64:nat83
-64:nat84
-64:nat85
-64:nat86
-64:nat87
-64:nat88
-64:nat89
-64:nat90
-64:nat91
-64:nat92
-64:nat93
-64:nat94
-64:nat95
-64:nat96
-64:nat97
-64:nat98
-64:nat99
-64:nat100
-64:nat101
-64:nat102
-64:nat103
-64:nat104
-64:nat105
-64:nat106
-64:nat107
-64:nat108
-64:nat109
-64:nat110
-64:nat111
-64:nat112
-64:nat113
-64:nat114
-64:nat115
-64:nat116
-64:nat117
-64:nat118
-64:nat119
-64:nat120
-64:nat121
-64:nat122
-64:nat123
-64:nat124
-64:nat125
-64:nat126
-64:nat127
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index f6459c72117..adfb945d056 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3376,10 +3376,21 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 
   switch (info.osabi)
     {
+    case GDB_OSABI_LINUX:
+      /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
+         have altivec registers.  If not, ptrace will fail the first time it's
+         called to access one and will not be called again.  This wart will
+         be removed when Daniel Jacobowitz's proposal for autodetecting target
+         registers is implemented. */
+      if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
+        {
+          tdep->ppc_vr0_regnum = 71;
+          tdep->ppc_vrsave_regnum = 104;
+        }
+      /* Fall Thru */
     case GDB_OSABI_NETBSD_AOUT:
     case GDB_OSABI_NETBSD_ELF:
     case GDB_OSABI_UNKNOWN:
-    case GDB_OSABI_LINUX:
       set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
       frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
       set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
@@ -3420,14 +3431,6 @@ rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
   /* FIXME: Dump gdbarch_tdep.  */
 }
 
-static struct cmd_list_element *info_powerpc_cmdlist = NULL;
-
-static void
-rs6000_info_powerpc_command (char *args, int from_tty)
-{
-  help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
-}
-
 /* Initialization code.  */
 
 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog
index 2e74bc84570..c4aad6937da 100644
--- a/gdb/testsuite/ChangeLog
+++ b/gdb/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* gdb.asm/asm-source.exp: Use -e instead of --entry.
+
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* gdb.base/bfp-test.exp: Properly anchor gdb_multiple_test usage.
+
 2005-10-17  Paul Gilliam  <pgilliam@us.ibm.com>
 
         * gdb.arch/altivec-regs.exp: Adjust "info reg vrsave" and "info reg
diff --git a/gdb/testsuite/gdb.ada/array_return/p.adb b/gdb/testsuite/gdb.ada/array_return/p.adb
new file mode 100644
index 00000000000..c465d2894b4
--- /dev/null
+++ b/gdb/testsuite/gdb.ada/array_return/p.adb
@@ -0,0 +1,10 @@
+with Pck; use Pck;
+
+procedure P is
+   Small : Data_Small;
+   Large : Data_Large;
+begin
+   Small := Create_Small;
+   Large := Create_Large;
+   Small (1) := Large (1);
+end P;
diff --git a/gdb/testsuite/gdb.ada/array_return/pck.adb b/gdb/testsuite/gdb.ada/array_return/pck.adb
new file mode 100644
index 00000000000..30282d1998c
--- /dev/null
+++ b/gdb/testsuite/gdb.ada/array_return/pck.adb
@@ -0,0 +1,13 @@
+package body Pck is
+
+   function Create_Small return Data_Small is
+   begin
+      return (others => 1);
+   end Create_Small;
+
+   function Create_Large return Data_Large is
+   begin
+      return (others => 2);
+   end Create_Large;
+
+end Pck;
diff --git a/gdb/testsuite/gdb.ada/array_return/pck.ads b/gdb/testsuite/gdb.ada/array_return/pck.ads
new file mode 100644
index 00000000000..2561ac73f29
--- /dev/null
+++ b/gdb/testsuite/gdb.ada/array_return/pck.ads
@@ -0,0 +1,10 @@
+package Pck is
+
+   type Data_Small is array (1 .. 2) of Integer;
+   type Data_Large is array (1 .. 4) of Integer;
+
+   function Create_Small return Data_Small;
+   function Create_Large return Data_Large;
+
+end Pck;
+
diff --git a/gdb/testsuite/gdb.ada/arrayidx/p.adb b/gdb/testsuite/gdb.ada/arrayidx/p.adb
new file mode 100644
index 00000000000..398e34d3f9f
--- /dev/null
+++ b/gdb/testsuite/gdb.ada/arrayidx/p.adb
@@ -0,0 +1,56 @@
+--  Copyright 2005 Free Software Foundation, Inc.
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+--  MA 02110-1301, USA
+
+procedure P is
+   type Index is (One, Two, Three);
+
+   type Table is array (Integer range 1 .. 3) of Integer;
+   type ETable is array (Index) of Integer;
+   type RTable is array (Index range Two .. Three) of Integer;
+   type UTable is array (Positive range <>) of Integer;
+
+   type PTable is array (Index) of Boolean;
+   pragma Pack (PTable);
+
+   function Get_UTable (I : Integer) return UTable is
+   begin
+      return Utable'(1 => I, 2 => 2, 3 => 3);
+   end Get_UTable;
+
+   One_Two_Three : Table := (1, 2, 3);
+   E_One_Two_Three : ETable := (1, 2, 3);
+   R_Two_Three : RTable := (2, 3);
+   U_One_Two_Three : UTable := Get_UTable (1);
+   P_One_Two_Three : PTable := (False, True, True);
+
+   Few_Reps : UTable := (1, 2, 3, 3, 3, 3, 3, 4, 5);
+   Many_Reps : UTable := (1, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5);
+
+   Empty : array (1 .. 0) of Integer := (others => 0);
+
+begin
+   One_Two_Three (1) := 4;  --  START
+   E_One_Two_Three (One) := 4;
+   R_Two_Three (Two) := 4;
+   U_One_Two_Three (U_One_Two_Three'First) := 4;
+   P_One_Two_Three (One) := True;
+
+   Few_Reps (Few_Reps'First) := 2;
+   Many_Reps (Many_Reps'First) := 2;
+
+   Empty := (others => 1);
+end P;
diff --git a/gdb/testsuite/gdb.asm/asm-source.exp b/gdb/testsuite/gdb.asm/asm-source.exp
index 2477e247eaa..5abe8eeae9e 100644
--- a/gdb/testsuite/gdb.asm/asm-source.exp
+++ b/gdb/testsuite/gdb.asm/asm-source.exp
@@ -34,7 +34,7 @@ set bug_id 0
 set asm-arch ""
 set asm-note "empty"
 set asm-flags ""
-set link-flags "--entry _start"
+set link-flags "-e _start"
 set debug-flags ""
 
 switch -glob -- [istarget] {
diff --git a/gdb/testsuite/gdb.base/bfp-test.exp b/gdb/testsuite/gdb.base/bfp-test.exp
index 43bf18753db..85f2028346e 100644
--- a/gdb/testsuite/gdb.base/bfp-test.exp
+++ b/gdb/testsuite/gdb.base/bfp-test.exp
@@ -59,7 +59,7 @@ gdb_test_multiple "set var b32=10.5f" "$test" {
     -re "$gdb_prompt $" {
 	pass "$test"
     }
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	fail "$test (do not recognize 10.5f)"
     }
 }
@@ -69,7 +69,7 @@ gdb_test_multiple "set var b64=20.25f" "$test" {
     -re "$gdb_prompt $" {
 	pass "$test"
     }
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	fail "$test (do not recognize 20.25f)"
     }
 }
@@ -79,7 +79,7 @@ gdb_test_multiple "set var b128=30.375l" "$test" {
     -re "$gdb_prompt $" {
 	pass "$test"
     }
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	fail "$test (do not recognize 30.375l)"
     }
 }
@@ -92,7 +92,7 @@ gdb_test "print b128" ".*9 = 30\.375.*" "The value of b128 is changed to 30.375"
 
 set test "set variable b32 = 100.5a"
 gdb_test_multiple "set var b32=100.5a" "$test" {
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	pass "$test"
     }
     -re "$gdb_prompt $" {
@@ -102,7 +102,7 @@ gdb_test_multiple "set var b32=100.5a" "$test" {
 
 set test "set variable b64 = 200.25x"
 gdb_test_multiple "set var b64=200.25x" "$test" {
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	pass "$test"
     }
     -re "$gdb_prompt $" {
@@ -112,7 +112,7 @@ gdb_test_multiple "set var b64=200.25x" "$test" {
 
 set test "set variable b128 = 300.375fl"
 gdb_test_multiple "set var b128=300.375fl" "$test" {
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	pass "$test"
     }
     -re "$gdb_prompt $" {
@@ -122,7 +122,7 @@ gdb_test_multiple "set var b128=300.375fl" "$test" {
 
 set test "set variable b128 = 300.375fff"
 gdb_test_multiple "set var b128=300.375fff" "$test" {
-    -re "Invalid number" {
+    -re "Invalid number.*$gdb_prompt $" {
 	pass "$test"
     }
     -re "$gdb_prompt $" {
diff --git a/gdb/tui/tui-command.c b/gdb/tui/tui-command.c
index 399ef85b8c5..7f3fc7599b2 100644
--- a/gdb/tui/tui-command.c
+++ b/gdb/tui/tui-command.c
@@ -68,33 +68,36 @@ tui_dispatch_ctrl_char (unsigned int ch)
          ** Seems like a bug in the curses library?
        */
       term = (char *) getenv ("TERM");
-      for (i = 0; (term && term[i]); i++)
-	term[i] = toupper (term[i]);
-      if ((strcmp (term, "XTERM") == 0) && key_is_start_sequence (ch))
+      if (term)
 	{
-	  unsigned int page_ch = 0;
-	  unsigned int tmp_char;
-
-	  tmp_char = 0;
-	  while (!key_is_end_sequence (tmp_char))
+	  for (i = 0; term[i]; i++)
+	    term[i] = toupper (term[i]);
+	  if ((strcmp (term, "XTERM") == 0) && key_is_start_sequence (ch))
 	    {
-	      tmp_char = (int) wgetch (w);
-	      if (tmp_char == ERR)
-		{
-		  return ch;
-		}
-	      if (!tmp_char)
-		break;
-	      if (tmp_char == 53)
-		page_ch = KEY_PPAGE;
-	      else if (tmp_char == 54)
-		page_ch = KEY_NPAGE;
-	      else
+	      unsigned int page_ch = 0;
+	      unsigned int tmp_char;
+
+	      tmp_char = 0;
+	      while (!key_is_end_sequence (tmp_char))
 		{
-		  return 0;
+		  tmp_char = (int) wgetch (w);
+		  if (tmp_char == ERR)
+		    {
+		      return ch;
+		    }
+		  if (!tmp_char)
+		    break;
+		  if (tmp_char == 53)
+		    page_ch = KEY_PPAGE;
+		  else if (tmp_char == 54)
+		    page_ch = KEY_NPAGE;
+		  else
+		    {
+		      return 0;
+		    }
 		}
+	      ch_copy = page_ch;
 	    }
-	  ch_copy = page_ch;
 	}
 
       switch (ch_copy)
diff --git a/gdb/tui/tui-data.c b/gdb/tui/tui-data.c
index 800d72a069f..746e85b8ce5 100644
--- a/gdb/tui/tui-data.c
+++ b/gdb/tui/tui-data.c
@@ -207,7 +207,8 @@ tui_clear_win_detail (struct tui_win_info * win_info)
 	{
 	case SRC_WIN:
 	case DISASSEM_WIN:
-	  win_info->detail.source_info.start_line_or_addr.addr = 0;
+	  win_info->detail.source_info.start_line_or_addr.loa = LOA_ADDRESS;
+	  win_info->detail.source_info.start_line_or_addr.u.addr = 0;
 	  win_info->detail.source_info.horizontal_offset = 0;
 	  break;
 	case CMD_WIN:
@@ -486,7 +487,8 @@ init_content_element (struct tui_win_element * element, enum tui_win_type type)
     case SRC_WIN:
     case DISASSEM_WIN:
       element->which_element.source.line = (char *) NULL;
-      element->which_element.source.line_or_addr.line_no = 0;
+      element->which_element.source.line_or_addr.loa = LOA_LINE;
+      element->which_element.source.line_or_addr.u.line_no = 0;
       element->which_element.source.is_exec_point = FALSE;
       element->which_element.source.has_break = FALSE;
       break;
@@ -537,7 +539,8 @@ init_win_info (struct tui_win_info * win_info)
       win_info->detail.source_info.execution_info = (struct tui_gen_win_info *) NULL;
       win_info->detail.source_info.has_locator = FALSE;
       win_info->detail.source_info.horizontal_offset = 0;
-      win_info->detail.source_info.start_line_or_addr.addr = 0;
+      win_info->detail.source_info.start_line_or_addr.loa = LOA_ADDRESS;
+      win_info->detail.source_info.start_line_or_addr.u.addr = 0;
       win_info->detail.source_info.filename = 0;
       break;
     case DATA_WIN:
diff --git a/gdb/tui/tui-data.h b/gdb/tui/tui-data.h
index 02bebb4e2be..4a6c4133151 100644
--- a/gdb/tui/tui-data.h
+++ b/gdb/tui/tui-data.h
@@ -147,10 +147,14 @@ enum tui_register_display_type
 };
 
 /* Structure describing source line or line address */
-union tui_line_or_address
+struct tui_line_or_address
 {
-  int line_no;
-  CORE_ADDR addr;
+  enum { LOA_LINE, LOA_ADDRESS } loa;
+  union
+    {
+      int line_no;
+      CORE_ADDR addr;
+    } u;
 };
 
 /* Current Layout definition */
@@ -166,7 +170,7 @@ struct tui_layout_def
 struct tui_source_element
 {
   char *line;
-  union tui_line_or_address line_or_addr;
+  struct tui_line_or_address line_or_addr;
   int is_exec_point;
   int has_break;
 };
@@ -259,7 +263,7 @@ struct tui_source_info
   /* Execution information window.  */
   struct tui_gen_win_info *execution_info;
   int horizontal_offset;	/* used for horizontal scroll */
-  union tui_line_or_address start_line_or_addr;
+  struct tui_line_or_address start_line_or_addr;
   char* filename;
 };
 
diff --git a/gdb/tui/tui-disasm.c b/gdb/tui/tui-disasm.c
index 9c3072bf74e..aa5a62caac3 100644
--- a/gdb/tui/tui-disasm.c
+++ b/gdb/tui/tui-disasm.c
@@ -188,7 +188,8 @@ tui_set_disassem_content (CORE_ADDR pc)
   if (ret != TUI_SUCCESS)
     return ret;
 
-  TUI_DISASM_WIN->detail.source_info.start_line_or_addr.addr = pc;
+  TUI_DISASM_WIN->detail.source_info.start_line_or_addr.loa = LOA_ADDRESS;
+  TUI_DISASM_WIN->detail.source_info.start_line_or_addr.u.addr = pc;
   cur_pc = (CORE_ADDR)
     (((struct tui_win_element *) locator->content[0])->which_element.locator.addr);
 
@@ -249,7 +250,8 @@ tui_set_disassem_content (CORE_ADDR pc)
       else
         src->line[0] = '\0';
 
-      src->line_or_addr.addr = asm_lines[i].addr;
+      src->line_or_addr.loa = LOA_ADDRESS;
+      src->line_or_addr.u.addr = asm_lines[i].addr;
       src->is_exec_point = asm_lines[i].addr == cur_pc;
 
       /* See whether there is a breakpoint installed.  */
@@ -270,9 +272,10 @@ tui_show_disassem (CORE_ADDR start_addr)
 {
   struct symtab *s = find_pc_symtab (start_addr);
   struct tui_win_info * win_with_focus = tui_win_with_focus ();
-  union tui_line_or_address val;
+  struct tui_line_or_address val;
 
-  val.addr = start_addr;
+  val.loa = LOA_ADDRESS;
+  val.u.addr = start_addr;
   tui_add_win_to_layout (DISASSEM_WIN);
   tui_update_source_window (TUI_DISASM_WIN, s, val, FALSE);
   /*
@@ -295,14 +298,15 @@ tui_show_disassem_and_update_source (CORE_ADDR start_addr)
   tui_show_disassem (start_addr);
   if (tui_current_layout () == SRC_DISASSEM_COMMAND)
     {
-      union tui_line_or_address val;
+      struct tui_line_or_address val;
 
       /*
          ** Update what is in the source window if it is displayed too,
          ** note that it follows what is in the disassembly window and visa-versa
        */
       sal = find_pc_line (start_addr, 0);
-      val.line_no = sal.line;
+      val.loa = LOA_LINE;
+      val.u.line_no = sal.line;
       tui_update_source_window (TUI_SRC_WIN, sal.symtab, val, TRUE);
       if (sal.symtab)
 	{
@@ -376,7 +380,7 @@ tui_vertical_disassem_scroll (enum tui_scroll_direction scroll_direction,
       CORE_ADDR pc;
       tui_win_content content;
       struct symtab *s;
-      union tui_line_or_address val;
+      struct tui_line_or_address val;
       int max_lines, dir;
       struct symtab_and_line cursal = get_current_source_symtab_and_line ();
 
@@ -388,10 +392,11 @@ tui_vertical_disassem_scroll (enum tui_scroll_direction scroll_direction,
 
       /* account for hilite */
       max_lines = TUI_DISASM_WIN->generic.height - 2;
-      pc = content[0]->which_element.source.line_or_addr.addr;
+      pc = content[0]->which_element.source.line_or_addr.u.addr;
       dir = (scroll_direction == FORWARD_SCROLL) ? max_lines : - max_lines;
 
-      val.addr = tui_find_disassembly_address (pc, dir);
+      val.loa = LOA_ADDRESS;
+      val.u.addr = tui_find_disassembly_address (pc, dir);
       tui_update_source_window_as_is (TUI_DISASM_WIN, s, val, FALSE);
     }
 }
diff --git a/gdb/tui/tui-layout.c b/gdb/tui/tui-layout.c
index d2d8efe11b2..5b6553388cc 100644
--- a/gdb/tui/tui-layout.c
+++ b/gdb/tui/tui-layout.c
@@ -519,14 +519,14 @@ extract_display_start_addr (void)
     case SRC_COMMAND:
     case SRC_DATA_COMMAND:
       find_line_pc (cursal.symtab,
-		    TUI_SRC_WIN->detail.source_info.start_line_or_addr.line_no,
+		    TUI_SRC_WIN->detail.source_info.start_line_or_addr.u.line_no,
 		    &pc);
       addr = pc;
       break;
     case DISASSEM_COMMAND:
     case SRC_DISASSEM_COMMAND:
     case DISASSEM_DATA_COMMAND:
-      addr = TUI_DISASM_WIN->detail.source_info.start_line_or_addr.addr;
+      addr = TUI_DISASM_WIN->detail.source_info.start_line_or_addr.u.addr;
       break;
     default:
       addr = 0;
diff --git a/gdb/tui/tui-source.c b/gdb/tui/tui-source.c
index d5154b11da1..2710f98b649 100644
--- a/gdb/tui/tui-source.c
+++ b/gdb/tui/tui-source.c
@@ -106,7 +106,8 @@ tui_set_source_content (struct symtab *s, int line_no, int noerror)
 		  stream = fdopen (desc, FOPEN_RT);
 		  clearerr (stream);
 		  cur_line = 0;
-		  cur_line_no = src->start_line_or_addr.line_no = line_no;
+		  src->start_line_or_addr.loa = LOA_LINE;
+		  cur_line_no = src->start_line_or_addr.u.line_no = line_no;
 		  if (offset > 0)
 		    src_line = (char *) xmalloc (
 					   (threshold + 1) * sizeof (char));
@@ -137,7 +138,9 @@ tui_set_source_content (struct symtab *s, int line_no, int noerror)
 
 		      /* Set whether element is the execution point and
 		         whether there is a break point on it.  */
-		      element->which_element.source.line_or_addr.line_no =
+		      element->which_element.source.line_or_addr.loa =
+			LOA_LINE;
+		      element->which_element.source.line_or_addr.u.line_no =
 			cur_line_no;
 		      element->which_element.source.is_exec_point =
 			(strcmp (((struct tui_win_element *)
@@ -247,7 +250,8 @@ tui_set_source_content_nil (struct tui_win_info * win_info, char *warning_string
 
       struct tui_win_element * element =
       (struct tui_win_element *) win_info->generic.content[curr_line];
-      element->which_element.source.line_or_addr.line_no = 0;
+      element->which_element.source.line_or_addr.loa = LOA_LINE;
+      element->which_element.source.line_or_addr.u.line_no = 0;
       element->which_element.source.is_exec_point = FALSE;
       element->which_element.source.has_break = FALSE;
 
@@ -295,7 +299,7 @@ tui_set_source_content_nil (struct tui_win_info * win_info, char *warning_string
 /* Function to display source in the source window.  This function
    initializes the horizontal scroll to 0.  */
 void
-tui_show_symtab_source (struct symtab *s, union tui_line_or_address line, int noerror)
+tui_show_symtab_source (struct symtab *s, struct tui_line_or_address line, int noerror)
 {
   TUI_SRC_WIN->detail.source_info.horizontal_offset = 0;
   tui_update_source_window_as_is (TUI_SRC_WIN, s, line, noerror);
@@ -320,7 +324,7 @@ tui_vertical_source_scroll (enum tui_scroll_direction scroll_direction,
 {
   if (TUI_SRC_WIN->generic.content != NULL)
     {
-      union tui_line_or_address l;
+      struct tui_line_or_address l;
       struct symtab *s;
       tui_win_content content = (tui_win_content) TUI_SRC_WIN->generic.content;
       struct symtab_and_line cursal = get_current_source_symtab_and_line ();
@@ -330,23 +334,24 @@ tui_vertical_source_scroll (enum tui_scroll_direction scroll_direction,
       else
 	s = cursal.symtab;
 
+      l.loa = LOA_LINE;
       if (scroll_direction == FORWARD_SCROLL)
 	{
-	  l.line_no = content[0]->which_element.source.line_or_addr.line_no +
-	    num_to_scroll;
-	  if (l.line_no > s->nlines)
+	  l.u.line_no = content[0]->which_element.source.line_or_addr.u.line_no
+	    + num_to_scroll;
+	  if (l.u.line_no > s->nlines)
 	    /*line = s->nlines - win_info->generic.content_size + 1; */
 	    /*elz: fix for dts 23398 */
-	    l.line_no = content[0]->which_element.source.line_or_addr.line_no;
+	    l.u.line_no = content[0]->which_element.source.line_or_addr.u.line_no;
 	}
       else
 	{
-	  l.line_no = content[0]->which_element.source.line_or_addr.line_no -
-	    num_to_scroll;
-	  if (l.line_no <= 0)
-	    l.line_no = 1;
+	  l.u.line_no = content[0]->which_element.source.line_or_addr.u.line_no
+	    - num_to_scroll;
+	  if (l.u.line_no <= 0)
+	    l.u.line_no = 1;
 	}
 
-      print_source_lines (s, l.line_no, l.line_no + 1, 0);
+      print_source_lines (s, l.u.line_no, l.u.line_no + 1, 0);
     }
 }
diff --git a/gdb/tui/tui-source.h b/gdb/tui/tui-source.h
index 3b61ca4374d..4e49488ddc9 100644
--- a/gdb/tui/tui-source.h
+++ b/gdb/tui/tui-source.h
@@ -33,7 +33,7 @@ struct tui_win_info;
 extern void tui_set_source_content_nil (struct tui_win_info *, char *);
 
 extern enum tui_status tui_set_source_content (struct symtab *, int, int);
-extern void tui_show_symtab_source (struct symtab *, union tui_line_or_address, int);
+extern void tui_show_symtab_source (struct symtab *, struct tui_line_or_address, int);
 extern int tui_source_is_displayed (char *);
 extern void tui_vertical_source_scroll (enum tui_scroll_direction, int);
 
diff --git a/gdb/tui/tui-stack.c b/gdb/tui/tui-stack.c
index c0a1b82c0c1..bba77fdcb23 100644
--- a/gdb/tui/tui-stack.c
+++ b/gdb/tui/tui-stack.c
@@ -364,14 +364,15 @@ tui_show_frame_info (struct frame_info *fi)
 
 	  if (win_info == TUI_SRC_WIN)
 	    {
-	      union tui_line_or_address l;
-	      l.line_no = start_line;
+	      struct tui_line_or_address l;
+	      l.loa = LOA_LINE;
+	      l.u.line_no = start_line;
 	      if (!(source_already_displayed
 		    && tui_line_is_displayed (item->locator.line_no, win_info, TRUE)))
 		tui_update_source_window (win_info, sal.symtab, l, TRUE);
 	      else
 		{
-		  l.line_no = item->locator.line_no;
+		  l.u.line_no = item->locator.line_no;
 		  tui_set_is_exec_point_at (l, win_info);
 		}
 	    }
@@ -379,13 +380,14 @@ tui_show_frame_info (struct frame_info *fi)
 	    {
 	      if (win_info == TUI_DISASM_WIN)
 		{
-		  union tui_line_or_address a;
-		  a.addr = low;
+		  struct tui_line_or_address a;
+		  a.loa = LOA_ADDRESS;
+		  a.u.addr = low;
 		  if (!tui_addr_is_displayed (item->locator.addr, win_info, TRUE))
 		    tui_update_source_window (win_info, sal.symtab, a, TRUE);
 		  else
 		    {
-		      a.addr = item->locator.addr;
+		      a.u.addr = item->locator.addr;
 		      tui_set_is_exec_point_at (a, win_info);
 		    }
 		}
diff --git a/gdb/tui/tui-win.c b/gdb/tui/tui-win.c
index cdd2550d2ce..739c53c7d6e 100644
--- a/gdb/tui/tui-win.c
+++ b/gdb/tui/tui-win.c
@@ -1322,31 +1322,30 @@ make_visible_with_new_height (struct tui_win_info * win_info)
       tui_make_visible (win_info->detail.source_info.execution_info);
       if (win_info->generic.content != NULL)
 	{
-	  union tui_line_or_address line_or_addr;
+	  struct tui_line_or_address line_or_addr;
 	  struct symtab_and_line cursal
 	    = get_current_source_symtab_and_line ();
 
-	  if (win_info->generic.type == SRC_WIN)
-	    line_or_addr.line_no =
-	      win_info->detail.source_info.start_line_or_addr.line_no;
-	  else
-	    line_or_addr.addr =
-	      win_info->detail.source_info.start_line_or_addr.addr;
+	  line_or_addr = win_info->detail.source_info.start_line_or_addr;
 	  tui_free_win_content (&win_info->generic);
 	  tui_update_source_window (win_info, cursal.symtab, line_or_addr, TRUE);
 	}
       else if (deprecated_selected_frame != (struct frame_info *) NULL)
 	{
-	  union tui_line_or_address line;
+	  struct tui_line_or_address line;
 	  struct symtab_and_line cursal = get_current_source_symtab_and_line ();
 
 
 	  s = find_pc_symtab (get_frame_pc (deprecated_selected_frame));
 	  if (win_info->generic.type == SRC_WIN)
-	    line.line_no = cursal.line;
+	    {
+	      line.loa = LOA_LINE;
+	      line.u.line_no = cursal.line;
+	    }
 	  else
 	    {
-	      find_line_pc (s, cursal.line, &line.addr);
+	      line.loa = LOA_ADDRESS;
+	      find_line_pc (s, cursal.line, &line.u.addr);
 	    }
 	  tui_update_source_window (win_info, s, line, TRUE);
 	}
diff --git a/gdb/tui/tui-winsource.c b/gdb/tui/tui-winsource.c
index de19d25c239..d5c786d1e61 100644
--- a/gdb/tui/tui-winsource.c
+++ b/gdb/tui/tui-winsource.c
@@ -41,6 +41,7 @@
 
 #include "gdb_string.h"
 #include "gdb_curses.h"
+#include "gdb_assert.h"
 
 /* Function to display the "main" routine.  */
 void
@@ -71,7 +72,7 @@ tui_display_main (void)
    initializes the horizontal scroll to 0.  */
 void
 tui_update_source_window (struct tui_win_info * win_info, struct symtab *s,
-			  union tui_line_or_address line_or_addr, int noerror)
+			  struct tui_line_or_address line_or_addr, int noerror)
 {
   win_info->detail.source_info.horizontal_offset = 0;
   tui_update_source_window_as_is (win_info, s, line_or_addr, noerror);
@@ -84,14 +85,14 @@ tui_update_source_window (struct tui_win_info * win_info, struct symtab *s,
    shows the source as specified by the horizontal offset.  */
 void
 tui_update_source_window_as_is (struct tui_win_info * win_info, struct symtab *s,
-				union tui_line_or_address line_or_addr, int noerror)
+				struct tui_line_or_address line_or_addr, int noerror)
 {
   enum tui_status ret;
 
   if (win_info->generic.type == SRC_WIN)
-    ret = tui_set_source_content (s, line_or_addr.line_no, noerror);
+    ret = tui_set_source_content (s, line_or_addr.u.line_no, noerror);
   else
-    ret = tui_set_disassem_content (line_or_addr.addr);
+    ret = tui_set_disassem_content (line_or_addr.u.addr);
 
   if (ret == TUI_FAILURE)
     {
@@ -107,7 +108,7 @@ tui_update_source_window_as_is (struct tui_win_info * win_info, struct symtab *s
 	{
 	  struct symtab_and_line sal;
 	  
-	  sal.line = line_or_addr.line_no +
+	  sal.line = line_or_addr.u.line_no +
 	    (win_info->generic.content_size - 2);
 	  sal.symtab = s;
 	  set_current_source_symtab_and_line (&sal);
@@ -134,7 +135,7 @@ tui_update_source_windows_with_addr (CORE_ADDR addr)
   if (addr != 0)
     {
       struct symtab_and_line sal;
-      union tui_line_or_address l;
+      struct tui_line_or_address l;
       
       switch (tui_current_layout ())
 	{
@@ -147,7 +148,8 @@ tui_update_source_windows_with_addr (CORE_ADDR addr)
 	  break;
 	default:
 	  sal = find_pc_line (addr, 0);
-	  l.line_no = sal.line;
+	  l.loa = LOA_LINE;
+	  l.u.line_no = sal.line;
 	  tui_show_symtab_source (sal.symtab, l, FALSE);
 	  break;
 	}
@@ -172,7 +174,7 @@ void
 tui_update_source_windows_with_line (struct symtab *s, int line)
 {
   CORE_ADDR pc;
-  union tui_line_or_address l;
+  struct tui_line_or_address l;
   
   switch (tui_current_layout ())
     {
@@ -182,7 +184,8 @@ tui_update_source_windows_with_line (struct symtab *s, int line)
       tui_update_source_windows_with_addr (pc);
       break;
     default:
-      l.line_no = line;
+      l.loa = LOA_LINE;
+      l.u.line_no = line;
       tui_show_symtab_source (s, l, FALSE);
       if (tui_current_layout () == SRC_DISASSEM_COMMAND)
 	{
@@ -336,7 +339,7 @@ tui_horizontal_source_scroll (struct tui_win_info * win_info,
 
 /* Set or clear the has_break flag in the line whose line is line_no.  */
 void
-tui_set_is_exec_point_at (union tui_line_or_address l, struct tui_win_info * win_info)
+tui_set_is_exec_point_at (struct tui_line_or_address l, struct tui_win_info * win_info)
 {
   int changed = 0;
   int i;
@@ -346,8 +349,15 @@ tui_set_is_exec_point_at (union tui_line_or_address l, struct tui_win_info * win
   while (i < win_info->generic.content_size)
     {
       int new_state;
-
-      if (content[i]->which_element.source.line_or_addr.addr == l.addr)
+      struct tui_line_or_address content_loa =
+	content[i]->which_element.source.line_or_addr;
+
+      gdb_assert (l.loa == LOA_ADDRESS || l.loa == LOA_LINE);
+      gdb_assert (content_loa.loa == LOA_LINE
+		  || content_loa.loa == LOA_ADDRESS);
+      if (content_loa.loa == l.loa
+	  && ((l.loa == LOA_LINE && content_loa.u.line_no == l.u.line_no)
+              || (content_loa.u.addr == l.u.addr)))
         new_state = TRUE;
       else
 	new_state = FALSE;
@@ -414,12 +424,16 @@ tui_update_breakpoint_info (struct tui_win_info * win, int current_only)
            bp != (struct breakpoint *) NULL;
            bp = bp->next)
         {
+	  gdb_assert (line->line_or_addr.loa == LOA_LINE
+		      || line->line_or_addr.loa == LOA_ADDRESS);
           if ((win == TUI_SRC_WIN
                && bp->source_file
                && (strcmp (src->filename, bp->source_file) == 0)
-               && bp->line_number == line->line_or_addr.line_no)
+	       && line->line_or_addr.loa == LOA_LINE
+               && bp->line_number == line->line_or_addr.u.line_no)
               || (win == TUI_DISASM_WIN
-                  && bp->loc->address == line->line_or_addr.addr))
+		  && line->line_or_addr.loa == LOA_ADDRESS
+                  && bp->loc->address == line->line_or_addr.u.addr))
             {
               if (bp->enable_state == bp_disabled)
                 mode |= TUI_BP_DISABLED;
@@ -614,8 +628,11 @@ tui_line_is_displayed (int line, struct tui_win_info * win_info,
   while (i < win_info->generic.content_size - threshold && !is_displayed)
     {
       is_displayed = (((struct tui_win_element *)
-		      win_info->generic.content[i])->which_element.source.line_or_addr.line_no
-		     == (int) line);
+		      win_info->generic.content[i])->which_element.source.line_or_addr.loa
+		      == LOA_LINE)
+		     && (((struct tui_win_element *)
+		      win_info->generic.content[i])->which_element.source.line_or_addr.u.line_no
+		      == (int) line);
       i++;
     }
 
@@ -640,8 +657,11 @@ tui_addr_is_displayed (CORE_ADDR addr, struct tui_win_info * win_info,
   while (i < win_info->generic.content_size - threshold && !is_displayed)
     {
       is_displayed = (((struct tui_win_element *)
-		      win_info->generic.content[i])->which_element.source.line_or_addr.addr
-		     == addr);
+		      win_info->generic.content[i])->which_element.source.line_or_addr.loa
+		      == LOA_ADDRESS)
+		     && (((struct tui_win_element *)
+		      win_info->generic.content[i])->which_element.source.line_or_addr.u.addr
+		      == addr);
       i++;
     }
 
diff --git a/gdb/tui/tui-winsource.h b/gdb/tui/tui-winsource.h
index e64589ba5f2..d45c5891b17 100644
--- a/gdb/tui/tui-winsource.h
+++ b/gdb/tui/tui-winsource.h
@@ -43,10 +43,10 @@ extern int tui_update_breakpoint_info (struct tui_win_info * win,
 /* Function to display the "main" routine.  */
 extern void tui_display_main (void);
 extern void tui_update_source_window (struct tui_win_info *, struct symtab *,
-				      union tui_line_or_address, int);
+				      struct  tui_line_or_address, int);
 extern void tui_update_source_window_as_is (struct tui_win_info *,
 					    struct symtab *,
-					    union tui_line_or_address, int);
+					    struct  tui_line_or_address, int);
 extern void tui_update_source_windows_with_addr (CORE_ADDR);
 extern void tui_update_source_windows_with_line (struct symtab *, int);
 extern void tui_clear_source_content (struct tui_win_info *, int);
@@ -60,7 +60,7 @@ extern void tui_erase_exec_info_content (struct tui_win_info *);
 extern void tui_clear_exec_info_content (struct tui_win_info *);
 extern void tui_update_exec_info (struct tui_win_info *);
 
-extern void tui_set_is_exec_point_at (union tui_line_or_address,
+extern void tui_set_is_exec_point_at (struct  tui_line_or_address,
 				      struct tui_win_info *);
 extern enum tui_status tui_alloc_source_buffer (struct tui_win_info *);
 extern int tui_line_is_displayed (int, struct tui_win_info *, int);
diff --git a/gdb/vax-tdep.c b/gdb/vax-tdep.c
index 58d82964fbe..625918c1cf9 100644
--- a/gdb/vax-tdep.c
+++ b/gdb/vax-tdep.c
@@ -23,6 +23,7 @@
 #include "defs.h"
 #include "arch-utils.h"
 #include "dis-asm.h"
+#include "floatformat.h"
 #include "frame.h"
 #include "frame-base.h"
 #include "frame-unwind.h"
@@ -476,6 +477,11 @@ vax_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 
   gdbarch = gdbarch_alloc (&info, NULL);
 
+  set_gdbarch_float_format (gdbarch, &floatformat_vax_f);
+  set_gdbarch_double_format (gdbarch, &floatformat_vax_d);
+  set_gdbarch_long_double_format (gdbarch, &floatformat_vax_d);
+  set_gdbarch_long_double_bit(gdbarch, 64);
+
   /* Register info */
   set_gdbarch_num_regs (gdbarch, VAX_NUM_REGS);
   set_gdbarch_register_name (gdbarch, vax_register_name);
diff --git a/gdb/version.in b/gdb/version.in
index 1c599bc2b80..338ce0a81d1 100644
--- a/gdb/version.in
+++ b/gdb/version.in
@@ -1 +1 @@
-6.3.50.20051020-cvs
+6.3.50.20051101-cvs
diff --git a/gdb/win32-nat.c b/gdb/win32-nat.c
index d9525727479..81c115f898f 100644
--- a/gdb/win32-nat.c
+++ b/gdb/win32-nat.c
@@ -53,10 +53,15 @@
 #include <sys/param.h>
 #include <unistd.h>
 #include "exec.h"
+#include "solist.h"
+#include "solib.h"
 
 #include "i386-tdep.h"
 #include "i387-tdep.h"
 
+static struct target_ops win32_ops;
+static struct target_so_ops win32_so_ops;
+
 /* If we're not using the old Cygwin header file set, define the
    following which never should have been in the generic Win32 API
    headers in the first place since they were our own invention... */
@@ -79,7 +84,9 @@ static int debug_registers_used;
 
 /* The string sent by cygwin when it processes a signal.
    FIXME: This should be in a cygwin include file. */
-#define CYGWIN_SIGNAL_STRING "cygwin: signal"
+#ifndef _CYGWIN_SIGNAL_STRING
+#define _CYGWIN_SIGNAL_STRING "cYgSiGw00f"
+#endif
 
 #define CHECK(x)	check (x, __FILE__,__LINE__)
 #define DEBUG_EXEC(x)	if (debug_exec)		printf_unfiltered x
@@ -87,9 +94,9 @@ static int debug_registers_used;
 #define DEBUG_MEM(x)	if (debug_memory)	printf_unfiltered x
 #define DEBUG_EXCEPT(x)	if (debug_exceptions)	printf_unfiltered x
 
-static void child_stop (void);
-static int win32_child_thread_alive (ptid_t);
-void child_kill_inferior (void);
+static void win32_stop (void);
+static int win32_win32_thread_alive (ptid_t);
+static void win32_kill_inferior (void);
 
 static enum target_signal last_sig = TARGET_SIGNAL_0;
 /* Set if a signal was received from the debugged process */
@@ -251,15 +258,14 @@ thread_rec (DWORD id, int get_context)
 
 /* Add a thread to the thread list */
 static thread_info *
-child_add_thread (DWORD id, HANDLE h)
+win32_add_thread (DWORD id, HANDLE h)
 {
   thread_info *th;
 
   if ((th = thread_rec (id, FALSE)))
     return th;
 
-  th = (thread_info *) xmalloc (sizeof (*th));
-  memset (th, 0, sizeof (*th));
+  th = XZALLOC (thread_info);
   th->id = id;
   th->h = h;
   th->next = thread_head.next;
@@ -287,11 +293,11 @@ child_add_thread (DWORD id, HANDLE h)
 /* Clear out any old thread list and reintialize it to a
    pristine state. */
 static void
-child_init_thread_list (void)
+win32_init_thread_list (void)
 {
   thread_info *th = &thread_head;
 
-  DEBUG_EVENTS (("gdb: child_init_thread_list\n"));
+  DEBUG_EVENTS (("gdb: win32_init_thread_list\n"));
   init_thread_list ();
   while (th->next != NULL)
     {
@@ -305,7 +311,7 @@ child_init_thread_list (void)
 
 /* Delete a thread from the list of threads */
 static void
-child_delete_thread (DWORD id)
+win32_delete_thread (DWORD id)
 {
   thread_info *th;
 
@@ -328,7 +334,7 @@ child_delete_thread (DWORD id)
 }
 
 static void
-do_child_fetch_inferior_registers (int r)
+do_win32_fetch_inferior_registers (int r)
 {
   char *context_offset = ((char *) &current_thread->context) + mappings[r];
   long l;
@@ -369,24 +375,24 @@ do_child_fetch_inferior_registers (int r)
   else
     {
       for (r = 0; r < NUM_REGS; r++)
-	do_child_fetch_inferior_registers (r);
+	do_win32_fetch_inferior_registers (r);
     }
 
 #undef I387_ST0_REGNUM
 }
 
 static void
-child_fetch_inferior_registers (int r)
+win32_fetch_inferior_registers (int r)
 {
   current_thread = thread_rec (PIDGET (inferior_ptid), TRUE);
   /* Check if current_thread exists.  Windows sometimes uses a non-existent
      thread id in its events */
   if (current_thread)
-    do_child_fetch_inferior_registers (r);
+    do_win32_fetch_inferior_registers (r);
 }
 
 static void
-do_child_store_inferior_registers (int r)
+do_win32_store_inferior_registers (int r)
 {
   if (!current_thread)
     /* Windows sometimes uses a non-existent thread id in its events */;
@@ -396,19 +402,19 @@ do_child_store_inferior_registers (int r)
   else
     {
       for (r = 0; r < NUM_REGS; r++)
-	do_child_store_inferior_registers (r);
+	do_win32_store_inferior_registers (r);
     }
 }
 
 /* Store a new register value into the current thread context */
 static void
-child_store_inferior_registers (int r)
+win32_store_inferior_registers (int r)
 {
   current_thread = thread_rec (PIDGET (inferior_ptid), TRUE);
   /* Check if current_thread exists.  Windows sometimes uses a non-existent
      thread id in its events */
   if (current_thread)
-    do_child_store_inferior_registers (r);
+    do_win32_store_inferior_registers (r);
 }
 
 static int psapi_loaded = 0;
@@ -417,7 +423,7 @@ static BOOL WINAPI (*psapi_EnumProcessModules) (HANDLE, HMODULE *, DWORD, LPDWOR
 static BOOL WINAPI (*psapi_GetModuleInformation) (HANDLE, HMODULE, LPMODULEINFO, DWORD) = NULL;
 static DWORD WINAPI (*psapi_GetModuleFileNameExA) (HANDLE, HMODULE, LPSTR, DWORD) = NULL;
 
-int
+static int
 psapi_get_dll_name (DWORD BaseAddress, char *dll_name_ret)
 {
   DWORD len;
@@ -510,27 +516,21 @@ struct safe_symbol_file_add_args
 };
 
 /* Maintain a linked list of "so" information. */
-struct so_stuff
+struct lm_info
 {
-  struct so_stuff *next;
   DWORD load_addr;
-  DWORD end_addr;
-  int loaded;
-  struct objfile *objfile;
-  char name[1];
-} solib_start, *solib_end;
+};
+
+static struct so_list solib_start, *solib_end;
 
 /* Call symbol_file_add with stderr redirected.  We don't care if there
    are errors. */
 static int
 safe_symbol_file_add_stub (void *argv)
 {
-#define p ((struct safe_symbol_file_add_args *)argv)
-  struct so_stuff *so = &solib_start;
+#define p ((struct safe_symbol_file_add_args *) argv)
+  struct so_list *so = &solib_start;
 
-  while ((so = so->next))
-    if (so->loaded && strcasecmp (so->name, p->name) == 0)
-      return 0;
   p->ret = symbol_file_add (p->name, p->from_tty, p->addrs, p->mainline, p->flags);
   return !!p->ret;
 #undef p
@@ -578,14 +578,121 @@ safe_symbol_file_add (char *name, int from_tty,
   return p.ret;
 }
 
-/* Remember the maximum DLL length for printing in info dll command. */
-int max_dll_name_len;
+/* Get the loaded address of all sections, given that .text was loaded
+   at text_load. Assumes that all sections are subject to the same
+   relocation offset. Returns NULL if problems occur or if the
+   sections were not relocated. */
+
+static struct section_addr_info *
+get_relocated_section_addrs (bfd *abfd, CORE_ADDR text_load)
+{
+  struct section_addr_info *result = NULL;
+  int section_count = bfd_count_sections (abfd);
+  asection *text_section = bfd_get_section_by_name (abfd, ".text");
+  CORE_ADDR text_vma;
+
+  if (!text_section)
+    {
+      /* Couldn't get the .text section. Weird. */
+    }
+
+  else if (text_load == (text_vma = bfd_get_section_vma (abfd, text_section)))
+    {
+      /* DLL wasn't relocated. */
+    }
+
+  else
+    {
+      /* Figure out all sections' loaded addresses. The offset here is
+	 such that taking a bfd_get_section_vma() result and adding
+	 offset will give the real load address of the section. */
+
+      CORE_ADDR offset = text_load - text_vma;
+
+      struct section_table *table_start = NULL;
+      struct section_table *table_end = NULL;
+      struct section_table *iter = NULL;
+
+      build_section_table (abfd, &table_start, &table_end);
 
+      for (iter = table_start; iter < table_end; ++iter)
+	{
+	  /* Relocated addresses. */
+	  iter->addr += offset;
+	  iter->endaddr += offset;
+	}
+
+      result = build_section_addr_info_from_section_table (table_start,
+							   table_end);
+
+      xfree (table_start);
+    }
+
+  return result;
+}
+
+/* Add DLL symbol information. */
 static void
-register_loaded_dll (const char *name, DWORD load_addr)
+solib_symbols_add (struct so_list *so, CORE_ADDR load_addr)
+{
+  struct section_addr_info *addrs = NULL;
+  static struct objfile *result = NULL;
+  char *name = so->so_name;
+  bfd *abfd = NULL;
+
+  /* The symbols in a dll are offset by 0x1000, which is the
+     the offset from 0 of the first byte in an image - because
+     of the file header and the section alignment. */
+
+  if (!name || !name[0])
+    return;
+
+  abfd = bfd_openr (name, "pei-i386");
+
+  if (!abfd)
+    {
+      /* pei failed - try pe */
+      abfd = bfd_openr (name, "pe-i386");
+    }
+
+  if (abfd)
+    {
+      if (bfd_check_format (abfd, bfd_object))
+	addrs = get_relocated_section_addrs (abfd, load_addr);
+
+      bfd_close (abfd);
+    }
+
+  if (addrs)
+    {
+      result = safe_symbol_file_add (name, 0, addrs, 0, OBJF_SHARED);
+      free_section_addr_info (addrs);
+    }
+  else
+    {
+      /* Fallback on handling just the .text section. */
+      struct cleanup *my_cleanups;
+
+      addrs = alloc_section_addr_info (1);
+      my_cleanups = make_cleanup (xfree, addrs);
+      addrs->other[0].name = ".text";
+      addrs->other[0].addr = load_addr;
+
+      result = safe_symbol_file_add (name, 0, addrs, 0, OBJF_SHARED);
+      do_cleanups (my_cleanups);
+    }
+
+  so->symbols_loaded = !!result;
+  return;
+}
+
+/* Remember the maximum DLL length for printing in info dll command. */
+static int max_dll_name_len;
+
+static char *
+register_loaded_dll (const char *name, DWORD load_addr, int readsyms)
 {
-  struct so_stuff *so;
-  char ppath[MAX_PATH + 1];
+  struct so_list *so;
   char buf[MAX_PATH + 1];
   char cwd[MAX_PATH + 1];
   char *p;
@@ -611,28 +718,28 @@ register_loaded_dll (const char *name, DWORD load_addr)
 	}
     }
 
-  cygwin_conv_to_posix_path (buf, ppath);
-  so = (struct so_stuff *) xmalloc (sizeof (struct so_stuff) + strlen (ppath) + 8 + 1);
-  so->loaded = 0;
-  so->load_addr = load_addr;
-  if (VirtualQueryEx (current_process_handle, (void *) load_addr, &m,
-		      sizeof (m)))
-    so->end_addr = (DWORD) m.AllocationBase + m.RegionSize;
-  else
-    so->end_addr = load_addr + 0x2000;	/* completely arbitrary */
-
-  so->next = NULL;
-  so->objfile = NULL;
-  strcpy (so->name, ppath);
+  if (strcasecmp (buf, "ntdll.dll") == 0)
+    {
+      GetSystemDirectory (buf, sizeof (buf));
+      strcat (buf, "\\ntdll.dll");
+    }
+  so = XZALLOC (struct so_list);
+  so->lm_info = (struct lm_info *) xmalloc (sizeof (struct lm_info));
+  so->lm_info->load_addr = load_addr;
+  cygwin_conv_to_posix_path (buf, so->so_name);
+  strcpy (so->so_original_name, so->so_name);
 
   solib_end->next = so;
   solib_end = so;
-  len = strlen (ppath);
+  len = strlen (so->so_name);
   if (len > max_dll_name_len)
     max_dll_name_len = len;
+  if (readsyms)
+    solib_symbols_add (so, (CORE_ADDR) load_addr);
+  return so->so_name;
 }
 
-char *
+static char *
 get_image_name (HANDLE h, void *address, int unicode)
 {
   static char buf[(2 * MAX_PATH) + 1];
@@ -695,175 +802,70 @@ handle_load_dll (void *dummy)
   if (!dll_name)
     return 1;
 
-  register_loaded_dll (dll_name, (DWORD) event->lpBaseOfDll + 0x1000);
+  register_loaded_dll (dll_name, (DWORD) event->lpBaseOfDll + 0x1000, auto_solib_add);
+  solib_add (NULL, 0, NULL, auto_solib_add);
 
   return 1;
 }
 
+static void
+win32_free_so (struct so_list *so)
+{
+  if (so->lm_info)
+    xfree (so->lm_info);
+}
+
+static void
+win32_relocate_section_addresses (struct so_list *so,
+				  struct section_table *sec)
+{
+  /* FIXME */
+  return;
+}
+
+static void
+win32_solib_create_inferior_hook (void)
+{
+  solib_add (NULL, 0, NULL, auto_solib_add);
+  return;
+}
+
 static int
 handle_unload_dll (void *dummy)
 {
   DWORD lpBaseOfDll = (DWORD) current_event.u.UnloadDll.lpBaseOfDll + 0x1000;
-  struct so_stuff *so;
+  struct so_list *so;
 
   for (so = &solib_start; so->next != NULL; so = so->next)
-    if (so->next->load_addr == lpBaseOfDll)
+    if (so->next->lm_info->load_addr == lpBaseOfDll)
       {
-	struct so_stuff *sodel = so->next;
+	struct so_list *sodel = so->next;
 	so->next = sodel->next;
 	if (!so->next)
 	  solib_end = so;
-	if (sodel->objfile)
-	  free_objfile (sodel->objfile);
-	xfree(sodel);
+	free_so (sodel);
+	solib_add (NULL, 0, NULL, auto_solib_add);
 	return 1;
       }
+
   error (_("Error: dll starting at 0x%lx not found."), (DWORD) lpBaseOfDll);
 
   return 0;
 }
 
-char *
-solib_address (CORE_ADDR address)
-{
-  struct so_stuff *so;
-  for (so = &solib_start; so->next != NULL; so = so->next)
-    if (address >= so->load_addr && address <= so->end_addr)
-      return so->name;
-  return NULL;
-}
-
-/* Return name of last loaded DLL. */
-char *
-child_solib_loaded_library_pathname (int pid)
-{
-  return !solib_end || !solib_end->name[0] ? NULL : solib_end->name;
-}
-
 /* Clear list of loaded DLLs. */
-void
-child_clear_solibs (void)
+static void
+win32_clear_solib (void)
 {
-  struct so_stuff *so, *so1 = solib_start.next;
-
-  while ((so = so1) != NULL)
-    {
-      so1 = so->next;
-      xfree (so);
-    }
-
   solib_start.next = NULL;
-  solib_start.objfile = NULL;
   solib_end = &solib_start;
   max_dll_name_len = sizeof ("DLL Name") - 1;
 }
 
-/* Get the loaded address of all sections, given that .text was loaded
-   at text_load. Assumes that all sections are subject to the same
-   relocation offset. Returns NULL if problems occur or if the
-   sections were not relocated. */
-
-static struct section_addr_info *
-get_relocated_section_addrs (bfd *abfd, CORE_ADDR text_load)
-{
-  struct section_addr_info *result = NULL;
-  int section_count = bfd_count_sections (abfd);
-  asection *text_section = bfd_get_section_by_name (abfd, ".text");
-  CORE_ADDR text_vma;
-
-  if (!text_section)
-    {
-      /* Couldn't get the .text section. Weird. */
-    }
-
-  else if (text_load == (text_vma = bfd_get_section_vma (abfd, text_section)))
-    {
-      /* DLL wasn't relocated. */
-    }
-
-  else
-    {
-      /* Figure out all sections' loaded addresses. The offset here is
-	 such that taking a bfd_get_section_vma() result and adding
-	 offset will give the real load address of the section. */
-
-      CORE_ADDR offset = text_load - text_vma;
-
-      struct section_table *table_start = NULL;
-      struct section_table *table_end = NULL;
-      struct section_table *iter = NULL;
-
-      build_section_table (abfd, &table_start, &table_end);
-
-      for (iter = table_start; iter < table_end; ++iter)
-	{
-	  /* Relocated addresses. */
-	  iter->addr += offset;
-	  iter->endaddr += offset;
-	}
-
-      result = build_section_addr_info_from_section_table (table_start,
-							   table_end);
-
-      xfree (table_start);
-    }
-
-  return result;
-}
-
-/* Add DLL symbol information. */
-static struct objfile *
-solib_symbols_add (char *name, int from_tty, CORE_ADDR load_addr)
+static void
+win32_special_symbol_handling (void)
 {
-  struct section_addr_info *addrs = NULL;
-  static struct objfile *result = NULL;
-  bfd *abfd = NULL;
-
-  /* The symbols in a dll are offset by 0x1000, which is the
-     the offset from 0 of the first byte in an image - because
-     of the file header and the section alignment. */
-
-  if (!name || !name[0])
-    return NULL;
-
-  abfd = bfd_openr (name, "pei-i386");
-
-  if (!abfd)
-    {
-      /* pei failed - try pe */
-      abfd = bfd_openr (name, "pe-i386");
-    }
-
-  if (abfd)
-    {
-      if (bfd_check_format (abfd, bfd_object))
-	{
-	  addrs = get_relocated_section_addrs (abfd, load_addr);
-	}
-
-      bfd_close (abfd);
-    }
-
-  if (addrs)
-    {
-      result = safe_symbol_file_add (name, from_tty, addrs, 0, OBJF_SHARED);
-      free_section_addr_info (addrs);
-    }
-  else
-    {
-      /* Fallback on handling just the .text section. */
-      struct cleanup *my_cleanups;
-
-      addrs = alloc_section_addr_info (1);
-      my_cleanups = make_cleanup (xfree, addrs);
-      addrs->other[0].name = ".text";
-      addrs->other[0].addr = load_addr;
-
-      result = safe_symbol_file_add (name, from_tty, addrs, 0, OBJF_SHARED);
-      do_cleanups (my_cleanups);
-    }
-
-  return result;
+  return;
 }
 
 /* Load DLL symbol info. */
@@ -888,22 +890,6 @@ dll_symbol_command (char *args, int from_tty)
   safe_symbol_file_add (args, from_tty, NULL, 0, OBJF_SHARED | OBJF_USERLOADED);
 }
 
-/* List currently loaded DLLs. */
-void
-info_dll_command (char *ignore, int from_tty)
-{
-  struct so_stuff *so = &solib_start;
-
-  if (!so->next)
-    return;
-
-  printf_filtered ("%*s  Load Address\n", -max_dll_name_len, "DLL Name");
-  while ((so = so->next) != NULL)
-    printf_filtered ("%*s  %08lx\n", -max_dll_name_len, so->name, so->load_addr);
-
-  return;
-}
-
 /* Handle DEBUG_STRING output from child process.
    Cygwin prepends its messages with a "cygwin:".  Interpret this as
    a Cygwin signal.  Otherwise just print the string as a warning. */
@@ -918,7 +904,7 @@ handle_output_debug_string (struct target_waitstatus *ourstatus)
       || !s || !*s)
     return gotasig;
 
-  if (strncmp (s, CYGWIN_SIGNAL_STRING, sizeof (CYGWIN_SIGNAL_STRING) - 1) != 0)
+  if (strncmp (s, _CYGWIN_SIGNAL_STRING, sizeof (_CYGWIN_SIGNAL_STRING) - 1) != 0)
     {
       if (strncmp (s, "cYg", 3) != 0)
 	warning (("%s"), s);
@@ -926,7 +912,7 @@ handle_output_debug_string (struct target_waitstatus *ourstatus)
   else
     {
       char *p;
-      int sig = strtol (s + sizeof (CYGWIN_SIGNAL_STRING) - 1, &p, 0);
+      int sig = strtol (s + sizeof (_CYGWIN_SIGNAL_STRING) - 1, &p, 0);
       gotasig = target_signal_from_host (sig);
       ourstatus->value.sig = gotasig;
       if (gotasig)
@@ -1175,7 +1161,7 @@ handle_exception (struct target_waitstatus *ourstatus)
 /* Resume all artificially suspended threads if we are continuing
    execution */
 static BOOL
-child_continue (DWORD continue_status, int id)
+win32_continue (DWORD continue_status, int id)
 {
   int i;
   thread_info *th;
@@ -1219,13 +1205,13 @@ child_continue (DWORD continue_status, int id)
 
 /* Called in pathological case where Windows fails to send a
    CREATE_PROCESS_DEBUG_EVENT after an attach.  */
-DWORD
+static DWORD
 fake_create_process (void)
 {
   current_process_handle = OpenProcess (PROCESS_ALL_ACCESS, FALSE,
 					current_event.dwProcessId);
   main_thread_id = current_event.dwThreadId;
-  current_thread = child_add_thread (main_thread_id,
+  current_thread = win32_add_thread (main_thread_id,
 				     current_event.u.CreateThread.hThread);
   return main_thread_id;
 }
@@ -1234,7 +1220,7 @@ fake_create_process (void)
    handling by WFI (or whatever).
  */
 static int
-get_child_debug_event (int pid, struct target_waitstatus *ourstatus)
+get_win32_debug_event (int pid, struct target_waitstatus *ourstatus)
 {
   BOOL debug_event;
   DWORD continue_status, event_code;
@@ -1274,7 +1260,7 @@ get_child_debug_event (int pid, struct target_waitstatus *ourstatus)
 	  break;
 	}
       /* Record the existence of this thread */
-      th = child_add_thread (current_event.dwThreadId,
+      th = win32_add_thread (current_event.dwThreadId,
 			     current_event.u.CreateThread.hThread);
       if (info_verbose)
 	printf_unfiltered ("[New %s]\n",
@@ -1290,7 +1276,7 @@ get_child_debug_event (int pid, struct target_waitstatus *ourstatus)
 		     "EXIT_THREAD_DEBUG_EVENT"));
       if (current_event.dwThreadId != main_thread_id)
 	{
-	  child_delete_thread (current_event.dwThreadId);
+	  win32_delete_thread (current_event.dwThreadId);
 	  th = &dummy_thread_info;
 	}
       break;
@@ -1309,10 +1295,10 @@ get_child_debug_event (int pid, struct target_waitstatus *ourstatus)
 
       current_process_handle = current_event.u.CreateProcessInfo.hProcess;
       if (main_thread_id)
-	child_delete_thread (main_thread_id);
+	win32_delete_thread (main_thread_id);
       main_thread_id = current_event.dwThreadId;
       /* Add the main thread */
-      th = child_add_thread (main_thread_id,
+      th = win32_add_thread (main_thread_id,
 			     current_event.u.CreateProcessInfo.hThread);
       retval = ourstatus->value.related_pid = current_event.dwThreadId;
       break;
@@ -1395,7 +1381,7 @@ get_child_debug_event (int pid, struct target_waitstatus *ourstatus)
     }
 
   if (!retval || saw_create != 1)
-    CHECK (child_continue (continue_status, -1));
+    CHECK (win32_continue (continue_status, -1));
   else
     {
       inferior_ptid = pid_to_ptid (retval);
@@ -1408,7 +1394,7 @@ out:
 
 /* Wait for interesting events to occur in the target process. */
 static ptid_t
-child_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
+win32_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
 {
   int pid = PIDGET (ptid);
 
@@ -1420,7 +1406,7 @@ child_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
 
   while (1)
     {
-      int retval = get_child_debug_event (pid, ourstatus);
+      int retval = get_win32_debug_event (pid, ourstatus);
       if (retval)
 	return pid_to_ptid (retval);
       else
@@ -1431,13 +1417,13 @@ child_wait (ptid_t ptid, struct target_waitstatus *ourstatus)
 	    detach = deprecated_ui_loop_hook (0);
 
 	  if (detach)
-	    child_kill_inferior ();
+	    win32_kill_inferior ();
 	}
     }
 }
 
 static void
-do_initial_child_stuff (DWORD pid)
+do_initial_win32_stuff (DWORD pid)
 {
   extern int stop_after_trap;
   int i;
@@ -1451,9 +1437,9 @@ do_initial_child_stuff (DWORD pid)
     dr[i] = 0;
   current_event.dwProcessId = pid;
   memset (&current_event, 0, sizeof (current_event));
-  push_target (&deprecated_child_ops);
+  push_target (&win32_ops);
   disable_breakpoints_in_shlibs (1);
-  child_clear_solibs ();
+  win32_clear_solib ();
   clear_proceed_status ();
   init_wait_for_inferior ();
 
@@ -1563,7 +1549,7 @@ set_process_privilege (const char *privilege, BOOL enable)
 #if 0
   /* Disabled, otherwise every `attach' in an unprivileged user session
      would raise the "Failed to get SE_DEBUG_NAME privilege" warning in
-     child_attach(). */
+     win32_attach(). */
   /* AdjustTokenPrivileges returns TRUE even if the privilege could not
      be enabled. GetLastError () returns an correct error code, though. */
   if (enable && GetLastError () == ERROR_NOT_ALL_ASSIGNED)
@@ -1581,7 +1567,7 @@ out:
 
 /* Attach to process PID, then initialize for debugging it.  */
 static void
-child_attach (char *args, int from_tty)
+win32_attach (char *args, int from_tty)
 {
   BOOL ok;
   DWORD pid;
@@ -1597,7 +1583,7 @@ child_attach (char *args, int from_tty)
 
   pid = strtoul (args, 0, 0);		/* Windows pid */
 
-  child_init_thread_list ();
+  win32_init_thread_list ();
   ok = DebugActiveProcess (pid);
   saw_create = 0;
 
@@ -1632,19 +1618,19 @@ child_attach (char *args, int from_tty)
       gdb_flush (gdb_stdout);
     }
 
-  do_initial_child_stuff (pid);
+  do_initial_win32_stuff (pid);
   target_terminal_ours ();
 }
 
 static void
-child_detach (char *args, int from_tty)
+win32_detach (char *args, int from_tty)
 {
   int detached = 1;
 
   if (has_detach_ability ())
     {
       delete_command (NULL, 0);
-      child_continue (DBG_CONTINUE, -1);
+      win32_continue (DBG_CONTINUE, -1);
       if (!DebugActiveProcessStop (current_event.dwProcessId))
 	{
 	  error (_("Can't detach process %lu (error %lu)"),
@@ -1663,11 +1649,11 @@ child_detach (char *args, int from_tty)
       gdb_flush (gdb_stdout);
     }
   inferior_ptid = null_ptid;
-  unpush_target (&deprecated_child_ops);
+  unpush_target (&win32_ops);
 }
 
-char *
-child_pid_to_exec_file (int pid)
+static char *
+win32_pid_to_exec_file (int pid)
 {
   /* Try to find the process path using the Cygwin internal process list
      pid isn't a valid pid, unfortunately.  Use current_event.dwProcessId
@@ -1682,31 +1668,31 @@ child_pid_to_exec_file (int pid)
   cygwin_internal (CW_LOCK_PINFO, 1000);
   for (cpid = 0;
        (pinfo = (struct external_pinfo *)
-                       cygwin_internal (CW_GETPINFO, cpid | CW_NEXTPID));
+	cygwin_internal (CW_GETPINFO, cpid | CW_NEXTPID));
        cpid = pinfo->pid)
     {
       if (pinfo->dwProcessId == current_event.dwProcessId) /* Got it */
        {
-         cygwin_conv_to_full_posix_path (pinfo->progname, path);
-         path_ptr = path; 
-         break;
+	 cygwin_conv_to_full_posix_path (pinfo->progname, path);
+	 path_ptr = path;
+	 break;
        }
     }
   cygwin_internal (CW_UNLOCK_PINFO);
-  return path_ptr; 
+  return path_ptr;
 }
 
 /* Print status information about what we're accessing.  */
 
 static void
-child_files_info (struct target_ops *ignore)
+win32_files_info (struct target_ops *ignore)
 {
   printf_unfiltered ("\tUsing the running image of %s %s.\n",
       attach_flag ? "attached" : "child", target_pid_to_str (inferior_ptid));
 }
 
 static void
-child_open (char *arg, int from_tty)
+win32_open (char *arg, int from_tty)
 {
   error (_("Use the \"run\" command to start a Unix child process."));
 }
@@ -1717,7 +1703,7 @@ child_open (char *arg, int from_tty)
    ENV is the environment vector to pass.  Errors reported with error().  */
 
 static void
-child_create_inferior (char *exec_file, char *allargs, char **env,
+win32_create_inferior (char *exec_file, char *allargs, char **env,
 		       int from_tty)
 {
   char *winenv;
@@ -1871,7 +1857,7 @@ child_create_inferior (char *exec_file, char *allargs, char **env,
 	}
     }
 
-  child_init_thread_list ();
+  win32_init_thread_list ();
   ret = CreateProcess (0,
 		       args,	/* command line */
 		       NULL,	/* Security */
@@ -1905,18 +1891,18 @@ child_create_inferior (char *exec_file, char *allargs, char **env,
   else
     saw_create = 0;
 
-  do_initial_child_stuff (pi.dwProcessId);
+  do_initial_win32_stuff (pi.dwProcessId);
 
-  /* child_continue (DBG_CONTINUE, -1); */
+  /* win32_continue (DBG_CONTINUE, -1); */
   proceed ((CORE_ADDR) - 1, TARGET_SIGNAL_0, 0);
 }
 
 static void
-child_mourn_inferior (void)
+win32_mourn_inferior (void)
 {
-  (void) child_continue (DBG_CONTINUE, -1);
+  (void) win32_continue (DBG_CONTINUE, -1);
   i386_cleanup_dregs();
-  unpush_target (&deprecated_child_ops);
+  unpush_target (&win32_ops);
   generic_mourn_inferior ();
 }
 
@@ -1924,15 +1910,15 @@ child_mourn_inferior (void)
    ^C on the controlling terminal. */
 
 static void
-child_stop (void)
+win32_stop (void)
 {
   DEBUG_EVENTS (("gdb: GenerateConsoleCtrlEvent (CTRLC_EVENT, 0)\n"));
   CHECK (GenerateConsoleCtrlEvent (CTRL_C_EVENT, current_event.dwProcessId));
   registers_changed ();		/* refresh register state */
 }
 
-int
-child_xfer_memory (CORE_ADDR memaddr, gdb_byte *our, int len,
+static int
+win32_xfer_memory (CORE_ADDR memaddr, gdb_byte *our, int len,
 		   int write, struct mem_attrib *mem,
 		   struct target_ops *target)
 {
@@ -1957,14 +1943,14 @@ child_xfer_memory (CORE_ADDR memaddr, gdb_byte *our, int len,
   return done;
 }
 
-void
-child_kill_inferior (void)
+static void
+win32_kill_inferior (void)
 {
   CHECK (TerminateProcess (current_process_handle, 0));
 
   for (;;)
     {
-      if (!child_continue (DBG_CONTINUE, -1))
+      if (!win32_continue (DBG_CONTINUE, -1))
 	break;
       if (!WaitForDebugEvent (&current_event, INFINITE))
 	break;
@@ -1977,11 +1963,11 @@ child_kill_inferior (void)
   /* this may fail in an attached process so don't check. */
   if (current_thread && current_thread->h)
     (void) CloseHandle (current_thread->h);
-  target_mourn_inferior ();	/* or just child_mourn_inferior? */
+  target_mourn_inferior ();	/* or just win32_mourn_inferior? */
 }
 
-void
-child_resume (ptid_t ptid, int step, enum target_signal sig)
+static void
+win32_resume (ptid_t ptid, int step, enum target_signal sig)
 {
   thread_info *th;
   DWORD continue_status = DBG_CONTINUE;
@@ -2024,7 +2010,7 @@ child_resume (ptid_t ptid, int step, enum target_signal sig)
 
   last_sig = TARGET_SIGNAL_0;
 
-  DEBUG_EXEC (("gdb: child_resume (pid=%d, step=%d, sig=%d);\n",
+  DEBUG_EXEC (("gdb: win32_resume (pid=%d, step=%d, sig=%d);\n",
 	       pid, step, sig));
 
   /* Get context for currently selected thread */
@@ -2034,7 +2020,7 @@ child_resume (ptid_t ptid, int step, enum target_signal sig)
       if (step)
 	{
 	  /* Single step by setting t bit */
-	  child_fetch_inferior_registers (PS_REGNUM);
+	  win32_fetch_inferior_registers (PS_REGNUM);
 	  th->context.EFlags |= FLAG_TRACE_BIT;
 	}
 
@@ -2058,197 +2044,30 @@ child_resume (ptid_t ptid, int step, enum target_signal sig)
   /* Allow continuing with the same signal that interrupted us.
      Otherwise complain. */
 
-  child_continue (continue_status, pid);
+  win32_continue (continue_status, pid);
 }
 
 static void
-child_prepare_to_store (void)
+win32_prepare_to_store (void)
 {
   /* Do nothing, since we can store individual regs */
 }
 
 static int
-child_can_run (void)
+win32_can_run (void)
 {
   return 1;
 }
 
 static void
-child_close (int x)
+win32_close (int x)
 {
-  DEBUG_EVENTS (("gdb: child_close, inferior_ptid=%d\n",
+  DEBUG_EVENTS (("gdb: win32_close, inferior_ptid=%d\n",
 		PIDGET (inferior_ptid)));
 }
 
-static void
-init_child_ops (void)
-{
-  deprecated_child_ops.to_shortname = "child";
-  deprecated_child_ops.to_longname = "Win32 child process";
-  deprecated_child_ops.to_doc = "Win32 child process (started by the \"run\" command).";
-  deprecated_child_ops.to_open = child_open;
-  deprecated_child_ops.to_close = child_close;
-  deprecated_child_ops.to_attach = child_attach;
-  deprecated_child_ops.to_detach = child_detach;
-  deprecated_child_ops.to_resume = child_resume;
-  deprecated_child_ops.to_wait = child_wait;
-  deprecated_child_ops.to_fetch_registers = child_fetch_inferior_registers;
-  deprecated_child_ops.to_store_registers = child_store_inferior_registers;
-  deprecated_child_ops.to_prepare_to_store = child_prepare_to_store;
-  deprecated_child_ops.deprecated_xfer_memory = child_xfer_memory;
-  deprecated_child_ops.to_files_info = child_files_info;
-  deprecated_child_ops.to_insert_breakpoint = memory_insert_breakpoint;
-  deprecated_child_ops.to_remove_breakpoint = memory_remove_breakpoint;
-  deprecated_child_ops.to_terminal_init = terminal_init_inferior;
-  deprecated_child_ops.to_terminal_inferior = terminal_inferior;
-  deprecated_child_ops.to_terminal_ours_for_output = terminal_ours_for_output;
-  deprecated_child_ops.to_terminal_ours = terminal_ours;
-  deprecated_child_ops.to_terminal_save_ours = terminal_save_ours;
-  deprecated_child_ops.to_terminal_info = child_terminal_info;
-  deprecated_child_ops.to_kill = child_kill_inferior;
-  deprecated_child_ops.to_create_inferior = child_create_inferior;
-  deprecated_child_ops.to_mourn_inferior = child_mourn_inferior;
-  deprecated_child_ops.to_can_run = child_can_run;
-  deprecated_child_ops.to_thread_alive = win32_child_thread_alive;
-  deprecated_child_ops.to_pid_to_str = cygwin_pid_to_str;
-  deprecated_child_ops.to_stop = child_stop;
-  deprecated_child_ops.to_stratum = process_stratum;
-  deprecated_child_ops.to_has_all_memory = 1;
-  deprecated_child_ops.to_has_memory = 1;
-  deprecated_child_ops.to_has_stack = 1;
-  deprecated_child_ops.to_has_registers = 1;
-  deprecated_child_ops.to_has_execution = 1;
-  deprecated_child_ops.to_magic = OPS_MAGIC;
-  deprecated_child_ops.to_pid_to_exec_file = child_pid_to_exec_file;
-}
-
-void
-_initialize_win32_nat (void)
-{
-  struct cmd_list_element *c;
-
-  init_child_ops ();
-
-  c = add_com ("dll-symbols", class_files, dll_symbol_command,
-	       _("Load dll library symbols from FILE."));
-  set_cmd_completer (c, filename_completer);
-
-  add_com_alias ("sharedlibrary", "dll-symbols", class_alias, 1);
-
-  add_setshow_boolean_cmd ("shell", class_support, &useshell, _("\
-Set use of shell to start subprocess."), _("\
-Show use of shell to start subprocess."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("new-console", class_support, &new_console, _("\
-Set creation of new console when creating child process."), _("\
-Show creation of new console when creating child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("new-group", class_support, &new_group, _("\
-Set creation of new group when creating child process."), _("\
-Show creation of new group when creating child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("debugexec", class_support, &debug_exec, _("\
-Set whether to display execution in child process."), _("\
-Show whether to display execution in child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("debugevents", class_support, &debug_events, _("\
-Set whether to display kernel events in child process."), _("\
-Show whether to display kernel events in child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("debugmemory", class_support, &debug_memory, _("\
-Set whether to display memory accesses in child process."), _("\
-Show whether to display memory accesses in child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_setshow_boolean_cmd ("debugexceptions", class_support,
-			   &debug_exceptions, _("\
-Set whether to display kernel exceptions in child process."), _("\
-Show whether to display kernel exceptions in child process."), NULL,
-			   NULL,
-			   NULL, /* FIXME: i18n: */
-			   &setlist, &showlist);
-
-  add_info ("dll", info_dll_command, _("Status of loaded DLLs."));
-  add_info_alias ("sharedlibrary", "dll", 1);
-
-  add_prefix_cmd ("w32", class_info, info_w32_command,
-		  _("Print information specific to Win32 debugging."),
-		  &info_w32_cmdlist, "info w32 ", 0, &infolist);
-
-  add_cmd ("selector", class_info, display_selectors,
-	   _("Display selectors infos."),
-	   &info_w32_cmdlist);
-
-  add_target (&deprecated_child_ops);
-}
-
-/* Hardware watchpoint support, adapted from go32-nat.c code.  */
-
-/* Pass the address ADDR to the inferior in the I'th debug register.
-   Here we just store the address in dr array, the registers will be
-   actually set up when child_continue is called.  */
-void
-cygwin_set_dr (int i, CORE_ADDR addr)
-{
-  if (i < 0 || i > 3)
-    internal_error (__FILE__, __LINE__,
-		    _("Invalid register %d in cygwin_set_dr.\n"), i);
-  dr[i] = (unsigned) addr;
-  debug_registers_changed = 1;
-  debug_registers_used = 1;
-}
-
-/* Pass the value VAL to the inferior in the DR7 debug control
-   register.  Here we just store the address in D_REGS, the watchpoint
-   will be actually set up in child_wait.  */
-void
-cygwin_set_dr7 (unsigned val)
-{
-  dr[7] = val;
-  debug_registers_changed = 1;
-  debug_registers_used = 1;
-}
-
-/* Get the value of the DR6 debug status register from the inferior.
-   Here we just return the value stored in dr[6]
-   by the last call to thread_rec for current_event.dwThreadId id.  */
-unsigned
-cygwin_get_dr6 (void)
-{
-  return dr[6];
-}
-
-/* Determine if the thread referenced by "pid" is alive
-   by "polling" it.  If WaitForSingleObject returns WAIT_OBJECT_0
-   it means that the pid has died.  Otherwise it is assumed to be alive. */
-static int
-win32_child_thread_alive (ptid_t ptid)
-{
-  int pid = PIDGET (ptid);
-
-  return WaitForSingleObject (thread_rec (pid, FALSE)->h, 0) == WAIT_OBJECT_0 ?
-    FALSE : TRUE;
-}
-
 /* Convert pid to printable format. */
-char *
+static char *
 cygwin_pid_to_str (ptid_t ptid)
 {
   static char buf[80];
@@ -2261,38 +2080,6 @@ cygwin_pid_to_str (ptid_t ptid)
   return buf;
 }
 
-static int
-core_dll_symbols_add (char *dll_name, DWORD base_addr)
-{
-  struct objfile *objfile;
-  char *objfile_basename;
-  const char *dll_basename;
-
-  if (!(dll_basename = strrchr (dll_name, '/')))
-    dll_basename = dll_name;
-  else
-    dll_basename++;
-
-  ALL_OBJFILES (objfile)
-  {
-    objfile_basename = strrchr (objfile->name, '/');
-
-    if (objfile_basename &&
-	strcmp (dll_basename, objfile_basename + 1) == 0)
-      {
-	printf_unfiltered ("%08lx:%s (symbols previously loaded)\n",
-			   base_addr, dll_name);
-	goto out;
-      }
-  }
-
-  register_loaded_dll (dll_name, base_addr + 0x1000);
-  solib_symbols_add (dll_name, 0, (CORE_ADDR) base_addr + 0x1000);
-
- out:
-  return 1;
-}
-
 typedef struct
 {
   struct target_ops *target;
@@ -2300,7 +2087,7 @@ typedef struct
 } map_code_section_args;
 
 static void
-map_single_dll_code_section (bfd * abfd, asection * sect, void *obj)
+map_single_dll_code_section (bfd *abfd, asection *sect, void *obj)
 {
   int old;
   int update_coreops;
@@ -2372,19 +2159,22 @@ dll_code_sections_add (const char *dll_name, int base_addr, struct target_ops *t
 }
 
 static void
-core_section_load_dll_symbols (bfd * abfd, asection * sect, void *obj)
+core_section_load_dll_symbols (bfd *abfd, asection *sect, void *obj)
 {
   struct target_ops *target = (struct target_ops *) obj;
 
   DWORD base_addr;
 
   int dll_name_size;
-  char *dll_name = NULL;
-  char *buf = NULL;
   struct win32_pstatus *pstatus;
+  struct so_list *so;
+  char *dll_name;
+  char *buf = NULL;
   char *p;
+  struct objfile *objfile;
+  const char *dll_basename;
 
-  if (strncmp (sect->name, ".module", 7))
+  if (strncmp (sect->name, ".module", 7) != 0)
     return;
 
   buf = (char *) xmalloc (bfd_get_section_size (sect) + 1);
@@ -2403,48 +2193,63 @@ core_section_load_dll_symbols (bfd * abfd, asection * sect, void *obj)
   if (offsetof (struct win32_pstatus, data.module_info.module_name) + dll_name_size > bfd_get_section_size (sect))
       goto out;
 
-  dll_name = (char *) xmalloc (dll_name_size + 1);
-  if (!dll_name)
-    {
-      printf_unfiltered ("memory allocation failed for %s\n", sect->name);
-      goto out;
-    }
-  strncpy (dll_name, pstatus->data.module_info.module_name, dll_name_size);
+  dll_name = pstatus->data.module_info.module_name;
+
+  if (!(dll_basename = strrchr (dll_name, '/')))
+    dll_basename = dll_name;
+  else
+    dll_basename++;
 
-  while ((p = strchr (dll_name, '\\')))
-    *p = '/';
+  ALL_OBJFILES (objfile)
+  {
+    char *objfile_basename = strrchr (objfile->name, '/');
 
-  if (!core_dll_symbols_add (dll_name, (DWORD) base_addr))
-    printf_unfiltered ("%s: Failed to load dll symbols.\n", dll_name);
+    if (objfile_basename &&
+	strcasecmp (dll_basename, objfile_basename + 1) == 0)
+      goto out;
+  }
+
+  base_addr += 0x1000;
+  dll_name = register_loaded_dll (dll_name, base_addr, 1);
 
-  if (!dll_code_sections_add (dll_name, (DWORD) base_addr + 0x1000, target))
+  if (!dll_code_sections_add (dll_name, (DWORD) base_addr, target))
     printf_unfiltered ("%s: Failed to map dll code sections.\n", dll_name);
 
 out:
   if (buf)
     xfree (buf);
-  if (dll_name)
-    xfree (dll_name);
   return;
 }
 
-void
-child_solib_add (char *filename, int from_tty, struct target_ops *target,
-		 int readsyms)
+static struct so_list *
+win32_current_sos (void)
 {
-  if (!readsyms)
-    return;
-  if (core_bfd)
+  struct so_list *sop;
+  struct so_list *start = NULL;
+  struct so_list *last;
+
+  if (!solib_start.next && core_bfd)
     {
-      child_clear_solibs ();
-      bfd_map_over_sections (core_bfd, &core_section_load_dll_symbols, target);
+      win32_clear_solib ();
+      bfd_map_over_sections (core_bfd, &core_section_load_dll_symbols,
+			     &win32_ops);
     }
-  else
+
+  for (sop = solib_start.next; sop; sop = sop->next)
     {
-      if (solib_end && solib_end->name)
-	     solib_end->objfile = solib_symbols_add (solib_end->name, from_tty,
-						solib_end->load_addr);
+      struct so_list *new = XZALLOC (struct so_list);
+      strcpy (new->so_name, sop->so_name);
+      strcpy (new->so_original_name, sop->so_original_name);
+      if (!start)
+	last = start = new;
+      else
+	{
+	  last->next = new;
+	  last = new;
+	}
     }
+
+  return start;
 }
 
 static void
@@ -2463,6 +2268,188 @@ fetch_elf_core_registers (char *core_reg_sect,
     regcache_raw_supply (current_regcache, r, core_reg_sect + mappings[r]);
 }
 
+static void
+init_win32_ops (void)
+{
+  win32_ops.to_shortname = "child";
+  win32_ops.to_longname = "Win32 child process";
+  win32_ops.to_doc = "Win32 child process (started by the \"run\" command).";
+  win32_ops.to_open = win32_open;
+  win32_ops.to_close = win32_close;
+  win32_ops.to_attach = win32_attach;
+  win32_ops.to_detach = win32_detach;
+  win32_ops.to_resume = win32_resume;
+  win32_ops.to_wait = win32_wait;
+  win32_ops.to_fetch_registers = win32_fetch_inferior_registers;
+  win32_ops.to_store_registers = win32_store_inferior_registers;
+  win32_ops.to_prepare_to_store = win32_prepare_to_store;
+  win32_ops.deprecated_xfer_memory = win32_xfer_memory;
+  win32_ops.to_files_info = win32_files_info;
+  win32_ops.to_insert_breakpoint = memory_insert_breakpoint;
+  win32_ops.to_remove_breakpoint = memory_remove_breakpoint;
+  win32_ops.to_terminal_init = terminal_init_inferior;
+  win32_ops.to_terminal_inferior = terminal_inferior;
+  win32_ops.to_terminal_ours_for_output = terminal_ours_for_output;
+  win32_ops.to_terminal_ours = terminal_ours;
+  win32_ops.to_terminal_save_ours = terminal_save_ours;
+  win32_ops.to_terminal_info = child_terminal_info;
+  win32_ops.to_kill = win32_kill_inferior;
+  win32_ops.to_create_inferior = win32_create_inferior;
+  win32_ops.to_mourn_inferior = win32_mourn_inferior;
+  win32_ops.to_can_run = win32_can_run;
+  win32_ops.to_thread_alive = win32_win32_thread_alive;
+  win32_ops.to_pid_to_str = cygwin_pid_to_str;
+  win32_ops.to_stop = win32_stop;
+  win32_ops.to_stratum = process_stratum;
+  win32_ops.to_has_all_memory = 1;
+  win32_ops.to_has_memory = 1;
+  win32_ops.to_has_stack = 1;
+  win32_ops.to_has_registers = 1;
+  win32_ops.to_has_execution = 1;
+  win32_ops.to_magic = OPS_MAGIC;
+  win32_ops.to_pid_to_exec_file = win32_pid_to_exec_file;
+
+  win32_so_ops.relocate_section_addresses = win32_relocate_section_addresses;
+  win32_so_ops.free_so = win32_free_so;
+  win32_so_ops.clear_solib = win32_clear_solib;
+  win32_so_ops.solib_create_inferior_hook = win32_solib_create_inferior_hook;
+  win32_so_ops.special_symbol_handling = win32_special_symbol_handling;
+  win32_so_ops.current_sos = win32_current_sos;
+  win32_so_ops.open_symbol_file_object = NULL;
+  win32_so_ops.in_dynsym_resolve_code = NULL;
+
+  /* FIXME: Don't do this here.  *_gdbarch_init() should set so_ops. */
+  current_target_so_ops = &win32_so_ops;
+}
+
+static void
+set_win32_aliases (char *argv0)
+{
+  add_info_alias ("dll", "sharedlibrary", 1);
+}
+
+void
+_initialize_win32_nat (void)
+{
+  struct cmd_list_element *c;
+
+  init_win32_ops ();
+
+  c = add_com ("dll-symbols", class_files, dll_symbol_command,
+	       _("Load dll library symbols from FILE."));
+  set_cmd_completer (c, filename_completer);
+
+  add_com_alias ("sharedlibrary", "dll-symbols", class_alias, 1);
+
+  add_setshow_boolean_cmd ("shell", class_support, &useshell, _("\
+Set use of shell to start subprocess."), _("\
+Show use of shell to start subprocess."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("new-console", class_support, &new_console, _("\
+Set creation of new console when creating child process."), _("\
+Show creation of new console when creating child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("new-group", class_support, &new_group, _("\
+Set creation of new group when creating child process."), _("\
+Show creation of new group when creating child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("debugexec", class_support, &debug_exec, _("\
+Set whether to display execution in child process."), _("\
+Show whether to display execution in child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("debugevents", class_support, &debug_events, _("\
+Set whether to display kernel events in child process."), _("\
+Show whether to display kernel events in child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("debugmemory", class_support, &debug_memory, _("\
+Set whether to display memory accesses in child process."), _("\
+Show whether to display memory accesses in child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_setshow_boolean_cmd ("debugexceptions", class_support,
+			   &debug_exceptions, _("\
+Set whether to display kernel exceptions in child process."), _("\
+Show whether to display kernel exceptions in child process."), NULL,
+			   NULL,
+			   NULL, /* FIXME: i18n: */
+			   &setlist, &showlist);
+
+  add_prefix_cmd ("w32", class_info, info_w32_command,
+		  _("Print information specific to Win32 debugging."),
+		  &info_w32_cmdlist, "info w32 ", 0, &infolist);
+
+  add_cmd ("selector", class_info, display_selectors,
+	   _("Display selectors infos."),
+	   &info_w32_cmdlist);
+  add_target (&win32_ops);
+  deprecated_init_ui_hook = set_win32_aliases;
+}
+
+/* Hardware watchpoint support, adapted from go32-nat.c code.  */
+
+/* Pass the address ADDR to the inferior in the I'th debug register.
+   Here we just store the address in dr array, the registers will be
+   actually set up when win32_continue is called.  */
+void
+cygwin_set_dr (int i, CORE_ADDR addr)
+{
+  if (i < 0 || i > 3)
+    internal_error (__FILE__, __LINE__,
+		    _("Invalid register %d in cygwin_set_dr.\n"), i);
+  dr[i] = (unsigned) addr;
+  debug_registers_changed = 1;
+  debug_registers_used = 1;
+}
+
+/* Pass the value VAL to the inferior in the DR7 debug control
+   register.  Here we just store the address in D_REGS, the watchpoint
+   will be actually set up in win32_wait.  */
+void
+cygwin_set_dr7 (unsigned val)
+{
+  dr[7] = val;
+  debug_registers_changed = 1;
+  debug_registers_used = 1;
+}
+
+/* Get the value of the DR6 debug status register from the inferior.
+   Here we just return the value stored in dr[6]
+   by the last call to thread_rec for current_event.dwThreadId id.  */
+unsigned
+cygwin_get_dr6 (void)
+{
+  return dr[6];
+}
+
+/* Determine if the thread referenced by "pid" is alive
+   by "polling" it.  If WaitForSingleObject returns WAIT_OBJECT_0
+   it means that the pid has died.  Otherwise it is assumed to be alive. */
+static int
+win32_win32_thread_alive (ptid_t ptid)
+{
+  int pid = PIDGET (ptid);
+
+  return WaitForSingleObject (thread_rec (pid, FALSE)->h, 0) == WAIT_OBJECT_0 ?
+    FALSE : TRUE;
+}
+
 static struct core_fns win32_elf_core_fns =
 {
   bfd_target_elf_flavour,
diff --git a/include/ChangeLog b/include/ChangeLog
index 8f00e91ab37..e2c90f819a7 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,8 +1,24 @@
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* floatformat.h (enum floatformat_byteorders): Add
+	floatformat_vax.
+	(floatformat_vax_aingle, floatformat_vax_double): Declare.
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
+	more exotic underlying types to be used.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	disasm.h: Add declaration for print_insn_z80
+
 2005-09-30  Catherine Moore  <clm@cm00re.com>
 
 	* dis-asm.h (print_insn_bfin): Declare.
-	* elf/bfin.h: New file.
-	* elf/common.h (EM_BLACKFIN): Define.
 	* opcode/bfin.h: New file.
 
 2005-09-26  Mark Mitchell  <mark@codesourcery.com>
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index ca201a12a63..a8b66cce2af 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,8 @@
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* internal.h: Add relocation number for Z80
+	* z80.h: New file.
+
 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 
 	* a29k.h: Delete.
diff --git a/include/coff/internal.h b/include/coff/internal.h
index 20e06c215ec..d7a83815aea 100644
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -1,7 +1,7 @@
 /* Internal format of COFF object file data structures, for GNU BFD.
    This file is part of BFD, the Binary File Descriptor library.
    
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004. 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -715,6 +715,10 @@ struct internal_reloc
 #define R_IMM4H   0x24		/* high nibble */
 #define R_DISP7   0x25          /* djnz displacement */
 
+/* Z80 modes */
+#define R_OFF8    0x32		/* 8 bit signed abs, for (i[xy]+d) */
+/* R_JR, R_IMM8, R_IMM16, R_IMM32 - as for Z8k */
+
 /* H8500 modes */
 
 #define R_H8500_IMM8  	1		/*  8 bit immediate 	*/
diff --git a/include/coff/z80.h b/include/coff/z80.h
new file mode 100644
index 00000000000..3c72c10dd9e
--- /dev/null
+++ b/include/coff/z80.h
@@ -0,0 +1,51 @@
+/* coff information for Zilog Z80
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+/* z80 backend does not use dots in section names.  */
+#undef  _TEXT
+#define _TEXT "text"
+#undef  _DATA
+#define _DATA "data"
+#undef  _BSS
+#define _BSS "bss"
+
+/* Type of cpu is stored in flags.  */
+#define F_MACHMASK 0xF000
+
+#define	Z80MAGIC   0x805A
+
+#define Z80BADMAG(x) (((x).f_magic != Z80MAGIC))
+
+/* Relocation directives.  */
+
+/* This format actually has more bits than we need.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
diff --git a/include/dis-asm.h b/include/dis-asm.h
index dd4e86e913c..ca6da9c21ea 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -78,7 +78,7 @@ typedef struct disassemble_info {
      for processors with run-time-switchable instruction sets.  The default,
      zero, means that there is no constraint.  CGEN-based opcodes ports
      may use ISA_foo masks.  */
-  unsigned long insn_sets;
+  void *insn_sets;
 
   /* Some targets need information about the current section to accurately
      display insns.  If this is NULL, the target disassembler function
@@ -208,6 +208,7 @@ extern int print_insn_i370		(bfd_vma, disassemble_info *);
 extern int print_insn_m68hc11		(bfd_vma, disassemble_info *);
 extern int print_insn_m68hc12		(bfd_vma, disassemble_info *);
 extern int print_insn_m68k		(bfd_vma, disassemble_info *);
+extern int print_insn_z80		(bfd_vma, disassemble_info *);
 extern int print_insn_z8001		(bfd_vma, disassemble_info *);
 extern int print_insn_z8002		(bfd_vma, disassemble_info *);
 extern int print_insn_h8300		(bfd_vma, disassemble_info *);
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index cf4b57805b0..485a78e32a8 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+	* common.h (EM_BLACKFIN): Define.
+
 2005-10-08  Paul Brook  <paul@codesourcery.com>
 
 	* arm.h: Add prototypes for BFD object attribute routines.
diff --git a/include/floatformat.h b/include/floatformat.h
index a2448743050..f1bd7f601f5 100644
--- a/include/floatformat.h
+++ b/include/floatformat.h
@@ -29,25 +29,26 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
    (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
    contains with the *_start and *_len fields.  */
 
-/* What is the order of the bytes. */
+/* What is the order of the bytes?  */
 
 enum floatformat_byteorders {
-
   /* Standard little endian byte order.
      EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
-
   floatformat_little,
 
   /* Standard big endian byte order.
      EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
-
   floatformat_big,
 
   /* Little endian byte order but big endian word order.
      EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
+  floatformat_littlebyte_bigword,
 
-  floatformat_littlebyte_bigword
-
+  /* VAX byte order.  Little endian byte order with 16-bit words.  The
+     following example is an illustration of the byte order only; VAX
+     doesn't have a fully IEEE compliant floating-point format.
+     EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */
+  floatformat_vax
 };
 
 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
@@ -97,6 +98,12 @@ extern const struct floatformat floatformat_ieee_double_little;
 
 extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
 
+/* floatformats for VAX.  */
+
+extern const struct floatformat floatformat_vax_f;
+extern const struct floatformat floatformat_vax_d;
+extern const struct floatformat floatformat_vax_g;
+
 /* floatformats for various extendeds.  */
 
 extern const struct floatformat floatformat_i387_ext;
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 08028706df8..a282a622261 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,43 @@
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2005-02-16  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
+	cgen_isa_mask_* to cgen_bitset_*.
+	* cgen.h: Likewise.
+
+	2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
+	(CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
+	(CGEN_CPU_TABLE): Make isas a ponter.
+
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
+	(CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
+	(CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
+
+	2002-12-13  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (symcat.h): #include it.
+	(cgen-bitset.h): #include it.
+	(CGEN_ATTR_VALUE_TYPE): Now a union.
+	(CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
+	(CGEN_ATTR_ENTRY): 'value' now unsigned.
+	(cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
+	* cgen-bitset.h: New file.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* ia64.h (enum ia64_opnd): Move memory operand out of set of
+	indirect operands.
+
 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
 	* hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
diff --git a/include/opcode/cgen-bitset.h b/include/opcode/cgen-bitset.h
new file mode 100644
index 00000000000..1b6fbe32cf9
--- /dev/null
+++ b/include/opcode/cgen-bitset.h
@@ -0,0 +1,55 @@
+/* Header file the type CGEN_BITSET.
+
+Copyright 2002, 2005 Free Software Foundation, Inc.
+
+This file is part of GDB, the GNU debugger, and the GNU Binutils.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+#ifndef CGEN_BITSET_H
+#define CGEN_BITSET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* A bitmask represented as a string.
+   Each member of the set is represented as a bit
+   in the string. Bytes are indexed from left to right in the string and
+   bits from most significant to least within each byte.
+
+   For example, the bit representing member number 6 is (set->bits[0] & 0x02).
+*/
+typedef struct cgen_bitset
+{
+  unsigned length;
+  char *bits;
+} CGEN_BITSET;
+
+extern CGEN_BITSET *cgen_bitset_create PARAMS ((unsigned));
+extern void cgen_bitset_init PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_clear PARAMS ((CGEN_BITSET *));
+extern void cgen_bitset_add PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_set PARAMS ((CGEN_BITSET *, unsigned));
+extern int cgen_bitset_compare PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern void cgen_bitset_union PARAMS ((CGEN_BITSET *, CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_intersect_p PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_contains PARAMS ((CGEN_BITSET *, unsigned));
+extern CGEN_BITSET *cgen_bitset_copy PARAMS ((CGEN_BITSET *));
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h
index efebadb6739..e8fd5d3d9f7 100644
--- a/include/opcode/cgen.h
+++ b/include/opcode/cgen.h
@@ -22,6 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef CGEN_H
 #define CGEN_H
 
+#include "symcat.h"
+#include "cgen-bitset.h"
 /* ??? This file requires bfd.h but only to get bfd_vma.
    Seems like an awful lot to require just to get such a fundamental type.
    Perhaps the definition of bfd_vma can be moved outside of bfd.h.
@@ -107,7 +109,13 @@ typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
 
 /* Type of attribute values.  */
 
-typedef int CGEN_ATTR_VALUE_TYPE;
+typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
+typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
+typedef union
+{
+  CGEN_ATTR_VALUE_BITSET_TYPE bitset;
+  CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
+} CGEN_ATTR_VALUE_TYPE;
 
 /* Struct to record attribute information.  */
 
@@ -153,7 +161,9 @@ struct { unsigned int bool; \
 #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
 ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
  ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
- : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET]))
+ : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
+#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
+ ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
 
 /* Attribute name/value tables.
    These are used to assist parsing of descriptions at run-time.  */
@@ -161,7 +171,7 @@ struct { unsigned int bool; \
 typedef struct
 {
   const char * name;
-  CGEN_ATTR_VALUE_TYPE value;
+  unsigned value;
 } CGEN_ATTR_ENTRY;
 
 /* For each domain (ifld,hw,operand,insn), list of attributes.  */
@@ -965,6 +975,7 @@ typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
 typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS = 0
 } CGEN_INSN_ATTR;
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
 #endif
 
 /* This struct defines each entry in the instruction table.  */
@@ -1016,6 +1027,8 @@ typedef struct
 /* Return value of attribute ATTR in INSN.  */
 #define CGEN_INSN_ATTR_VALUE(insn, attr) \
 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
+#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
+  CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
 } CGEN_IBASE;
 
 /* Return non-zero if INSN is the "invalid" insn marker.  */
@@ -1179,10 +1192,9 @@ typedef struct cgen_cpu_desc
   /* Bitmap of selected machine(s) (a la BFD machine number).  */
   int machs;
 
-  /* Bitmap of selected isa(s).
-     ??? Simultaneous multiple isas might not make sense, but it's not (yet)
-     precluded.  */
-  int isas;
+  /* Bitmap of selected isa(s).  */
+  CGEN_BITSET *isas;
+#define CGEN_CPU_ISAS(cd) ((cd)->isas)
 
   /* Current endian.  */
   enum cgen_endian endian;
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index 58553b3ad63..164594b8c7f 100644
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -75,13 +75,15 @@ enum ia64_opnd
     IA64_OPND_R3,	/* third register # */
     IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
 
+    /* memory operands: */
+    IA64_OPND_MR3,	/* memory at addr of third register # */
+
     /* indirect operands: */
     IA64_OPND_CPUID_R3,	/* cpuid[reg] */
     IA64_OPND_DBR_R3,	/* dbr[reg] */
     IA64_OPND_DTR_R3,	/* dtr[reg] */
     IA64_OPND_ITR_R3,	/* itr[reg] */
     IA64_OPND_IBR_R3,	/* ibr[reg] */
-    IA64_OPND_MR3,	/* memory at addr of third register # */
     IA64_OPND_MSR_R3,	/* msr[reg] */
     IA64_OPND_PKR_R3,	/* pkr[reg] */
     IA64_OPND_PMC_R3,	/* pmc[reg] */
diff --git a/intl/ChangeLog b/intl/ChangeLog
deleted file mode 100644
index 172f44cec1d..00000000000
--- a/intl/ChangeLog
+++ /dev/null
@@ -1,1106 +0,0 @@
-2005-05-13  Nick Clifton  <nickc@redhat.com>
-
-	* Update the address and phone number of the FSF organization in
-	the GPL notices in the following files:
-	Makefile.in, bindtextdom.c, cat-compat.c, dcgettext.c,
-	dgettext.c, explodename.c, finddomain.c, gettext.c, gettext.h,
-	gettextP.h, hash-string.h, intl-compat.c, intlh.inst.in,
-	l10nflist.c, libgettext.h, libintl.glibc, linux-msg.sed,
-	loadinfo.h, loadmsgcat.c, localealias.c, po2tbl.sed.in,
-	textdomain.c, xopen-msg.sed
-	
-2004-11-30  Tero Niemela  <tero_niemela@yahoo.com>
-
-	* Makefile.in: Change LOCALEDIR to $(datadir)/share.
-
-2002-01-21  Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at>
-
-	* linux-msg.sed: Comment typo fix.
-	* xopen-msg.sed: Likewise.
-
-1998-04-29  Ulrich Drepper  <drepper@cygnus.com>
-
-	* intl/localealias.c (read_alias_file): Use unsigned char for
-	local variables.  Remove unused variable tp.
-	* intl/l10nflist.c (_nl_normalize_codeset): Use unsigned char *
-	for type of codeset.  For loosing Solaris systems.
-	* intl/loadinfo.h: Adapt prototype of _nl_normalize_codeset.
-	* intl/bindtextdom.c (BINDTEXTDOMAIN): Don't define local variable
-	len if not needed.
-	Patches by Jim Meyering.
-
-1998-04-28  Ulrich Drepper  <drepper@cygnus.com>
-
-	* loadmsgcat.c (_nl_load_domain): Don't assign the element use_mmap if
-	mmap is not supported.
-
-	* hash-string.h: Don't include <values.h>.
-
-1998-04-27  Ulrich Drepper  <drepper@cygnus.com>
-
-	* textdomain.c: Use strdup is available.
-
-	* localealias.c: Define HAVE_MEMPCPY so that we can use this
-	function.  Define and use semapahores to protect modfication of
-	global objects when compiling for glibc.  Add code to allow
-	freeing alias table.
-
-	* l10nflist.c: Don't assume stpcpy not being a macro.
-
-	* gettextP.h: Define internal_function macri if not already done.
-	Use glibc byte-swap macros instead of defining SWAP when compiled
-	for glibc.
-	(struct loaded_domain): Add elements to allow unloading.
-
-	* Makefile.in (distclean): Don't remove libintl.h here.
-
-	* bindtextdomain.c: Carry over changes from glibc.  Use strdup if
-	available.
-
-	* dcgettext.c: Don't assume stpcpy not being a macro.  Mark internal
-	functions.  Add memory freeing code for glibc.
-
-	* dgettext.c: Update copyright.
-
-	* explodename.c: Include stdlib.h and string.h only if they exist.
-	Use strings.h eventually.
-
-	* finddomain.c: Mark internal functions.  Use strdup if available.
-	Add memory freeing code for glibc.
-
-1997-10-10 20:00  Ulrich Drepper  <drepper@cygnus.com>
-
-	* libgettext.h: Fix dummy textdomain and bindtextdomain macros.
-	They should return reasonable values.
-	Reported by Tom Tromey <tromey@cygnus.com>.
-
-1997-09-16 03:33  Ulrich Drepper  <drepper@cygnus.com>
-
-	* libgettext.h: Define PARAMS also to `args' if __cplusplus is defined.
-	* intlh.inst.in: Likewise.
-	Reported by Jean-Marc Lasgouttes <Jean-Marc.Lasgouttes@inria.fr>.
-
-	* libintl.glibc: Update from current glibc version.
-
-1997-09-06 02:10  Ulrich Drepper  <drepper@cygnus.com>
-
-	* intlh.inst.in: Reformat copyright.
-
-1997-08-19 15:22  Ulrich Drepper  <drepper@cygnus.com>
-
-	* dcgettext.c (DCGETTEXT): Remove wrong comment.
-
-1997-08-16 00:13  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (install-data): Don't change directory to install.
-
-1997-08-01 14:30  Ulrich Drepper  <drepper@cygnus.com>
-
-	* cat-compat.c: Fix copyright.
-
-	* localealias.c: Don't define strchr unless !HAVE_STRCHR.
-
-	* loadmsgcat.c: Update copyright.  Fix typos.
-
-	* l10nflist.c: Don't define strchr unless !HAVE_STRCHR.
-	(_nl_make_l10nflist): Handle sponsor and revision correctly.
-
-	* gettext.c: Update copyright.
-	* gettext.h: Likewise.
-	* hash-string.h: Likewise.
-
-	* finddomain.c: Remoave dead code.  Define strchr only if
-	!HAVE_STRCHR.
-
-	* explodename.c: Include <sys/types.h>.
-
-	* explodename.c: Reformat copyright text.
-	(_nl_explode_name): Fix typo.
-
-	* dcgettext.c: Define and use __set_errno.
-	(guess_category_value): Don't use setlocale if HAVE_LC_MESSAGES is
-	not defined.
-
-	* bindtextdom.c: Pretty printing.
-
-1997-05-01 02:25  Ulrich Drepper  <drepper@cygnus.com>
-
-	* dcgettext.c (guess_category_value): Don't depend on
-	HAVE_LC_MESSAGES.  We don't need the macro here.
-	Patch by Bruno Haible <haible@ilog.fr>.
-
-	* cat-compat.c (textdomain): DoN't refer to HAVE_SETLOCALE_NULL
-	macro.  Instead use HAVE_LOCALE_NULL and define it when using
-	glibc, as in dcgettext.c.
-	Patch by Bruno Haible <haible@ilog.fr>.
-
-	* Makefile.in (CPPFLAGS): New variable.  Reported by Franc,ois
-	Pinard.
-
-Mon Mar 10 06:51:17 1997  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in: Implement handling of libtool.
-
-	* gettextP.h: Change data structures for use of generic lowlevel
-	i18n file handling.
-
-Wed Dec  4 20:21:18 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* textdomain.c: Put parentheses around arguments of memcpy macro
-	definition.
-	* localealias.c: Likewise.
-	* l10nflist.c: Likewise.
-	* finddomain.c: Likewise.
-	* bindtextdom.c: Likewise.
-	Reported by Thomas Esken.
-
-Mon Nov 25 22:57:51 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* textdomain.c: Move definition of `memcpy` macro to right
-	position.
-
-Fri Nov 22 04:01:58 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* finddomain.c [!HAVE_STRING_H && !_LIBC]: Define memcpy using
- 	bcopy if not already defined.  Reported by Thomas Esken.
-	* bindtextdom.c: Likewise.
-	* l10nflist.c: Likewise.
-	* localealias.c: Likewise.
-	* textdomain.c: Likewise.
-
-Tue Oct 29 11:10:27 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (libdir): Change to use exec_prefix instead of
- 	prefix.  Reported by Knut-H�vardAksnes <etokna@eto.ericsson.se>.
-
-Sat Aug 31 03:07:09 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* l10nflist.c (_nl_normalize_codeset): We convert to lower case,
-	so don't prepend uppercase `ISO' for only numeric arg.
-
-Fri Jul 19 00:15:46 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* l10nflist.c: Move inclusion of argz.h, ctype.h, stdlib.h after
-	definition of _GNU_SOURCE.  Patch by Roland McGrath.
-
-	* Makefile.in (uninstall): Fix another bug with `for' loop and
-	empty arguments.  Patch by Jim Meyering.  Correct name os
-	uninstalled files: no intl- prefix anymore.
-
-	* Makefile.in (install-data): Again work around shells which
-	cannot handle mpty for list.  Reported by Jim Meyering.
-
-Sat Jul 13 18:11:35 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (install): Split goal.  Now depend on install-exec
-        and install-data.
-	(install-exec, install-data): New goals.  Created from former
-	install goal.
-	Reported by Karl Berry.
-
-Sat Jun 22 04:58:14 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (MKINSTALLDIRS): New variable.  Path to
-        mkinstalldirs script.
-	(install): use MKINSTALLDIRS variable or if the script is not present
-	try to find it in the $top_scrdir).
-
-Wed Jun 19 02:56:56 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* l10nflist.c: Linux libc *partly* includes the argz_* functions.
-	Grr.  Work around by renaming the static version and use macros
-	for renaming.
-
-Tue Jun 18 20:11:17 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* l10nflist.c: Correct presence test macros of __argz_* functions.
-
-	* l10nflist.c: Include <argz.h> based on test of it instead when
-	__argz_* functions are available.
-	Reported by Andreas Schwab.
-
-Thu Jun 13 15:17:44 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* explodename.c, l10nflist.c: Define NULL for dumb systems.
-
-Tue Jun 11 17:05:13 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* intlh.inst.in, libgettext.h (dcgettext): Rename local variable
-	result to __result to prevent name clash.
-
-	* l10nflist.c, localealias.c, dcgettext.c: Define _GNU_SOURCE to
-        get prototype for stpcpy and strcasecmp.
-
-	* intlh.inst.in, libgettext.h: Move declaration of
-	`_nl_msg_cat_cntr' outside __extension__ block to prevent warning
-	from gcc's -Wnested-extern option.
-
-Fri Jun  7 01:58:00 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (install): Remove comment.
-
-Thu Jun  6 17:28:17 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (install): Work around for another Buglix stupidity.
-	Always use an `else' close for `if's.  Reported by Nelson Beebe.
-
-	* Makefile.in (intlh.inst): Correct typo in phony rule.
-	Reported by Nelson Beebe.
-
-Thu Jun  6 01:49:52 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* dcgettext.c (read_alias_file): Rename variable alloca_list to
-	block_list as the macro calls assume.
-	Patch by Eric Backus.
-
-	* localealias.c [!HAVE_ALLOCA]: Define alloca as macro using
-        malloc.
-	(read_alias_file): Rename varriabe alloca_list to block_list as the
-	macro calls assume.
-	Patch by Eric Backus.
-
-	* l10nflist.c: Correct conditional for <argz.h> inclusion.
-	Reported by Roland McGrath.
-
-	* Makefile.in (all): Depend on all-@USE_INCLUDED_LIBINTL@, not
-        all-@USE_NLS@.
-
-	* Makefile.in (install): intlh.inst comes from local dir, not
-        $(srcdir).
-
-	* Makefile.in (intlh.inst): Special handling of this goal.  If
-	used in gettext, this is really a rul to construct this file.  If
-	used in any other package it is defined as a .PHONY rule with
-	empty body.
-
-	* finddomain.c: Extract locale file information handling into
-	l10nfile.c.  Rename local stpcpy__ function to stpcpy.
-
-	* dcgettext.c (stpcpy): Add local definition.
-
-	* l10nflist.c: Solve some portability problems.  Patches partly by
-	Thomas Esken.  Add local definition of stpcpy.
-
-Tue Jun  4 02:47:49 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* intlh.inst.in: Don't depend including <locale.h> on
-	HAVE_LOCALE_H.  Instead configure must rewrite this fiile
-	depending on the result of the configure run.
-
-	* Makefile.in (install): libintl.inst is now called intlh.inst.
-	Add rules for updating intlh.inst from intlh.inst.in.
-
-	* libintl.inst: Renamed to intlh.inst.in.
-
-	* localealias.c, dcgettext.c [__GNUC__]: Define HAVE_ALLOCA to 1
-        because gcc has __buitlin_alloca.
-	Reported by Roland McGrath.
-
-Mon Jun  3 00:32:16 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* Makefile.in (installcheck): New goal to fulfill needs of
-        automake's distcheck.
-
-	* Makefile.in (install): Reorder commands so that VERSION is
-        found.
-
-	* Makefile.in (gettextsrcdir): Now use subdirectory intl/ in
-        @datadir@/gettext.
-	(COMSRCS): Add l10nfile.c.
-	(OBJECTS): Add l10nfile.o.
-	(DISTFILES): Rename to DISTFILE.normal.  Remove $(DISTFILES.common).
-	(DISTFILE.gettext): Remove $(DISTFILES.common).
-	(all-gettext): Remove goal.
-	(install): If $(PACKAGE) = gettext install, otherwose do nothing.  No
-	package but gettext itself should install libintl.h + headers.
-	(dist): Extend goal to work for gettext, too.
-	(dist-gettext): Remove goal.
-
-	* dcgettext.c [!HAVE_ALLOCA]: Define macro alloca by using malloc.
-
-Sun Jun  2 17:33:06 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* loadmsgcat.c (_nl_load_domain): Parameter is now comes from
-        find_l10nfile.
-
-Sat Jun  1 02:23:03 1996  Ulrich Drepper  <drepper@cygnus.com>
-
-	* l10nflist.c (__argz_next): Add definition.
-
-	* dcgettext.c [!HAVE_ALLOCA]: Add code for handling missing alloca
-	code.  Use new l10nfile handling.
-
-	* localealias.c [!HAVE_ALLOCA]: Add code for handling missing
-        alloca code.
-
-	* l10nflist.c: Initial revision.
-
-Tue Apr  2 18:51:18 1996  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (all-gettext): New goal.  Same as all-yes.
-
-Thu Mar 28 23:01:22 1996  Karl Eichwalder  <ke@ke.central.de>
-
-	* Makefile.in (gettextsrcdir): Define using @datadir@.
-
-Tue Mar 26 12:39:14 1996  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c: Include <ctype.h>.  Reported by Roland McGrath.
-
-Sat Mar 23 02:00:35 1996  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (stpcpy): Rename to stpcpy__ to prevent clashing
-        with external declaration.
-
-Sat Mar  2 00:47:09 1996  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (all-no): Rename from all_no.
-
-Sat Feb 17 00:25:59 1996  Ulrich Drepper  <drepper@myware>
-
-	* gettextP.h [loaded_domain]: Array `successor' must now contain up
-        to 63 elements (because of codeset name normalization).
-
-	* finddomain.c: Implement codeset name normalization.
-
-Thu Feb 15 04:39:09 1996  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (all): Define to `all-@USE_NLS@'.
-	(all-yes, all_no): New goals.  `all-no' is noop, `all-yes'
-	is former all.
-
-Mon Jan 15 21:46:01 1996  Howard Gayle  <howard@hal.com>
-
-	* localealias.c (alias_compare): Increment string pointers in loop
-        of strcasecmp replacement.
-
-Fri Dec 29 21:16:34 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (install-src): Who commented this goal out ? :-)
-
-Fri Dec 29 15:08:16 1995  Ulrich Drepper  <drepper@myware>
-
-	* dcgettext.c (DCGETTEXT): Save `errno'.  Failing system calls
-	should not effect it because a missing catalog is no error.
-	Reported by Harald K<o:>nig <koenig@tat.physik.uni-tuebingen.de>.
-
-Tue Dec 19 22:09:13 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (Makefile): Explicitly use $(SHELL) for running
-        shell scripts.
-
-Fri Dec 15 17:34:59 1995  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
-
-	* Makefile.in (install-src): Only install library and header when
-	we use the own implementation.  Don't do it when using the
-	system's gettext or catgets functions.
-
-	* dcgettext.c (find_msg): Must not swap domain->hash_size here.
-
-Sat Dec  9 16:24:37 1995  Ulrich Drepper  <drepper@myware>
-
-	* localealias.c, libintl.inst, libgettext.h, hash-string.h,
-	gettextP.h, finddomain.c, dcgettext.c, cat-compat.c:
-	Use PARAMS instead of __P.  Suggested by Roland McGrath.
-
-Tue Dec  5 11:39:14 1995  Larry Schwimmer  <rosebud@cyclone.stanford.edu>
-
-	* libgettext.h: Use `#if !defined (_LIBINTL_H)' instead of `#if
-	!_LIBINTL_H' because Solaris defines _LIBINTL_H as empty.
-
-Mon Dec  4 15:42:07 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (install-src):
-	Install libintl.inst instead of libintl.h.install.
-
-Sat Dec  2 22:51:38 1995  Marcus Daniels  <marcus@sysc.pdx.edu>
-
-	* cat-compat.c (textdomain):
-	Reverse order in which files are tried you load.  First
-	try local file, when this failed absolute path.
-
-Wed Nov 29 02:03:53 1995  Nelson H. F. Beebe  <beebe@math.utah.edu>
-
-	* cat-compat.c (bindtextdomain): Add missing { }.
-
-Sun Nov 26 18:21:41 1995  Ulrich Drepper  <drepper@myware>
-
-	* libintl.inst: Add missing __P definition.  Reported by Nelson Beebe.
-
-	* Makefile.in:
-	Add dummy `all' and `dvi' goals.  Reported by Tom Tromey.
-
-Sat Nov 25 16:12:01 1995  Franc,ois Pinard  <pinard@iro.umontreal.ca>
-
-	* hash-string.h: Capitalize arguments of macros.
-
-Sat Nov 25 12:01:36 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (DISTFILES): Prevent files names longer than 13
-	characters.  libintl.h.glibc->libintl.glibc,
-	libintl.h.install->libintl.inst.  Reported by Joshua R. Poulson.
-
-Sat Nov 25 11:31:12 1995  Eric Backus  <ericb@lsid.hp.com>
-
-	* dcgettext.c: Fix bug in preprocessor conditionals.
-
-Sat Nov 25 02:35:27 1995  Nelson H. F. Beebe  <beebe@math.utah.edu>
-
-	* libgettext.h: Solaris cc does not understand
-	 #if !SYMBOL1 && !SYMBOL2.  Sad	but true.
-
-Thu Nov 23 16:22:14 1995  Ulrich Drepper  <drepper@myware>
-
-	* hash-string.h (hash_string):
-	Fix for machine with >32 bit `unsigned long's.
-
-	* dcgettext.c (DCGETTEXT):
-	Fix horrible bug in loop for alternative translation.
-
-Thu Nov 23 01:45:29 1995  Ulrich Drepper  <drepper@myware>
-
-	* po2tbl.sed.in, linux-msg.sed, xopen-msg.sed:
-	Some further simplifications in message number generation.
-
-Mon Nov 20 21:08:43 1995  Ulrich Drepper  <drepper@myware>
-
-	* libintl.h.glibc: Use __const instead of const in prototypes.
-
-	* Makefile.in (install-src):
-	Install libintl.h.install instead of libintl.h.  This
-	is a stripped-down version.  Suggested by Peter Miller.
-
-	* libintl.h.install, libintl.h.glibc: Initial revision.
-
-	* localealias.c (_nl_expand_alias, read_alias_file):
-	Protect prototypes in type casts by __P.
-
-Tue Nov 14 16:43:58 1995  Ulrich Drepper  <drepper@myware>
-
-	* hash-string.h: Correct prototype for hash_string.
-
-Sun Nov 12 12:42:30 1995  Ulrich Drepper  <drepper@myware>
-
-	* hash-string.h (hash_string): Add prototype.
-
-	* gettextP.h: Fix copyright.
-	(SWAP): Add prototype.
-
-Wed Nov  8 22:56:33 1995  Ulrich Drepper  <drepper@myware>
-
-	* localealias.c (read_alias_file): Forgot sizeof.
-	Avoid calling *printf function.  This introduces a big overhead.
-	Patch by Roland McGrath.
-
-Tue Nov  7 14:21:08 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c, cat-compat.c: Wrong indentation in #if for stpcpy.
-
-	* finddomain.c (stpcpy):
-	Define substitution function local.  The macro was to flaky.
-
-	* cat-compat.c: Fix typo.
-
-	* xopen-msg.sed, linux-msg.sed:
-	While bringing message number to right place only accept digits.
-
-	* linux-msg.sed, xopen-msg.sed: Now that the counter does not have
-	leading 0s we don't need to remove them.  Reported by Marcus
-	Daniels.
-
-	* Makefile.in (../po/cat-id-tbl.o): Use $(top_srdir) in
-	dependency.  Reported by Marcus Daniels.
-
-	* cat-compat.c: (stpcpy) [!_LIBC && !HAVE_STPCPY]: Define replacement.
-	Generally cleanup using #if instead of #ifndef.
-
-	* Makefile.in: Correct typos in comment.  By Franc,ois Pinard.
-
-Mon Nov  6 00:27:02 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (install-src): Don't install libintl.h and libintl.a
-	if we use an available gettext implementation.
-
-Sun Nov  5 22:02:08 1995  Ulrich Drepper  <drepper@myware>
-
-	* libgettext.h: Fix typo: HAVE_CATGETTS -> HAVE_CATGETS.  Reported
-	by Franc,ois Pinard.
-
-	* libgettext.h: Use #if instead of #ifdef/#ifndef.
-
-	* finddomain.c:
-	Comments describing what has to be done should start with FIXME.
-
-Sun Nov  5 19:38:01 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (DISTFILES): Split.  Use DISTFILES with normal meaning.
-	DISTFILES.common names the files common to both dist goals.
-	DISTFILES.gettext are the files only distributed in GNU gettext.
-
-Sun Nov  5 17:32:54 1995  Ulrich Drepper  <drepper@myware>
-
-	* dcgettext.c (DCGETTEXT): Correct searching in derived locales.
-	This was necessary since a change in _nl_find_msg several weeks
-	ago.  I really don't know this is still not fixed.
-
-Sun Nov  5 12:43:12 1995  Ulrich Drepper  <drepper@myware>
-
-	* loadmsgcat.c (_nl_load_domain): Test for FILENAME == NULL.  This
-	might mark a special condition.
-
-	* finddomain.c (make_entry_rec): Don't make illegal entry as decided.
-
-	* Makefile.in (dist): Suppress error message when ln failed.
-	Get files from $(srcdir) explicitly.
-
-	* libgettext.h (gettext_const): Rename to gettext_noop.
-
-Fri Nov  3 07:36:50 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (make_entry_rec):
-	Protect against wrong locale names by testing mask.
-
-	* libgettext.h (gettext_const): Add macro definition.
-	Capitalize macro arguments.
-
-Thu Nov  2 23:15:51 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (_nl_find_domain):
-	Test for pointer != NULL before accessing value.
-	Reported by Tom Tromey.
-
-	* gettext.c (NULL):
-	Define as (void*)0 instad of 0.  Reported by Franc,ois Pinard.
-
-Mon Oct 30 21:28:52 1995  Ulrich Drepper  <drepper@myware>
-
-	* po2tbl.sed.in: Serious typo bug fixed by Jim Meyering.
-
-Sat Oct 28 23:20:47 1995  Ulrich Drepper  <drepper@myware>
-
-	* libgettext.h: Disable dcgettext optimization for Solaris 2.3.
-
-	* localealias.c (alias_compare):
-	Peter Miller reported that tolower in some systems is
-	even dumber than I thought.  Protect call by `isupper'.
-
-Fri Oct 27 22:22:51 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (libdir, includedir): New variables.
-	(install-src): Install libintl.a and libintl.h in correct dirs.
-
-Fri Oct 27 22:07:29 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (SOURCES): Fix typo: intrl.compat.c -> intl-compat.c.
-
-	* po2tbl.sed.in: Patch for buggy SEDs by Christian von Roques.
-
-	* localealias.c:
-	Fix typo and superflous test.  Reported by Christian von Roques.
-
-Fri Oct  6 11:52:05 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (_nl_find_domain):
-	Correct some remainder from the pre-CEN syntax.  Now
-	we don't have a constant number of successors anymore.
-
-Wed Sep 27 21:41:13 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (DISTFILES): Add libintl.h.glibc.
-
-	* Makefile.in (dist-libc): Add goal for packing sources for glibc.
-	(COMSRCS, COMHDRS): Splitted to separate sources shared with glibc.
-
-	* loadmsgcat.c: Forget to continue #if line.
-
-	* localealias.c:
-	[_LIBC]: Rename strcasecmp to __strcasecmp to keep ANSI C name
-	space clean.
-
-	* dcgettext.c, finddomain.c: Better comment to last change.
-
-	* loadmsgcat.c:
-	[_LIBC]: Rename fstat, open, close, read, mmap, and munmap to
-	__fstat, __open, __close, __read, __mmap, and __munmap resp
-	to keep ANSI C name space clean.
-
-	* finddomain.c:
-	[_LIBC]: Rename stpcpy to __stpcpy to keep ANSI C name space clean.
-
-	* dcgettext.c:
-	[_LIBC]: Rename getced and stpcpy to __getcwd and __stpcpy resp to
-	keep ANSI C name space clean.
-
-	* libgettext.h:
-	Include sys/types.h for those old SysV systems out there.
-	Reported by Francesco Potorti`.
-
-	* loadmsgcat.c (use_mmap): Define if compiled for glibc.
-
-	* bindtextdom.c: Include all those standard headers
-	unconditionally if _LIBC is defined.
-
-	* finddomain.c: Fix 2 times defiend -> defined.
-
-	* textdomain.c: Include libintl.h instead of libgettext.h when
-	compiling for glibc.  Include all those standard headers
-	unconditionally if _LIBC is defined.
-
-	* localealias.c, loadmsgcat.c: Prepare to be compiled in glibc.
-
-	* gettext.c:
-	Include libintl.h instead of libgettext.h when compiling for glibc.
-	Get NULL from stddef.h if we compile for glibc.
-
-	* finddomain.c: Include libintl.h instead of libgettext.h when
-	compiling for glibc.  Include all those standard headers
-	unconditionally if _LIBC is defined.
-
-	* dcgettext.c: Include all those standard headers unconditionally
-	if _LIBC is defined.
-
-	* dgettext.c: If compiled in glibc include libintl.h instead of
-	libgettext.h.
-	(locale.h): Don't rely on HAVE_LOCALE_H when compiling for glibc.
-
-	* dcgettext.c: If compiled in glibc include libintl.h instead of
-	libgettext.h.
-	(getcwd): Don't rely on HAVE_GETCWD when compiling for glibc.
-
-	* bindtextdom.c:
-	If compiled in glibc include libintl.h instead of libgettext.h.
-
-Mon Sep 25 22:23:06 1995  Ulrich Drepper  <drepper@myware>
-
-	* localealias.c (_nl_expand_alias): Don't call bsearch if NMAP <= 0.
-	Reported by Marcus Daniels.
-
-	* cat-compat.c (bindtextdomain):
-	String used in putenv must not be recycled.
-	Reported by Marcus Daniels.
-
-	* libgettext.h (__USE_GNU_GETTEXT):
-	Additional symbol to signal that we use GNU gettext
-	library.
-
-	* cat-compat.c (bindtextdomain):
-	Fix bug with the strange stpcpy replacement.
-	Reported by Nelson Beebe.
-
-Sat Sep 23 08:23:51 1995  Ulrich Drepper  <drepper@myware>
-
-	* cat-compat.c: Include <string.h> for stpcpy prototype.
-
-	* localealias.c (read_alias_file):
-	While expand strdup code temporary variable `cp' hided
-	higher level variable with same name.  Rename to `tp'.
-
-	* textdomain.c (textdomain):
-	Avoid warning by using temporary variable in strdup code.
-
-	* finddomain.c (_nl_find_domain): Remove unused variable `application'.
-
-Thu Sep 21 15:51:44 1995  Ulrich Drepper  <drepper@myware>
-
-	* localealias.c (alias_compare):
-	Use strcasecmp() only if available.  Else use
-	implementation in place.
-
-	* intl-compat.c:
-	Wrapper functions now call *__ functions instead of __*.
-
-	* libgettext.h: Declare prototypes for *__ functions instead for __*.
-
-	* cat-compat.c, loadmsgcat.c:
-	Don't use xmalloc, xstrdup, and stpcpy.  These functions are not part
-	of the standard libc and so prevent libintl.a from being used
-	standalone.
-
-	* bindtextdom.c:
-	Don't use xmalloc, xstrdup, and stpcpy.  These functions are not part
-	of the standard libc and so prevent libintl.a from being used
-	standalone.
-	Rename to bindtextdomain__ if not used in GNU C Library.
-
-	* dgettext.c:
-	Rename function to dgettext__ if not used in GNU C Library.
-
-	* gettext.c:
-	Don't use xmalloc, xstrdup, and stpcpy.  These functions are not part
-	of the standard libc and so prevent libintl.a from being used
-	standalone.
-	Functions now called gettext__ if not used in GNU C Library.
-
-	* dcgettext.c, localealias.c, textdomain.c, finddomain.c:
-	Don't use xmalloc, xstrdup, and stpcpy.  These functions are not part
-	of the standard libc and so prevent libintl.a from being used
-	standalone.
-
-Sun Sep 17 23:14:49 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c: Correct some bugs in handling of CEN standard
- 	locale definitions.
-
-Thu Sep  7 01:49:28 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c: Implement CEN syntax.
-
-	* gettextP.h (loaded_domain): Extend number of successors to 31.
-
-Sat Aug 19 19:25:29 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (aliaspath): Remove path to X11 locale dir.
-
-	* Makefile.in: Make install-src depend on install.  This helps
- 	gettext to install the sources and other packages can use the
- 	install goal.
-
-Sat Aug 19 15:19:33 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (uninstall): Remove stuff installed by install-src.
-
-Tue Aug 15 13:13:53 1995  Ulrich Drepper  <drepper@myware>
-
-	* VERSION.in: Initial revision.
-
-	* Makefile.in (DISTFILES):
-	Add VERSION file.  This is not necessary for gettext, but
-	for other packages using this library.
-
-Tue Aug 15 06:16:44 1995  Ulrich Drepper  <drepper@myware>
-
-	* gettextP.h (_nl_find_domain):
-	New prototype after changing search strategy.
-
-	* finddomain.c (_nl_find_domain):
-	We now try only to find a specified catalog.  Fall back to other
-	catalogs listed in the locale list is now done in __dcgettext.
-
-	* dcgettext.c (__dcgettext):
-	Now we provide message fall back even to different languages.
-	I.e. if a message is not available in one language all the other
- 	in the locale list a tried.  Formerly fall back was only possible
- 	within one language.  Implemented by moving one loop from
- 	_nl_find_domain to here.
-
-Mon Aug 14 23:45:50 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (gettextsrcdir):
-	Directory where source of GNU gettext library are made
-	available.
-	(INSTALL, INSTALL_DATA): Programs used for installing sources.
-	(gettext-src): New.  Rule to install GNU gettext sources for use in
-	gettextize shell script.
-
-Sun Aug 13 14:40:48 1995  Ulrich Drepper  <drepper@myware>
-
-	* loadmsgcat.c (_nl_load_domain):
-	Use mmap for loading only when munmap function is
-	also available.
-
-	* Makefile.in (install): Depend on `all' goal.
-
-Wed Aug  9 11:04:33 1995  Ulrich Drepper  <drepper@myware>
-
-	* localealias.c (read_alias_file):
-	Do not overwrite '\n' when terminating alias value string.
-
-	* localealias.c (read_alias_file):
-	Handle long lines.  Ignore the rest not fitting in
-	the buffer after the initial `fgets' call.
-
-Wed Aug  9 00:54:29 1995  Ulrich Drepper  <drepper@myware>
-
-	* gettextP.h (_nl_load_domain):
-	Add prototype, replacing prototype for _nl_load_msg_cat.
-
-	* finddomain.c (_nl_find_domain):
-	Remove unneeded variable filename and filename_len.
-	(expand_alias): Remove prototype because functions does not
- 	exist anymore.
-
-	* localealias.c (read_alias_file):
-	Change type of fname_len parameter to int.
-	(xmalloc): Add prototype.
-
-	* loadmsgcat.c: Better prototypes for xmalloc.
-
-Tue Aug  8 22:30:39 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (_nl_find_domain):
-	Allow alias name to be constructed from the four components.
-
-	* Makefile.in (aliaspath): New variable.  Set to preliminary value.
-	(SOURCES): Add localealias.c.
-	(OBJECTS): Add localealias.o.
-
-	* gettextP.h: Add prototype for _nl_expand_alias.
-
-	* finddomain.c: Aliasing handled in intl/localealias.c.
-
-	* localealias.c: Aliasing for locale names.
-
-	* bindtextdom.c: Better prototypes for xmalloc and xstrdup.
-
-Mon Aug  7 23:47:42 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (DISTFILES): gettext.perl is now found in misc/.
-
-	* cat-compat.c (bindtextdomain):
-	Correct implementation.  dirname parameter was not used.
-	Reported by Marcus Daniels.
-
-	* gettextP.h (loaded_domain):
-	New fields `successor' and `decided' for oo, lazy
-	message handling implementation.
-
-	* dcgettext.c:
-	Adopt for oo, lazy message handliing.
-  	Now we can inherit translations from less specific locales.
-	(find_msg): New function.
-
-	* loadmsgcat.c, finddomain.c:
-	Complete rewrite.  Implement oo, lazy message handling :-).
-  	We now have an additional environment variable `LANGUAGE' with
- 	a higher priority than LC_ALL for the LC_MESSAGE locale.
-  	Here we can set a colon separated list of specifications each
- 	of the form `language[_territory[.codeset]][@modifier]'.
-
-Sat Aug  5 09:55:42 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (unistd.h):
-	Include to get _PC_PATH_MAX defined on system having it.
-
-Fri Aug  4 22:42:00 1995  Ulrich Drepper  <drepper@myware>
-
-	* finddomain.c (stpcpy): Include prototype.
-
-	* Makefile.in (dist): Remove `copying instead' message.
-
-Wed Aug  2 18:52:03 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (ID, TAGS): Do not use $^.
-
-Tue Aug  1 20:07:11 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (TAGS, ID): Use $^ as command argument.
-	(TAGS): Give etags -o option t write to current directory,
- 	not $(srcdir).
-	(ID): Use $(srcdir) instead os $(top_srcdir)/src.
-	(distclean): Remove ID.
-
-Sun Jul 30 11:51:46 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (gnulocaledir):
-	New variable, always using share/ for data directory.
-	(DEFS): Add GNULOCALEDIR, used in finddomain.c.
-
-	* finddomain.c (_nl_default_dirname):
-	Set to GNULOCALEDIR, because it always has to point
-	to the directory where GNU gettext Library writes it to.
-
-	* intl-compat.c (textdomain, bindtextdomain):
-	Undefine macros before function definition.
-
-Sat Jul 22 01:10:02 1995  Ulrich Drepper  <drepper@myware>
-
-	* libgettext.h (_LIBINTL_H):
-	Protect definition in case where this file is included as
-	libgettext.h on Solaris machines.  Add comment about this.
-
-Wed Jul 19 02:36:42 1995  Ulrich Drepper  <drepper@myware>
-
-	* intl-compat.c (textdomain): Correct typo.
-
-Wed Jul 19 01:51:35 1995  Ulrich Drepper  <drepper@myware>
-
-	* dcgettext.c (dcgettext): Function now called __dcgettext.
-
-	* dgettext.c (dgettext): Now called __dgettext and calls
- 	__dcgettext.
-
-	* gettext.c (gettext):
-	Function now called __gettext and calls __dgettext.
-
-	* textdomain.c (textdomain): Function now called __textdomain.
-
-	* bindtextdom.c (bindtextdomain): Function now called
- 	__bindtextdomain.
-
-	* intl-compat.c: Initial revision.
-
-	* Makefile.in (SOURCES): Add intl-compat.c.
-	(OBJECTS): We always compile the GNU gettext library functions.
-  	OBJECTS contains all objects but cat-compat.o, ../po/cat-if-tbl.o,
- 	and intl-compat.o.
-  	(GETTOBJS): Contains now only intl-compat.o.
-
-	* libgettext.h:
-	Re-include protection matches dualistic character of libgettext.h.
-	For all functions in GNU gettext library define __ counter part.
-
-	* finddomain.c (strchr): Define as index if not found in C library.
-	(_nl_find_domain): For relative paths paste / in between.
-
-Tue Jul 18 16:37:45 1995  Ulrich Drepper  <drepper@myware>
-
-	* loadmsgcat.c, finddomain.c: Add inclusion of sys/types.h.
-
-	* xopen-msg.sed: Fix bug with `msgstr ""' lines.
-	A little bit better comments.
-
-Tue Jul 18 01:18:27 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in:
-	po-mode.el, makelinks, combine-sh are now found in ../misc.
-
-	* po-mode.el, makelinks, combine-sh, elisp-comp:
-	Moved to ../misc/.
-
-	* libgettext.h, gettextP.h, gettext.h: Uniform test for __STDC__.
-
-Sun Jul 16 22:33:02 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (INSTALL, INSTALL_DATA): New variables.
-	(install-data, uninstall): Install/uninstall .elc file.
-
-	* po-mode.el (Installation comment):
-	Add .pox as possible extension of .po files.
-
-Sun Jul 16 13:23:27 1995  Ulrich Drepper  <drepper@myware>
-
-	* elisp-comp: Complete new version by Franc,ois: This does not
- 	fail when not compiling in the source directory.
-
-Sun Jul 16 00:12:17 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (../po/cat-id-tbl.o):
-	Use $(MAKE) instead of make for recursive make.
-
-	* Makefile.in (.el.elc): Use $(SHELL) instead of /bin/sh.
-	(install-exec): Add missing dummy goal.
-	(install-data, uninstall): @ in multi-line shell command at
- 	beginning, not in front of echo.  Reported by Eric Backus.
-
-Sat Jul 15 00:21:28 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (DISTFILES):
-	Rename libgettext.perl to gettext.perl to fit in 14 chars
-	file systems.
-
-	* gettext.perl:
- 	Rename to gettext.perl to fit in 14 chars file systems.
-
-Thu Jul 13 23:17:20 1995  Ulrich Drepper  <drepper@myware>
-
-	* cat-compat.c: If !STDC_HEADERS try to include malloc.h.
-
-Thu Jul 13 20:55:02 1995  Ulrich Drepper  <drepper@myware>
-
-	* po2tbl.sed.in: Pretty printing.
-
-	* linux-msg.sed, xopen-msg.sed:
-	Correct bugs with handling substitute flags in branches.
-
-	* hash-string.h (hash_string):
-	Old K&R compilers don't under stand `unsigned char'.
-
-	* gettext.h (nls_uint32):
-	Some old K&R compilers (eg HP) don't understand `unsigned int'.
-
-	* cat-compat.c (msg_to_cat_id): De-ANSI-fy prototypes.
-
-Thu Jul 13 01:34:33 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (ELCFILES): New variable.
-	(DISTFILES): Add elisp-comp.
-	Add implicit rule for .el -> .elc compilation.
-	(install-data): install $ELCFILES
-	(clean): renamed po-to-tbl and po-to-msg to po2tbl and po2msg resp.
-
-	* elisp-comp: Initial revision
-
-Wed Jul 12 16:14:52 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in:
-	cat-id-tbl.c is now found in po/.  This enables us to use an identical
-	intl/ directory in all packages.
-
-	* dcgettext.c (dcgettext): hashing does not work for table size <= 2.
-
-	* textdomain.c: fix typo (#if def -> #if defined)
-
-Tue Jul 11 18:44:43 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in (stamp-cat-id): use top_srcdir to address source files
-	(DISTFILES,distclean): move tupdate.perl to src/
-
-	* po-to-tbl.sed.in:
-	add additional jump to clear change flag to recognize multiline strings
-
-Tue Jul 11 01:32:50 1995  Ulrich Drepper  <drepper@myware>
-
-	* textdomain.c: Protect inclusion of stdlib.h and string.h.
-
-	* loadmsgcat.c: Protect inclusion of stdlib.h.
-
-	* libgettext.h: Protect inclusion of locale.h.
-	Allow use in C++ programs.
-	Define NULL is not happened already.
-
-	* Makefile.in (DISTFILES): ship po-to-tbl.sed.in instead of
-	po-to-tbl.sed.
-	(distclean): remove po-to-tbl.sed and tupdate.perl.
-
-	* tupdate.perl.in: Substitute Perl path even in exec line.
-	Don't include entries without translation from old .po file.
-
-Tue Jul  4 00:41:51 1995  Ulrich Drepper  <drepper@myware>
-
-	* tupdate.perl.in: use "Updated: " in msgid "".
-
-	* cat-compat.c: Fix typo (LOCALDIR -> LOCALEDIR).
- 	Define getenv if !__STDC__.
-
-	* bindtextdom.c: Protect stdlib.h and string.h inclusion.
- 	Define free if !__STDC__.
-
-	* finddomain.c: Change DEF_MSG_DOM_DIR to LOCALEDIR.
- 	Define free if !__STDC__.
-
-	* cat-compat.c: Change DEF_MSG_DOM_DIR to LOCALEDIR.
-
-Mon Jul  3 23:56:30 1995  Ulrich Drepper  <drepper@myware>
-
-	* Makefile.in: Use LOCALEDIR instead of DEF_MSG_DOM_DIR.
-	Remove unneeded $(srcdir) from Makefile.in dependency.
-
-	* makelinks: Add copyright and short description.
-
-	* po-mode.el: Last version for 0.7.
-
-	* tupdate.perl.in: Fix die message.
-
-	* dcgettext.c: Protect include of string.h.
-
-	* gettext.c: Protect include of stdlib.h and further tries to get NULL.
-
-	* finddomain.c: Some corrections in includes.
-
-	* Makefile.in (INCLUDES): Prune list correct path to Makefile.in.
-
-	* po-to-tbl.sed: Adopt for new .po file format.
-
-	* linux-msg.sed, xopen-msg.sed: Adopt for new .po file format.
-
-Sun Jul  2 23:55:03 1995  Ulrich Drepper  <drepper@myware>
-
-	* tupdate.perl.in: Complete rewrite for new .po file format.
-
-Sun Jul  2 02:06:50 1995  Ulrich Drepper  <drepper@myware>
-
-	* First official release.  This directory contains all the code
-	needed to internationalize own packages.  It provides functions
-	which allow to use the X/Open catgets function with an interface
-	like the Uniforum gettext function.  For system which does not
-	have neither of those a complete implementation is provided.
diff --git a/intl/Makefile.in b/intl/Makefile.in
deleted file mode 100644
index f3664ae3dca..00000000000
--- a/intl/Makefile.in
+++ /dev/null
@@ -1,214 +0,0 @@
-# Makefile for directory with message catalog handling in GNU NLS Utilities.
-# Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-PACKAGE = @PACKAGE@
-VERSION = @VERSION@
-
-SHELL = /bin/sh
-
-srcdir = @srcdir@
-top_srcdir = @top_srcdir@
-top_builddir = ..
-VPATH = @srcdir@
-
-prefix = @prefix@
-exec_prefix = @exec_prefix@
-transform = @program_transform_name@
-libdir = $(exec_prefix)/lib
-includedir = $(prefix)/include
-datadir = $(prefix)/@DATADIRNAME@
-localedir = $(datadir)/locale
-gnulocaledir = $(datadir)/locale
-gettextsrcdir = @datadir@/gettext/intl
-aliaspath = $(localedir):.
-subdir = intl
-
-INSTALL = @INSTALL@
-INSTALL_DATA = @INSTALL_DATA@
-MKINSTALLDIRS = @MKINSTALLDIRS@
-
-l = @l@
-
-AR = ar
-CC = @CC@
-LIBTOOL = @LIBTOOL@
-RANLIB = @RANLIB@
-
-DEFS = -DLOCALEDIR=\"$(localedir)\" -DGNULOCALEDIR=\"$(gnulocaledir)\" \
--DLOCALE_ALIAS_PATH=\"$(aliaspath)\" @DEFS@
-CPPFLAGS = @CPPFLAGS@
-CFLAGS = @CFLAGS@
-LDFLAGS = @LDFLAGS@
-
-COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS)
-
-HEADERS = $(COMHDRS) libgettext.h loadinfo.h
-COMHDRS = gettext.h gettextP.h hash-string.h
-SOURCES = $(COMSRCS) intl-compat.c cat-compat.c
-COMSRCS = bindtextdom.c dcgettext.c dgettext.c gettext.c \
-finddomain.c loadmsgcat.c localealias.c textdomain.c l10nflist.c \
-explodename.c
-OBJECTS = @INTLOBJS@ bindtextdom.$lo dcgettext.$lo dgettext.$lo gettext.$lo \
-finddomain.$lo loadmsgcat.$lo localealias.$lo textdomain.$lo l10nflist.$lo \
-explodename.$lo
-CATOBJS = cat-compat.$lo ../po/cat-id-tbl.$lo
-GETTOBJS = intl-compat.$lo
-DISTFILES.common = ChangeLog Makefile.in linux-msg.sed po2tbl.sed.in \
-xopen-msg.sed $(HEADERS) $(SOURCES)
-DISTFILES.normal = VERSION
-DISTFILES.gettext = libintl.glibc intlh.inst.in
-
-.SUFFIXES:
-.SUFFIXES: .c .o .lo
-.c.o:
-	$(COMPILE) $<
-.c.lo:
-	$(LIBTOOL) --mode=compile $(COMPILE) $<
-
-INCLUDES = -I. -I$(srcdir)
-
-all: all-@USE_INCLUDED_LIBINTL@
-
-all-yes: libintl.$la intlh.inst
-all-no:
-install-info:
-
-libintl.a: $(OBJECTS)
-	rm -f $@
-	$(AR) cru $@ $(OBJECTS)
-	$(RANLIB) $@
-
-libintl.la: $(OBJECTS)
-	$(LIBTOOL) --mode=link $(CC) $(LDFLAGS) -o $@ $(OBJECTS) \
-		   -version-info 1:0 -rpath $(libdir)
-
-../po/cat-id-tbl.$lo: ../po/cat-id-tbl.c $(top_srcdir)/po/$(PACKAGE).pot
-	cd ../po && $(MAKE) cat-id-tbl.$lo
-
-check: all
-
-# This installation goal is only used in GNU gettext.  Packages which
-# only use the library should use install instead.
-
-# We must not install the libintl.h/libintl.a files if we are on a
-# system which has the gettext() function in its C library or in a
-# separate library or use the catgets interface.  A special case is
-# where configure found a previously installed GNU gettext library.
-# If you want to use the one which comes with this version of the
-# package, you have to use `configure --with-included-gettext'.
-install: install-exec install-data
-install-exec: all
-	if test "$(PACKAGE)" = "gettext" \
-	   && test '@INTLOBJS@' = '$(GETTOBJS)'; then \
-	  if test -r $(MKINSTALLDIRS); then \
-	    $(MKINSTALLDIRS) $(libdir) $(includedir); \
-	  else \
-	    $(top_srcdir)/mkinstalldirs $(libdir) $(includedir); \
-	  fi; \
-	  $(INSTALL_DATA) intlh.inst $(includedir)/libintl.h; \
-	  $(INSTALL_DATA) libintl.a $(libdir)/libintl.a; \
-	else \
-	  : ; \
-	fi
-install-data: all
-	if test "$(PACKAGE)" = "gettext"; then \
-	  if test -r $(MKINSTALLDIRS); then \
-	    $(MKINSTALLDIRS) $(gettextsrcdir); \
-	  else \
-	    $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \
-	  fi; \
-	  $(INSTALL_DATA) VERSION $(gettextsrcdir)/VERSION; \
-	  dists="$(DISTFILES.common)"; \
-	  for file in $$dists; do \
-	    $(INSTALL_DATA) $(srcdir)/$$file $(gettextsrcdir)/$$file; \
-	  done; \
-	else \
-	  : ; \
-	fi
-
-# Define this as empty until I found a useful application.
-installcheck:
-
-uninstall:
-	dists="$(DISTFILES.common)"; \
-	for file in $$dists; do \
-	  rm -f $(gettextsrcdir)/$$file; \
-	done
-
-info dvi:
-
-$(OBJECTS): config.h libgettext.h
-bindtextdom.$lo finddomain.$lo loadmsgcat.$lo: gettextP.h gettext.h loadinfo.h
-dcgettext.$lo: gettextP.h gettext.h hash-string.h loadinfo.h
-
-tags: TAGS
-
-TAGS: $(HEADERS) $(SOURCES)
-	here=`pwd`; cd $(srcdir) && etags -o $$here/TAGS $(HEADERS) $(SOURCES)
-
-id: ID
-
-ID: $(HEADERS) $(SOURCES)
-	here=`pwd`; cd $(srcdir) && mkid -f$$here/ID $(HEADERS) $(SOURCES)
-
-
-mostlyclean:
-	rm -f *.a *.o *.lo core core.*
-
-clean: mostlyclean
-
-distclean: clean
-	rm -f Makefile ID TAGS po2msg.sed po2tbl.sed libintl.h config.log
-
-maintainer-clean: distclean
-	@echo "This command is intended for maintainers to use;"
-	@echo "it deletes files that may require special tools to rebuild."
-
-
-# GNU gettext needs not contain the file `VERSION' but contains some
-# other files which should not be distributed in other packages.
-distdir = ../$(PACKAGE)-$(VERSION)/$(subdir)
-dist distdir: Makefile $(DISTFILES)
-	if test "$(PACKAGE)" = gettext; then \
-	  additional="$(DISTFILES.gettext)"; \
-	else \
-	  additional="$(DISTFILES.normal)"; \
-	fi; \
-	for file in $(DISTFILES.common) $$additional; do \
-	  ln $(srcdir)/$$file $(distdir) 2> /dev/null \
-	    || cp -p $(srcdir)/$$file $(distdir); \
-	done
-
-dist-libc:
-	tar zcvf intl-glibc.tar.gz $(COMSRCS) $(COMHDRS) libintl.h.glibc
-
-Makefile: Makefile.in config.status
-	CONFIG_FILES=$@ CONFIG_HEADERS= $(SHELL) ./config.status
-
-# The dependency for intlh.inst is different in gettext and all other
-# packages.  Because we cannot you GNU make features we have to solve
-# the problem while rewriting Makefile.in.
-@GT_YES@intlh.inst: intlh.inst.in ../config.status
-@GT_YES@	cd .. \
-@GT_YES@	&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= \
-@GT_YES@	  $(SHELL) ./config.status
-@GT_NO@.PHONY: intlh.inst
-@GT_NO@intlh.inst:
-
-# Tell versions [3.59,3.63) of GNU make not to export all variables.
-# Otherwise a system limit (for SysV at least) may be exceeded.
-.NOEXPORT:
diff --git a/intl/acconfig.h b/intl/acconfig.h
deleted file mode 100644
index 70f81f80898..00000000000
--- a/intl/acconfig.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
-#undef HAVE_CATGETS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
diff --git a/intl/aclocal.m4 b/intl/aclocal.m4
deleted file mode 100644
index 225439f2125..00000000000
--- a/intl/aclocal.m4
+++ /dev/null
@@ -1,387 +0,0 @@
-dnl aclocal.m4 generated automatically by aclocal 1.3
-
-dnl Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-dnl This Makefile.in is free software; the Free Software Foundation
-dnl gives unlimited permission to copy and/or distribute it,
-dnl with or without modifications, as long as this notice is preserved.
-
-dnl This program is distributed in the hope that it will be useful,
-dnl but WITHOUT ANY WARRANTY, to the extent permitted by law; without
-dnl even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-dnl PARTICULAR PURPOSE.
-
-# Like AC_CONFIG_HEADER, but automatically create stamp file.
-
-AC_DEFUN(AM_CONFIG_HEADER,
-[AC_PREREQ([2.12])
-AC_CONFIG_HEADER([$1])
-dnl When config.status generates a header, we must update the stamp-h file.
-dnl This file resides in the same directory as the config header
-dnl that is generated.  We must strip everything past the first ":",
-dnl and everything past the last "/".
-AC_OUTPUT_COMMANDS(changequote(<<,>>)dnl
-ifelse(patsubst(<<$1>>, <<[^ ]>>, <<>>), <<>>,
-<<test -z "<<$>>CONFIG_HEADERS" || echo timestamp > patsubst(<<$1>>, <<^\([^:]*/\)?.*>>, <<\1>>)stamp-h<<>>dnl>>,
-<<am_indx=1
-for am_file in <<$1>>; do
-  case " <<$>>CONFIG_HEADERS " in
-  *" <<$>>am_file "*<<)>>
-    echo timestamp > `echo <<$>>am_file | sed -e 's%:.*%%' -e 's%[^/]*$%%'`stamp-h$am_indx
-    ;;
-  esac
-  am_indx=`expr "<<$>>am_indx" + 1`
-done<<>>dnl>>)
-changequote([,]))])
-
-
-# serial 1
-
-AC_DEFUN(AM_PROG_INSTALL,
-[AC_REQUIRE([AC_PROG_INSTALL])
-test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
-AC_SUBST(INSTALL_SCRIPT)dnl
-])
-
-# This file is derived from `gettext.m4'.  The difference is that the
-# included macros assume Cygnus-style source and build trees.
-
-# Macro to add for using GNU gettext.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 3
-
-AC_DEFUN(CY_WITH_NLS,
-  [AC_MSG_CHECKING([whether NLS is requested])
-    dnl Default is enabled NLS
-    AC_ARG_ENABLE(nls,
-      [  --disable-nls           do not use Native Language Support],
-      USE_NLS=$enableval, USE_NLS=yes)
-    AC_MSG_RESULT($USE_NLS)
-    AC_SUBST(USE_NLS)
-
-    USE_INCLUDED_LIBINTL=no
-
-    dnl If we use NLS figure out what method
-    if test "$USE_NLS" = "yes"; then
-      AC_DEFINE(ENABLE_NLS)
-      AC_MSG_CHECKING([whether included gettext is requested])
-      AC_ARG_WITH(included-gettext,
-        [  --with-included-gettext use the GNU gettext library included here],
-        nls_cv_force_use_gnu_gettext=$withval,
-        nls_cv_force_use_gnu_gettext=no)
-      AC_MSG_RESULT($nls_cv_force_use_gnu_gettext)
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-        dnl User does not insist on using GNU NLS library.  Figure out what
-        dnl to use.  If gettext or catgets are available (in this order) we
-        dnl use this.  Else we have to fall back to GNU NLS library.
-	dnl catgets is only used if permitted by option --with-catgets.
-	nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=NONE
-
-	AC_CHECK_HEADER(libintl.h,
-	  [AC_CACHE_CHECK([for gettext in libc], gt_cv_func_gettext_libc,
-	    [AC_TRY_LINK([#include <libintl.h>], [return (int) gettext ("")],
-	       gt_cv_func_gettext_libc=yes, gt_cv_func_gettext_libc=no)])
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     AC_CHECK_LIB(intl, bindtextdomain,
-	       [AC_CACHE_CHECK([for gettext in libintl],
-		 gt_cv_func_gettext_libintl,
-		 [AC_TRY_LINK([], [return (int) gettext ("")],
-		 gt_cv_func_gettext_libintl=yes,
-		 gt_cv_func_gettext_libintl=no)])])
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-	      AC_DEFINE(HAVE_GETTEXT)
-	      AM_PATH_PROG_WITH_TEST(MSGFMT, msgfmt,
-		[test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"], no)dnl
-	      if test "$MSGFMT" != "no"; then
-		AC_CHECK_FUNCS(dcgettext)
-		AC_PATH_PROG(GMSGFMT, gmsgfmt, $MSGFMT)
-		AM_PATH_PROG_WITH_TEST(XGETTEXT, xgettext,
-		  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"], :)
-		AC_TRY_LINK(, [extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr],
-		  [CATOBJEXT=.gmo
-		   DATADIRNAME=share],
-		  [CATOBJEXT=.mo
-		   DATADIRNAME=lib])
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-	])
-
-	dnl In the standard gettext, we would now check for catgets.
-        dnl However, we never want to use catgets for our releases.
-
-        if test "$CATOBJEXT" = "NONE"; then
-	  dnl Neither gettext nor catgets in included in the C library.
-	  dnl Fall back on GNU gettext library.
-	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-        dnl Mark actions used to generate GNU NLS library.
-        INTLOBJS="\$(GETTOBJS)"
-        AM_PATH_PROG_WITH_TEST(MSGFMT, msgfmt,
-	  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"], msgfmt)
-        AC_PATH_PROG(GMSGFMT, gmsgfmt, $MSGFMT)
-        AM_PATH_PROG_WITH_TEST(XGETTEXT, xgettext,
-	  [test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"], :)
-        AC_SUBST(MSGFMT)
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-      dnl Test whether we really found GNU xgettext.
-      if test "$XGETTEXT" != ":"; then
-	dnl If it is no GNU xgettext we define it as : so that the
-	dnl Makefiles still can work.
-	if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  AC_MSG_RESULT(
-	    [found xgettext programs is not GNU xgettext; ignore it])
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
-    else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
-    fi
-
-    dnl These rules are solely for the distribution goal.  While doing this
-    dnl we only have to keep exactly one list of the available catalogs
-    dnl in configure.in.
-    for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-    dnl Make all variables we use known to autoconf.
-    AC_SUBST(USE_INCLUDED_LIBINTL)
-    AC_SUBST(CATALOGS)
-    AC_SUBST(CATOBJEXT)
-    AC_SUBST(DATADIRNAME)
-    AC_SUBST(GMOFILES)
-    AC_SUBST(INSTOBJEXT)
-    AC_SUBST(INTLDEPS)
-    AC_SUBST(INTLLIBS)
-    AC_SUBST(INTLOBJS)
-    AC_SUBST(POFILES)
-    AC_SUBST(POSUB)
-  ])
-
-AC_DEFUN(CY_GNU_GETTEXT,
-  [AC_REQUIRE([AC_PROG_MAKE_SET])dnl
-   AC_REQUIRE([AC_PROG_CC])dnl
-   AC_REQUIRE([AC_PROG_RANLIB])dnl
-   AC_REQUIRE([AC_ISC_POSIX])dnl
-   AC_REQUIRE([AC_HEADER_STDC])dnl
-   AC_REQUIRE([AC_C_CONST])dnl
-   AC_REQUIRE([AC_C_INLINE])dnl
-   AC_REQUIRE([AC_TYPE_OFF_T])dnl
-   AC_REQUIRE([AC_TYPE_SIZE_T])dnl
-   AC_REQUIRE([AC_FUNC_ALLOCA])dnl
-   AC_REQUIRE([AC_FUNC_MMAP])dnl
-
-   AC_CHECK_HEADERS([argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h])
-   AC_CHECK_FUNCS([getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next])
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-     AC_CHECK_FUNCS(stpcpy)
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-     AC_DEFINE(HAVE_STPCPY)
-   fi
-
-   AM_LC_MESSAGES
-   CY_WITH_NLS
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       AC_MSG_CHECKING(for catalogs to be installed)
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       AC_MSG_RESULT($LINGUAS)
-     fi
-
-     dnl Construct list of names of catalog files to be constructed.
-     if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-   dnl The reference to <locale.h> in the installed <libintl.h> file
-   dnl must be resolved because we cannot expect the users of this
-   dnl to define HAVE_LOCALE_H.
-   if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-   AC_SUBST(INCLUDE_LOCALE_H)
-
-   dnl Determine which catalog format we have (if any is needed)
-   dnl For now we know about two different formats:
-   dnl   Linux libc-5 and the normal X/Open format
-   if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 AC_CHECK_HEADER(linux/version.h, msgformat=linux, msgformat=xopen)
-
-	 dnl Transform the SED scripts while copying because some dumb SEDs
-         dnl cannot handle comments.
-	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-      dnl po2tbl.sed is always needed.
-      sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-   dnl In the intl/Makefile.in we have a special dependency which makes
-   dnl only sense for gettext.  We comment this out for non-gettext
-   dnl packages.
-   if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-   AC_SUBST(GT_NO)
-   AC_SUBST(GT_YES)
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-   AC_SUBST(MKINSTALLDIRS)
-
-   dnl *** For now the libtool support in intl/Makefile is not for real.
-   l=
-   AC_SUBST(l)
-
-   dnl Generate list of files to be processed by xgettext which will
-   dnl be included in po/Makefile.  But only do this if the po directory
-   dnl exists in srcdir.
-   if test -d $srcdir/po; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
-  ])
-
-# Search path for a program which passes the given test.
-# Ulrich Drepper <drepper@cygnus.com>, 1996.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-dnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR,
-dnl   TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]])
-AC_DEFUN(AM_PATH_PROG_WITH_TEST,
-[# Extract the first word of "$2", so it can be a program name with args.
-set dummy $2; ac_word=[$]2
-AC_MSG_CHECKING([for $ac_word])
-AC_CACHE_VAL(ac_cv_path_$1,
-[case "[$]$1" in
-  /*)
-  ac_cv_path_$1="[$]$1" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in ifelse([$5], , $PATH, [$5]); do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if [$3]; then
-	ac_cv_path_$1="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-dnl If no 4th arg is given, leave the cache variable unset,
-dnl so AC_PATH_PROGS will keep looking.
-ifelse([$4], , , [  test -z "[$]ac_cv_path_$1" && ac_cv_path_$1="$4"
-])dnl
-  ;;
-esac])dnl
-$1="$ac_cv_path_$1"
-if test -n "[$]$1"; then
-  AC_MSG_RESULT([$]$1)
-else
-  AC_MSG_RESULT(no)
-fi
-AC_SUBST($1)dnl
-])
-
-# Check whether LC_MESSAGES is available in <locale.h>.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-AC_DEFUN(AM_LC_MESSAGES,
-  [if test $ac_cv_header_locale_h = yes; then
-    AC_CACHE_CHECK([for LC_MESSAGES], am_cv_val_LC_MESSAGES,
-      [AC_TRY_LINK([#include <locale.h>], [return LC_MESSAGES],
-       am_cv_val_LC_MESSAGES=yes, am_cv_val_LC_MESSAGES=no)])
-    if test $am_cv_val_LC_MESSAGES = yes; then
-      AC_DEFINE(HAVE_LC_MESSAGES)
-    fi
-  fi])
-
diff --git a/intl/bindtextdom.c b/intl/bindtextdom.c
deleted file mode 100644
index 42b87d297b8..00000000000
--- a/intl/bindtextdom.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Implementation of the bindtextdomain(3) function
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#else
-# ifdef HAVE_MALLOC_H
-#  include <malloc.h>
-# else
-void free ();
-# endif
-#endif
-
-#if defined HAVE_STRING_H || defined _LIBC
-# include <string.h>
-#else
-# include <strings.h>
-# ifndef memcpy
-#  define memcpy(Dst, Src, Num) bcopy (Src, Dst, Num)
-# endif
-#endif
-
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-#include "gettext.h"
-#include "gettextP.h"
-
-/* @@ end of prolog @@ */
-
-/* Contains the default location of the message catalogs.  */
-extern const char _nl_default_dirname[];
-
-/* List with bindings of specific domains.  */
-extern struct binding *_nl_domain_bindings;
-
-
-/* Names for the libintl functions are a problem.  They must not clash
-   with existing names and they should follow ANSI C.  But this source
-   code is also used in GNU C Library where the names have a __
-   prefix.  So we have to make a difference here.  */
-#ifdef _LIBC
-# define BINDTEXTDOMAIN __bindtextdomain
-# ifndef strdup
-#  define strdup(str) __strdup (str)
-# endif
-#else
-# define BINDTEXTDOMAIN bindtextdomain__
-#endif
-
-/* Specify that the DOMAINNAME message catalog will be found
-   in DIRNAME rather than in the system locale data base.  */
-char *
-BINDTEXTDOMAIN (domainname, dirname)
-     const char *domainname;
-     const char *dirname;
-{
-  struct binding *binding;
-
-  /* Some sanity checks.  */
-  if (domainname == NULL || domainname[0] == '\0')
-    return NULL;
-
-  for (binding = _nl_domain_bindings; binding != NULL; binding = binding->next)
-    {
-      int compare = strcmp (domainname, binding->domainname);
-      if (compare == 0)
-	/* We found it!  */
-	break;
-      if (compare < 0)
-	{
-	  /* It is not in the list.  */
-	  binding = NULL;
-	  break;
-	}
-    }
-
-  if (dirname == NULL)
-    /* The current binding has be to returned.  */
-    return binding == NULL ? (char *) _nl_default_dirname : binding->dirname;
-
-  if (binding != NULL)
-    {
-      /* The domain is already bound.  If the new value and the old
-	 one are equal we simply do nothing.  Otherwise replace the
-	 old binding.  */
-      if (strcmp (dirname, binding->dirname) != 0)
-	{
-	  char *new_dirname;
-
-	  if (strcmp (dirname, _nl_default_dirname) == 0)
-	    new_dirname = (char *) _nl_default_dirname;
-	  else
-	    {
-#if defined _LIBC || defined HAVE_STRDUP
-	      new_dirname = strdup (dirname);
-	      if (new_dirname == NULL)
-		return NULL;
-#else
-	      size_t len = strlen (dirname) + 1;
-	      new_dirname = (char *) malloc (len);
-	      if (new_dirname == NULL)
-		return NULL;
-
-	      memcpy (new_dirname, dirname, len);
-#endif
-	    }
-
-	  if (binding->dirname != _nl_default_dirname)
-	    free (binding->dirname);
-
-	  binding->dirname = new_dirname;
-	}
-    }
-  else
-    {
-      /* We have to create a new binding.  */
-#if !defined _LIBC && !defined HAVE_STRDUP
-      size_t len;
-#endif
-      struct binding *new_binding =
-	(struct binding *) malloc (sizeof (*new_binding));
-
-      if (new_binding == NULL)
-	return NULL;
-
-#if defined _LIBC || defined HAVE_STRDUP
-      new_binding->domainname = strdup (domainname);
-      if (new_binding->domainname == NULL)
-	return NULL;
-#else
-      len = strlen (domainname) + 1;
-      new_binding->domainname = (char *) malloc (len);
-      if (new_binding->domainname == NULL)
-	return NULL;
-      memcpy (new_binding->domainname, domainname, len);
-#endif
-
-      if (strcmp (dirname, _nl_default_dirname) == 0)
-	new_binding->dirname = (char *) _nl_default_dirname;
-      else
-	{
-#if defined _LIBC || defined HAVE_STRDUP
-	  new_binding->dirname = strdup (dirname);
-	  if (new_binding->dirname == NULL)
-	    return NULL;
-#else
-	  len = strlen (dirname) + 1;
-	  new_binding->dirname = (char *) malloc (len);
-	  if (new_binding->dirname == NULL)
-	    return NULL;
-	  memcpy (new_binding->dirname, dirname, len);
-#endif
-	}
-
-      /* Now enqueue it.  */
-      if (_nl_domain_bindings == NULL
-	  || strcmp (domainname, _nl_domain_bindings->domainname) < 0)
-	{
-	  new_binding->next = _nl_domain_bindings;
-	  _nl_domain_bindings = new_binding;
-	}
-      else
-	{
-	  binding = _nl_domain_bindings;
-	  while (binding->next != NULL
-		 && strcmp (domainname, binding->next->domainname) > 0)
-	    binding = binding->next;
-
-	  new_binding->next = binding->next;
-	  binding->next = new_binding;
-	}
-
-      binding = new_binding;
-    }
-
-  return binding->dirname;
-}
-
-#ifdef _LIBC
-/* Alias for function name in GNU C Library.  */
-weak_alias (__bindtextdomain, bindtextdomain);
-#endif
diff --git a/intl/cat-compat.c b/intl/cat-compat.c
deleted file mode 100644
index be4afff87b5..00000000000
--- a/intl/cat-compat.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* Compatibility code for gettext-using-catgets interface.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include <stdio.h>
-
-#ifdef STDC_HEADERS
-# include <stdlib.h>
-# include <string.h>
-#else
-char *getenv ();
-# ifdef HAVE_MALLOC_H
-#  include <malloc.h>
-# endif
-#endif
-
-#ifdef HAVE_NL_TYPES_H
-# include <nl_types.h>
-#endif
-
-#include "libgettext.h"
-
-/* @@ end of prolog @@ */
-
-/* XPG3 defines the result of `setlocale (category, NULL)' as:
-   ``Directs `setlocale()' to query `category' and return the current
-     setting of `local'.''
-   However it does not specify the exact format.  And even worse: POSIX
-   defines this not at all.  So we can use this feature only on selected
-   system (e.g. those using GNU C Library).  */
-#ifdef _LIBC
-# define HAVE_LOCALE_NULL
-#endif
-
-/* The catalog descriptor.  */
-static nl_catd catalog = (nl_catd) -1;
-
-/* Name of the default catalog.  */
-static const char default_catalog_name[] = "messages";
-
-/* Name of currently used catalog.  */
-static const char *catalog_name = default_catalog_name;
-
-/* Get ID for given string.  If not found return -1.  */
-static int msg_to_cat_id PARAMS ((const char *msg));
-
-/* Substitution for systems lacking this function in their C library.  */
-#if !_LIBC && !HAVE_STPCPY
-static char *stpcpy PARAMS ((char *dest, const char *src));
-#endif
-
-
-/* Set currently used domain/catalog.  */
-char *
-textdomain (domainname)
-     const char *domainname;
-{
-  nl_catd new_catalog;
-  char *new_name;
-  size_t new_name_len;
-  char *lang;
-
-#if defined HAVE_SETLOCALE && defined HAVE_LC_MESSAGES \
-    && defined HAVE_LOCALE_NULL
-  lang = setlocale (LC_MESSAGES, NULL);
-#else
-  lang = getenv ("LC_ALL");
-  if (lang == NULL || lang[0] == '\0')
-    {
-      lang = getenv ("LC_MESSAGES");
-      if (lang == NULL || lang[0] == '\0')
-	lang = getenv ("LANG");
-    }
-#endif
-  if (lang == NULL || lang[0] == '\0')
-    lang = "C";
-
-  /* See whether name of currently used domain is asked.  */
-  if (domainname == NULL)
-    return (char *) catalog_name;
-
-  if (domainname[0] == '\0')
-    domainname = default_catalog_name;
-
-  /* Compute length of added path element.  */
-  new_name_len = sizeof (LOCALEDIR) - 1 + 1 + strlen (lang)
-		 + sizeof ("/LC_MESSAGES/") - 1 + sizeof (PACKAGE) - 1
-		 + sizeof (".cat");
-
-  new_name = (char *) malloc (new_name_len);
-  if (new_name == NULL)
-    return NULL;
-
-  strcpy (new_name, PACKAGE);
-  new_catalog = catopen (new_name, 0);
-
-  if (new_catalog == (nl_catd) -1)
-    {
-      /* NLSPATH search didn't work, try absolute path */
-      sprintf (new_name, "%s/%s/LC_MESSAGES/%s.cat", LOCALEDIR, lang,
-	       PACKAGE);
-      new_catalog = catopen (new_name, 0);
-
-      if (new_catalog == (nl_catd) -1)
-	{
-	  free (new_name);
-	  return (char *) catalog_name;
-	}
-    }
-
-  /* Close old catalog.  */
-  if (catalog != (nl_catd) -1)
-    catclose (catalog);
-  if (catalog_name != default_catalog_name)
-    free ((char *) catalog_name);
-
-  catalog = new_catalog;
-  catalog_name = new_name;
-
-  return (char *) catalog_name;
-}
-
-char *
-bindtextdomain (domainname, dirname)
-     const char *domainname;
-     const char *dirname;
-{
-#if HAVE_SETENV || HAVE_PUTENV
-  char *old_val, *new_val, *cp;
-  size_t new_val_len;
-
-  /* This does not make much sense here but to be compatible do it.  */
-  if (domainname == NULL)
-    return NULL;
-
-  /* Compute length of added path element.  If we use setenv we don't need
-     the first byts for NLSPATH=, but why complicate the code for this
-     peanuts.  */
-  new_val_len = sizeof ("NLSPATH=") - 1 + strlen (dirname)
-		+ sizeof ("/%L/LC_MESSAGES/%N.cat");
-
-  old_val = getenv ("NLSPATH");
-  if (old_val == NULL || old_val[0] == '\0')
-    {
-      old_val = NULL;
-      new_val_len += 1 + sizeof (LOCALEDIR) - 1
-	             + sizeof ("/%L/LC_MESSAGES/%N.cat");
-    }
-  else
-    new_val_len += strlen (old_val);
-
-  new_val = (char *) malloc (new_val_len);
-  if (new_val == NULL)
-    return NULL;
-
-# if HAVE_SETENV
-  cp = new_val;
-# else
-  cp = stpcpy (new_val, "NLSPATH=");
-# endif
-
-  cp = stpcpy (cp, dirname);
-  cp = stpcpy (cp, "/%L/LC_MESSAGES/%N.cat:");
-
-  if (old_val == NULL)
-    {
-# if __STDC__
-      stpcpy (cp, LOCALEDIR "/%L/LC_MESSAGES/%N.cat");
-# else
-
-      cp = stpcpy (cp, LOCALEDIR);
-      stpcpy (cp, "/%L/LC_MESSAGES/%N.cat");
-# endif
-    }
-  else
-    stpcpy (cp, old_val);
-
-# if HAVE_SETENV
-  setenv ("NLSPATH", new_val, 1);
-  free (new_val);
-# else
-  putenv (new_val);
-  /* Do *not* free the environment entry we just entered.  It is used
-     from now on.   */
-# endif
-
-#endif
-
-  return (char *) domainname;
-}
-
-#undef gettext
-char *
-gettext (msg)
-     const char *msg;
-{
-  int msgid;
-
-  if (msg == NULL || catalog == (nl_catd) -1)
-    return (char *) msg;
-
-  /* Get the message from the catalog.  We always use set number 1.
-     The message ID is computed by the function `msg_to_cat_id'
-     which works on the table generated by `po-to-tbl'.  */
-  msgid = msg_to_cat_id (msg);
-  if (msgid == -1)
-    return (char *) msg;
-
-  return catgets (catalog, 1, msgid, (char *) msg);
-}
-
-/* Look through the table `_msg_tbl' which has `_msg_tbl_length' entries
-   for the one equal to msg.  If it is found return the ID.  In case when
-   the string is not found return -1.  */
-static int
-msg_to_cat_id (msg)
-     const char *msg;
-{
-  int cnt;
-
-  for (cnt = 0; cnt < _msg_tbl_length; ++cnt)
-    if (strcmp (msg, _msg_tbl[cnt]._msg) == 0)
-      return _msg_tbl[cnt]._msg_number;
-
-  return -1;
-}
-
-
-/* @@ begin of epilog @@ */
-
-/* We don't want libintl.a to depend on any other library.  So we
-   avoid the non-standard function stpcpy.  In GNU C Library this
-   function is available, though.  Also allow the symbol HAVE_STPCPY
-   to be defined.  */
-#if !_LIBC && !HAVE_STPCPY
-static char *
-stpcpy (dest, src)
-     char *dest;
-     const char *src;
-{
-  while ((*dest++ = *src++) != '\0')
-    /* Do nothing. */ ;
-  return dest - 1;
-}
-#endif
diff --git a/intl/config.in b/intl/config.in
deleted file mode 100644
index 8a9049b80de..00000000000
--- a/intl/config.in
+++ /dev/null
@@ -1,128 +0,0 @@
-/* config.in.  Generated automatically from configure.in by autoheader.  */
-
-/* Define if using alloca.c.  */
-#undef C_ALLOCA
-
-/* Define to empty if the keyword does not work.  */
-#undef const
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define if you have a working `mmap' system call.  */
-#undef HAVE_MMAP
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#undef inline
-
-/* Define to `long' if <sys/types.h> doesn't define.  */
-#undef off_t
-
-/* Define if you need to in order for stat and other things to work.  */
-#undef _POSIX_SOURCE
-
-/* Define to `unsigned' if <sys/types.h> doesn't define.  */
-#undef size_t
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#undef STACK_DIRECTION
-
-/* Define if you have the ANSI C header files.  */
-#undef STDC_HEADERS
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
-#undef HAVE_CATGETS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
-
-/* Define if you have the __argz_count function.  */
-#undef HAVE___ARGZ_COUNT
-
-/* Define if you have the __argz_next function.  */
-#undef HAVE___ARGZ_NEXT
-
-/* Define if you have the __argz_stringify function.  */
-#undef HAVE___ARGZ_STRINGIFY
-
-/* Define if you have the dcgettext function.  */
-#undef HAVE_DCGETTEXT
-
-/* Define if you have the getcwd function.  */
-#undef HAVE_GETCWD
-
-/* Define if you have the getpagesize function.  */
-#undef HAVE_GETPAGESIZE
-
-/* Define if you have the munmap function.  */
-#undef HAVE_MUNMAP
-
-/* Define if you have the putenv function.  */
-#undef HAVE_PUTENV
-
-/* Define if you have the setenv function.  */
-#undef HAVE_SETENV
-
-/* Define if you have the setlocale function.  */
-#undef HAVE_SETLOCALE
-
-/* Define if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if you have the strcasecmp function.  */
-#undef HAVE_STRCASECMP
-
-/* Define if you have the strchr function.  */
-#undef HAVE_STRCHR
-
-/* Define if you have the <argz.h> header file.  */
-#undef HAVE_ARGZ_H
-
-/* Define if you have the <limits.h> header file.  */
-#undef HAVE_LIMITS_H
-
-/* Define if you have the <locale.h> header file.  */
-#undef HAVE_LOCALE_H
-
-/* Define if you have the <malloc.h> header file.  */
-#undef HAVE_MALLOC_H
-
-/* Define if you have the <nl_types.h> header file.  */
-#undef HAVE_NL_TYPES_H
-
-/* Define if you have the <string.h> header file.  */
-#undef HAVE_STRING_H
-
-/* Define if you have the <sys/param.h> header file.  */
-#undef HAVE_SYS_PARAM_H
-
-/* Define if you have the <unistd.h> header file.  */
-#undef HAVE_UNISTD_H
-
-/* Define if you have the <values.h> header file.  */
-#undef HAVE_VALUES_H
-
-/* Define if you have the i library (-li).  */
-#undef HAVE_LIBI
diff --git a/intl/configure b/intl/configure
deleted file mode 100755
index 341eea019ae..00000000000
--- a/intl/configure
+++ /dev/null
@@ -1,2950 +0,0 @@
-#! /bin/sh
-
-# Guess values for system-dependent variables and create Makefiles.
-# Generated automatically using autoconf version 2.12.1 
-# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
-#
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-
-# Defaults:
-ac_help=
-ac_default_prefix=/usr/local
-# Any additions from configure.in:
-ac_help="$ac_help
-  --disable-nls           do not use Native Language Support"
-ac_help="$ac_help
-  --with-included-gettext use the GNU gettext library included here"
-
-# Initialize some variables set by options.
-# The variables have the same names as the options, with
-# dashes changed to underlines.
-build=NONE
-cache_file=./config.cache
-exec_prefix=NONE
-host=NONE
-no_create=
-nonopt=NONE
-no_recursion=
-prefix=NONE
-program_prefix=NONE
-program_suffix=NONE
-program_transform_name=s,x,x,
-silent=
-site=
-srcdir=
-target=NONE
-verbose=
-x_includes=NONE
-x_libraries=NONE
-bindir='${exec_prefix}/bin'
-sbindir='${exec_prefix}/sbin'
-libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
-sysconfdir='${prefix}/etc'
-sharedstatedir='${prefix}/com'
-localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
-includedir='${prefix}/include'
-oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
-
-# Initialize some other variables.
-subdirs=
-MFLAGS= MAKEFLAGS=
-SHELL=${CONFIG_SHELL-/bin/sh}
-# Maximum number of lines to put in a shell here document.
-ac_max_here_lines=12
-
-ac_prev=
-for ac_option
-do
-
-  # If the previous option needs an argument, assign it.
-  if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
-    ac_prev=
-    continue
-  fi
-
-  case "$ac_option" in
-  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
-  *) ac_optarg= ;;
-  esac
-
-  # Accept the important Cygnus configure options, so we can diagnose typos.
-
-  case "$ac_option" in
-
-  -bindir | --bindir | --bindi | --bind | --bin | --bi)
-    ac_prev=bindir ;;
-  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
-    bindir="$ac_optarg" ;;
-
-  -build | --build | --buil | --bui | --bu)
-    ac_prev=build ;;
-  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
-    build="$ac_optarg" ;;
-
-  -cache-file | --cache-file | --cache-fil | --cache-fi \
-  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
-    ac_prev=cache_file ;;
-  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
-  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
-    cache_file="$ac_optarg" ;;
-
-  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
-    ac_prev=datadir ;;
-  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
-  | --da=*)
-    datadir="$ac_optarg" ;;
-
-  -disable-* | --disable-*)
-    ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
-    # Reject names that are not valid shell variable names.
-    if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
-      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
-    fi
-    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
-    eval "enable_${ac_feature}=no" ;;
-
-  -enable-* | --enable-*)
-    ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
-    # Reject names that are not valid shell variable names.
-    if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
-      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
-    fi
-    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
-    case "$ac_option" in
-      *=*) ;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "enable_${ac_feature}='$ac_optarg'" ;;
-
-  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
-  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
-  | --exec | --exe | --ex)
-    ac_prev=exec_prefix ;;
-  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
-  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
-  | --exec=* | --exe=* | --ex=*)
-    exec_prefix="$ac_optarg" ;;
-
-  -gas | --gas | --ga | --g)
-    # Obsolete; use --with-gas.
-    with_gas=yes ;;
-
-  -help | --help | --hel | --he)
-    # Omit some internal or obsolete options to make the list less imposing.
-    # This message is too long to be a string in the A/UX 3.1 sh.
-    cat << EOF
-Usage: configure [options] [host]
-Options: [defaults in brackets after descriptions]
-Configuration:
-  --cache-file=FILE       cache test results in FILE
-  --help                  print this message
-  --no-create             do not create output files
-  --quiet, --silent       do not print \`checking...' messages
-  --version               print the version of autoconf that created configure
-Directory and file names:
-  --prefix=PREFIX         install architecture-independent files in PREFIX
-                          [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-                          [same as prefix]
-  --bindir=DIR            user executables in DIR [EPREFIX/bin]
-  --sbindir=DIR           system admin executables in DIR [EPREFIX/sbin]
-  --libexecdir=DIR        program executables in DIR [EPREFIX/libexec]
-  --datadir=DIR           read-only architecture-independent data in DIR
-                          [PREFIX/share]
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-  for ac_dir in $PATH; do
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-
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:783: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
-
-ac_ext=c
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-  echo "configure: failed program was:" >&5
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-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:817: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
-echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
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-echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
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-
-echo "$ac_t""$ac_cv_prog_gcc" 1>&6
-
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-  CFLAGS=
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-echo "configure:846: checking whether ${CC-cc} accepts -g" >&5
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-
-# Extract the first word of "ranlib", so it can be a program name with args.
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-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:876: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
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-  if test -n "$RANLIB"; then
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-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
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-  echo "$ac_t""no" 1>&6
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-
-echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
-echo "configure:903: checking for POSIXized ISC" >&5
-if test -d /etc/conf/kconfig.d &&
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-then
-  echo "$ac_t""yes" 1>&6
-  ISC=yes # If later tests want to check for ISC.
-  cat >> confdefs.h <<\EOF
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-
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-  echo "$ac_t""no" 1>&6
-  ISC=
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-
-echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
-echo "configure:924: checking for ANSI C header files" >&5
-if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 929 "configure"
-#include "confdefs.h"
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-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:937: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out`
-if test -z "$ac_err"; then
-  rm -rf conftest*
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-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_header_stdc=no
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-rm -f conftest*
-
-if test $ac_cv_header_stdc = yes; then
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-#line 954 "configure"
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-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
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-#line 972 "configure"
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-
-fi
-
-if test $ac_cv_header_stdc = yes; then
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-#line 993 "configure"
-#include "confdefs.h"
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-
-EOF
-if { (eval echo configure:1004: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
-then
-  :
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-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_header_stdc=no
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-rm -fr conftest*
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-
-fi
-fi
-
-echo "$ac_t""$ac_cv_header_stdc" 1>&6
-if test $ac_cv_header_stdc = yes; then
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-
-fi
-
-echo $ac_n "checking for working const""... $ac_c" 1>&6
-echo "configure:1028: checking for working const" >&5
-if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1033 "configure"
-#include "confdefs.h"
-
-int main() {
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-/* Ultrix mips cc rejects this.  */
-typedef int charset[2]; const charset x;
-/* SunOS 4.1.1 cc rejects this.  */
-char const *const *ccp;
-char **p;
-/* NEC SVR4.0.2 mips cc rejects this.  */
-struct point {int x, y;};
-static struct point const zero = {0,0};
-/* AIX XL C 1.02.0.0 rejects this.
-   It does not let you subtract one const X* pointer from another in an arm
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-ccp = &g + (g ? g-g : 0);
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-ccp = (char const *const *) p;
-{ /* SCO 3.2v4 cc rejects this.  */
-  char *t;
-  char const *s = 0 ? (char *) 0 : (char const *) 0;
-
-  *t++ = 0;
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-{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
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-{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
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-  ++p;
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-{ /* AIX XL C 1.02.0.0 rejects this saying
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-  struct s { int j; const int *ap[3]; };
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-{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
-  const int foo = 10;
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-
-; return 0; }
-EOF
-if { (eval echo configure:1082: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_c_const=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_c_const=no
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-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_c_const" 1>&6
-if test $ac_cv_c_const = no; then
-  cat >> confdefs.h <<\EOF
-#define const 
-EOF
-
-fi
-
-echo $ac_n "checking for inline""... $ac_c" 1>&6
-echo "configure:1103: checking for inline" >&5
-if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_cv_c_inline=no
-for ac_kw in inline __inline__ __inline; do
-  cat > conftest.$ac_ext <<EOF
-#line 1110 "configure"
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-
-int main() {
-} $ac_kw foo() {
-; return 0; }
-EOF
-if { (eval echo configure:1117: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_c_inline=$ac_kw; break
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-
-fi
-
-echo "$ac_t""$ac_cv_c_inline" 1>&6
-case "$ac_cv_c_inline" in
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-#define inline 
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-  *)  cat >> confdefs.h <<EOF
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-EOF
- ;;
-esac
-
-echo $ac_n "checking for off_t""... $ac_c" 1>&6
-echo "configure:1143: checking for off_t" >&5
-if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1148 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#if STDC_HEADERS
-#include <stdlib.h>
-#include <stddef.h>
-#endif
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_type_off_t=yes
-else
-  rm -rf conftest*
-  ac_cv_type_off_t=no
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-rm -f conftest*
-
-fi
-echo "$ac_t""$ac_cv_type_off_t" 1>&6
-if test $ac_cv_type_off_t = no; then
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-#define off_t long
-EOF
-
-fi
-
-echo $ac_n "checking for size_t""... $ac_c" 1>&6
-echo "configure:1176: checking for size_t" >&5
-if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1181 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#if STDC_HEADERS
-#include <stdlib.h>
-#include <stddef.h>
-#endif
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_type_size_t=yes
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-  rm -rf conftest*
-  ac_cv_type_size_t=no
-fi
-rm -f conftest*
-
-fi
-echo "$ac_t""$ac_cv_type_size_t" 1>&6
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-
-fi
-
-# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
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-echo "configure:1211: checking for working alloca.h" >&5
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-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1216 "configure"
-#include "confdefs.h"
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-int main() {
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-EOF
-if { (eval echo configure:1223: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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-  ac_cv_header_alloca_h=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_header_alloca_h=no
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-rm -f conftest*
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-
-echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
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-EOF
-
-fi
-
-echo $ac_n "checking for alloca""... $ac_c" 1>&6
-echo "configure:1244: checking for alloca" >&5
-if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1249 "configure"
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-
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-#else
-# if HAVE_ALLOCA_H
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-# else
-#  ifdef _AIX
- #pragma alloca
-#  else
-#   ifndef alloca /* predefined by HP cc +Olibcalls */
-char *alloca ();
-#   endif
-#  endif
-# endif
-#endif
-
-int main() {
-char *p = (char *) alloca(1);
-; return 0; }
-EOF
-if { (eval echo configure:1272: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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-  ac_cv_func_alloca_works=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_func_alloca_works=no
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-rm -f conftest*
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-
-echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
-if test $ac_cv_func_alloca_works = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_ALLOCA 1
-EOF
-
-fi
-
-if test $ac_cv_func_alloca_works = no; then
-  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
-  # that cause trouble.  Some versions do not even contain alloca or
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-  ALLOCA=alloca.o
-  cat >> confdefs.h <<\EOF
-#define C_ALLOCA 1
-EOF
-
-
-echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:1304: checking whether alloca needs Cray hooks" >&5
-if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1309 "configure"
-#include "confdefs.h"
-#if defined(CRAY) && ! defined(CRAY2)
-webecray
-#else
-wenotbecray
-#endif
-
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "webecray" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_os_cray=yes
-else
-  rm -rf conftest*
-  ac_cv_os_cray=no
-fi
-rm -f conftest*
-
-fi
-
-echo "$ac_t""$ac_cv_os_cray" 1>&6
-if test $ac_cv_os_cray = yes; then
-for ac_func in _getb67 GETB67 getb67; do
-  echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1334: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1339 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1362: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  cat >> confdefs.h <<EOF
-#define CRAY_STACKSEG_END $ac_func
-EOF
-
-  break
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-done
-fi
-
-echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:1389: checking stack direction for C alloca" >&5
-if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_c_stack_direction=0
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1397 "configure"
-#include "confdefs.h"
-find_stack_direction ()
-{
-  static char *addr = 0;
-  auto char dummy;
-  if (addr == 0)
-    {
-      addr = &dummy;
-      return find_stack_direction ();
-    }
-  else
-    return (&dummy > addr) ? 1 : -1;
-}
-main ()
-{
-  exit (find_stack_direction() < 0);
-}
-EOF
-if { (eval echo configure:1416: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_c_stack_direction=1
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_c_stack_direction=-1
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
-cat >> confdefs.h <<EOF
-#define STACK_DIRECTION $ac_cv_c_stack_direction
-EOF
-
-fi
-
-for ac_hdr in unistd.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:1441: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1446 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1451: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_func in getpagesize
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1480: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1485 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1508: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:1533: checking for working mmap" >&5
-if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1541 "configure"
-#include "confdefs.h"
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the filesystem buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propogated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-#include <sys/types.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#ifndef HAVE_GETPAGESIZE
-# ifdef HAVE_UNISTD_H
-#  include <unistd.h>
-# endif
-
-/* Assume that all systems that can run configure have sys/param.h.  */
-# ifndef HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  ifdef HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-#ifdef __cplusplus
-extern "C" { void *malloc(unsigned); }
-#else
-char *malloc();
-#endif
-
-int
-main()
-{
-	char *data, *data2, *data3;
-	int i, pagesize;
-	int fd;
-
-	pagesize = getpagesize();
-
-	/*
-	 * First, make a file with some known garbage in it.
-	 */
-	data = malloc(pagesize);
-	if (!data)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		*(data + i) = rand();
-	umask(0);
-	fd = creat("conftestmmap", 0600);
-	if (fd < 0)
-		exit(1);
-	if (write(fd, data, pagesize) != pagesize)
-		exit(1);
-	close(fd);
-
-	/*
-	 * Next, try to mmap the file at a fixed address which
-	 * already has something else allocated at it.  If we can,
-	 * also make sure that we see the same garbage.
-	 */
-	fd = open("conftestmmap", O_RDWR);
-	if (fd < 0)
-		exit(1);
-	data2 = malloc(2 * pagesize);
-	if (!data2)
-		exit(1);
-	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
-	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
-	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data2 + i))
-			exit(1);
-
-	/*
-	 * Finally, make sure that changes to the mapped area
-	 * do not percolate back to the file as seen by read().
-	 * (This is a bug on some variants of i386 svr4.0.)
-	 */
-	for (i = 0; i < pagesize; ++i)
-		*(data2 + i) = *(data2 + i) + 1;
-	data3 = malloc(pagesize);
-	if (!data3)
-		exit(1);
-	if (read(fd, data3, pagesize) != pagesize)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data3 + i))
-			exit(1);
-	close(fd);
-	unlink("conftestmmap");
-	exit(0);
-}
-
-EOF
-if { (eval echo configure:1681: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_MMAP 1
-EOF
-
-fi
-
-                              
-   for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:1709: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1714 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1719: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-   for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1749: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1754 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1777: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-     for ac_func in stpcpy
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1806: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1811 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1834: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-     cat >> confdefs.h <<\EOF
-#define HAVE_STPCPY 1
-EOF
-
-   fi
-
-   if test $ac_cv_header_locale_h = yes; then
-    echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
-echo "configure:1868: checking for LC_MESSAGES" >&5
-if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1873 "configure"
-#include "confdefs.h"
-#include <locale.h>
-int main() {
-return LC_MESSAGES
-; return 0; }
-EOF
-if { (eval echo configure:1880: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  am_cv_val_LC_MESSAGES=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  am_cv_val_LC_MESSAGES=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
-    if test $am_cv_val_LC_MESSAGES = yes; then
-      cat >> confdefs.h <<\EOF
-#define HAVE_LC_MESSAGES 1
-EOF
-
-    fi
-  fi
-   echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
-echo "configure:1901: checking whether NLS is requested" >&5
-        # Check whether --enable-nls or --disable-nls was given.
-if test "${enable_nls+set}" = set; then
-  enableval="$enable_nls"
-  USE_NLS=$enableval
-else
-  USE_NLS=yes
-fi
-
-    echo "$ac_t""$USE_NLS" 1>&6
-    
-
-    USE_INCLUDED_LIBINTL=no
-
-        if test "$USE_NLS" = "yes"; then
-      cat >> confdefs.h <<\EOF
-#define ENABLE_NLS 1
-EOF
-
-      echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
-echo "configure:1921: checking whether included gettext is requested" >&5
-      # Check whether --with-included-gettext or --without-included-gettext was given.
-if test "${with_included_gettext+set}" = set; then
-  withval="$with_included_gettext"
-  nls_cv_force_use_gnu_gettext=$withval
-else
-  nls_cv_force_use_gnu_gettext=no
-fi
-
-      echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-                        		nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=NONE
-
-	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
-echo "configure:1940: checking for libintl.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1945 "configure"
-#include "confdefs.h"
-#include <libintl.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1950: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
-echo "configure:1967: checking for gettext in libc" >&5
-if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1972 "configure"
-#include "confdefs.h"
-#include <libintl.h>
-int main() {
-return (int) gettext ("")
-; return 0; }
-EOF
-if { (eval echo configure:1979: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  gt_cv_func_gettext_libc=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  gt_cv_func_gettext_libc=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
-echo "configure:1995: checking for bindtextdomain in -lintl" >&5
-ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lintl  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 2003 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char bindtextdomain();
-
-int main() {
-bindtextdomain()
-; return 0; }
-EOF
-if { (eval echo configure:2014: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
-echo "configure:2030: checking for gettext in libintl" >&5
-if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2035 "configure"
-#include "confdefs.h"
-
-int main() {
-return (int) gettext ("")
-; return 0; }
-EOF
-if { (eval echo configure:2042: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  gt_cv_func_gettext_libintl=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  gt_cv_func_gettext_libintl=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-	      cat >> confdefs.h <<\EOF
-#define HAVE_GETTEXT 1
-EOF
-
-	      # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2070: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$ac_t""$MSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-	      if test "$MSGFMT" != "no"; then
-		for ac_func in dcgettext
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2104: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2109 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:2132: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-		# Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2159: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GMSGFMT" in
-  /*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT="$ac_cv_path_GMSGFMT"
-if test -n "$GMSGFMT"; then
-  echo "$ac_t""$GMSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-		# Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2194: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$ac_t""$XGETTEXT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-		cat > conftest.$ac_ext <<EOF
-#line 2226 "configure"
-#include "confdefs.h"
-
-int main() {
-extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr
-; return 0; }
-EOF
-if { (eval echo configure:2234: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
-  rm -rf conftest*
-  CATOBJEXT=.gmo
-		   DATADIRNAME=share
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CATOBJEXT=.mo
-		   DATADIRNAME=lib
-fi
-rm -f conftest*
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-	
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-	        
-        if test "$CATOBJEXT" = "NONE"; then
-	  	  	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-                INTLOBJS="\$(GETTOBJS)"
-        # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2266: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$ac_t""$MSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        # Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2300: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GMSGFMT" in
-  /*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT="$ac_cv_path_GMSGFMT"
-if test -n "$GMSGFMT"; then
-  echo "$ac_t""$GMSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        # Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2335: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$ac_t""$XGETTEXT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-            if test "$XGETTEXT" != ":"; then
-			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
-    else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
-    fi
-
-                for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-        
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-  
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
-echo "configure:2425: checking for catalogs to be installed" >&5
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       echo "$ac_t""$LINGUAS" 1>&6
-     fi
-
-          if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-            if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-   
-
-            if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
-echo "configure:2453: checking for linux/version.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2458 "configure"
-#include "confdefs.h"
-#include <linux/version.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2463: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  msgformat=linux
-else
-  echo "$ac_t""no" 1>&6
-msgformat=xopen
-fi
-
-
-	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-            if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-   
-   
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-   
-
-      l=
-   
-
-            if test -d $srcdir/po; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
-  
-
-
-trap '' 1 2 15
-cat > confcache <<\EOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs.  It is not useful on other systems.
-# If it contains results you don't want to keep, you may remove or edit it.
-#
-# By default, configure uses ./config.cache as the cache file,
-# creating it if it does not exist already.  You can give configure
-# the --cache-file=FILE option to use a different cache file; that is
-# what configure does when it calls configure scripts in
-# subdirectories, so they share the cache.
-# Giving --cache-file=/dev/null disables caching, for debugging configure.
-# config.status only pays attention to the cache file if you give it the
-# --recheck option to rerun configure.
-#
-EOF
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-(set) 2>&1 |
-  case `(ac_space=' '; set) 2>&1 | grep ac_space` in
-  *ac_space=\ *)
-    # `set' does not quote correctly, so add quotes (double-quote substitution
-    # turns \\\\ into \\, and sed turns \\ into \).
-    sed -n \
-      -e "s/'/'\\\\''/g" \
-      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
-    ;;
-  *)
-    # `set' quotes correctly as required by POSIX, so do not add quotes.
-    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
-    ;;
-  esac >> confcache
-if cmp -s $cache_file confcache; then
-  :
-else
-  if test -w $cache_file; then
-    echo "updating cache $cache_file"
-    cat confcache > $cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# Any assignment to VPATH causes Sun make to only execute
-# the first set of double-colon rules, so remove it if not needed.
-# If there is a colon in the path, we need to keep it.
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
-fi
-
-trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
-
-DEFS=-DHAVE_CONFIG_H
-
-# Without the "./", some shells look in PATH for config.status.
-: ${CONFIG_STATUS=./config.status}
-
-echo creating $CONFIG_STATUS
-rm -f $CONFIG_STATUS
-cat > $CONFIG_STATUS <<EOF
-#! /bin/sh
-# Generated automatically by configure.
-# Run this file to recreate the current configuration.
-# This directory was configured as follows,
-# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
-#
-# $0 $ac_configure_args
-#
-# Compiler output produced by configure, useful for debugging
-# configure, is in ./config.log if it exists.
-
-ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
-for ac_option
-do
-  case "\$ac_option" in
-  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
-    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
-    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
-    echo "$CONFIG_STATUS generated by autoconf version 2.12.1"
-    exit 0 ;;
-  -help | --help | --hel | --he | --h)
-    echo "\$ac_cs_usage"; exit 0 ;;
-  *) echo "\$ac_cs_usage"; exit 1 ;;
-  esac
-done
-
-ac_given_srcdir=$srcdir
-ac_given_INSTALL="$INSTALL"
-
-trap 'rm -fr `echo "Makefile config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-# Protect against being on the right side of a sed subst in config.status.
-sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
- s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
-$ac_vpsub
-$extrasub
-s%@SHELL@%$SHELL%g
-s%@CFLAGS@%$CFLAGS%g
-s%@CPPFLAGS@%$CPPFLAGS%g
-s%@CXXFLAGS@%$CXXFLAGS%g
-s%@DEFS@%$DEFS%g
-s%@LDFLAGS@%$LDFLAGS%g
-s%@LIBS@%$LIBS%g
-s%@exec_prefix@%$exec_prefix%g
-s%@prefix@%$prefix%g
-s%@program_transform_name@%$program_transform_name%g
-s%@bindir@%$bindir%g
-s%@sbindir@%$sbindir%g
-s%@libexecdir@%$libexecdir%g
-s%@datadir@%$datadir%g
-s%@sysconfdir@%$sysconfdir%g
-s%@sharedstatedir@%$sharedstatedir%g
-s%@localstatedir@%$localstatedir%g
-s%@libdir@%$libdir%g
-s%@includedir@%$includedir%g
-s%@oldincludedir@%$oldincludedir%g
-s%@infodir@%$infodir%g
-s%@mandir@%$mandir%g
-s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
-s%@INSTALL_DATA@%$INSTALL_DATA%g
-s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
-s%@SET_MAKE@%$SET_MAKE%g
-s%@CC@%$CC%g
-s%@RANLIB@%$RANLIB%g
-s%@CPP@%$CPP%g
-s%@ALLOCA@%$ALLOCA%g
-s%@USE_NLS@%$USE_NLS%g
-s%@MSGFMT@%$MSGFMT%g
-s%@GMSGFMT@%$GMSGFMT%g
-s%@XGETTEXT@%$XGETTEXT%g
-s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g
-s%@CATALOGS@%$CATALOGS%g
-s%@CATOBJEXT@%$CATOBJEXT%g
-s%@DATADIRNAME@%$DATADIRNAME%g
-s%@GMOFILES@%$GMOFILES%g
-s%@INSTOBJEXT@%$INSTOBJEXT%g
-s%@INTLDEPS@%$INTLDEPS%g
-s%@INTLLIBS@%$INTLLIBS%g
-s%@INTLOBJS@%$INTLOBJS%g
-s%@POFILES@%$POFILES%g
-s%@POSUB@%$POSUB%g
-s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g
-s%@GT_NO@%$GT_NO%g
-s%@GT_YES@%$GT_YES%g
-s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
-s%@l@%$l%g
-
-CEOF
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-
-# Split the substitutions into bite-sized pieces for seds with
-# small command number limits, like on Digital OSF/1 and HP-UX.
-ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
-ac_file=1 # Number of current file.
-ac_beg=1 # First line for current file.
-ac_end=$ac_max_sed_cmds # Line after last line for current file.
-ac_more_lines=:
-ac_sed_cmds=""
-while $ac_more_lines; do
-  if test $ac_beg -gt 1; then
-    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
-  else
-    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
-  fi
-  if test ! -s conftest.s$ac_file; then
-    ac_more_lines=false
-    rm -f conftest.s$ac_file
-  else
-    if test -z "$ac_sed_cmds"; then
-      ac_sed_cmds="sed -f conftest.s$ac_file"
-    else
-      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
-    fi
-    ac_file=`expr $ac_file + 1`
-    ac_beg=$ac_end
-    ac_end=`expr $ac_end + $ac_max_sed_cmds`
-  fi
-done
-if test -z "$ac_sed_cmds"; then
-  ac_sed_cmds=cat
-fi
-EOF
-
-cat >> $CONFIG_STATUS <<EOF
-
-CONFIG_FILES=\${CONFIG_FILES-"Makefile"}
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case "$ac_file" in
-  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
-  esac
-
-  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
-
-  # Remove last slash and all that follows it.  Not all systems have dirname.
-  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
-  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
-    # The file is in a subdirectory.
-    test ! -d "$ac_dir" && mkdir "$ac_dir"
-    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dir_suffix.
-    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
-  else
-    ac_dir_suffix= ac_dots=
-  fi
-
-  case "$ac_given_srcdir" in
-  .)  srcdir=.
-      if test -z "$ac_dots"; then top_srcdir=.
-      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
-  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
-  *) # Relative path.
-    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
-    top_srcdir="$ac_dots$ac_given_srcdir" ;;
-  esac
-
-  case "$ac_given_INSTALL" in
-  [/$]*) INSTALL="$ac_given_INSTALL" ;;
-  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
-  esac
-
-  echo creating "$ac_file"
-  rm -f "$ac_file"
-  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
-  case "$ac_file" in
-  *Makefile*) ac_comsub="1i\\
-# $configure_input" ;;
-  *) ac_comsub= ;;
-  esac
-
-  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
-  sed -e "$ac_comsub
-s%@configure_input@%$configure_input%g
-s%@srcdir@%$srcdir%g
-s%@top_srcdir@%$top_srcdir%g
-s%@INSTALL@%$INSTALL%g
-" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
-fi; done
-rm -f conftest.s*
-
-# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
-# NAME is the cpp macro being defined and VALUE is the value it is being given.
-#
-# ac_d sets the value in "#define NAME VALUE" lines.
-ac_dA='s%^\([ 	]*\)#\([ 	]*define[ 	][ 	]*\)'
-ac_dB='\([ 	][ 	]*\)[^ 	]*%\1#\2'
-ac_dC='\3'
-ac_dD='%g'
-# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
-ac_uA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
-ac_uB='\([ 	]\)%\1#\2define\3'
-ac_uC=' '
-ac_uD='\4%g'
-# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
-ac_eA='s%^\([ 	]*\)#\([ 	]*\)undef\([ 	][ 	]*\)'
-ac_eB='$%\1#\2define\3'
-ac_eC=' '
-ac_eD='%g'
-
-if test "${CONFIG_HEADERS+set}" != set; then
-EOF
-cat >> $CONFIG_STATUS <<EOF
-  CONFIG_HEADERS="config.h:config.in"
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-fi
-for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case "$ac_file" in
-  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
-  esac
-
-  echo creating $ac_file
-
-  rm -f conftest.frag conftest.in conftest.out
-  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
-  cat $ac_file_inputs > conftest.in
-
-EOF
-
-# Transform confdefs.h into a sed script conftest.vals that substitutes
-# the proper values into config.h.in to produce config.h.  And first:
-# Protect against being on the right side of a sed subst in config.status.
-# Protect against being in an unquoted here document in config.status.
-rm -f conftest.vals
-cat > conftest.hdr <<\EOF
-s/[\\&%]/\\&/g
-s%[\\$`]%\\&%g
-s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
-s%ac_d%ac_u%gp
-s%ac_u%ac_e%gp
-EOF
-sed -n -f conftest.hdr confdefs.h > conftest.vals
-rm -f conftest.hdr
-
-# This sed command replaces #undef with comments.  This is necessary, for
-# example, in the case of _POSIX_SOURCE, which is predefined and required
-# on some systems where configure will not decide to define it.
-cat >> conftest.vals <<\EOF
-s%^[ 	]*#[ 	]*undef[ 	][ 	]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
-EOF
-
-# Break up conftest.vals because some shells have a limit on
-# the size of here documents, and old seds have small limits too.
-
-rm -f conftest.tail
-while :
-do
-  ac_lines=`grep -c . conftest.vals`
-  # grep -c gives empty output for an empty file on some AIX systems.
-  if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
-  # Write a limited-size here document to conftest.frag.
-  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
-  echo 'CEOF
-  sed -f conftest.frag conftest.in > conftest.out
-  rm -f conftest.in
-  mv conftest.out conftest.in
-' >> $CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
-  rm -f conftest.vals
-  mv conftest.tail conftest.vals
-done
-rm -f conftest.vals
-
-cat >> $CONFIG_STATUS <<\EOF
-  rm -f conftest.frag conftest.h
-  echo "/* $ac_file.  Generated automatically by configure.  */" > conftest.h
-  cat conftest.in >> conftest.h
-  rm -f conftest.in
-  if cmp -s $ac_file conftest.h 2>/dev/null; then
-    echo "$ac_file is unchanged"
-    rm -f conftest.h
-  else
-    # Remove last slash and all that follows it.  Not all systems have dirname.
-      ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
-      if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
-      # The file is in a subdirectory.
-      test ! -d "$ac_dir" && mkdir "$ac_dir"
-    fi
-    rm -f $ac_file
-    mv conftest.h $ac_file
-  fi
-fi; done
-
-EOF
-
-cat >> $CONFIG_STATUS <<EOF
-ac_sources="$nls_cv_header_libgt"
-ac_dests="$nls_cv_header_intl"
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-srcdir=$ac_given_srcdir
-while test -n "$ac_sources"; do
-  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
-  set $ac_sources; ac_source=$1; shift; ac_sources=$*
-
-  echo "linking $srcdir/$ac_source to $ac_dest"
-
-  if test ! -r $srcdir/$ac_source; then
-    { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; }
-  fi
-  rm -f $ac_dest
-
-  # Make relative symlinks.
-  # Remove last slash and all that follows it.  Not all systems have dirname.
-  ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'`
-  if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then
-    # The dest file is in a subdirectory.
-    test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
-    ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dest_dir_suffix.
-    ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
-  else
-    ac_dest_dir_suffix= ac_dots=
-  fi
-
-  case "$srcdir" in
-  [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
-  *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
-  esac
-
-  # Make a symlink if possible; otherwise try a hard link.
-  if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
-    ln $srcdir/$ac_source $ac_dest; then :
-  else
-    { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
-  fi
-done
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h
-
-exit 0
-EOF
-chmod +x $CONFIG_STATUS
-rm -fr confdefs* $ac_clean_files
-test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
-
diff --git a/intl/configure.in b/intl/configure.in
deleted file mode 100644
index 4ba9c244efa..00000000000
--- a/intl/configure.in
+++ /dev/null
@@ -1,10 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-
-AC_INIT(dgettext.c)
-AM_CONFIG_HEADER(config.h:config.in)
-
-AM_PROG_INSTALL
-CY_GNU_GETTEXT
-AC_LINK_FILES($nls_cv_header_libgt, $nls_cv_header_intl)
-
-AC_OUTPUT(Makefile)
diff --git a/intl/dcgettext.c b/intl/dcgettext.c
deleted file mode 100644
index 27586e9159a..00000000000
--- a/intl/dcgettext.c
+++ /dev/null
@@ -1,624 +0,0 @@
-/* Implementation of the dcgettext(3) function.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include <sys/types.h>
-
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-# define HAVE_ALLOCA 1
-#else
-# if defined HAVE_ALLOCA_H || defined _LIBC
-#  include <alloca.h>
-# else
-#  ifdef _AIX
- #pragma alloca
-#  else
-#   ifndef alloca
-char *alloca ();
-#   endif
-#  endif
-# endif
-#endif
-
-#include <errno.h>
-#ifndef errno
-extern int errno;
-#endif
-#ifndef __set_errno
-# define __set_errno(val) errno = (val)
-#endif
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#else
-char *getenv ();
-# ifdef HAVE_MALLOC_H
-#  include <malloc.h>
-# else
-void free ();
-# endif
-#endif
-
-#if defined HAVE_STRING_H || defined _LIBC
-# ifndef _GNU_SOURCE
-#  define _GNU_SOURCE	1
-# endif
-# include <string.h>
-#else
-# include <strings.h>
-#endif
-#if !HAVE_STRCHR && !defined _LIBC
-# ifndef strchr
-#  define strchr index
-# endif
-#endif
-
-#if defined HAVE_UNISTD_H || defined _LIBC
-# include <unistd.h>
-#endif
-
-#include "gettext.h"
-#include "gettextP.h"
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-#include "hash-string.h"
-
-/* @@ end of prolog @@ */
-
-#ifdef _LIBC
-/* Rename the non ANSI C functions.  This is required by the standard
-   because some ANSI C functions will require linking with this object
-   file and the name space must not be polluted.  */
-# define getcwd __getcwd
-# ifndef stpcpy
-#  define stpcpy __stpcpy
-# endif
-#else
-# if !defined HAVE_GETCWD
-char *getwd ();
-#  define getcwd(buf, max) getwd (buf)
-# else
-char *getcwd ();
-# endif
-# ifndef HAVE_STPCPY
-static char *stpcpy PARAMS ((char *dest, const char *src));
-# endif
-#endif
-
-/* Amount to increase buffer size by in each try.  */
-#define PATH_INCR 32
-
-/* The following is from pathmax.h.  */
-/* Non-POSIX BSD systems might have gcc's limits.h, which doesn't define
-   PATH_MAX but might cause redefinition warnings when sys/param.h is
-   later included (as on MORE/BSD 4.3).  */
-#if defined(_POSIX_VERSION) || (defined(HAVE_LIMITS_H) && !defined(__GNUC__))
-# include <limits.h>
-#endif
-
-#ifndef _POSIX_PATH_MAX
-# define _POSIX_PATH_MAX 255
-#endif
-
-#if !defined(PATH_MAX) && defined(_PC_PATH_MAX)
-# define PATH_MAX (pathconf ("/", _PC_PATH_MAX) < 1 ? 1024 : pathconf ("/", _PC_PATH_MAX))
-#endif
-
-/* Don't include sys/param.h if it already has been.  */
-#if defined(HAVE_SYS_PARAM_H) && !defined(PATH_MAX) && !defined(MAXPATHLEN)
-# include <sys/param.h>
-#endif
-
-#if !defined(PATH_MAX) && defined(MAXPATHLEN)
-# define PATH_MAX MAXPATHLEN
-#endif
-
-#ifndef PATH_MAX
-# define PATH_MAX _POSIX_PATH_MAX
-#endif
-
-/* XPG3 defines the result of `setlocale (category, NULL)' as:
-   ``Directs `setlocale()' to query `category' and return the current
-     setting of `local'.''
-   However it does not specify the exact format.  And even worse: POSIX
-   defines this not at all.  So we can use this feature only on selected
-   system (e.g. those using GNU C Library).  */
-#ifdef _LIBC
-# define HAVE_LOCALE_NULL
-#endif
-
-/* Name of the default domain used for gettext(3) prior any call to
-   textdomain(3).  The default value for this is "messages".  */
-const char _nl_default_default_domain[] = "messages";
-
-/* Value used as the default domain for gettext(3).  */
-const char *_nl_current_default_domain = _nl_default_default_domain;
-
-/* Contains the default location of the message catalogs.  */
-const char _nl_default_dirname[] = GNULOCALEDIR;
-
-/* List with bindings of specific domains created by bindtextdomain()
-   calls.  */
-struct binding *_nl_domain_bindings;
-
-/* Prototypes for local functions.  */
-static char *find_msg PARAMS ((struct loaded_l10nfile *domain_file,
-			       const char *msgid)) internal_function;
-static const char *category_to_name PARAMS ((int category)) internal_function;
-static const char *guess_category_value PARAMS ((int category,
-						 const char *categoryname))
-     internal_function;
-
-
-/* For those loosing systems which don't have `alloca' we have to add
-   some additional code emulating it.  */
-#ifdef HAVE_ALLOCA
-/* Nothing has to be done.  */
-# define ADD_BLOCK(list, address) /* nothing */
-# define FREE_BLOCKS(list) /* nothing */
-#else
-struct block_list
-{
-  void *address;
-  struct block_list *next;
-};
-# define ADD_BLOCK(list, addr)						      \
-  do {									      \
-    struct block_list *newp = (struct block_list *) malloc (sizeof (*newp));  \
-    /* If we cannot get a free block we cannot add the new element to	      \
-       the list.  */							      \
-    if (newp != NULL) {							      \
-      newp->address = (addr);						      \
-      newp->next = (list);						      \
-      (list) = newp;							      \
-    }									      \
-  } while (0)
-# define FREE_BLOCKS(list)						      \
-  do {									      \
-    while (list != NULL) {						      \
-      struct block_list *old = list;					      \
-      list = list->next;						      \
-      free (old);							      \
-    }									      \
-  } while (0)
-# undef alloca
-# define alloca(size) (malloc (size))
-#endif	/* have alloca */
-
-
-/* Names for the libintl functions are a problem.  They must not clash
-   with existing names and they should follow ANSI C.  But this source
-   code is also used in GNU C Library where the names have a __
-   prefix.  So we have to make a difference here.  */
-#ifdef _LIBC
-# define DCGETTEXT __dcgettext
-#else
-# define DCGETTEXT dcgettext__
-#endif
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current CATEGORY
-   locale.  */
-char *
-DCGETTEXT (domainname, msgid, category)
-     const char *domainname;
-     const char *msgid;
-     int category;
-{
-#ifndef HAVE_ALLOCA
-  struct block_list *block_list = NULL;
-#endif
-  struct loaded_l10nfile *domain;
-  struct binding *binding;
-  const char *categoryname;
-  const char *categoryvalue;
-  char *dirname, *xdomainname;
-  char *single_locale;
-  char *retval;
-  int saved_errno = errno;
-
-  /* If no real MSGID is given return NULL.  */
-  if (msgid == NULL)
-    return NULL;
-
-  /* If DOMAINNAME is NULL, we are interested in the default domain.  If
-     CATEGORY is not LC_MESSAGES this might not make much sense but the
-     defintion left this undefined.  */
-  if (domainname == NULL)
-    domainname = _nl_current_default_domain;
-
-  /* First find matching binding.  */
-  for (binding = _nl_domain_bindings; binding != NULL; binding = binding->next)
-    {
-      int compare = strcmp (domainname, binding->domainname);
-      if (compare == 0)
-	/* We found it!  */
-	break;
-      if (compare < 0)
-	{
-	  /* It is not in the list.  */
-	  binding = NULL;
-	  break;
-	}
-    }
-
-  if (binding == NULL)
-    dirname = (char *) _nl_default_dirname;
-  else if (binding->dirname[0] == '/')
-    dirname = binding->dirname;
-  else
-    {
-      /* We have a relative path.  Make it absolute now.  */
-      size_t dirname_len = strlen (binding->dirname) + 1;
-      size_t path_max;
-      char *ret;
-
-      path_max = (unsigned) PATH_MAX;
-      path_max += 2;		/* The getcwd docs say to do this.  */
-
-      dirname = (char *) alloca (path_max + dirname_len);
-      ADD_BLOCK (block_list, dirname);
-
-      __set_errno (0);
-      while ((ret = getcwd (dirname, path_max)) == NULL && errno == ERANGE)
-	{
-	  path_max += PATH_INCR;
-	  dirname = (char *) alloca (path_max + dirname_len);
-	  ADD_BLOCK (block_list, dirname);
-	  __set_errno (0);
-	}
-
-      if (ret == NULL)
-	{
-	  /* We cannot get the current working directory.  Don't signal an
-	     error but simply return the default string.  */
-	  FREE_BLOCKS (block_list);
-	  __set_errno (saved_errno);
-	  return (char *) msgid;
-	}
-
-      stpcpy (stpcpy (strchr (dirname, '\0'), "/"), binding->dirname);
-    }
-
-  /* Now determine the symbolic name of CATEGORY and its value.  */
-  categoryname = category_to_name (category);
-  categoryvalue = guess_category_value (category, categoryname);
-
-  xdomainname = (char *) alloca (strlen (categoryname)
-				 + strlen (domainname) + 5);
-  ADD_BLOCK (block_list, xdomainname);
-
-  stpcpy (stpcpy (stpcpy (stpcpy (xdomainname, categoryname), "/"),
-		  domainname),
-	  ".mo");
-
-  /* Creating working area.  */
-  single_locale = (char *) alloca (strlen (categoryvalue) + 1);
-  ADD_BLOCK (block_list, single_locale);
-
-
-  /* Search for the given string.  This is a loop because we perhaps
-     got an ordered list of languages to consider for th translation.  */
-  while (1)
-    {
-      /* Make CATEGORYVALUE point to the next element of the list.  */
-      while (categoryvalue[0] != '\0' && categoryvalue[0] == ':')
-	++categoryvalue;
-      if (categoryvalue[0] == '\0')
-	{
-	  /* The whole contents of CATEGORYVALUE has been searched but
-	     no valid entry has been found.  We solve this situation
-	     by implicitly appending a "C" entry, i.e. no translation
-	     will take place.  */
-	  single_locale[0] = 'C';
-	  single_locale[1] = '\0';
-	}
-      else
-	{
-	  char *cp = single_locale;
-	  while (categoryvalue[0] != '\0' && categoryvalue[0] != ':')
-	    *cp++ = *categoryvalue++;
-	  *cp = '\0';
-	}
-
-      /* If the current locale value is C (or POSIX) we don't load a
-	 domain.  Return the MSGID.  */
-      if (strcmp (single_locale, "C") == 0
-	  || strcmp (single_locale, "POSIX") == 0)
-	{
-	  FREE_BLOCKS (block_list);
-	  __set_errno (saved_errno);
-	  return (char *) msgid;
-	}
-
-
-      /* Find structure describing the message catalog matching the
-	 DOMAINNAME and CATEGORY.  */
-      domain = _nl_find_domain (dirname, single_locale, xdomainname);
-
-      if (domain != NULL)
-	{
-	  retval = find_msg (domain, msgid);
-
-	  if (retval == NULL)
-	    {
-	      int cnt;
-
-	      for (cnt = 0; domain->successor[cnt] != NULL; ++cnt)
-		{
-		  retval = find_msg (domain->successor[cnt], msgid);
-
-		  if (retval != NULL)
-		    break;
-		}
-	    }
-
-	  if (retval != NULL)
-	    {
-	      FREE_BLOCKS (block_list);
-	      __set_errno (saved_errno);
-	      return retval;
-	    }
-	}
-    }
-  /* NOTREACHED */
-}
-
-#ifdef _LIBC
-/* Alias for function name in GNU C Library.  */
-weak_alias (__dcgettext, dcgettext);
-#endif
-
-
-static char *
-internal_function
-find_msg (domain_file, msgid)
-     struct loaded_l10nfile *domain_file;
-     const char *msgid;
-{
-  size_t top, act, bottom;
-  struct loaded_domain *domain;
-
-  if (domain_file->decided == 0)
-    _nl_load_domain (domain_file);
-
-  if (domain_file->data == NULL)
-    return NULL;
-
-  domain = (struct loaded_domain *) domain_file->data;
-
-  /* Locate the MSGID and its translation.  */
-  if (domain->hash_size > 2 && domain->hash_tab != NULL)
-    {
-      /* Use the hashing table.  */
-      nls_uint32 len = strlen (msgid);
-      nls_uint32 hash_val = hash_string (msgid);
-      nls_uint32 idx = hash_val % domain->hash_size;
-      nls_uint32 incr = 1 + (hash_val % (domain->hash_size - 2));
-      nls_uint32 nstr = W (domain->must_swap, domain->hash_tab[idx]);
-
-      if (nstr == 0)
-	/* Hash table entry is empty.  */
-	return NULL;
-
-      if (W (domain->must_swap, domain->orig_tab[nstr - 1].length) == len
-	  && strcmp (msgid,
-		     domain->data + W (domain->must_swap,
-				       domain->orig_tab[nstr - 1].offset)) == 0)
-	return (char *) domain->data + W (domain->must_swap,
-					  domain->trans_tab[nstr - 1].offset);
-
-      while (1)
-	{
-	  if (idx >= domain->hash_size - incr)
-	    idx -= domain->hash_size - incr;
-	  else
-	    idx += incr;
-
-	  nstr = W (domain->must_swap, domain->hash_tab[idx]);
-	  if (nstr == 0)
-	    /* Hash table entry is empty.  */
-	    return NULL;
-
-	  if (W (domain->must_swap, domain->orig_tab[nstr - 1].length) == len
-	      && strcmp (msgid,
-			 domain->data + W (domain->must_swap,
-					   domain->orig_tab[nstr - 1].offset))
-	         == 0)
-	    return (char *) domain->data
-	      + W (domain->must_swap, domain->trans_tab[nstr - 1].offset);
-	}
-      /* NOTREACHED */
-    }
-
-  /* Now we try the default method:  binary search in the sorted
-     array of messages.  */
-  bottom = 0;
-  top = domain->nstrings;
-  while (bottom < top)
-    {
-      int cmp_val;
-
-      act = (bottom + top) / 2;
-      cmp_val = strcmp (msgid, domain->data
-			       + W (domain->must_swap,
-				    domain->orig_tab[act].offset));
-      if (cmp_val < 0)
-	top = act;
-      else if (cmp_val > 0)
-	bottom = act + 1;
-      else
-	break;
-    }
-
-  /* If an translation is found return this.  */
-  return bottom >= top ? NULL : (char *) domain->data
-                                + W (domain->must_swap,
-				     domain->trans_tab[act].offset);
-}
-
-
-/* Return string representation of locale CATEGORY.  */
-static const char *
-internal_function
-category_to_name (category)
-     int category;
-{
-  const char *retval;
-
-  switch (category)
-  {
-#ifdef LC_COLLATE
-  case LC_COLLATE:
-    retval = "LC_COLLATE";
-    break;
-#endif
-#ifdef LC_CTYPE
-  case LC_CTYPE:
-    retval = "LC_CTYPE";
-    break;
-#endif
-#ifdef LC_MONETARY
-  case LC_MONETARY:
-    retval = "LC_MONETARY";
-    break;
-#endif
-#ifdef LC_NUMERIC
-  case LC_NUMERIC:
-    retval = "LC_NUMERIC";
-    break;
-#endif
-#ifdef LC_TIME
-  case LC_TIME:
-    retval = "LC_TIME";
-    break;
-#endif
-#ifdef LC_MESSAGES
-  case LC_MESSAGES:
-    retval = "LC_MESSAGES";
-    break;
-#endif
-#ifdef LC_RESPONSE
-  case LC_RESPONSE:
-    retval = "LC_RESPONSE";
-    break;
-#endif
-#ifdef LC_ALL
-  case LC_ALL:
-    /* This might not make sense but is perhaps better than any other
-       value.  */
-    retval = "LC_ALL";
-    break;
-#endif
-  default:
-    /* If you have a better idea for a default value let me know.  */
-    retval = "LC_XXX";
-  }
-
-  return retval;
-}
-
-/* Guess value of current locale from value of the environment variables.  */
-static const char *
-internal_function
-guess_category_value (category, categoryname)
-     int category;
-     const char *categoryname;
-{
-  const char *retval;
-
-  /* The highest priority value is the `LANGUAGE' environment
-     variable.  This is a GNU extension.  */
-  retval = getenv ("LANGUAGE");
-  if (retval != NULL && retval[0] != '\0')
-    return retval;
-
-  /* `LANGUAGE' is not set.  So we have to proceed with the POSIX
-     methods of looking to `LC_ALL', `LC_xxx', and `LANG'.  On some
-     systems this can be done by the `setlocale' function itself.  */
-#if defined HAVE_SETLOCALE && defined HAVE_LC_MESSAGES && defined HAVE_LOCALE_NULL
-  return setlocale (category, NULL);
-#else
-  /* Setting of LC_ALL overwrites all other.  */
-  retval = getenv ("LC_ALL");
-  if (retval != NULL && retval[0] != '\0')
-    return retval;
-
-  /* Next comes the name of the desired category.  */
-  retval = getenv (categoryname);
-  if (retval != NULL && retval[0] != '\0')
-    return retval;
-
-  /* Last possibility is the LANG environment variable.  */
-  retval = getenv ("LANG");
-  if (retval != NULL && retval[0] != '\0')
-    return retval;
-
-  /* We use C as the default domain.  POSIX says this is implementation
-     defined.  */
-  return "C";
-#endif
-}
-
-/* @@ begin of epilog @@ */
-
-/* We don't want libintl.a to depend on any other library.  So we
-   avoid the non-standard function stpcpy.  In GNU C Library this
-   function is available, though.  Also allow the symbol HAVE_STPCPY
-   to be defined.  */
-#if !_LIBC && !HAVE_STPCPY
-static char *
-stpcpy (dest, src)
-     char *dest;
-     const char *src;
-{
-  while ((*dest++ = *src++) != '\0')
-    /* Do nothing. */ ;
-  return dest - 1;
-}
-#endif
-
-
-#ifdef _LIBC
-/* If we want to free all resources we have to do some work at
-   program's end.  */
-static void __attribute__ ((unused))
-free_mem (void)
-{
-  struct binding *runp;
-
-  for (runp = _nl_domain_bindings; runp != NULL; runp = runp->next)
-    {
-      free (runp->domainname);
-      if (runp->dirname != _nl_default_dirname)
-	/* Yes, this is a pointer comparison.  */
-	free (runp->dirname);
-    }
-
-  if (_nl_current_default_domain != _nl_default_default_domain)
-    /* Yes, again a pointer comparison.  */
-    free ((char *) _nl_current_default_domain);
-}
-
-text_set_element (__libc_subfreeres, free_mem);
-#endif
diff --git a/intl/dgettext.c b/intl/dgettext.c
deleted file mode 100644
index e4a0cfdb6e0..00000000000
--- a/intl/dgettext.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Implementation of the dgettext(3) function
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#if defined HAVE_LOCALE_H || defined _LIBC
-# include <locale.h>
-#endif
-
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-
-/* @@ end of prolog @@ */
-
-/* Names for the libintl functions are a problem.  They must not clash
-   with existing names and they should follow ANSI C.  But this source
-   code is also used in GNU C Library where the names have a __
-   prefix.  So we have to make a difference here.  */
-#ifdef _LIBC
-# define DGETTEXT __dgettext
-# define DCGETTEXT __dcgettext
-#else
-# define DGETTEXT dgettext__
-# define DCGETTEXT dcgettext__
-#endif
-
-/* Look up MSGID in the DOMAINNAME message catalog of the current
-   LC_MESSAGES locale.  */
-char *
-DGETTEXT (domainname, msgid)
-     const char *domainname;
-     const char *msgid;
-{
-  return DCGETTEXT (domainname, msgid, LC_MESSAGES);
-}
-
-#ifdef _LIBC
-/* Alias for function name in GNU C Library.  */
-weak_alias (__dgettext, dgettext);
-#endif
diff --git a/intl/explodename.c b/intl/explodename.c
deleted file mode 100644
index 5a911cee91b..00000000000
--- a/intl/explodename.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#endif
-
-#if defined HAVE_STRING_H || defined _LIBC
-# include <string.h>
-#else
-# include <strings.h>
-#endif
-#include <sys/types.h>
-
-#include "loadinfo.h"
-
-/* On some strange systems still no definition of NULL is found.  Sigh!  */
-#ifndef NULL
-# if defined __STDC__ && __STDC__
-#  define NULL ((void *) 0)
-# else
-#  define NULL 0
-# endif
-#endif
-
-/* @@ end of prolog @@ */
-
-int
-_nl_explode_name (name, language, modifier, territory, codeset,
-		  normalized_codeset, special, sponsor, revision)
-     char *name;
-     const char **language;
-     const char **modifier;
-     const char **territory;
-     const char **codeset;
-     const char **normalized_codeset;
-     const char **special;
-     const char **sponsor;
-     const char **revision;
-{
-  enum { undecided, xpg, cen } syntax;
-  char *cp;
-  int mask;
-
-  *modifier = NULL;
-  *territory = NULL;
-  *codeset = NULL;
-  *normalized_codeset = NULL;
-  *special = NULL;
-  *sponsor = NULL;
-  *revision = NULL;
-
-  /* Now we determine the single parts of the locale name.  First
-     look for the language.  Termination symbols are `_' and `@' if
-     we use XPG4 style, and `_', `+', and `,' if we use CEN syntax.  */
-  mask = 0;
-  syntax = undecided;
-  *language = cp = name;
-  while (cp[0] != '\0' && cp[0] != '_' && cp[0] != '@'
-	 && cp[0] != '+' && cp[0] != ',')
-    ++cp;
-
-  if (*language == cp)
-    /* This does not make sense: language has to be specified.  Use
-       this entry as it is without exploding.  Perhaps it is an alias.  */
-    cp = strchr (*language, '\0');
-  else if (cp[0] == '_')
-    {
-      /* Next is the territory.  */
-      cp[0] = '\0';
-      *territory = ++cp;
-
-      while (cp[0] != '\0' && cp[0] != '.' && cp[0] != '@'
-	     && cp[0] != '+' && cp[0] != ',' && cp[0] != '_')
-	++cp;
-
-      mask |= TERRITORY;
-
-      if (cp[0] == '.')
-	{
-	  /* Next is the codeset.  */
-	  syntax = xpg;
-	  cp[0] = '\0';
-	  *codeset = ++cp;
-
-	  while (cp[0] != '\0' && cp[0] != '@')
-	    ++cp;
-
-	  mask |= XPG_CODESET;
-
-	  if (*codeset != cp && (*codeset)[0] != '\0')
-	    {
-	      *normalized_codeset = _nl_normalize_codeset (*codeset,
-							   cp - *codeset);
-	      if (strcmp (*codeset, *normalized_codeset) == 0)
-		free ((char *) *normalized_codeset);
-	      else
-		mask |= XPG_NORM_CODESET;
-	    }
-	}
-    }
-
-  if (cp[0] == '@' || (syntax != xpg && cp[0] == '+'))
-    {
-      /* Next is the modifier.  */
-      syntax = cp[0] == '@' ? xpg : cen;
-      cp[0] = '\0';
-      *modifier = ++cp;
-
-      while (syntax == cen && cp[0] != '\0' && cp[0] != '+'
-	     && cp[0] != ',' && cp[0] != '_')
-	++cp;
-
-      mask |= XPG_MODIFIER | CEN_AUDIENCE;
-    }
-
-  if (syntax != xpg && (cp[0] == '+' || cp[0] == ',' || cp[0] == '_'))
-    {
-      syntax = cen;
-
-      if (cp[0] == '+')
-	{
- 	  /* Next is special application (CEN syntax).  */
-	  cp[0] = '\0';
-	  *special = ++cp;
-
-	  while (cp[0] != '\0' && cp[0] != ',' && cp[0] != '_')
-	    ++cp;
-
-	  mask |= CEN_SPECIAL;
-	}
-
-      if (cp[0] == ',')
-	{
- 	  /* Next is sponsor (CEN syntax).  */
-	  cp[0] = '\0';
-	  *sponsor = ++cp;
-
-	  while (cp[0] != '\0' && cp[0] != '_')
-	    ++cp;
-
-	  mask |= CEN_SPONSOR;
-	}
-
-      if (cp[0] == '_')
-	{
- 	  /* Next is revision (CEN syntax).  */
-	  cp[0] = '\0';
-	  *revision = ++cp;
-
-	  mask |= CEN_REVISION;
-	}
-    }
-
-  /* For CEN syntax values it might be important to have the
-     separator character in the file name, not for XPG syntax.  */
-  if (syntax == xpg)
-    {
-      if (*territory != NULL && (*territory)[0] == '\0')
-	mask &= ~TERRITORY;
-
-      if (*codeset != NULL && (*codeset)[0] == '\0')
-	mask &= ~XPG_CODESET;
-
-      if (*modifier != NULL && (*modifier)[0] == '\0')
-	mask &= ~XPG_MODIFIER;
-    }
-
-  return mask;
-}
diff --git a/intl/finddomain.c b/intl/finddomain.c
deleted file mode 100644
index 5409565fd3d..00000000000
--- a/intl/finddomain.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Handle list of needed message catalogs
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Written by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include <ctype.h>
-#include <errno.h>
-#include <stdio.h>
-#include <sys/types.h>
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#else
-# ifdef HAVE_MALLOC_H
-#  include <malloc.h>
-# else
-void free ();
-# endif
-#endif
-
-#if defined HAVE_STRING_H || defined _LIBC
-# include <string.h>
-#else
-# include <strings.h>
-# ifndef memcpy
-#  define memcpy(Dst, Src, Num) bcopy (Src, Dst, Num)
-# endif
-#endif
-#if !HAVE_STRCHR && !defined _LIBC
-# ifndef strchr
-#  define strchr index
-# endif
-#endif
-
-#if defined HAVE_UNISTD_H || defined _LIBC
-# include <unistd.h>
-#endif
-
-#include "gettext.h"
-#include "gettextP.h"
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-
-/* @@ end of prolog @@ */
-/* List of already loaded domains.  */
-static struct loaded_l10nfile *_nl_loaded_domains;
-
-
-/* Return a data structure describing the message catalog described by
-   the DOMAINNAME and CATEGORY parameters with respect to the currently
-   established bindings.  */
-struct loaded_l10nfile *
-internal_function
-_nl_find_domain (dirname, locale, domainname)
-     const char *dirname;
-     char *locale;
-     const char *domainname;
-{
-  struct loaded_l10nfile *retval;
-  const char *language;
-  const char *modifier;
-  const char *territory;
-  const char *codeset;
-  const char *normalized_codeset;
-  const char *special;
-  const char *sponsor;
-  const char *revision;
-  const char *alias_value;
-  int mask;
-
-  /* LOCALE can consist of up to four recognized parts for the XPG syntax:
-
-		language[_territory[.codeset]][@modifier]
-
-     and six parts for the CEN syntax:
-
-	language[_territory][+audience][+special][,[sponsor][_revision]]
-
-     Beside the first part all of them are allowed to be missing.  If
-     the full specified locale is not found, the less specific one are
-     looked for.  The various parts will be stripped off according to
-     the following order:
-		(1) revision
-		(2) sponsor
-		(3) special
-		(4) codeset
-		(5) normalized codeset
-		(6) territory
-		(7) audience/modifier
-   */
-
-  /* If we have already tested for this locale entry there has to
-     be one data set in the list of loaded domains.  */
-  retval = _nl_make_l10nflist (&_nl_loaded_domains, dirname,
-			       strlen (dirname) + 1, 0, locale, NULL, NULL,
-			       NULL, NULL, NULL, NULL, NULL, domainname, 0);
-  if (retval != NULL)
-    {
-      /* We know something about this locale.  */
-      int cnt;
-
-      if (retval->decided == 0)
-	_nl_load_domain (retval);
-
-      if (retval->data != NULL)
-	return retval;
-
-      for (cnt = 0; retval->successor[cnt] != NULL; ++cnt)
-	{
-	  if (retval->successor[cnt]->decided == 0)
-	    _nl_load_domain (retval->successor[cnt]);
-
-	  if (retval->successor[cnt]->data != NULL)
-	    break;
-	}
-      return cnt >= 0 ? retval : NULL;
-      /* NOTREACHED */
-    }
-
-  /* See whether the locale value is an alias.  If yes its value
-     *overwrites* the alias name.  No test for the original value is
-     done.  */
-  alias_value = _nl_expand_alias (locale);
-  if (alias_value != NULL)
-    {
-#if defined _LIBC || defined HAVE_STRDUP
-      locale = strdup (alias_value);
-      if (locale == NULL)
-	return NULL;
-#else
-      size_t len = strlen (alias_value) + 1;
-      locale = (char *) malloc (len);
-      if (locale == NULL)
-	return NULL;
-
-      memcpy (locale, alias_value, len);
-#endif
-    }
-
-  /* Now we determine the single parts of the locale name.  First
-     look for the language.  Termination symbols are `_' and `@' if
-     we use XPG4 style, and `_', `+', and `,' if we use CEN syntax.  */
-  mask = _nl_explode_name (locale, &language, &modifier, &territory,
-			   &codeset, &normalized_codeset, &special,
-			   &sponsor, &revision);
-
-  /* Create all possible locale entries which might be interested in
-     generalization.  */
-  retval = _nl_make_l10nflist (&_nl_loaded_domains, dirname,
-			       strlen (dirname) + 1, mask, language, territory,
-			       codeset, normalized_codeset, modifier, special,
-			       sponsor, revision, domainname, 1);
-  if (retval == NULL)
-    /* This means we are out of core.  */
-    return NULL;
-
-  if (retval->decided == 0)
-    _nl_load_domain (retval);
-  if (retval->data == NULL)
-    {
-      int cnt;
-      for (cnt = 0; retval->successor[cnt] != NULL; ++cnt)
-	{
-	  if (retval->successor[cnt]->decided == 0)
-	    _nl_load_domain (retval->successor[cnt]);
-	  if (retval->successor[cnt]->data != NULL)
-	    break;
-	}
-    }
-
-  /* The room for an alias was dynamically allocated.  Free it now.  */
-  if (alias_value != NULL)
-    free (locale);
-
-  return retval;
-}
-
-
-#ifdef _LIBC
-static void __attribute__ ((unused))
-free_mem (void)
-{
-  struct loaded_l10nfile *runp = _nl_loaded_domains;
-
-  while (runp != NULL)
-    {
-      struct loaded_l10nfile *here = runp;
-      if (runp->data != NULL)
-	_nl_unload_domain ((struct loaded_domain *) runp->data);
-      runp = runp->next;
-      free (here);
-    }
-}
-
-text_set_element (__libc_subfreeres, free_mem);
-#endif
diff --git a/intl/gettext.c b/intl/gettext.c
deleted file mode 100644
index 6bc5b94d3e8..00000000000
--- a/intl/gettext.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Implementation of gettext(3) function.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#ifdef _LIBC
-# define __need_NULL
-# include <stddef.h>
-#else
-# ifdef STDC_HEADERS
-#  include <stdlib.h>		/* Just for NULL.  */
-# else
-#  ifdef HAVE_STRING_H
-#   include <string.h>
-#  else
-#   define NULL ((void *) 0)
-#  endif
-# endif
-#endif
-
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-
-/* @@ end of prolog @@ */
-
-/* Names for the libintl functions are a problem.  They must not clash
-   with existing names and they should follow ANSI C.  But this source
-   code is also used in GNU C Library where the names have a __
-   prefix.  So we have to make a difference here.  */
-#ifdef _LIBC
-# define GETTEXT __gettext
-# define DGETTEXT __dgettext
-#else
-# define GETTEXT gettext__
-# define DGETTEXT dgettext__
-#endif
-
-/* Look up MSGID in the current default message catalog for the current
-   LC_MESSAGES locale.  If not found, returns MSGID itself (the default
-   text).  */
-char *
-GETTEXT (msgid)
-     const char *msgid;
-{
-  return DGETTEXT (NULL, msgid);
-}
-
-#ifdef _LIBC
-/* Alias for function name in GNU C Library.  */
-weak_alias (__gettext, gettext);
-#endif
diff --git a/intl/gettext.h b/intl/gettext.h
deleted file mode 100644
index 3887e876402..00000000000
--- a/intl/gettext.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Internal header for GNU gettext internationalization functions.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If not,
-   write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-#ifndef _GETTEXT_H
-#define _GETTEXT_H 1
-
-#include <stdio.h>
-
-#if HAVE_LIMITS_H || _LIBC
-# include <limits.h>
-#endif
-
-/* @@ end of prolog @@ */
-
-/* The magic number of the GNU message catalog format.  */
-#define _MAGIC 0x950412de
-#define _MAGIC_SWAPPED 0xde120495
-
-/* Revision number of the currently used .mo (binary) file format.  */
-#define MO_REVISION_NUMBER 0
-
-/* The following contortions are an attempt to use the C preprocessor
-   to determine an unsigned integral type that is 32 bits wide.  An
-   alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but
-   doing that would require that the configure script compile and *run*
-   the resulting executable.  Locally running cross-compiled executables
-   is usually not possible.  */
-
-#if __STDC__
-# define UINT_MAX_32_BITS 4294967295U
-#else
-# define UINT_MAX_32_BITS 0xFFFFFFFF
-#endif
-
-/* If UINT_MAX isn't defined, assume it's a 32-bit type.
-   This should be valid for all systems GNU cares about because
-   that doesn't include 16-bit systems, and only modern systems
-   (that certainly have <limits.h>) have 64+-bit integral types.  */
-
-#ifndef UINT_MAX
-# define UINT_MAX UINT_MAX_32_BITS
-#endif
-
-#if UINT_MAX == UINT_MAX_32_BITS
-typedef unsigned nls_uint32;
-#else
-# if USHRT_MAX == UINT_MAX_32_BITS
-typedef unsigned short nls_uint32;
-# else
-#  if ULONG_MAX == UINT_MAX_32_BITS
-typedef unsigned long nls_uint32;
-#  else
-  /* The following line is intended to throw an error.  Using #error is
-     not portable enough.  */
-  "Cannot determine unsigned 32-bit data type."
-#  endif
-# endif
-#endif
-
-
-/* Header for binary .mo file format.  */
-struct mo_file_header
-{
-  /* The magic number.  */
-  nls_uint32 magic;
-  /* The revision number of the file format.  */
-  nls_uint32 revision;
-  /* The number of strings pairs.  */
-  nls_uint32 nstrings;
-  /* Offset of table with start offsets of original strings.  */
-  nls_uint32 orig_tab_offset;
-  /* Offset of table with start offsets of translation strings.  */
-  nls_uint32 trans_tab_offset;
-  /* Size of hashing table.  */
-  nls_uint32 hash_tab_size;
-  /* Offset of first hashing entry.  */
-  nls_uint32 hash_tab_offset;
-};
-
-struct string_desc
-{
-  /* Length of addressed string.  */
-  nls_uint32 length;
-  /* Offset of string in file.  */
-  nls_uint32 offset;
-};
-
-/* @@ begin of epilog @@ */
-
-#endif	/* gettext.h  */
diff --git a/intl/gettextP.h b/intl/gettextP.h
deleted file mode 100644
index 61e2f871bc8..00000000000
--- a/intl/gettextP.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Header describing internals of gettext library
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Written by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifndef _GETTEXTP_H
-#define _GETTEXTP_H
-
-#include "loadinfo.h"
-
-/* @@ end of prolog @@ */
-
-#ifndef PARAMS
-# if __STDC__
-#  define PARAMS(args) args
-# else
-#  define PARAMS(args) ()
-# endif
-#endif
-
-#ifndef internal_function
-# define internal_function
-#endif
-
-#ifndef W
-# define W(flag, data) ((flag) ? SWAP (data) : (data))
-#endif
-
-
-#ifdef _LIBC
-# include <byteswap.h>
-# define SWAP(i) bswap_32 (i)
-#else
-static nls_uint32 SWAP PARAMS ((nls_uint32 i));
-
-static inline nls_uint32
-SWAP (i)
-     nls_uint32 i;
-{
-  return (i << 24) | ((i & 0xff00) << 8) | ((i >> 8) & 0xff00) | (i >> 24);
-}
-#endif
-
-
-struct loaded_domain
-{
-  const char *data;
-  int use_mmap;
-  size_t mmap_size;
-  int must_swap;
-  nls_uint32 nstrings;
-  struct string_desc *orig_tab;
-  struct string_desc *trans_tab;
-  nls_uint32 hash_size;
-  nls_uint32 *hash_tab;
-};
-
-struct binding
-{
-  struct binding *next;
-  char *domainname;
-  char *dirname;
-};
-
-struct loaded_l10nfile *_nl_find_domain PARAMS ((const char *__dirname,
-						 char *__locale,
-						 const char *__domainname))
-     internal_function;
-void _nl_load_domain PARAMS ((struct loaded_l10nfile *__domain))
-     internal_function;
-void _nl_unload_domain PARAMS ((struct loaded_domain *__domain))
-     internal_function;
-
-/* @@ begin of epilog @@ */
-
-#endif /* gettextP.h  */
diff --git a/intl/hash-string.h b/intl/hash-string.h
deleted file mode 100644
index 66281078364..00000000000
--- a/intl/hash-string.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Implements a string hashing function.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If not,
-   write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* @@ end of prolog @@ */
-
-#ifndef PARAMS
-# if __STDC__
-#  define PARAMS(Args) Args
-# else
-#  define PARAMS(Args) ()
-# endif
-#endif
-
-/* We assume to have `unsigned long int' value with at least 32 bits.  */
-#define HASHWORDBITS 32
-
-
-/* Defines the so called `hashpjw' function by P.J. Weinberger
-   [see Aho/Sethi/Ullman, COMPILERS: Principles, Techniques and Tools,
-   1986, 1987 Bell Telephone Laboratories, Inc.]  */
-static unsigned long hash_string PARAMS ((const char *__str_param));
-
-static inline unsigned long
-hash_string (str_param)
-     const char *str_param;
-{
-  unsigned long int hval, g;
-  const char *str = str_param;
-
-  /* Compute the hash value for the given string.  */
-  hval = 0;
-  while (*str != '\0')
-    {
-      hval <<= 4;
-      hval += (unsigned long) *str++;
-      g = hval & ((unsigned long) 0xf << (HASHWORDBITS - 4));
-      if (g != 0)
-	{
-	  hval ^= g >> (HASHWORDBITS - 8);
-	  hval ^= g;
-	}
-    }
-  return hval;
-}
diff --git a/intl/intl-compat.c b/intl/intl-compat.c
deleted file mode 100644
index 415a0f3b4f8..00000000000
--- a/intl/intl-compat.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* intl-compat.c - Stub functions to call gettext functions from GNU gettext
-   Library.
-   Copyright (C) 1995 Software Foundation, Inc.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include "libgettext.h"
-
-/* @@ end of prolog @@ */
-
-
-#undef gettext
-#undef dgettext
-#undef dcgettext
-#undef textdomain
-#undef bindtextdomain
-
-
-char *
-bindtextdomain (domainname, dirname)
-     const char *domainname;
-     const char *dirname;
-{
-  return bindtextdomain__ (domainname, dirname);
-}
-
-
-char *
-dcgettext (domainname, msgid, category)
-     const char *domainname;
-     const char *msgid;
-     int category;
-{
-  return dcgettext__ (domainname, msgid, category);
-}
-
-
-char *
-dgettext (domainname, msgid)
-     const char *domainname;
-     const char *msgid;
-{
-  return dgettext__ (domainname, msgid);
-}
-
-
-char *
-gettext (msgid)
-     const char *msgid;
-{
-  return gettext__ (msgid);
-}
-
-
-char *
-textdomain (domainname)
-     const char *domainname;
-{
-  return textdomain__ (domainname);
-}
diff --git a/intl/intlh.inst.in b/intl/intlh.inst.in
deleted file mode 100644
index 95e15a8f266..00000000000
--- a/intl/intlh.inst.in
+++ /dev/null
@@ -1,111 +0,0 @@
-/* Message catalogs for internationalization.
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
-   USA.  */
-
-#ifndef _LIBINTL_H
-#define _LIBINTL_H	1
-
-@INCLUDE_LOCALE_H@
-
-/* We define an additional symbol to signal that we use the GNU
-   implementation of gettext.  */
-#define __USE_GNU_GETTEXT 1
-
-#ifndef PARAMS
-# if __STDC__ || defined __cplusplus
-#  define PARAMS(args) args
-# else
-#  define PARAMS(args) ()
-# endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Look up MSGID in the current default message catalog for the current
-   LC_MESSAGES locale.  If not found, returns MSGID itself (the default
-   text).  */
-extern char *gettext PARAMS ((const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current
-   LC_MESSAGES locale.  */
-extern char *dgettext PARAMS ((const char *__domainname, const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current CATEGORY
-   locale.  */
-extern char *dcgettext PARAMS ((const char *__domainname, const char *__msgid,
-				int __category));
-
-
-/* Set the current default message catalog to DOMAINNAME.
-   If DOMAINNAME is null, return the current default.
-   If DOMAINNAME is "", reset to the default of "messages".  */
-extern char *textdomain PARAMS ((const char *__domainname));
-
-/* Specify that the DOMAINNAME message catalog will be found
-   in DIRNAME rather than in the system locale data base.  */
-extern char *bindtextdomain PARAMS ((const char *__domainname,
-				     const char *__dirname));
-
-
-/* Optimized version of the functions above.  */
-#if defined __OPTIMIZED
-/* These must be a macro.  Inlined functions are useless because the
-   `__builtin_constant_p' predicate in dcgettext would always return
-   false.  */
-
-# define gettext(msgid) dgettext ((char *) 0, msgid)
-
-# define dgettext(domainname, msgid)					      \
-  dcgettext (domainname, msgid, LC_MESSAGES)
-
-# if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 7)
-/* This global variable is defined in loadmsgcat.c.  We need a sign,
-   whether a new catalog was loaded, which can be associated with all
-   translations.  */
-extern int _nl_msg_cat_cntr;
-
-#  define dcgettext(domainname, msgid, category)			      \
-  (__extension__							      \
-   ({									      \
-     char *__result;							      \
-     if (__builtin_constant_p (msgid))					      \
-       {								      \
-	 static char *__translation__;					      \
-	 static int __catalog_counter__;				      \
-	 if (! __translation__ || __catalog_counter__ != _nl_msg_cat_cntr)    \
-	   {								      \
-	     __translation__ =						      \
-	       (dcgettext) ((domainname), (msgid), (category));		      \
-	     __catalog_counter__ = _nl_msg_cat_cntr;			      \
-	   }								      \
-	 __result = __translation__;					      \
-       }								      \
-     else								      \
-       __result = (dcgettext) ((domainname), (msgid), (category));	      \
-     __result;								      \
-    }))
-# endif
-#endif /* Optimizing. */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* libintl.h */
diff --git a/intl/l10nflist.c b/intl/l10nflist.c
deleted file mode 100644
index 3ef93b84733..00000000000
--- a/intl/l10nflist.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* Handle list of needed message catalogs
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-
-#if defined HAVE_STRING_H || defined _LIBC
-# ifndef _GNU_SOURCE
-#  define _GNU_SOURCE	1
-# endif
-# include <string.h>
-#else
-# include <strings.h>
-# ifndef memcpy
-#  define memcpy(Dst, Src, Num) bcopy (Src, Dst, Num)
-# endif
-#endif
-#if !HAVE_STRCHR && !defined _LIBC
-# ifndef strchr
-#  define strchr index
-# endif
-#endif
-
-#if defined _LIBC || defined HAVE_ARGZ_H
-# include <argz.h>
-#endif
-#include <ctype.h>
-#include <sys/types.h>
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#endif
-
-#include "loadinfo.h"
-
-/* On some strange systems still no definition of NULL is found.  Sigh!  */
-#ifndef NULL
-# if defined __STDC__ && __STDC__
-#  define NULL ((void *) 0)
-# else
-#  define NULL 0
-# endif
-#endif
-
-/* @@ end of prolog @@ */
-
-#ifdef _LIBC
-/* Rename the non ANSI C functions.  This is required by the standard
-   because some ANSI C functions will require linking with this object
-   file and the name space must not be polluted.  */
-# ifndef stpcpy
-#  define stpcpy(dest, src) __stpcpy(dest, src)
-# endif
-#else
-# ifndef HAVE_STPCPY
-static char *stpcpy PARAMS ((char *dest, const char *src));
-# endif
-#endif
-
-/* Define function which are usually not available.  */
-
-#if !defined _LIBC && !defined HAVE___ARGZ_COUNT
-/* Returns the number of strings in ARGZ.  */
-static size_t argz_count__ PARAMS ((const char *argz, size_t len));
-
-static size_t
-argz_count__ (argz, len)
-     const char *argz;
-     size_t len;
-{
-  size_t count = 0;
-  while (len > 0)
-    {
-      size_t part_len = strlen (argz);
-      argz += part_len + 1;
-      len -= part_len + 1;
-      count++;
-    }
-  return count;
-}
-# undef __argz_count
-# define __argz_count(argz, len) argz_count__ (argz, len)
-#endif	/* !_LIBC && !HAVE___ARGZ_COUNT */
-
-#if !defined _LIBC && !defined HAVE___ARGZ_STRINGIFY
-/* Make '\0' separated arg vector ARGZ printable by converting all the '\0's
-   except the last into the character SEP.  */
-static void argz_stringify__ PARAMS ((char *argz, size_t len, int sep));
-
-static void
-argz_stringify__ (argz, len, sep)
-     char *argz;
-     size_t len;
-     int sep;
-{
-  while (len > 0)
-    {
-      size_t part_len = strlen (argz);
-      argz += part_len;
-      len -= part_len + 1;
-      if (len > 0)
-	*argz++ = sep;
-    }
-}
-# undef __argz_stringify
-# define __argz_stringify(argz, len, sep) argz_stringify__ (argz, len, sep)
-#endif	/* !_LIBC && !HAVE___ARGZ_STRINGIFY */
-
-#if !defined _LIBC && !defined HAVE___ARGZ_NEXT
-static char *argz_next__ PARAMS ((char *argz, size_t argz_len,
-				  const char *entry));
-
-static char *
-argz_next__ (argz, argz_len, entry)
-     char *argz;
-     size_t argz_len;
-     const char *entry;
-{
-  if (entry)
-    {
-      if (entry < argz + argz_len)
-        entry = strchr (entry, '\0') + 1;
-
-      return entry >= argz + argz_len ? NULL : (char *) entry;
-    }
-  else
-    if (argz_len > 0)
-      return argz;
-    else
-      return 0;
-}
-# undef __argz_next
-# define __argz_next(argz, len, entry) argz_next__ (argz, len, entry)
-#endif	/* !_LIBC && !HAVE___ARGZ_NEXT */
-
-
-/* Return number of bits set in X.  */
-static int pop PARAMS ((int x));
-
-static inline int
-pop (x)
-     int x;
-{
-  /* We assume that no more than 16 bits are used.  */
-  x = ((x & ~0x5555) >> 1) + (x & 0x5555);
-  x = ((x & ~0x3333) >> 2) + (x & 0x3333);
-  x = ((x >> 4) + x) & 0x0f0f;
-  x = ((x >> 8) + x) & 0xff;
-
-  return x;
-}
-
-
-struct loaded_l10nfile *
-_nl_make_l10nflist (l10nfile_list, dirlist, dirlist_len, mask, language,
-		    territory, codeset, normalized_codeset, modifier, special,
-		    sponsor, revision, filename, do_allocate)
-     struct loaded_l10nfile **l10nfile_list;
-     const char *dirlist;
-     size_t dirlist_len;
-     int mask;
-     const char *language;
-     const char *territory;
-     const char *codeset;
-     const char *normalized_codeset;
-     const char *modifier;
-     const char *special;
-     const char *sponsor;
-     const char *revision;
-     const char *filename;
-     int do_allocate;
-{
-  char *abs_filename;
-  struct loaded_l10nfile *last = NULL;
-  struct loaded_l10nfile *retval;
-  char *cp;
-  size_t entries;
-  int cnt;
-
-  /* Allocate room for the full file name.  */
-  abs_filename = (char *) malloc (dirlist_len
-				  + strlen (language)
-				  + ((mask & TERRITORY) != 0
-				     ? strlen (territory) + 1 : 0)
-				  + ((mask & XPG_CODESET) != 0
-				     ? strlen (codeset) + 1 : 0)
-				  + ((mask & XPG_NORM_CODESET) != 0
-				     ? strlen (normalized_codeset) + 1 : 0)
-				  + (((mask & XPG_MODIFIER) != 0
-				      || (mask & CEN_AUDIENCE) != 0)
-				     ? strlen (modifier) + 1 : 0)
-				  + ((mask & CEN_SPECIAL) != 0
-				     ? strlen (special) + 1 : 0)
-				  + (((mask & CEN_SPONSOR) != 0
-				      || (mask & CEN_REVISION) != 0)
-				     ? (1 + ((mask & CEN_SPONSOR) != 0
-					     ? strlen (sponsor) + 1 : 0)
-					+ ((mask & CEN_REVISION) != 0
-					   ? strlen (revision) + 1 : 0)) : 0)
-				  + 1 + strlen (filename) + 1);
-
-  if (abs_filename == NULL)
-    return NULL;
-
-  retval = NULL;
-  last = NULL;
-
-  /* Construct file name.  */
-  memcpy (abs_filename, dirlist, dirlist_len);
-  __argz_stringify (abs_filename, dirlist_len, ':');
-  cp = abs_filename + (dirlist_len - 1);
-  *cp++ = '/';
-  cp = stpcpy (cp, language);
-
-  if ((mask & TERRITORY) != 0)
-    {
-      *cp++ = '_';
-      cp = stpcpy (cp, territory);
-    }
-  if ((mask & XPG_CODESET) != 0)
-    {
-      *cp++ = '.';
-      cp = stpcpy (cp, codeset);
-    }
-  if ((mask & XPG_NORM_CODESET) != 0)
-    {
-      *cp++ = '.';
-      cp = stpcpy (cp, normalized_codeset);
-    }
-  if ((mask & (XPG_MODIFIER | CEN_AUDIENCE)) != 0)
-    {
-      /* This component can be part of both syntaces but has different
-	 leading characters.  For CEN we use `+', else `@'.  */
-      *cp++ = (mask & CEN_AUDIENCE) != 0 ? '+' : '@';
-      cp = stpcpy (cp, modifier);
-    }
-  if ((mask & CEN_SPECIAL) != 0)
-    {
-      *cp++ = '+';
-      cp = stpcpy (cp, special);
-    }
-  if ((mask & (CEN_SPONSOR | CEN_REVISION)) != 0)
-    {
-      *cp++ = ',';
-      if ((mask & CEN_SPONSOR) != 0)
-	cp = stpcpy (cp, sponsor);
-      if ((mask & CEN_REVISION) != 0)
-	{
-	  *cp++ = '_';
-	  cp = stpcpy (cp, revision);
-	}
-    }
-
-  *cp++ = '/';
-  stpcpy (cp, filename);
-
-  /* Look in list of already loaded domains whether it is already
-     available.  */
-  last = NULL;
-  for (retval = *l10nfile_list; retval != NULL; retval = retval->next)
-    if (retval->filename != NULL)
-      {
-	int compare = strcmp (retval->filename, abs_filename);
-	if (compare == 0)
-	  /* We found it!  */
-	  break;
-	if (compare < 0)
-	  {
-	    /* It's not in the list.  */
-	    retval = NULL;
-	    break;
-	  }
-
-	last = retval;
-      }
-
-  if (retval != NULL || do_allocate == 0)
-    {
-      free (abs_filename);
-      return retval;
-    }
-
-  retval = (struct loaded_l10nfile *)
-    malloc (sizeof (*retval) + (__argz_count (dirlist, dirlist_len)
-				* (1 << pop (mask))
-				* sizeof (struct loaded_l10nfile *)));
-  if (retval == NULL)
-    return NULL;
-
-  retval->filename = abs_filename;
-  retval->decided = (__argz_count (dirlist, dirlist_len) != 1
-		     || ((mask & XPG_CODESET) != 0
-			 && (mask & XPG_NORM_CODESET) != 0));
-  retval->data = NULL;
-
-  if (last == NULL)
-    {
-      retval->next = *l10nfile_list;
-      *l10nfile_list = retval;
-    }
-  else
-    {
-      retval->next = last->next;
-      last->next = retval;
-    }
-
-  entries = 0;
-  /* If the DIRLIST is a real list the RETVAL entry corresponds not to
-     a real file.  So we have to use the DIRLIST separation mechanism
-     of the inner loop.  */
-  cnt = __argz_count (dirlist, dirlist_len) == 1 ? mask - 1 : mask;
-  for (; cnt >= 0; --cnt)
-    if ((cnt & ~mask) == 0
-	&& ((cnt & CEN_SPECIFIC) == 0 || (cnt & XPG_SPECIFIC) == 0)
-	&& ((cnt & XPG_CODESET) == 0 || (cnt & XPG_NORM_CODESET) == 0))
-      {
-	/* Iterate over all elements of the DIRLIST.  */
-	char *dir = NULL;
-
-	while ((dir = __argz_next ((char *) dirlist, dirlist_len, dir))
-	       != NULL)
-	  retval->successor[entries++]
-	    = _nl_make_l10nflist (l10nfile_list, dir, strlen (dir) + 1, cnt,
-				  language, territory, codeset,
-				  normalized_codeset, modifier, special,
-				  sponsor, revision, filename, 1);
-      }
-  retval->successor[entries] = NULL;
-
-  return retval;
-}
-
-/* Normalize codeset name.  There is no standard for the codeset
-   names.  Normalization allows the user to use any of the common
-   names.  */
-const char *
-_nl_normalize_codeset (codeset, name_len)
-     const unsigned char *codeset;
-     size_t name_len;
-{
-  int len = 0;
-  int only_digit = 1;
-  char *retval;
-  char *wp;
-  size_t cnt;
-
-  for (cnt = 0; cnt < name_len; ++cnt)
-    if (isalnum (codeset[cnt]))
-      {
-	++len;
-
-	if (isalpha (codeset[cnt]))
-	  only_digit = 0;
-      }
-
-  retval = (char *) malloc ((only_digit ? 3 : 0) + len + 1);
-
-  if (retval != NULL)
-    {
-      if (only_digit)
-	wp = stpcpy (retval, "iso");
-      else
-	wp = retval;
-
-      for (cnt = 0; cnt < name_len; ++cnt)
-	if (isalpha (codeset[cnt]))
-	  *wp++ = tolower (codeset[cnt]);
-	else if (isdigit (codeset[cnt]))
-	  *wp++ = codeset[cnt];
-
-      *wp = '\0';
-    }
-
-  return (const char *) retval;
-}
-
-
-/* @@ begin of epilog @@ */
-
-/* We don't want libintl.a to depend on any other library.  So we
-   avoid the non-standard function stpcpy.  In GNU C Library this
-   function is available, though.  Also allow the symbol HAVE_STPCPY
-   to be defined.  */
-#if !_LIBC && !HAVE_STPCPY
-static char *
-stpcpy (dest, src)
-     char *dest;
-     const char *src;
-{
-  while ((*dest++ = *src++) != '\0')
-    /* Do nothing. */ ;
-  return dest - 1;
-}
-#endif
diff --git a/intl/libgettext.h b/intl/libgettext.h
deleted file mode 100644
index f8c224e47f7..00000000000
--- a/intl/libgettext.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* Message catalogs for internationalization.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-/* Because on some systems (e.g. Solaris) we sometimes have to include
-   the systems libintl.h as well as this file we have more complex
-   include protection above.  But the systems header might perhaps also
-   define _LIBINTL_H and therefore we have to protect the definition here.  */
-
-#if !defined _LIBINTL_H || !defined _LIBGETTEXT_H
-#ifndef _LIBINTL_H
-# define _LIBINTL_H	1
-#endif
-#define _LIBGETTEXT_H	1
-
-/* We define an additional symbol to signal that we use the GNU
-   implementation of gettext.  */
-#define __USE_GNU_GETTEXT 1
-
-#include <sys/types.h>
-
-#if HAVE_LOCALE_H
-# include <locale.h>
-#endif
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* @@ end of prolog @@ */
-
-#ifndef PARAMS
-# if __STDC__ || defined __cplusplus
-#  define PARAMS(args) args
-# else
-#  define PARAMS(args) ()
-# endif
-#endif
-
-#ifndef NULL
-# if !defined __cplusplus || defined __GNUC__
-#  define NULL ((void *) 0)
-# else
-#  define NULL (0)
-# endif
-#endif
-
-#if !HAVE_LC_MESSAGES
-/* This value determines the behaviour of the gettext() and dgettext()
-   function.  But some system does not have this defined.  Define it
-   to a default value.  */
-# define LC_MESSAGES (-1)
-#endif
-
-
-/* Declarations for gettext-using-catgets interface.  Derived from
-   Jim Meyering's libintl.h.  */
-struct _msg_ent
-{
-  const char *_msg;
-  int _msg_number;
-};
-
-
-#if HAVE_CATGETS
-/* These two variables are defined in the automatically by po-to-tbl.sed
-   generated file `cat-id-tbl.c'.  */
-extern const struct _msg_ent _msg_tbl[];
-extern int _msg_tbl_length;
-#endif
-
-
-/* For automatical extraction of messages sometimes no real
-   translation is needed.  Instead the string itself is the result.  */
-#define gettext_noop(Str) (Str)
-
-/* Look up MSGID in the current default message catalog for the current
-   LC_MESSAGES locale.  If not found, returns MSGID itself (the default
-   text).  */
-extern char *gettext PARAMS ((const char *__msgid));
-extern char *gettext__ PARAMS ((const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current
-   LC_MESSAGES locale.  */
-extern char *dgettext PARAMS ((const char *__domainname, const char *__msgid));
-extern char *dgettext__ PARAMS ((const char *__domainname,
-				 const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current CATEGORY
-   locale.  */
-extern char *dcgettext PARAMS ((const char *__domainname, const char *__msgid,
-				int __category));
-extern char *dcgettext__ PARAMS ((const char *__domainname,
-				  const char *__msgid, int __category));
-
-
-/* Set the current default message catalog to DOMAINNAME.
-   If DOMAINNAME is null, return the current default.
-   If DOMAINNAME is "", reset to the default of "messages".  */
-extern char *textdomain PARAMS ((const char *__domainname));
-extern char *textdomain__ PARAMS ((const char *__domainname));
-
-/* Specify that the DOMAINNAME message catalog will be found
-   in DIRNAME rather than in the system locale data base.  */
-extern char *bindtextdomain PARAMS ((const char *__domainname,
-				  const char *__dirname));
-extern char *bindtextdomain__ PARAMS ((const char *__domainname,
-				    const char *__dirname));
-
-#if ENABLE_NLS
-
-/* Solaris 2.3 has the gettext function but dcgettext is missing.
-   So we omit this optimization for Solaris 2.3.  BTW, Solaris 2.4
-   has dcgettext.  */
-# if !HAVE_CATGETS && (!HAVE_GETTEXT || HAVE_DCGETTEXT)
-
-#  define gettext(Msgid)						      \
-     dgettext (NULL, Msgid)
-
-#  define dgettext(Domainname, Msgid)					      \
-     dcgettext (Domainname, Msgid, LC_MESSAGES)
-
-#  if defined __GNUC__ && __GNUC__ == 2 && __GNUC_MINOR__ >= 7
-/* This global variable is defined in loadmsgcat.c.  We need a sign,
-   whether a new catalog was loaded, which can be associated with all
-   translations.  */
-extern int _nl_msg_cat_cntr;
-
-#   define dcgettext(Domainname, Msgid, Category)			      \
-  (__extension__							      \
-   ({									      \
-     char *__result;							      \
-     if (__builtin_constant_p (Msgid))					      \
-       {								      \
-	 static char *__translation__;					      \
-	 static int __catalog_counter__;				      \
-	 if (! __translation__ || __catalog_counter__ != _nl_msg_cat_cntr)    \
-	   {								      \
-	     __translation__ =						      \
-	       dcgettext__ (Domainname, Msgid, Category);		      \
-	     __catalog_counter__ = _nl_msg_cat_cntr;			      \
-	   }								      \
-	 __result = __translation__;					      \
-       }								      \
-     else								      \
-       __result = dcgettext__ (Domainname, Msgid, Category);		      \
-     __result;								      \
-    }))
-#  endif
-# endif
-
-#else
-
-# define gettext(Msgid) (Msgid)
-# define dgettext(Domainname, Msgid) (Msgid)
-# define dcgettext(Domainname, Msgid, Category) (Msgid)
-# define textdomain(Domainname) ((char *) Domainname)
-# define bindtextdomain(Domainname, Dirname) ((char *) Dirname)
-
-#endif
-
-/* @@ begin of epilog @@ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/intl/libintl.glibc b/intl/libintl.glibc
deleted file mode 100644
index c55b447678b..00000000000
--- a/intl/libintl.glibc
+++ /dev/null
@@ -1,120 +0,0 @@
-/* Message catalogs for internationalization.
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-   This file is derived from the file libgettext.h in the GNU gettext package.
-
-   This file is part of the GNU C Library.  Its master source is NOT part of
-   the C library, however.
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Library General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If not,
-   write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-#ifndef _LIBINTL_H
-#define _LIBINTL_H	1
-
-#include <features.h>
-
-/* We define an additional symbol to signal that we use the GNU
-   implementation of gettext.  */
-#define __USE_GNU_GETTEXT 1
-
-__BEGIN_DECLS
-
-/* Look up MSGID in the current default message catalog for the current
-   LC_MESSAGES locale.  If not found, returns MSGID itself (the default
-   text).  */
-extern char *gettext __P ((__const char *__msgid));
-extern char *__gettext __P ((__const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current
-   LC_MESSAGES locale.  */
-extern char *dgettext __P ((__const char *__domainname,
-			    __const char *__msgid));
-extern char *__dgettext __P ((__const char *__domainname,
-			      __const char *__msgid));
-
-/* Look up MSGID in the DOMAINNAME message catalog for the current CATEGORY
-   locale.  */
-extern char *dcgettext __P ((__const char *__domainname,
-			     __const char *__msgid, int __category));
-extern char *__dcgettext __P ((__const char *__domainname,
-			       __const char *__msgid, int __category));
-
-
-/* Set the current default message catalog to DOMAINNAME.
-   If DOMAINNAME is null, return the current default.
-   If DOMAINNAME is "", reset to the default of "messages".  */
-extern char *textdomain __P ((__const char *__domainname));
-extern char *__textdomain __P ((__const char *__domainname));
-
-/* Specify that the DOMAINNAME message catalog will be found
-   in DIRNAME rather than in the system locale data base.  */
-extern char *bindtextdomain __P ((__const char *__domainname,
-				  __const char *__dirname));
-extern char *__bindtextdomain __P ((__const char *__domainname,
-				    __const char *__dirname));
-
-
-/* Optimized version of the function above.  */
-#if defined __OPTIMIZE__
-
-/* We need NULL for `gettext'.  */
-# define __need_NULL
-# include <stddef.h>
-
-/* We need LC_MESSAGES for `dgettext'.  */
-# include <locale.h>
-
-/* These must be macros.  Inlined functions are useless because the
-   `__builtin_constant_p' predicate in dcgettext would always return
-   false.  */
-
-# define gettext(msgid) dgettext (NULL, msgid)
-
-# define dgettext(domainname, msgid)					      \
-  dcgettext (domainname, msgid, LC_MESSAGES)
-
-# if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 7)
-/* Variable defined in loadmsgcat.c which gets incremented every time a
-   new catalog is loaded.  */
-extern int _nl_msg_cat_cntr;
-
-#  define dcgettext(domainname, msgid, category)			      \
-  (__extension__							      \
-   ({									      \
-     char *__result;							      \
-     if (__builtin_constant_p (msgid))					      \
-       {								      \
-	 static char *__translation__;					      \
-	 static int __catalog_counter__;				      \
-	 if (! __translation__ || __catalog_counter__ != _nl_msg_cat_cntr)    \
-	   {								      \
-	     __translation__ =						      \
-	       __dcgettext ((domainname), (msgid), (category));		      \
-	     __catalog_counter__ = _nl_msg_cat_cntr;			      \
-	   }								      \
-	 __result = __translation__;					      \
-       }								      \
-     else								      \
-       __result = __dcgettext ((domainname), (msgid), (category));	      \
-     __result;								      \
-    }))
-# endif
-#endif /* Optimizing. */
-
-
-__END_DECLS
-
-#endif /* libintl.h */
diff --git a/intl/linux-msg.sed b/intl/linux-msg.sed
deleted file mode 100644
index f9b8188d783..00000000000
--- a/intl/linux-msg.sed
+++ /dev/null
@@ -1,100 +0,0 @@
-# po2msg.sed - Convert Uniforum style .po file to Linux style .msg file
-# Copyright 1995, 2002 Free Software Foundation, Inc.
-# Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-#
-#
-# The first directive in the .msg should be the definition of the
-# message set number.  We use always set number 1.
-#
-1 {
-  i\
-$set 1 # Automatically created by po2msg.sed
-  h
-  s/.*/0/
-  x
-}
-#
-# Mitch's old catalog format does not allow comments.
-#
-# We copy the original message as a comment into the .msg file.
-#
-/^msgid/ {
-  s/msgid[ 	]*"//
-#
-# This does not work now with the new format.
-# /"$/! {
-#   s/\\$//
-#   s/$/ ... (more lines following)"/
-# }
-  x
-# The following nice solution is by
-# Bruno <Haible@ma2s2.mathematik.uni-karlsruhe.de>
-  td
-# Increment a decimal number in pattern space.
-# First hide trailing `9' digits.
-  :d
-  s/9\(_*\)$/_\1/
-  td
-# Assure at least one digit is available.
-  s/^\(_*\)$/0\1/
-# Increment the last digit.
-  s/8\(_*\)$/9\1/
-  s/7\(_*\)$/8\1/
-  s/6\(_*\)$/7\1/
-  s/5\(_*\)$/6\1/
-  s/4\(_*\)$/5\1/
-  s/3\(_*\)$/4\1/
-  s/2\(_*\)$/3\1/
-  s/1\(_*\)$/2\1/
-  s/0\(_*\)$/1\1/
-# Convert the hidden `9' digits to `0's.
-  s/_/0/g
-  x
-  G
-  s/\(.*\)"\n\([0-9]*\)/$ #\2 Original Message:(\1)/p
-}
-#
-# The .msg file contains, other than the .po file, only the translations
-# but each given a unique ID.  Starting from 1 and incrementing by 1 for
-# each message we assign them to the messages.
-# It is important that the .po file used to generate the cat-id-tbl.c file
-# (with po-to-tbl) is the same as the one used here.  (At least the order
-# of declarations must not be changed.)
-#
-/^msgstr/ {
-  s/msgstr[ 	]*"\(.*\)"/# \1/
-# Clear substitution flag.
-  tb
-# Append the next line.
-  :b
-  N
-# Look whether second part is continuation line.
-  s/\(.*\n\)"\(.*\)"/\1\2/
-# Yes, then branch.
-  ta
-  P
-  D
-# Note that D includes a jump to the start!!
-# We found a continuation line.  But before printing insert '\'.
-  :a
-  s/\(.*\)\(\n.*\)/\1\\\2/
-  P
-# We cannot use D here.
-  s/.*\n\(.*\)/\1/
-  tb
-}
-d
diff --git a/intl/loadinfo.h b/intl/loadinfo.h
deleted file mode 100644
index b797c0c5bae..00000000000
--- a/intl/loadinfo.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-   Contributed by Ulrich Drepper <drepper@cygnus.com>, 1996.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifndef PARAMS
-# if __STDC__
-#  define PARAMS(args) args
-# else
-#  define PARAMS(args) ()
-# endif
-#endif
-
-/* Encoding of locale name parts.  */
-#define CEN_REVISION		1
-#define CEN_SPONSOR		2
-#define CEN_SPECIAL		4
-#define XPG_NORM_CODESET	8
-#define XPG_CODESET		16
-#define TERRITORY		32
-#define CEN_AUDIENCE		64
-#define XPG_MODIFIER		128
-
-#define CEN_SPECIFIC	(CEN_REVISION|CEN_SPONSOR|CEN_SPECIAL|CEN_AUDIENCE)
-#define XPG_SPECIFIC	(XPG_CODESET|XPG_NORM_CODESET|XPG_MODIFIER)
-
-
-struct loaded_l10nfile
-{
-  const char *filename;
-  int decided;
-
-  const void *data;
-
-  struct loaded_l10nfile *next;
-  struct loaded_l10nfile *successor[1];
-};
-
-
-extern const char *_nl_normalize_codeset PARAMS ((const unsigned char *codeset,
-						  size_t name_len));
-
-extern struct loaded_l10nfile *
-_nl_make_l10nflist PARAMS ((struct loaded_l10nfile **l10nfile_list,
-			    const char *dirlist, size_t dirlist_len, int mask,
-			    const char *language, const char *territory,
-			    const char *codeset,
-			    const char *normalized_codeset,
-			    const char *modifier, const char *special,
-			    const char *sponsor, const char *revision,
-			    const char *filename, int do_allocate));
-
-
-extern const char *_nl_expand_alias PARAMS ((const char *name));
-
-extern int _nl_explode_name PARAMS ((char *name, const char **language,
-				     const char **modifier,
-				     const char **territory,
-				     const char **codeset,
-				     const char **normalized_codeset,
-				     const char **special,
-				     const char **sponsor,
-				     const char **revision));
diff --git a/intl/loadmsgcat.c b/intl/loadmsgcat.c
deleted file mode 100644
index ab11bc95d5c..00000000000
--- a/intl/loadmsgcat.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Load needed message catalogs.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#endif
-
-#if defined HAVE_UNISTD_H || defined _LIBC
-# include <unistd.h>
-#endif
-
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP) || defined _LIBC
-# include <sys/mman.h>
-#endif
-
-#include "gettext.h"
-#include "gettextP.h"
-
-/* @@ end of prolog @@ */
-
-#ifdef _LIBC
-/* Rename the non ISO C functions.  This is required by the standard
-   because some ISO C functions will require linking with this object
-   file and the name space must not be polluted.  */
-# define open   __open
-# define close  __close
-# define read   __read
-# define mmap   __mmap
-# define munmap __munmap
-#endif
-
-/* We need a sign, whether a new catalog was loaded, which can be associated
-   with all translations.  This is important if the translations are
-   cached by one of GCC's features.  */
-int _nl_msg_cat_cntr = 0;
-
-
-/* Load the message catalogs specified by FILENAME.  If it is no valid
-   message catalog do nothing.  */
-void
-internal_function
-_nl_load_domain (domain_file)
-     struct loaded_l10nfile *domain_file;
-{
-  int fd;
-  size_t size;
-  struct stat st;
-  struct mo_file_header *data = (struct mo_file_header *) -1;
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP && !defined DISALLOW_MMAP) \
-    || defined _LIBC
-  int use_mmap = 0;
-#endif
-  struct loaded_domain *domain;
-
-  domain_file->decided = 1;
-  domain_file->data = NULL;
-
-  /* If the record does not represent a valid locale the FILENAME
-     might be NULL.  This can happen when according to the given
-     specification the locale file name is different for XPG and CEN
-     syntax.  */
-  if (domain_file->filename == NULL)
-    return;
-
-  /* Try to open the addressed file.  */
-  fd = open (domain_file->filename, O_RDONLY);
-  if (fd == -1)
-    return;
-
-  /* We must know about the size of the file.  */
-  if (fstat (fd, &st) != 0
-      || (size = (size_t) st.st_size) != st.st_size
-      || size < sizeof (struct mo_file_header))
-    {
-      /* Something went wrong.  */
-      close (fd);
-      return;
-    }
-
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP && !defined DISALLOW_MMAP) \
-    || defined _LIBC
-  /* Now we are ready to load the file.  If mmap() is available we try
-     this first.  If not available or it failed we try to load it.  */
-  data = (struct mo_file_header *) mmap (NULL, size, PROT_READ,
-					 MAP_PRIVATE, fd, 0);
-
-  if (data != (struct mo_file_header *) -1)
-    {
-      /* mmap() call was successful.  */
-      close (fd);
-      use_mmap = 1;
-    }
-#endif
-
-  /* If the data is not yet available (i.e. mmap'ed) we try to load
-     it manually.  */
-  if (data == (struct mo_file_header *) -1)
-    {
-      size_t to_read;
-      char *read_ptr;
-
-      data = (struct mo_file_header *) malloc (size);
-      if (data == NULL)
-	return;
-
-      to_read = size;
-      read_ptr = (char *) data;
-      do
-	{
-	  long int nb = (long int) read (fd, read_ptr, to_read);
-	  if (nb == -1)
-	    {
-	      close (fd);
-	      return;
-	    }
-
-	  read_ptr += nb;
-	  to_read -= nb;
-	}
-      while (to_read > 0);
-
-      close (fd);
-    }
-
-  /* Using the magic number we can test whether it really is a message
-     catalog file.  */
-  if (data->magic != _MAGIC && data->magic != _MAGIC_SWAPPED)
-    {
-      /* The magic number is wrong: not a message catalog file.  */
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP && !defined DISALLOW_MMAP) \
-    || defined _LIBC
-      if (use_mmap)
-	munmap ((caddr_t) data, size);
-      else
-#endif
-	free (data);
-      return;
-    }
-
-  domain_file->data
-    = (struct loaded_domain *) malloc (sizeof (struct loaded_domain));
-  if (domain_file->data == NULL)
-    return;
-
-  domain = (struct loaded_domain *) domain_file->data;
-  domain->data = (char *) data;
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP && !defined DISALLOW_MMAP) \
-    || defined _LIBC
-  domain->use_mmap = use_mmap;
-#endif
-  domain->mmap_size = size;
-  domain->must_swap = data->magic != _MAGIC;
-
-  /* Fill in the information about the available tables.  */
-  switch (W (domain->must_swap, data->revision))
-    {
-    case 0:
-      domain->nstrings = W (domain->must_swap, data->nstrings);
-      domain->orig_tab = (struct string_desc *)
-	((char *) data + W (domain->must_swap, data->orig_tab_offset));
-      domain->trans_tab = (struct string_desc *)
-	((char *) data + W (domain->must_swap, data->trans_tab_offset));
-      domain->hash_size = W (domain->must_swap, data->hash_tab_size);
-      domain->hash_tab = (nls_uint32 *)
-	((char *) data + W (domain->must_swap, data->hash_tab_offset));
-      break;
-    default:
-      /* This is an illegal revision.  */
-#if (defined HAVE_MMAP && defined HAVE_MUNMAP && !defined DISALLOW_MMAP) \
-    || defined _LIBC
-      if (use_mmap)
-	munmap ((caddr_t) data, size);
-      else
-#endif
-	free (data);
-      free (domain);
-      domain_file->data = NULL;
-      return;
-    }
-
-  /* Show that one domain is changed.  This might make some cached
-     translations invalid.  */
-  ++_nl_msg_cat_cntr;
-}
-
-
-#ifdef _LIBC
-void
-internal_function
-_nl_unload_domain (domain)
-     struct loaded_domain *domain;
-{
-  if (domain->use_mmap)
-    munmap ((caddr_t) domain->data, domain->mmap_size);
-  else
-    free ((void *) domain->data);
-
-  free (domain);
-}
-#endif
diff --git a/intl/localealias.c b/intl/localealias.c
deleted file mode 100644
index 833df0351aa..00000000000
--- a/intl/localealias.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* Handle aliases for locale names.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Written by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#include <ctype.h>
-#include <stdio.h>
-#include <sys/types.h>
-
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-# define HAVE_ALLOCA 1
-#else
-# if defined HAVE_ALLOCA_H || defined _LIBC
-#  include <alloca.h>
-# else
-#  ifdef _AIX
- #pragma alloca
-#  else
-#   ifndef alloca
-char *alloca ();
-#   endif
-#  endif
-# endif
-#endif
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#else
-char *getenv ();
-# ifdef HAVE_MALLOC_H
-#  include <malloc.h>
-# else
-void free ();
-# endif
-#endif
-
-#if defined HAVE_STRING_H || defined _LIBC
-# ifndef _GNU_SOURCE
-#  define _GNU_SOURCE	1
-# endif
-# include <string.h>
-#else
-# include <strings.h>
-# ifndef memcpy
-#  define memcpy(Dst, Src, Num) bcopy (Src, Dst, Num)
-# endif
-#endif
-#if !HAVE_STRCHR && !defined _LIBC
-# ifndef strchr
-#  define strchr index
-# endif
-#endif
-
-#include "gettext.h"
-#include "gettextP.h"
-
-/* @@ end of prolog @@ */
-
-#ifdef _LIBC
-/* Rename the non ANSI C functions.  This is required by the standard
-   because some ANSI C functions will require linking with this object
-   file and the name space must not be polluted.  */
-# define strcasecmp __strcasecmp
-
-# define mempcpy __mempcpy
-# define HAVE_MEMPCPY	1
-
-/* We need locking here since we can be called from different places.  */
-# include <bits/libc-lock.h>
-
-__libc_lock_define_initialized (static, lock);
-#endif
-
-
-/* For those loosing systems which don't have `alloca' we have to add
-   some additional code emulating it.  */
-#ifdef HAVE_ALLOCA
-/* Nothing has to be done.  */
-# define ADD_BLOCK(list, address) /* nothing */
-# define FREE_BLOCKS(list) /* nothing */
-#else
-struct block_list
-{
-  void *address;
-  struct block_list *next;
-};
-# define ADD_BLOCK(list, addr)						      \
-  do {									      \
-    struct block_list *newp = (struct block_list *) malloc (sizeof (*newp));  \
-    /* If we cannot get a free block we cannot add the new element to	      \
-       the list.  */							      \
-    if (newp != NULL) {							      \
-      newp->address = (addr);						      \
-      newp->next = (list);						      \
-      (list) = newp;							      \
-    }									      \
-  } while (0)
-# define FREE_BLOCKS(list)						      \
-  do {									      \
-    while (list != NULL) {						      \
-      struct block_list *old = list;					      \
-      list = list->next;						      \
-      free (old);							      \
-    }									      \
-  } while (0)
-# undef alloca
-# define alloca(size) (malloc (size))
-#endif	/* have alloca */
-
-
-struct alias_map
-{
-  const char *alias;
-  const char *value;
-};
-
-
-static char *string_space = NULL;
-static size_t string_space_act = 0;
-static size_t string_space_max = 0;
-static struct alias_map *map;
-static size_t nmap = 0;
-static size_t maxmap = 0;
-
-
-/* Prototypes for local functions.  */
-static size_t read_alias_file PARAMS ((const char *fname, int fname_len))
-     internal_function;
-static void extend_alias_table PARAMS ((void));
-static int alias_compare PARAMS ((const struct alias_map *map1,
-				  const struct alias_map *map2));
-
-
-const char *
-_nl_expand_alias (name)
-    const char *name;
-{
-  static const char *locale_alias_path = LOCALE_ALIAS_PATH;
-  struct alias_map *retval;
-  const char *result = NULL;
-  size_t added;
-
-#ifdef _LIBC
-  __libc_lock_lock (lock);
-#endif
-
-  do
-    {
-      struct alias_map item;
-
-      item.alias = name;
-
-      if (nmap > 0)
-	retval = (struct alias_map *) bsearch (&item, map, nmap,
-					       sizeof (struct alias_map),
-					       (int (*) PARAMS ((const void *,
-								 const void *))
-						) alias_compare);
-      else
-	retval = NULL;
-
-      /* We really found an alias.  Return the value.  */
-      if (retval != NULL)
-	{
-	  result = retval->value;
-	  break;
-	}
-
-      /* Perhaps we can find another alias file.  */
-      added = 0;
-      while (added == 0 && locale_alias_path[0] != '\0')
-	{
-	  const char *start;
-
-	  while (locale_alias_path[0] == ':')
-	    ++locale_alias_path;
-	  start = locale_alias_path;
-
-	  while (locale_alias_path[0] != '\0' && locale_alias_path[0] != ':')
-	    ++locale_alias_path;
-
-	  if (start < locale_alias_path)
-	    added = read_alias_file (start, locale_alias_path - start);
-	}
-    }
-  while (added != 0);
-
-#ifdef _LIBC
-  __libc_lock_unlock (lock);
-#endif
-
-  return result;
-}
-
-
-static size_t
-internal_function
-read_alias_file (fname, fname_len)
-     const char *fname;
-     int fname_len;
-{
-#ifndef HAVE_ALLOCA
-  struct block_list *block_list = NULL;
-#endif
-  FILE *fp;
-  char *full_fname;
-  size_t added;
-  static const char aliasfile[] = "/locale.alias";
-
-  full_fname = (char *) alloca (fname_len + sizeof aliasfile);
-  ADD_BLOCK (block_list, full_fname);
-#ifdef HAVE_MEMPCPY
-  mempcpy (mempcpy (full_fname, fname, fname_len),
-	   aliasfile, sizeof aliasfile);
-#else
-  memcpy (full_fname, fname, fname_len);
-  memcpy (&full_fname[fname_len], aliasfile, sizeof aliasfile);
-#endif
-
-  fp = fopen (full_fname, "r");
-  if (fp == NULL)
-    {
-      FREE_BLOCKS (block_list);
-      return 0;
-    }
-
-  added = 0;
-  while (!feof (fp))
-    {
-      /* It is a reasonable approach to use a fix buffer here because
-	 a) we are only interested in the first two fields
-	 b) these fields must be usable as file names and so must not
-	    be that long
-       */
-      unsigned char buf[BUFSIZ];
-      unsigned char *alias;
-      unsigned char *value;
-      unsigned char *cp;
-
-      if (fgets (buf, sizeof buf, fp) == NULL)
-	/* EOF reached.  */
-	break;
-
-      /* Possibly not the whole line fits into the buffer.  Ignore
-	 the rest of the line.  */
-      if (strchr (buf, '\n') == NULL)
-	{
-	  char altbuf[BUFSIZ];
-	  do
-	    if (fgets (altbuf, sizeof altbuf, fp) == NULL)
-	      /* Make sure the inner loop will be left.  The outer loop
-		 will exit at the `feof' test.  */
-	      break;
-	  while (strchr (altbuf, '\n') == NULL);
-	}
-
-      cp = buf;
-      /* Ignore leading white space.  */
-      while (isspace (cp[0]))
-	++cp;
-
-      /* A leading '#' signals a comment line.  */
-      if (cp[0] != '\0' && cp[0] != '#')
-	{
-	  alias = cp++;
-	  while (cp[0] != '\0' && !isspace (cp[0]))
-	    ++cp;
-	  /* Terminate alias name.  */
-	  if (cp[0] != '\0')
-	    *cp++ = '\0';
-
-	  /* Now look for the beginning of the value.  */
-	  while (isspace (cp[0]))
-	    ++cp;
-
-	  if (cp[0] != '\0')
-	    {
-	      size_t alias_len;
-	      size_t value_len;
-
-	      value = cp++;
-	      while (cp[0] != '\0' && !isspace (cp[0]))
-		++cp;
-	      /* Terminate value.  */
-	      if (cp[0] == '\n')
-		{
-		  /* This has to be done to make the following test
-		     for the end of line possible.  We are looking for
-		     the terminating '\n' which do not overwrite here.  */
-		  *cp++ = '\0';
-		  *cp = '\n';
-		}
-	      else if (cp[0] != '\0')
-		*cp++ = '\0';
-
-	      if (nmap >= maxmap)
-		extend_alias_table ();
-
-	      alias_len = strlen (alias) + 1;
-	      value_len = strlen (value) + 1;
-
-	      if (string_space_act + alias_len + value_len > string_space_max)
-		{
-		  /* Increase size of memory pool.  */
-		  size_t new_size = (string_space_max
-				     + (alias_len + value_len > 1024
-					? alias_len + value_len : 1024));
-		  char *new_pool = (char *) realloc (string_space, new_size);
-		  if (new_pool == NULL)
-		    {
-		      FREE_BLOCKS (block_list);
-		      return added;
-		    }
-		  string_space = new_pool;
-		  string_space_max = new_size;
-		}
-
-	      map[nmap].alias = memcpy (&string_space[string_space_act],
-					alias, alias_len);
-	      string_space_act += alias_len;
-
-	      map[nmap].value = memcpy (&string_space[string_space_act],
-					value, value_len);
-	      string_space_act += value_len;
-
-	      ++nmap;
-	      ++added;
-	    }
-	}
-    }
-
-  /* Should we test for ferror()?  I think we have to silently ignore
-     errors.  --drepper  */
-  fclose (fp);
-
-  if (added > 0)
-    qsort (map, nmap, sizeof (struct alias_map),
-	   (int (*) PARAMS ((const void *, const void *))) alias_compare);
-
-  FREE_BLOCKS (block_list);
-  return added;
-}
-
-
-static void
-extend_alias_table ()
-{
-  size_t new_size;
-  struct alias_map *new_map;
-
-  new_size = maxmap == 0 ? 100 : 2 * maxmap;
-  new_map = (struct alias_map *) realloc (map, (new_size
-						* sizeof (struct alias_map)));
-  if (new_map == NULL)
-    /* Simply don't extend: we don't have any more core.  */
-    return;
-
-  map = new_map;
-  maxmap = new_size;
-}
-
-
-#ifdef _LIBC
-static void __attribute__ ((unused))
-free_mem (void)
-{
-  if (string_space != NULL)
-    free (string_space);
-  if (map != NULL)
-    free (map);
-}
-text_set_element (__libc_subfreeres, free_mem);
-#endif
-
-
-static int
-alias_compare (map1, map2)
-     const struct alias_map *map1;
-     const struct alias_map *map2;
-{
-#if defined _LIBC || defined HAVE_STRCASECMP
-  return strcasecmp (map1->alias, map2->alias);
-#else
-  const unsigned char *p1 = (const unsigned char *) map1->alias;
-  const unsigned char *p2 = (const unsigned char *) map2->alias;
-  unsigned char c1, c2;
-
-  if (p1 == p2)
-    return 0;
-
-  do
-    {
-      /* I know this seems to be odd but the tolower() function in
-	 some systems libc cannot handle nonalpha characters.  */
-      c1 = isupper (*p1) ? tolower (*p1) : *p1;
-      c2 = isupper (*p2) ? tolower (*p2) : *p2;
-      if (c1 == '\0')
-	break;
-      ++p1;
-      ++p2;
-    }
-  while (c1 == c2);
-
-  return c1 - c2;
-#endif
-}
diff --git a/intl/po2tbl.sed.in b/intl/po2tbl.sed.in
deleted file mode 100644
index ebb32f29353..00000000000
--- a/intl/po2tbl.sed.in
+++ /dev/null
@@ -1,102 +0,0 @@
-# po2tbl.sed - Convert Uniforum style .po file to lookup table for catgets
-# Copyright (C) 1995 Free Software Foundation, Inc.
-# Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-#
-1 {
-  i\
-/* Automatically generated by po2tbl.sed from @PACKAGE NAME@.pot.  */\
-\
-#if HAVE_CONFIG_H\
-# include <config.h>\
-#endif\
-\
-#include "libgettext.h"\
-\
-const struct _msg_ent _msg_tbl[] = {
-  h
-  s/.*/0/
-  x
-}
-#
-# Write msgid entries in C array form.
-#
-/^msgid/ {
-  s/msgid[ 	]*\(".*"\)/  {\1/
-  tb
-# Append the next line
-  :b
-  N
-# Look whether second part is continuation line.
-  s/\(.*\)"\(\n\)"\(.*"\)/\1\2\3/
-# Yes, then branch.
-  ta
-# Because we assume that the input file correctly formed the line
-# just read cannot be again be a msgid line.  So it's safe to ignore
-# it.
-  s/\(.*\)\n.*/\1/
-  bc
-# We found a continuation line.  But before printing insert '\'.
-  :a
-  s/\(.*\)\(\n.*\)/\1\\\2/
-  P
-# We cannot use D here.
-  s/.*\n\(.*\)/\1/
-# Some buggy seds do not clear the `successful substitution since last ``t'''
-# flag on `N', so we do a `t' here to clear it.
-  tb
-# Not reached
-  :c
-  x
-# The following nice solution is by
-# Bruno <Haible@ma2s2.mathematik.uni-karlsruhe.de>
-  td
-# Increment a decimal number in pattern space.
-# First hide trailing `9' digits.
-  :d
-  s/9\(_*\)$/_\1/
-  td
-# Assure at least one digit is available.
-  s/^\(_*\)$/0\1/
-# Increment the last digit.
-  s/8\(_*\)$/9\1/
-  s/7\(_*\)$/8\1/
-  s/6\(_*\)$/7\1/
-  s/5\(_*\)$/6\1/
-  s/4\(_*\)$/5\1/
-  s/3\(_*\)$/4\1/
-  s/2\(_*\)$/3\1/
-  s/1\(_*\)$/2\1/
-  s/0\(_*\)$/1\1/
-# Convert the hidden `9' digits to `0's.
-  s/_/0/g
-  x
-  G
-  s/\(.*\)\n\([0-9]*\)/\1, \2},/
-  s/\(.*\)"$/\1/
-  p
-}
-#
-# Last line.
-#
-$ {
-  i\
-};\
-
-  g
-  s/0*\(.*\)/int _msg_tbl_length = \1;/p
-}
-d
diff --git a/intl/textdomain.c b/intl/textdomain.c
deleted file mode 100644
index 9cec75cb5e3..00000000000
--- a/intl/textdomain.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Implementation of the textdomain(3) function.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Written by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifdef HAVE_CONFIG_H
-# include <config.h>
-#endif
-
-#if defined STDC_HEADERS || defined _LIBC
-# include <stdlib.h>
-#endif
-
-#if defined STDC_HEADERS || defined HAVE_STRING_H || defined _LIBC
-# include <string.h>
-#else
-# include <strings.h>
-# ifndef memcpy
-#  define memcpy(Dst, Src, Num) bcopy (Src, Dst, Num)
-# endif
-#endif
-
-#ifdef _LIBC
-# include <libintl.h>
-#else
-# include "libgettext.h"
-#endif
-
-/* @@ end of prolog @@ */
-
-/* Name of the default text domain.  */
-extern const char _nl_default_default_domain[];
-
-/* Default text domain in which entries for gettext(3) are to be found.  */
-extern const char *_nl_current_default_domain;
-
-
-/* Names for the libintl functions are a problem.  They must not clash
-   with existing names and they should follow ANSI C.  But this source
-   code is also used in GNU C Library where the names have a __
-   prefix.  So we have to make a difference here.  */
-#ifdef _LIBC
-# define TEXTDOMAIN __textdomain
-# ifndef strdup
-#  define strdup(str) __strdup (str)
-# endif
-#else
-# define TEXTDOMAIN textdomain__
-#endif
-
-/* Set the current default message catalog to DOMAINNAME.
-   If DOMAINNAME is null, return the current default.
-   If DOMAINNAME is "", reset to the default of "messages".  */
-char *
-TEXTDOMAIN (domainname)
-     const char *domainname;
-{
-  char *old;
-
-  /* A NULL pointer requests the current setting.  */
-  if (domainname == NULL)
-    return (char *) _nl_current_default_domain;
-
-  old = (char *) _nl_current_default_domain;
-
-  /* If domain name is the null string set to default domain "messages".  */
-  if (domainname[0] == '\0'
-      || strcmp (domainname, _nl_default_default_domain) == 0)
-    _nl_current_default_domain = _nl_default_default_domain;
-  else
-    {
-      /* If the following malloc fails `_nl_current_default_domain'
-	 will be NULL.  This value will be returned and so signals we
-	 are out of core.  */
-#if defined _LIBC || defined HAVE_STRDUP
-      _nl_current_default_domain = strdup (domainname);
-#else
-      size_t len = strlen (domainname) + 1;
-      char *cp = (char *) malloc (len);
-      if (cp != NULL)
-	memcpy (cp, domainname, len);
-      _nl_current_default_domain = cp;
-#endif
-    }
-
-  if (old != _nl_default_default_domain)
-    free (old);
-
-  return (char *) _nl_current_default_domain;
-}
-
-#ifdef _LIBC
-/* Alias for function name in GNU C Library.  */
-weak_alias (__textdomain, textdomain);
-#endif
diff --git a/intl/xopen-msg.sed b/intl/xopen-msg.sed
deleted file mode 100644
index 1d257d3e0b9..00000000000
--- a/intl/xopen-msg.sed
+++ /dev/null
@@ -1,104 +0,0 @@
-# po2msg.sed - Convert Uniforum style .po file to X/Open style .msg file
-# Copyright 1995, 2002 Free Software Foundation, Inc.
-# Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1995.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-#
-#
-# The first directive in the .msg should be the definition of the
-# message set number.  We use always set number 1.
-#
-1 {
-  i\
-$set 1 # Automatically created by po2msg.sed
-  h
-  s/.*/0/
-  x
-}
-#
-# We copy all comments into the .msg file.  Perhaps they can help.
-#
-/^#/ s/^#[ 	]*/$ /p
-#
-# We copy the original message as a comment into the .msg file.
-#
-/^msgid/ {
-# Does not work now
-#  /"$/! {
-#    s/\\$//
-#    s/$/ ... (more lines following)"/
-#  }
-  s/^msgid[ 	]*"\(.*\)"$/$ Original Message: \1/
-  p
-}
-#
-# The .msg file contains, other than the .po file, only the translations
-# but each given a unique ID.  Starting from 1 and incrementing by 1 for
-# each message we assign them to the messages.
-# It is important that the .po file used to generate the cat-id-tbl.c file
-# (with po-to-tbl) is the same as the one used here.  (At least the order
-# of declarations must not be changed.)
-#
-/^msgstr/ {
-  s/msgstr[ 	]*"\(.*\)"/\1/
-  x
-# The following nice solution is by
-# Bruno <Haible@ma2s2.mathematik.uni-karlsruhe.de>
-  td
-# Increment a decimal number in pattern space.
-# First hide trailing `9' digits.
-  :d
-  s/9\(_*\)$/_\1/
-  td
-# Assure at least one digit is available.
-  s/^\(_*\)$/0\1/
-# Increment the last digit.
-  s/8\(_*\)$/9\1/
-  s/7\(_*\)$/8\1/
-  s/6\(_*\)$/7\1/
-  s/5\(_*\)$/6\1/
-  s/4\(_*\)$/5\1/
-  s/3\(_*\)$/4\1/
-  s/2\(_*\)$/3\1/
-  s/1\(_*\)$/2\1/
-  s/0\(_*\)$/1\1/
-# Convert the hidden `9' digits to `0's.
-  s/_/0/g
-  x
-# Bring the line in the format `<number> <message>'
-  G
-  s/^[^\n]*$/& /
-  s/\(.*\)\n\([0-9]*\)/\2 \1/
-# Clear flag from last substitution.
-  tb
-# Append the next line.
-  :b
-  N
-# Look whether second part is a continuation line.
-  s/\(.*\n\)"\(.*\)"/\1\2/
-# Yes, then branch.
-  ta
-  P
-  D
-# Note that `D' includes a jump to the start!!
-# We found a continuation line.  But before printing insert '\'.
-  :a
-  s/\(.*\)\(\n.*\)/\1\\\2/
-  P
-# We cannot use the sed command `D' here
-  s/.*\n\(.*\)/\1/
-  tb
-}
-d
diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog
index d2bda7022ed..eeae1e3435f 100644
--- a/libiberty/ChangeLog
+++ b/libiberty/ChangeLog
@@ -1,3 +1,8 @@
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* floatformat.c (floatformat_vax_aingle, floatformat_vax_double):
+	New variables.
+
 2005-10-07  Mark Mitchell  <mark@codesourcery.com>
 
 	* at-file.texi: Fix typo.
diff --git a/libiberty/floatformat.c b/libiberty/floatformat.c
index 8f0d7894641..28c9fbf662d 100644
--- a/libiberty/floatformat.c
+++ b/libiberty/floatformat.c
@@ -108,6 +108,30 @@ const struct floatformat floatformat_ieee_double_littlebyte_bigword =
   floatformat_always_valid
 };
 
+/* floatformat for VAX.  Not quite IEEE, but close enough.  */
+
+const struct floatformat floatformat_vax_f =
+{
+  floatformat_vax, 32, 0, 1, 8, 129, 0, 9, 23,
+  floatformat_intbit_no,
+  "floatformat_vax_f",
+  floatformat_always_valid
+};
+const struct floatformat floatformat_vax_d =
+{
+  floatformat_vax, 64, 0, 1, 8, 129, 0, 9, 55,
+  floatformat_intbit_no,
+  "floatformat_vax_d",
+  floatformat_always_valid
+};
+const struct floatformat floatformat_vax_g =
+{
+  floatformat_vax, 64, 0, 1, 11, 1025, 0, 12, 52,
+  floatformat_intbit_no,
+  "floatformat_vax_g",
+  floatformat_always_valid
+};
+
 static int floatformat_i387_ext_is_valid (const struct floatformat *fmt,
 					  const void *from);
 
diff --git a/mmalloc/COPYING.LIB b/mmalloc/COPYING.LIB
deleted file mode 100644
index eb685a5ec98..00000000000
--- a/mmalloc/COPYING.LIB
+++ /dev/null
@@ -1,481 +0,0 @@
-		  GNU LIBRARY GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1991 Free Software Foundation, Inc.
-                    675 Mass Ave, Cambridge, MA 02139, USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the library GPL.  It is
- numbered 2 because it goes with version 2 of the ordinary GPL.]
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
-  This license, the Library General Public License, applies to some
-specially designated Free Software Foundation software, and to any
-other libraries whose authors decide to use it.  You can use it for
-your libraries, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if
-you distribute copies of the library, or if you modify it.
-
-  For example, if you distribute copies of the library, whether gratis
-or for a fee, you must give the recipients all the rights that we gave
-you.  You must make sure that they, too, receive or can get the source
-code.  If you link a program with the library, you must provide
-complete object files to the recipients so that they can relink them
-with the library, after making changes to the library and recompiling
-it.  And you must show them these terms so they know their rights.
-
-  Our method of protecting your rights has two steps: (1) copyright
-the library, and (2) offer you this license which gives you legal
-permission to copy, distribute and/or modify the library.
-
-  Also, for each distributor's protection, we want to make certain
-that everyone understands that there is no warranty for this free
-library.  If the library is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original
-version, so that any problems introduced by others will not reflect on
-the original authors' reputations.
-
-  Finally, any free program is threatened constantly by software
-patents.  We wish to avoid the danger that companies distributing free
-software will individually obtain patent licenses, thus in effect
-transforming the program into proprietary software.  To prevent this,
-we have made it clear that any patent must be licensed for everyone's
-free use or not licensed at all.
-
-  Most GNU software, including some libraries, is covered by the ordinary
-GNU General Public License, which was designed for utility programs.  This
-license, the GNU Library General Public License, applies to certain
-designated libraries.  This license is quite different from the ordinary
-one; be sure to read it in full, and don't assume that anything in it is
-the same as in the ordinary license.
-
-  The reason we have a separate public license for some libraries is that
-they blur the distinction we usually make between modifying or adding to a
-program and simply using it.  Linking a program with a library, without
-changing the library, is in some sense simply using the library, and is
-analogous to running a utility program or application program.  However, in
-a textual and legal sense, the linked executable is a combined work, a
-derivative of the original library, and the ordinary General Public License
-treats it as such.
-
-  Because of this blurred distinction, using the ordinary General
-Public License for libraries did not effectively promote software
-sharing, because most developers did not use the libraries.  We
-concluded that weaker conditions might promote sharing better.
-
-  However, unrestricted linking of non-free programs would deprive the
-users of those programs of all benefit from the free status of the
-libraries themselves.  This Library General Public License is intended to
-permit developers of non-free programs to use free libraries, while
-preserving your freedom as a user of such programs to change the free
-libraries that are incorporated in them.  (We have not seen how to achieve
-this as regards changes in header files, but we have achieved it as regards
-changes in the actual functions of the Library.)  The hope is that this
-will lead to faster development of free libraries.
-
-  The precise terms and conditions for copying, distribution and
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-former contains code derived from the library, while the latter only
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-
-  Note that it is possible for a library to be covered by the ordinary
-General Public License rather than by this special one.
-
-		  GNU LIBRARY GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License Agreement applies to any software library which
-contains a notice placed by the copyright holder or other authorized
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-  3. You may opt to apply the terms of the ordinary GNU General Public
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-That's all there is to it!
diff --git a/mmalloc/ChangeLog b/mmalloc/ChangeLog
deleted file mode 100644
index a1e3ad0af07..00000000000
--- a/mmalloc/ChangeLog
+++ /dev/null
@@ -1,491 +0,0 @@
-2003-08-08  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* Makefile.in (install-info): Create dest dir. Support DESTDIR.
-	(install): Likewise.
-
-2002-11-28  Elena Zannoni  <ezannoni@redhat.com>
-
-	* Makefile.in (install): Move install-info to here...
-	(all): ...from here.
-
-2002-11-26  Elena Zannoni  <ezannoni@redhat.com>
-
-	* Makefile.in (INFO_DEPS): Define.
-	(all): Add install-info to the rule.
-	(info): Unse INFO_DEPS.
-	(install-info): Rewrite.
-	(uninstall-info): New.
-	(uninstall): New.
-
-2002-04-07  Andrew Cagney  <ac131313@redhat.com>
-
-	From 2002-03-05 Scott Pakin <pakin@uiuc.edu>
-	* mmap-sup.c (MAP_PRIVATE_OR_SHARED): Define.
-	(__mmalloc_mmap_morecore): Use.
-	(__mmalloc_remap_core): Use.
-	
-2000-05-17  Eli Zaretskii  <eliz@is.elta.co.il>
-
-	* Makefile.in (install-info): Make sure $(infodir) exists.  Run
-	install-info program on the installed Info files.
-
-2000-03-20  Eli Zaretskii  <eliz@is.elta.co.il>
-
-	* Makefile.in (install): Append "n", not ".n" to libmmalloc.a,
-	since the latter loses on DOS 8+3 filesystems.
-
-Mon Feb 28 10:33:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* MAINTAINERS: New file.
-
-2000-02-18  Frank Ch. Eigler  <fche@redhat.com>
-
-	From Jason "crash" Molenda <jsm@cygnus.com>:
-	* configure.in: Check for getpagesize declaration.
-	* mvmalloc.c, mmap-sup.c: Conditionally declare getpagesize.
-	* configure: Regenerated.
-
-Fri Feb 18 11:42:21 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in: Check for <unistd.h>.
-	* configure: Regenerate.
-
-	From 2000-02-17 RodneyBrown@pmsc.com:
-	* mm.c, attach.c, mmap-sup.c, sbrk-sup.c: Include <unistd.h> for
- 	sbrk and lseek declarations.  Update copyright.
-
-2000-02-04  Kevin Buettner  (kevinb@cygnus.com)
-
-	* acinclude.m4, aclocal.m4: New files.
-	* configure.in (sbrk): Use BFD_NEED_DECLARATION to test for
-	presence of a suitable declaration in the system headers.
-	* configure: Regenerated.
-	* sbrk-sup.c (sbrk): Ifdef'd with NEED_DECLARATION_SBRK.
-
-1999-01-04  Jason Molenda  (jsm@bugshack.cygnus.com)
-
-	* configure.in: Requires autoconf 2.12.1 or higher.
-	* configure: Regenerated.
-
-1998-07-24  Jim Blandy  <jimb@zwingli.cygnus.com>
-
-	* mcalloc.c: #include <sys/types.h> before <string.h>.  HP/UX 11.0
-	needs this.
-
-Thu Apr 23 12:19:22 1998  Philippe De Muyter  <phdm@macqel.be>
-
-        * mmalloc.h: Include sys/types.h and stdio.h #ifndef HAVE_STDDEF_H.
-        * mmprivate.h: Do not handle HAVE_STDDEF_H here, since we include
-        mmalloc.h.
-
-Tue Mar 24 17:07:02 1998  Stu Grossman  <grossman@bhuna.cygnus.co.uk>
-
-	* Makefile.in:  Get SHELL from configure.
-	* configure:  Regenerate with autoconf 2.12.1 to fix shell issues for
-	NT native builds.
-
-Mon Feb  7 13:06:45 1997  Philippe De Muyter  <phdm@macqel.be>
-
-        * mmalloc/detach.c: Do not include fcntl.h.
-
-Thu Aug 28 13:15:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mrealloc.c (realloc): Store result in local variable before
- 	returning it.  Makes debugging much easier at negligible cost.
-
-Tue Feb  4 16:30:59 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* mvalloc.c (cache_pagesize): Rename from pagesize, so that if we
-	are building mm.o, it does not conflict with the variable of the
-	same name in mmap-sup.c.
-
-Sat Dec 28 12:48:32 1996  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (mm.o): New target that combines all the functions
-	into a single object module.  This avoids client programs picking
- 	up part of the allocation routines from mmalloc and part from libc,
- 	which can lead to undefined behavior.
-	(CFILES): Add mm.c
-	(TARGETOBJS): Define to be either the individual objects or the
-	single combined object.
-	(TARGETLIB): Create the archive using TARGETOBJS.
-	* mm.c: New file that simply #includes the other source C files.
-	
-Thu Oct  3 15:45:23 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
-
-	* Makefile.in (maintainer-clean): Depend on distclean, remove
-	duplication.
-
-Tue Sep 10 17:52:06 1996  Fred Fish  <fnf@cygnus.com>
-
-	* mmcheck.c (checkhdr): Add prototype.
-	(mfree_check): Ditto.
-	(mmalloc_check): Ditto.
-	(mrealloc_check): Ditto.
-	* mmtrace.c (tr_break): Ditto.
-	(tr_freehook): Ditto.
-	(tr_mallochook): Ditto.
-	(tr_reallochook): Ditto.
-	* sbrk-sup.c (sbrk_morecore): Ditto.
-
-Wed Sep  4 18:02:45 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* configure configure.in:  Don't default CC to cc.  It causes problems
-	when starting a compile in the mmalloc directory.
-
-Wed Jul 24 00:53:34 1996  Fred Fish  <fnf@cygnus.com>
-
-	* mmalloc.h (mmalloc_findbase): Add prototype.
-
-Fri Jul 12 18:35:34 1996  Fred Fish  <fnf@cygnus.com>
-
-	* mmap-sup.c (mmalloc_findbase): Change to not require /dev/zero
-	if MMAP_ANONYMOUS is available.
-
-Wed Jul 10 23:53:42 1996  Fred Fish  <fnf@cygnus.com>
-
-	* detach.c (mmalloc_detach): Fix bug in computation of negative
-	brk value.
-	* mmcheck.c (mmcheckf): Renamed from mmcheck and new FORCE argument
-	added.  Replaced hack that always allowed checking routines to be
- 	installed and enforce restriction that they have to be installed
-	prior to allocating any memory on the used heap or the FORCE argument
-	has to be non-NULL.
-	(mmcheck): New function that calls mmcheckf with FORCE set to zero,
-	for backwards compatibility.
-	* mmalloc.c (malloc): Store result in local variable before
-	returning it.  Makes debugging much easier at negligible cost.
-	* mmalloc.h (mmcheckf): Declare.
-	* attach.c (reuse): Call mmcheckf rather than mmcheck.
-	* mmap-sup.c (__mmalloc_mmap_morecore): Improve to allow mmap
-	to select a base mapping address if none is otherwise given.
-	(mmalloc_findbase): New function that user can call to find
-	an available mapping address of a given size.
-	
-Tue Jun 25 22:54:06 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
-
-	* Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir):
-	Use autoconf-set values.
-	(docdir): Removed.
-	* configure.in (AC_PREREQ): autoconf 2.5 or higher.
-	* configure: Rebuilt.
-
-Tue May 28 13:51:22 1996  Fred Fish  <fnf@cygnus.com>
-
-	From: Thomas A Peterson <tap@src.honeywell.com>
-	* Makefile.in (install-info): Apply patch to install
-	mmalloc.info from srcdir if not found in build dir.
-
-Sun Apr  7 20:55:30 1996  Fred Fish  <fnf@rtl.cygnus.com>
-
-	From: Miles Bader  <miles@gnu.ai.mit.edu>
-	* configure.in: Use AC_CHECK_TOOL to find AR & RANLIB.
-	* configure: Regenerate with autoconf.
-	* Makefile.in: Use AR set by configure substitution.
-	
-Fri Mar 29 09:57:36 1996  Fred Fish  <fnf@cygnus.com>
-
-	* mmalloc.h (mmtrace): Add prototype.
-
-Sat Feb  3 12:41:00 1996  Fred Fish  <fnf@cygnus.com>
-
-	From H.J. Lu (hjl@gnu.ai.mit.edu):
-	* mvalloc.c (valloc): new.
-	* mmemalign.c: Allocate (SIZE + ALIGNMENT - 1) and then trim
-	if possible.
-	(memalign): don't put the node on the _aligned_blocks list more
- 	than once.
-
-Mon Nov 20 12:04:32 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (OFILES): Make objects depend upon Makefile,
-	since Makefile sets DEFS which can definitely affect how
-	objects are to be compiled.
-
-Mon Nov  6 14:12:13 1995  Jason Molenda  (crash@phydeaux.cygnus.com)
-
-	* configure.in (AC_CHECK_HEADERS): add limits.h.
-	(AC_HEADER_STDC): remove.
-
-	* mmalloc.h: document necessity of defining size_t before
-	including mmalloc.h.
-
-	* mmprivate.h: add check for limits.h, remove definition of
-	NULL and size_t.
-
-Sun Nov  5 00:27:36 1995  Jason Molenda  (crash@phydeaux.cygnus.com)
-
-	* configure.in: AC_CHECK_HEADERS, not AC_CHECK_HEADER.
-
-Sun Nov  5 00:14:13 1995  Jason Molenda  (crash@phydeaux.cygnus.com)
-
-	* configure.in: add check for stddef.h
-	* mmalloc.h: include stddef.h if HAVE_STDDEF_H is defined.
-
-Sat Nov  4 19:10:13 1995  Jason Molenda  (crash@phydeaux.cygnus.com)
-
-	* configure.in: add AC_HEADER_STDC check.
-
-	* mmalloc.h: check if STDC_HEADERS instead of __STDC__.
-
-	* mmprivate.h: check if STDC_HEADERS instead of __STDC__.
-
-Tue Oct 24 13:17:44 1995  Stan Shebs  <shebs@andros.cygnus.com>
-
-	* mmprivate.h: Remove declarations (PTR, etc) that are already
-	provided by ansidecl.h, include mmalloc.h earlier in file.
-
-Tue Oct 10 11:04:47 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Makefile.in (BISON):  Remove macro.
-
-Wed Sep 20 12:51:13 1995  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (maintainer-clean): New target, synonym for
-	realclean.  Add GNU standard maintainer-clean echos.
-
-Thu Aug  3 10:45:37 1995  Fred Fish  <fnf@cygnus.com>
-
-	* Update all FSF addresses except those in COPYING* files
-	and shar archive of original FSF files.
-
-Mon Jun 12 12:11:57 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* Makefile.in (distclean, realclean): Remove config.cache and
-	  config.log.
-
-Wed May 17 17:47:44 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* Makefile.in (Makefile): Added config.status to dependency list.
-	  (config.status): New target.
-
-Fri May  5 15:17:53 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* mmap-sup.c: Removed munmap prototype.  Some systems have a
-	  slightly different prototype.
-
-Wed May  3 17:18:13 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
-
-	* Makefile.in, configure.in: Converted to use autoconf.
-	* configure: New file, generated with autoconf 2.3.
-	* config/{mh-go32, mh-irix, mh-ncr3000, mh-sunos4, 
-	  mh-sysv4}: Removed.
-
-Thu Nov  3 23:55:21 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
-
-	* Makefile.in (install-info): Name destination file correctly,
-	rather than using undefined shell variable.
-
-Fri Oct 28 16:46:58 1994  Stan Shebs  (shebs@andros.cygnus.com)
-
-	* mmprivate.h: New file, was mmalloc.h.
-	(mmalloc.h): Include.
-	* mmalloc.h: Remove all but declarations of mmalloc functions.
-	(ansidecl.h): Include.
-	* attach.c, et al: Include mmprivate.h instead of mmalloc.h.
-
-Wed Aug 24 12:55:33 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
-
-	* configure.in: Change i[34]86 to i[345]86.
-
-Mon Aug 22 11:36:40 1994  Stan Shebs  (shebs@andros.cygnus.com)
-
-	* Makefile.in (distclean): Separate from realclean.
-	(realclean): Remove mmalloc.info.
-
-Fri May  6 13:04:25 1994  Steve Chamberlain  (sac@cygnus.com)
-
-        * config/go32.mh: New file
-	* configure.in (host==go32):  Use new fragment.
-
-Tue Feb  8 00:32:28 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
-
-	* mmtrace.c (tr_freehook, tr_mallochook, tr_reallochook):
-	Cast addresses put out via fprintf to unsigned long and use %lx.
-
-Tue Nov 16 20:33:17 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
-
-	* COPYING.LIB: New file (standard version 2 LGPL, as already cited
-	by the source files).
-
-Fri Nov  5 11:47:33 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* Makefile.in (info dvi install-info): Actually make the manual.
-
-Mon Nov  1 14:20:25 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* mmalloc.texi: Fix typo ("for for" -> "for").
-
-Fri Jul 16 15:27:08 1993  Jim Kingdon  (kingdon@rtl.cygnus.com)
-
-	* test1.c: New file which tests for bug fixed below.
-	* Makefile.in (check): Put in commands to run it (but commented out
-	because it won't work for Canadian cross).
-
-	* mmalloc.c (mmalloc): When extending a free block at the end of the
-	heap, check whether which block is at the end changed.
-
-	* Makefile.in (TAGS): make work when srcdir != objdir.
-
-Thu Jul 15 07:56:47 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* attach.c, detach.c: Include <sys/types.h> before <fcntl.h>.
-
-Wed Jun 30 11:00:53 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
-
-	* Makefile.in: Add mostlyclean and realclean targets.
-
-Wed Mar 24 01:58:12 1993  david d `zoo' zuhn  (zoo at poseidon.cygnus.com)
-
-	* Makefile.in: add dvi and installcheck targets
-
-Fri Mar 12 18:35:43 1993  david d `zoo' zuhn  (zoo at cirdan.cygnus.com)
-
-	* configure.in: recognize *-*-solaris2* instead of *-*-solaris* (a
-	number of people want to call SunOS 4.1.2 "solaris1.0" and get it right)
-
-Mon Feb 22 18:08:53 1993  John Gilmore  (gnu@cygnus.com)
-
-	* Makefile.in (distclean):  Add.
-
-Tue Feb 16 08:09:15 1993  Fred Fish  (fnf@cygnus.com)
-
-	* Makefile.in, attach.c, detach.c, keys.c, mmap-sup.c, mmtrace.c,
-	sbrk-sup.c:  Use GNU Library General Public License, like other
-	files.
-
-Wed Nov 18 19:18:59 1992  John Gilmore  (gnu@cygnus.com)
-
-	* configure.in:  Regularize list of host configs.
-
-Fri Oct 30 00:59:46 1992  John Gilmore  (gnu@cygnus.com)
-
-	* mmalloc.texi:  Add missing doubled @.  Bugfix by Paul Eggert.
-
-Fri Oct 23 01:50:52 1992  Stu Grossman  (grossman at cygnus.com)
-
-	* configure.in:  Handle solaris same as sysv4.
-
-Thu Oct  1 23:34:20 1992  david d `zoo' zuhn  (zoo at cirdan.cygnus.com)
-
-	* configure.in: use cpu-vendor-os triple instead of nested cases
-
-Sun Aug 23 11:09:46 1992  Fred Fish  (fnf@cygnus.com)
-
-	* sbrk-sup.c (__mmalloc_brk_init):  Ensure base of sbrk'd region
-	is aligned.  Bug reported by Andrew Heybey (ath@lcs.mit.edu).
-
-Wed Aug 19 14:49:23 1992  Ian Lance Taylor  (ian@cygnus.com)
-
-	* Makefile.in: always create installation directories.
-
-Mon Jul 20 21:15:44 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mrealloc.c:  Minor code format style changes for consistency.
-
-Fri Jul  3 20:25:30 1992  Fred Fish  (fnf@cygnus.com)
-
-	* attach.c, detach.c, mcalloc.c, mmalloc.c, mmtrace.c, mrealloc.c,
-	sbrk-sup.c:  Remove "(void)" casts from function calls where the
-	return value is ignored, in accordance with GNU coding standards.
-
-Tue Jun 30 16:44:41 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mmalloc.h (struct mdesc):  Add FIXME comments to point out the
-	need to save some data on a per-process basis for mapped regions
-	that are shared.
-	* attach.c (reuse):  Update the morecore field for reused mapped
-	regions to be correct for the current process.
-
-Mon Jun 29 10:45:25 1992  Fred Fish  (fnf at cygnus.com)
-
-	* mmtrace.c:  Lint.
-
-Mon Jun 15 12:20:16 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mmalloc.h (struct mdesc):  Change member "errno" to
-	"saved_errno" to avoid possible conflict with ANSI C environments,
-	where it is allowed to be a macro.
-	* config/mh-ncr3000 (INSTALL):  Don't use /usr/ucb/install,
-	it is broken on ncr 3000's.
-	* config/mh-ncr3000 (RANLIB):  Use RANLIB=true.
-
-Fri Jun 12 21:34:21 1992  John Gilmore  (gnu at cygnus.com)
-
-	* mmap-sup.c:  Avoid ANSI C "empty translation unit" idiocy.
-
-Tue Jun  9 17:29:04 1992  Fred Fish  (fnf@cygnus.com)
-
-	* config/{mh-ncr3000, mh-sysv4}:  Add definition for INSTALL using
-	/usr/ucb/install.
-
-Thu Apr 30 22:36:31 1992  Fred Fish  (fnf@cygnus.com)
-
-	* sbrk-sup.c (sbrk_morecore):  Fix sbrk() error return test.
-
-Mon Apr 20 21:03:30 1992  K. Richard Pixley  (rich@cygnus.com)
-
-	* Makefile.in: rework CFLAGS so that they can be passed from the
-	  command line.  remove MINUS_G.  Default CFLAGS to -g.
-
-Thu Apr 16 20:00:21 1992  Fred Fish  (fnf@cygnus.com)
-
-	* TODO:  New file.
-	* attach.c, mcalloc.c, mfree.c, mmalloc.c, mmalloc.h, mmap-sup.c,
-	mmcheck.c, mtrace.c, mrealloc.c, mvalloc.c, sbrk-sup.c:  Lint.
-
-Fri Apr 10 22:59:17 1992  Fred Fish  (fnf@cygnus.com)
-
-	* configure.in:  Recognize new ncr3000 config.
-	* config/mh-ncr3000:  New config file.
-	* Makefile.in (MINUS_G):  Add macro and default to -g.
-
-Wed Apr  8 09:34:53 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mmalloc.c:  Minor fix to comment.
-	* mmalloc.texi:  Update to match actual implementation
-	* mmalloc.h (morecore):  Change prototype's 2nd arg to int.
-
-Tue Apr  7 22:16:09 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mmalloc.h (size_t, CHAR_BIT):  Only redefine if not already
-	defined.
-
-Mon Apr  6 20:49:33 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mmalloc.h:  Remove include of <stdlib.h>.  This also gets rid
-	of the ugly kludge installed on 1-Apr-92.
-
-Mon Apr  6 16:33:37 1992  Stu Grossman  (grossman at cygnus.com)
-
-	* detach.c (mmalloc_detach):  Arg should be PTR, not void *.
-	Fixes complaints from non __STDC__ systems.
-
-Wed Apr  1 11:47:02 1992  Fred Fish  (fnf@cygnus.com)
-
-	* mcalloc.c, mfree.c, mmalloc.c, mrealloc.c:  Minor comment
-	change.
-	* mmalloc.h:  Add ugly kludge to band-aid over problems with
-	bogus vendor <stdlib.h> files.
-
-Sun Mar 29 12:41:31 1992  John Gilmore  (gnu at cygnus.com)
-
-	* attach.c, mmalloc.c, mmcheck.c:  Lint.
-
-Thu Mar 26 17:06:04 1992  Fred Fish  (fnf@cygnus.com)
-
-	* attach.c (reuse):  Explicitly discard return value of mmcheck.
-	* mmcheck.c (mmcheck):  Document requirements for installing
-	corruption checking hooks and set up to enforce restrictions.
-
-Tue Mar 24 23:41:10 1992  K. Richard Pixley  (rich@cygnus.com)
-
-	* config/mh-irix4: new file.
-
-	* Makefile.in: added standard targets, fixed install directories.
-
-Sat Mar 14 17:34:59 1992  Fred Fish  (fnf@cygnus.com)
-
-	* Initial release, incorporated into gdb.
-
-
diff --git a/mmalloc/MAINTAINERS b/mmalloc/MAINTAINERS
deleted file mode 100644
index 0904867d658..00000000000
--- a/mmalloc/MAINTAINERS
+++ /dev/null
@@ -1,5 +0,0 @@
-The mmalloc directory is maintained by the GDB group's Host
-maintainers.
-
-This code is in a maintain-only phase - only configury patches fixing
-host compile problems are generally accepted.
diff --git a/mmalloc/Makefile.in b/mmalloc/Makefile.in
deleted file mode 100644
index b05aea7b08c..00000000000
--- a/mmalloc/Makefile.in
+++ /dev/null
@@ -1,247 +0,0 @@
-# Copyright (C) 1992 Free Software Foundation, Inc.
-# This file is part of the GNU C Library.
-
-# The GNU C Library is free software; you can redistribute it and/or
-# modify it under the terms of the GNU Library General Public License as
-# published by the Free Software Foundation; either version 2 of the
-# License, or (at your option) any later version.
-
-# The GNU C Library is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# Library General Public License for more details.
-
-# You should have received a copy of the GNU Library General Public
-# License along with the GNU C Library; see the file COPYING.LIB.  If
-# not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-
-#
-# Makefile for mmalloc directory
-#
-
-# Directory containing source files.  Don't clean up the spacing,
-# this exact string is matched for by the "configure" script.
-
-VPATH = @srcdir@
-srcdir = @srcdir@
-
-prefix =	@prefix@
-exec_prefix =	@exec_prefix@
-
-bindir =	@bindir@
-libdir =	@libdir@
-
-datadir =	@datadir@
-mandir =	@mandir@
-man1dir =	$(mandir)/man1
-man2dir =	$(mandir)/man2
-man3dir =	$(mandir)/man3
-man4dir =	$(mandir)/man4
-man5dir =	$(mandir)/man5
-man6dir =	$(mandir)/man6
-man7dir =	$(mandir)/man7
-man8dir =	$(mandir)/man8
-man9dir =	$(mandir)/man9
-infodir =	@infodir@
-includedir =	@includedir@
-
-SHELL =		@SHELL@
-
-INSTALL =	@INSTALL@
-INSTALL_PROGRAM=@INSTALL_PROGRAM@
-INSTALL_DATA =	@INSTALL_DATA@
-
-AR =		@AR@
-AR_FLAGS =	qv
-CFLAGS =	-g
-MAKEINFO =	makeinfo
-RANLIB =	@RANLIB@
-RM =		rm
-
-# where to find makeinfo
-MAKEINFO=makeinfo
-
-SET_TEXINPUTS = TEXINPUTS=${TEXIDIR}:.:$(srcdir):$(READLINE_DIR):$$TEXINPUTS
-
-# Files which should be generated via 'info' and installed by 'install-info'
-INFO_DEPS = mmalloc.info
-
-# The TeX formatter
-TEX = tex
-
-TARGETLIB =	libmmalloc.a
-
-CFILES =	mcalloc.c mfree.c mmalloc.c mmcheck.c mmemalign.c mmstats.c \
-		mmtrace.c mrealloc.c mvalloc.c mmap-sup.c attach.c detach.c \
-		keys.c sbrk-sup.c mm.c
-
-HFILES =	mmalloc.h
-
-OFILES =	mcalloc.o mfree.o mmalloc.o mmcheck.o mmemalign.o mmstats.o \
-		mmtrace.o mrealloc.o mvalloc.o mmap-sup.o attach.o detach.o \
-		keys.o sbrk-sup.o
-
-DEFS =		@DEFS@
-
-# The current default is to build a single object module with all the mmalloc
-# functions.  To build a more traditional library, flip this macro definition.
-#TARGETOBJS =	$(OFILES)
-TARGETOBJS =	mm.o
-
-.c.o:
-		$(CC) -c $(CFLAGS) $(DEFS) -I. -I$(srcdir)/../include $<
-
-# Do we want/need any config overrides?
-#	 
-
-STAGESTUFF =	$(TARGETLIB) *.o
-
-all:		$(TARGETLIB)
-
-info: $(INFO_DEPS)
-dvi: mmalloc.dvi
-clean-info:
-installcheck:
-
-mmalloc.info: mmalloc.texi
-	$(MAKEINFO) -I $(srcdir) -o ./mmalloc.info mmalloc.texi
-
-# This file doesn't need texindex currently.
-mmalloc.dvi: mmalloc.texi
-	$(SET_TEXINPUTS) $(TEX) mmalloc.texi
-	rm -f mmalloc.?? mmalloc.??s mmalloc.log mmalloc.aux mmalloc.toc
-
-install-info: info
-	$(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(infodir)
-	@list='$(INFO_DEPS)'; \
-	for file in $$list; do \
-	  if test -f $$file; then d=.; else d=$(srcdir); fi; \
-	  for ifile in `cd $$d && echo $$file $$file-[0-9] $$file-[0-9][0-9]`; do \
-	    if test -f $$d/$$ifile; then \
-	      echo " $(INSTALL_DATA) $$d/$$ifile $(DESTDIR)$(infodir)/$$ifile"; \
-	      $(INSTALL_DATA) $$d/$$ifile $(DESTDIR)$(infodir)/$$ifile; \
-	    else : ; fi; \
-	  done; \
-	done
-	$(POST_INSTALL)
-	@if $(SHELL) -c 'install-info --version | sed 1q | fgrep -s -v -i debian' >/dev/null 2>&1; then \
-	  list='$(INFO_DEPS)'; \
-	  for file in $$list; do \
-	    echo " install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$file";\
-	    install-info --info-dir=$(DESTDIR)$(infodir) $(DESTDIR)$(infodir)/$$file || :;\
-	  done; \
-	else : ; fi
-
-uninstall-info:
-	$(PRE_UNINSTALL)
-	@if $(SHELL) -c 'install-info --version | sed 1q | fgrep -s -v -i debian' >/dev/null 2>&1; then \
-	  ii=yes; \
-	else ii=; fi; \
-	list='$(INFO_DEPS)'; \
-	for file in $$list; do \
-	  test -z "$$ii" \
-	    || install-info --info-dir=$(DESTDIR)$(infodir) --remove $$file; \
-	done
-	$(NORMAL_UNINSTALL)
-	list='$(INFO_DEPS)'; \
-	for file in $$list; do \
-	  (cd $(DESTDIR)$(infodir) && rm -f $$file $$file-[0-9] $$file-[0-9][0-9]); \
-	done
-
-check: test1.c
-#	$(CC) -g $(srcdir)/test1.c libmmalloc.a
-# This loses for Canadian cross (building mmalloc with a cross-compiler).
-# There is probably some dejagnu-ish solution (such as what we are doing
-# for gdb, perhaps).
-#	./a.out
-
-install:	all install-info
-		$(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(libdir)
-		$(INSTALL_DATA) $(TARGETLIB) $(DESTDIR)$(libdir)/$(TARGETLIB)n
-		$(RANLIB) $(DESTDIR)$(libdir)/$(TARGETLIB)n
-		mv -f $(DESTDIR)$(libdir)/$(TARGETLIB)n $(DESTDIR)$(libdir)/$(TARGETLIB)
-
-uninstall:	uninstall-info
-
-$(TARGETLIB):	$(TARGETOBJS)
-		$(RM) -rf $@
-		$(AR) $(AR_FLAGS) $@ $(TARGETOBJS)
-		$(RANLIB) $@
-
-$(OFILES) :	$(HFILES) Makefile
-
-mm.o:		$(HFILES) $(CFILES)
-		$(CC) -c $(CFLAGS) $(DEFS) -I. -I$(srcdir)/../include $(srcdir)/mm.c
-
-.always.:
-# Do nothing.
-
-.PHONEY: all etags tags ls clean stage1 stage2 .always.
-
-stage1:		force
-		-mkdir stage1
-		-mv -f $(STAGESTUFF) stage1
-
-stage2:		force
-		-mkdir stage2
-		-mv -f $(STAGESTUFF) stage2
-
-stage3:		force
-		-mkdir stage3
-		-mv -f $(STAGESTUFF) stage3
-
-stage4:		force
-		-mkdir stage4
-		-mv -f $(STAGESTUFF) stage4
-
-against=stage2
-
-comparison:	force
-		for i in *.o ; do cmp $$i $(against)/$$i || exit 1 ; done
-
-de-stage1:	force
-		-(cd stage1 ; mv -f * ..)
-		-rmdir stage1
-
-de-stage2:	force
-		-(cd stage2 ; mv -f * ..)
-		-rmdir stage2
-
-de-stage3:	force
-		-(cd stage3 ; mv -f * ..)
-		-rmdir stage3
-
-de-stage4:	force
-		-(cd stage4 ; mv -f * ..)
-		-rmdir stage4
-
-etags tags:	TAGS
-
-TAGS:		$(CFILES)
-	etags `for i in $(HFILES) $(CFILES); do echo $(srcdir)/$$i ; done`
-
-ls:
-		@echo Makefile $(HFILES) $(CFILES)
-
-# Need to deal with profiled libraries, too.
-
-mostlyclean clean:
-		rm -f *.a *.o core errs *~ \#* TAGS *.E a.out errors 
-
-distclean:	clean 
-		rm -f config.cache config.log config.status
-		rm -f Makefile depend
-
-maintainer-clean realclean: distclean clean
-		@echo "This command is intended for maintainers to use;"
-		@echo "it deletes files that may require special tools to rebuild."
-		rm -f mmalloc.info
-
-force:
-
-Makefile:	Makefile.in config.status
-		$(SHELL) config.status
-
-config.status:	configure
-		$(SHELL) config.status --recheck
diff --git a/mmalloc/TODO b/mmalloc/TODO
deleted file mode 100644
index 94120439a7c..00000000000
--- a/mmalloc/TODO
+++ /dev/null
@@ -1,17 +0,0 @@
-Things that still need attention:
-
-   *	Make implementation changes necessary to allow multiple processes
-	to use the mmalloc managed region simultaneously.  This requires,
-	at the minimum, some sort of cooperative locking that ensures that
-	only one process at a time is changing any of the mmalloc managed
-	data structures (its ok for the mmalloc managed data regions to be
-	changed at any time since we don't care about their contents).
-
-   *	In order to support multiple processes using the mmalloc managed
-	region, the malloc descriptor needs to be broken into two parts,
-	one part which is specific to the given process and is maintained
-	separately on a per process basis, and another part which is common
-	to all processes.  As an example, the file descriptor is specific
-	to a given process, as are the morecore and abortfunc pointers.
-	However magic[], the version number, the flags field, etc are
-	common to all processes.
diff --git a/mmalloc/acinclude.m4 b/mmalloc/acinclude.m4
deleted file mode 100644
index 71b09b9f6ac..00000000000
--- a/mmalloc/acinclude.m4
+++ /dev/null
@@ -1 +0,0 @@
-sinclude(../bfd/acinclude.m4)
diff --git a/mmalloc/aclocal.m4 b/mmalloc/aclocal.m4
deleted file mode 100644
index 7cf2a1e51d6..00000000000
--- a/mmalloc/aclocal.m4
+++ /dev/null
@@ -1,14 +0,0 @@
-dnl aclocal.m4 generated automatically by aclocal 1.4
-
-dnl Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.
-dnl This file is free software; the Free Software Foundation
-dnl gives unlimited permission to copy and/or distribute it,
-dnl with or without modifications, as long as this notice is preserved.
-
-dnl This program is distributed in the hope that it will be useful,
-dnl but WITHOUT ANY WARRANTY, to the extent permitted by law; without
-dnl even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-dnl PARTICULAR PURPOSE.
-
-sinclude(../bfd/acinclude.m4)
-
diff --git a/mmalloc/attach.c b/mmalloc/attach.c
deleted file mode 100644
index 2bd70bfdf05..00000000000
--- a/mmalloc/attach.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Initialization for access to a mmap'd malloc managed region.
-   Copyright 1992, 2000 Free Software Foundation, Inc.
-
-   Contributed by Fred Fish at Cygnus Support.   fnf@cygnus.com
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sys/types.h>
-#include <fcntl.h> /* After sys/types.h, at least for dpx/2.  */
-#include <sys/stat.h>
-#include <string.h>
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>	/* Prototypes for lseek */
-#endif
-#include "mmprivate.h"
-
-#ifndef SEEK_SET
-#define SEEK_SET 0
-#endif
-
-
-#if defined(HAVE_MMAP)
-
-/* Forward declarations/prototypes for local functions */
-
-static struct mdesc *reuse PARAMS ((int));
-
-/* Initialize access to a mmalloc managed region.
-
-   If FD is a valid file descriptor for an open file then data for the
-   mmalloc managed region is mapped to that file, otherwise "/dev/zero"
-   is used and the data will not exist in any filesystem object.
-
-   If the open file corresponding to FD is from a previous use of
-   mmalloc and passes some basic sanity checks to ensure that it is
-   compatible with the current mmalloc package, then it's data is
-   mapped in and is immediately accessible at the same addresses in
-   the current process as the process that created the file.
-
-   If BASEADDR is not NULL, the mapping is established starting at the
-   specified address in the process address space.  If BASEADDR is NULL,
-   the mmalloc package chooses a suitable address at which to start the
-   mapped region, which will be the value of the previous mapping if
-   opening an existing file which was previously built by mmalloc, or
-   for new files will be a value chosen by mmap.
-
-   Specifying BASEADDR provides more control over where the regions
-   start and how big they can be before bumping into existing mapped
-   regions or future mapped regions.
-
-   On success, returns a "malloc descriptor" which is used in subsequent
-   calls to other mmalloc package functions.  It is explicitly "void *"
-   ("char *" for systems that don't fully support void) so that users
-   of the package don't have to worry about the actual implementation
-   details.
-
-   On failure returns NULL. */
-
-PTR
-mmalloc_attach (fd, baseaddr)
-  int fd;
-  PTR baseaddr;
-{
-  struct mdesc mtemp;
-  struct mdesc *mdp;
-  PTR mbase;
-  struct stat sbuf;
-
-  /* First check to see if FD is a valid file descriptor, and if so, see
-     if the file has any current contents (size > 0).  If it does, then
-     attempt to reuse the file.  If we can't reuse the file, either
-     because it isn't a valid mmalloc produced file, was produced by an
-     obsolete version, or any other reason, then we fail to attach to
-     this file. */
-
-  if (fd >= 0)
-    {
-      if (fstat (fd, &sbuf) < 0)
-	{
-	  return (NULL);
-	}
-      else if (sbuf.st_size > 0)
-	{
-	  return ((PTR) reuse (fd));
-	}
-    }
-
-  /* We start off with the malloc descriptor allocated on the stack, until
-     we build it up enough to call _mmalloc_mmap_morecore() to allocate the
-     first page of the region and copy it there.  Ensure that it is zero'd and
-     then initialize the fields that we know values for. */
-
-  mdp = &mtemp;
-  memset ((char *) mdp, 0, sizeof (mtemp));
-  strncpy (mdp -> magic, MMALLOC_MAGIC, MMALLOC_MAGIC_SIZE);
-  mdp -> headersize = sizeof (mtemp);
-  mdp -> version = MMALLOC_VERSION;
-  mdp -> morecore = __mmalloc_mmap_morecore;
-  mdp -> fd = fd;
-  mdp -> base = mdp -> breakval = mdp -> top = baseaddr;
-
-  /* If we have not been passed a valid open file descriptor for the file
-     to map to, then open /dev/zero and use that to map to. */
-
-  if (mdp -> fd < 0)
-    {
-      if ((mdp -> fd = open ("/dev/zero", O_RDWR)) < 0)
-	{
-	  return (NULL);
-	}
-      else
-	{
-	  mdp -> flags |= MMALLOC_DEVZERO;
-	}
-    }
-
-  /*  Now try to map in the first page, copy the malloc descriptor structure
-      there, and arrange to return a pointer to this new copy.  If the mapping
-      fails, then close the file descriptor if it was opened by us, and arrange
-      to return a NULL. */
-
-  if ((mbase = mdp -> morecore (mdp, sizeof (mtemp))) != NULL)
-    {
-      memcpy (mbase, mdp, sizeof (mtemp));
-      mdp = (struct mdesc *) mbase;
-    }
-  else
-    {
-      if (mdp -> flags & MMALLOC_DEVZERO)
-	{
-	  close (mdp -> fd);
-	}
-      mdp = NULL;
-    }
-
-  return ((PTR) mdp);
-}
-
-/* Given an valid file descriptor on an open file, test to see if that file
-   is a valid mmalloc produced file, and if so, attempt to remap it into the
-   current process at the same address to which it was previously mapped.
-
-   Note that we have to update the file descriptor number in the malloc-
-   descriptor read from the file to match the current valid one, before
-   trying to map the file in, and again after a successful mapping and
-   after we've switched over to using the mapped in malloc descriptor 
-   rather than the temporary one on the stack.
-
-   Once we've switched over to using the mapped in malloc descriptor, we
-   have to update the pointer to the morecore function, since it almost
-   certainly will be at a different address if the process reusing the
-   mapped region is from a different executable.
-
-   Also note that if the heap being remapped previously used the mmcheckf()
-   routines, we need to update the hooks since their target functions
-   will have certainly moved if the executable has changed in any way.
-   We do this by calling mmcheckf() internally.
-
-   Returns a pointer to the malloc descriptor if successful, or NULL if
-   unsuccessful for some reason. */
-
-static struct mdesc *
-reuse (fd)
-  int fd;
-{
-  struct mdesc mtemp;
-  struct mdesc *mdp = NULL;
-
-  if ((lseek (fd, 0L, SEEK_SET) == 0) &&
-      (read (fd, (char *) &mtemp, sizeof (mtemp)) == sizeof (mtemp)) &&
-      (mtemp.headersize == sizeof (mtemp)) &&
-      (strcmp (mtemp.magic, MMALLOC_MAGIC) == 0) &&
-      (mtemp.version <= MMALLOC_VERSION))
-    {
-      mtemp.fd = fd;
-      if (__mmalloc_remap_core (&mtemp) == mtemp.base)
-	{
-	  mdp = (struct mdesc *) mtemp.base;
-	  mdp -> fd = fd;
-	  mdp -> morecore = __mmalloc_mmap_morecore;
-	  if (mdp -> mfree_hook != NULL)
-	    {
-	      mmcheckf ((PTR) mdp, (void (*) PARAMS ((void))) NULL, 1);
-	    }
-	}
-    }
-  return (mdp);
-}
-
-#else	/* !defined (HAVE_MMAP) */
-
-/* For systems without mmap, the library still supplies an entry point
-   to link to, but trying to initialize access to an mmap'd managed region
-   always fails. */
-
-/* ARGSUSED */
-PTR
-mmalloc_attach (fd, baseaddr)
-  int fd;
-  PTR baseaddr;
-{
-   return (NULL);
-}
-
-#endif	/* defined (HAVE_MMAP) */
-
diff --git a/mmalloc/configure b/mmalloc/configure
deleted file mode 100755
index 8420dfada29..00000000000
--- a/mmalloc/configure
+++ /dev/null
@@ -1,1747 +0,0 @@
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-running configure, to aid debugging if configure makes a mistake.
-" 1>&5
-
-# Strip out --no-create and --no-recursion so they do not pile up.
-# Also quote any args containing shell metacharacters.
-ac_configure_args=
-for ac_arg
-do
-  case "$ac_arg" in
-  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
-  | --no-cr | --no-c) ;;
-  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
-  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
-  *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
-  ac_configure_args="$ac_configure_args '$ac_arg'" ;;
-  *) ac_configure_args="$ac_configure_args $ac_arg" ;;
-  esac
-done
-
-# NLS nuisances.
-# Only set these to C if already set.  These must not be set unconditionally
-# because not all systems understand e.g. LANG=C (notably SCO).
-# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
-# Non-C LC_CTYPE values break the ctype check.
-if test "${LANG+set}"   = set; then LANG=C;   export LANG;   fi
-if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
-if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
-if test "${LC_CTYPE+set}"    = set; then LC_CTYPE=C;    export LC_CTYPE;    fi
-
-# confdefs.h avoids OS command line length limits that DEFS can exceed.
-rm -rf conftest* confdefs.h
-# AIX cpp loses on an empty file, so make sure it contains at least a newline.
-echo > confdefs.h
-
-# A filename unique to this package, relative to the directory that
-# configure is in, which we can look for to find out if srcdir is correct.
-ac_unique_file=mmalloc.c
-
-# Find the source files, if location was not specified.
-if test -z "$srcdir"; then
-  ac_srcdir_defaulted=yes
-  # Try the directory containing this script, then its parent.
-  ac_prog=$0
-  ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
-  test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
-  srcdir=$ac_confdir
-  if test ! -r $srcdir/$ac_unique_file; then
-    srcdir=..
-  fi
-else
-  ac_srcdir_defaulted=no
-fi
-if test ! -r $srcdir/$ac_unique_file; then
-  if test "$ac_srcdir_defaulted" = yes; then
-    { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
-  else
-    { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
-  fi
-fi
-srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
-
-# Prefer explicitly selected file to automatically selected ones.
-if test -z "$sitefile"; then
-  if test -z "$CONFIG_SITE"; then
-    if test "x$prefix" != xNONE; then
-      CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
-    else
-      CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
-    fi
-  fi
-else
-  CONFIG_SITE="$sitefile"
-fi
-for ac_site_file in $CONFIG_SITE; do
-  if test -r "$ac_site_file"; then
-    echo "loading site script $ac_site_file"
-    . "$ac_site_file"
-  fi
-done
-
-if test -r "$cache_file"; then
-  echo "loading cache $cache_file"
-  . $cache_file
-else
-  echo "creating cache $cache_file"
-  > $cache_file
-fi
-
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-ac_exeext=
-ac_objext=o
-if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
-  # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
-  if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
-    ac_n= ac_c='
-' ac_t='	'
-  else
-    ac_n=-n ac_c= ac_t=
-  fi
-else
-  ac_n= ac_c='\c' ac_t=
-fi
-
-
-
-# Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:540: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="gcc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:570: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_prog_rejected=no
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
-        ac_prog_rejected=yes
-	continue
-      fi
-      ac_cv_prog_CC="cc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# -gt 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    set dummy "$ac_dir/$ac_word" "$@"
-    shift
-    ac_cv_prog_CC="$@"
-  fi
-fi
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-  if test -z "$CC"; then
-    case "`uname -s`" in
-    *win32* | *WIN32*)
-      # Extract the first word of "cl", so it can be a program name with args.
-set dummy cl; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:621: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="cl"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
- ;;
-    esac
-  fi
-  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
-fi
-
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:653: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
-
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-cat > conftest.$ac_ext << EOF
-
-#line 664 "configure"
-#include "confdefs.h"
-
-main(){return(0);}
-EOF
-if { (eval echo configure:669: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  ac_cv_prog_cc_works=yes
-  # If we can't run a trivial program, we are probably using a cross compiler.
-  if (./conftest; exit) 2>/dev/null; then
-    ac_cv_prog_cc_cross=no
-  else
-    ac_cv_prog_cc_cross=yes
-  fi
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  ac_cv_prog_cc_works=no
-fi
-rm -fr conftest*
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
-if test $ac_cv_prog_cc_works = no; then
-  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
-fi
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:695: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
-echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
-cross_compiling=$ac_cv_prog_cc_cross
-
-echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:700: checking whether we are using GNU C" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.c <<EOF
-#ifdef __GNUC__
-  yes;
-#endif
-EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:709: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
-  ac_cv_prog_gcc=yes
-else
-  ac_cv_prog_gcc=no
-fi
-fi
-
-echo "$ac_t""$ac_cv_prog_gcc" 1>&6
-
-if test $ac_cv_prog_gcc = yes; then
-  GCC=yes
-else
-  GCC=
-fi
-
-ac_test_CFLAGS="${CFLAGS+set}"
-ac_save_CFLAGS="$CFLAGS"
-CFLAGS=
-echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:728: checking whether ${CC-cc} accepts -g" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  echo 'void f(){}' > conftest.c
-if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
-  ac_cv_prog_cc_g=yes
-else
-  ac_cv_prog_cc_g=no
-fi
-rm -f conftest*
-
-fi
-
-echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS="$ac_save_CFLAGS"
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-
-ac_aux_dir=
-for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { echo "configure: error: can not find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." 1>&2; exit 1; }
-fi
-ac_config_guess=$ac_aux_dir/config.guess
-ac_config_sub=$ac_aux_dir/config.sub
-ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
-
-# Find a good install program.  We prefer a C program (faster),
-# so one script is as good as another.  But avoid the broken or
-# incompatible versions:
-# SysV /etc/install, /usr/sbin/install
-# SunOS /usr/etc/install
-# IRIX /sbin/install
-# AIX /bin/install
-# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
-# AFS /usr/afsws/bin/install, which mishandles nonexistent args
-# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
-# ./install, which can be erroneously created by make from ./install.sh.
-echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:790: checking for a BSD compatible install" >&5
-if test -z "$INSTALL"; then
-if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-    IFS="${IFS= 	}"; ac_save_IFS="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    # Account for people who put trailing slashes in PATH elements.
-    case "$ac_dir/" in
-    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
-    *)
-      # OSF1 and SCO ODT 3.0 have their own names for install.
-      # Don't use installbsd from OSF since it installs stuff as root
-      # by default.
-      for ac_prog in ginstall scoinst install; do
-        if test -f $ac_dir/$ac_prog; then
-	  if test $ac_prog = install &&
-            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
-	    # AIX install.  It has an incompatible calling convention.
-	    :
-	  else
-	    ac_cv_path_install="$ac_dir/$ac_prog -c"
-	    break 2
-	  fi
-	fi
-      done
-      ;;
-    esac
-  done
-  IFS="$ac_save_IFS"
-
-fi
-  if test "${ac_cv_path_install+set}" = set; then
-    INSTALL="$ac_cv_path_install"
-  else
-    # As a last resort, use the slow shell script.  We don't cache a
-    # path for INSTALL within a source directory, because that will
-    # break other packages using the cache if that directory is
-    # removed, or if the path is relative.
-    INSTALL="$ac_install_sh"
-  fi
-fi
-echo "$ac_t""$INSTALL" 1>&6
-
-# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
-# It thinks the first close brace ends the variable substitution.
-test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
-
-test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
-
-test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
-
-
-# Make sure we can run config.sub.
-if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
-else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
-fi
-
-echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:849: checking host system type" >&5
-
-host_alias=$host
-case "$host_alias" in
-NONE)
-  case $nonopt in
-  NONE)
-    if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
-    else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
-    fi ;;
-  *) host_alias=$nonopt ;;
-  esac ;;
-esac
-
-host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
-host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-echo "$ac_t""$host" 1>&6
-
-echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:870: checking build system type" >&5
-
-build_alias=$build
-case "$build_alias" in
-NONE)
-  case $nonopt in
-  NONE) build_alias=$host_alias ;;
-  *) build_alias=$nonopt ;;
-  esac ;;
-esac
-
-build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
-build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-echo "$ac_t""$build" 1>&6
-
-if test $host != $build; then
-  ac_tool_prefix=${host_alias}-
-else
-  ac_tool_prefix=
-fi
-
-# Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ar; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:896: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$AR"; then
-  ac_cv_prog_AR="$AR" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_AR="${ac_tool_prefix}ar"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_prog_AR" && ac_cv_prog_AR="ar"
-fi
-fi
-AR="$ac_cv_prog_AR"
-if test -n "$AR"; then
-  echo "$ac_t""$AR" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-
-# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:928: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-RANLIB="$ac_cv_prog_RANLIB"
-if test -n "$RANLIB"; then
-  echo "$ac_t""$RANLIB" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-if test -z "$ac_cv_prog_RANLIB"; then
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:960: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_RANLIB="ranlib"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
-fi
-fi
-RANLIB="$ac_cv_prog_RANLIB"
-if test -n "$RANLIB"; then
-  echo "$ac_t""$RANLIB" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-else
-  RANLIB=":"
-fi
-fi
-
-
-echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
-echo "configure:994: checking how to run the C preprocessor" >&5
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-    # This must be in double quotes, not single quotes, because CPP may get
-  # substituted into the Makefile and "${CC-cc}" will confuse make.
-  CPP="${CC-cc} -E"
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp.
-  cat > conftest.$ac_ext <<EOF
-#line 1009 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1015: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP="${CC-cc} -E -traditional-cpp"
-  cat > conftest.$ac_ext <<EOF
-#line 1026 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1032: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP="${CC-cc} -nologo -E"
-  cat > conftest.$ac_ext <<EOF
-#line 1043 "configure"
-#include "confdefs.h"
-#include <assert.h>
-Syntax Error
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1049: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  :
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CPP=/lib/cpp
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-fi
-rm -f conftest*
-  ac_cv_prog_CPP="$CPP"
-fi
-  CPP="$ac_cv_prog_CPP"
-else
-  ac_cv_prog_CPP="$CPP"
-fi
-echo "$ac_t""$CPP" 1>&6
-
-for ac_hdr in unistd.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:1077: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1082 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1087: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_func in getpagesize
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1116: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1121 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1144: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:1169: checking for working mmap" >&5
-if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1177 "configure"
-#include "confdefs.h"
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the filesystem buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propogated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-#include <sys/types.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#ifndef HAVE_GETPAGESIZE
-# ifdef HAVE_UNISTD_H
-#  include <unistd.h>
-# endif
-
-/* Assume that all systems that can run configure have sys/param.h.  */
-# ifndef HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  ifdef HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-#ifdef __cplusplus
-extern "C" { void *malloc(unsigned); }
-#else
-char *malloc();
-#endif
-
-int
-main()
-{
-	char *data, *data2, *data3;
-	int i, pagesize;
-	int fd;
-
-	pagesize = getpagesize();
-
-	/*
-	 * First, make a file with some known garbage in it.
-	 */
-	data = malloc(pagesize);
-	if (!data)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		*(data + i) = rand();
-	umask(0);
-	fd = creat("conftestmmap", 0600);
-	if (fd < 0)
-		exit(1);
-	if (write(fd, data, pagesize) != pagesize)
-		exit(1);
-	close(fd);
-
-	/*
-	 * Next, try to mmap the file at a fixed address which
-	 * already has something else allocated at it.  If we can,
-	 * also make sure that we see the same garbage.
-	 */
-	fd = open("conftestmmap", O_RDWR);
-	if (fd < 0)
-		exit(1);
-	data2 = malloc(2 * pagesize);
-	if (!data2)
-		exit(1);
-	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
-	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
-	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data2 + i))
-			exit(1);
-
-	/*
-	 * Finally, make sure that changes to the mapped area
-	 * do not percolate back to the file as seen by read().
-	 * (This is a bug on some variants of i386 svr4.0.)
-	 */
-	for (i = 0; i < pagesize; ++i)
-		*(data2 + i) = *(data2 + i) + 1;
-	data3 = malloc(pagesize);
-	if (!data3)
-		exit(1);
-	if (read(fd, data3, pagesize) != pagesize)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data3 + i))
-			exit(1);
-	close(fd);
-	unlink("conftestmmap");
-	exit(0);
-}
-
-EOF
-if { (eval echo configure:1317: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_MMAP 1
-EOF
-
-fi
-
-for ac_hdr in limits.h stddef.h unistd.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:1343: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1348 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1353: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-
-echo $ac_n "checking whether sbrk must be declared""... $ac_c" 1>&6
-echo "configure:1381: checking whether sbrk must be declared" >&5
-if eval "test \"`echo '$''{'bfd_cv_decl_needed_sbrk'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1386 "configure"
-#include "confdefs.h"
-
-#include <stdio.h>
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-int main() {
-char *(*pfn) = (char *(*)) sbrk
-; return 0; }
-EOF
-if { (eval echo configure:1407: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  bfd_cv_decl_needed_sbrk=no
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  bfd_cv_decl_needed_sbrk=yes
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$bfd_cv_decl_needed_sbrk" 1>&6
-if test $bfd_cv_decl_needed_sbrk = yes; then
-  cat >> confdefs.h <<\EOF
-#define NEED_DECLARATION_SBRK 1
-EOF
-
-fi
-
-echo $ac_n "checking whether getpagesize must be declared""... $ac_c" 1>&6
-echo "configure:1428: checking whether getpagesize must be declared" >&5
-if eval "test \"`echo '$''{'bfd_cv_decl_needed_getpagesize'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1433 "configure"
-#include "confdefs.h"
-
-#include <stdio.h>
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-int main() {
-char *(*pfn) = (char *(*)) getpagesize
-; return 0; }
-EOF
-if { (eval echo configure:1454: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  bfd_cv_decl_needed_getpagesize=no
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  bfd_cv_decl_needed_getpagesize=yes
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$bfd_cv_decl_needed_getpagesize" 1>&6
-if test $bfd_cv_decl_needed_getpagesize = yes; then
-  cat >> confdefs.h <<\EOF
-#define NEED_DECLARATION_GETPAGESIZE 1
-EOF
-
-fi
-
-
-trap '' 1 2 15
-cat > confcache <<\EOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs.  It is not useful on other systems.
-# If it contains results you don't want to keep, you may remove or edit it.
-#
-# By default, configure uses ./config.cache as the cache file,
-# creating it if it does not exist already.  You can give configure
-# the --cache-file=FILE option to use a different cache file; that is
-# what configure does when it calls configure scripts in
-# subdirectories, so they share the cache.
-# Giving --cache-file=/dev/null disables caching, for debugging configure.
-# config.status only pays attention to the cache file if you give it the
-# --recheck option to rerun configure.
-#
-EOF
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-(set) 2>&1 |
-  case `(ac_space=' '; set | grep ac_space) 2>&1` in
-  *ac_space=\ *)
-    # `set' does not quote correctly, so add quotes (double-quote substitution
-    # turns \\\\ into \\, and sed turns \\ into \).
-    sed -n \
-      -e "s/'/'\\\\''/g" \
-      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
-    ;;
-  *)
-    # `set' quotes correctly as required by POSIX, so do not add quotes.
-    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
-    ;;
-  esac >> confcache
-if cmp -s $cache_file confcache; then
-  :
-else
-  if test -w $cache_file; then
-    echo "updating cache $cache_file"
-    cat confcache > $cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# Any assignment to VPATH causes Sun make to only execute
-# the first set of double-colon rules, so remove it if not needed.
-# If there is a colon in the path, we need to keep it.
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
-fi
-
-trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
-
-# Transform confdefs.h into DEFS.
-# Protect against shell expansion while executing Makefile rules.
-# Protect against Makefile macro expansion.
-cat > conftest.defs <<\EOF
-s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g
-s%[ 	`~#$^&*(){}\\|;'"<>?]%\\&%g
-s%\[%\\&%g
-s%\]%\\&%g
-s%\$%$$%g
-EOF
-DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '`
-rm -f conftest.defs
-
-
-# Without the "./", some shells look in PATH for config.status.
-: ${CONFIG_STATUS=./config.status}
-
-echo creating $CONFIG_STATUS
-rm -f $CONFIG_STATUS
-cat > $CONFIG_STATUS <<EOF
-#! /bin/sh
-# Generated automatically by configure.
-# Run this file to recreate the current configuration.
-# This directory was configured as follows,
-# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
-#
-# $0 $ac_configure_args
-#
-# Compiler output produced by configure, useful for debugging
-# configure, is in ./config.log if it exists.
-
-ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
-for ac_option
-do
-  case "\$ac_option" in
-  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
-    echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
-    exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
-    echo "$CONFIG_STATUS generated by autoconf version 2.13"
-    exit 0 ;;
-  -help | --help | --hel | --he | --h)
-    echo "\$ac_cs_usage"; exit 0 ;;
-  *) echo "\$ac_cs_usage"; exit 1 ;;
-  esac
-done
-
-ac_given_srcdir=$srcdir
-ac_given_INSTALL="$INSTALL"
-
-trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-# Protect against being on the right side of a sed subst in config.status.
-sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
- s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
-$ac_vpsub
-$extrasub
-s%@SHELL@%$SHELL%g
-s%@CFLAGS@%$CFLAGS%g
-s%@CPPFLAGS@%$CPPFLAGS%g
-s%@CXXFLAGS@%$CXXFLAGS%g
-s%@FFLAGS@%$FFLAGS%g
-s%@DEFS@%$DEFS%g
-s%@LDFLAGS@%$LDFLAGS%g
-s%@LIBS@%$LIBS%g
-s%@exec_prefix@%$exec_prefix%g
-s%@prefix@%$prefix%g
-s%@program_transform_name@%$program_transform_name%g
-s%@bindir@%$bindir%g
-s%@sbindir@%$sbindir%g
-s%@libexecdir@%$libexecdir%g
-s%@datadir@%$datadir%g
-s%@sysconfdir@%$sysconfdir%g
-s%@sharedstatedir@%$sharedstatedir%g
-s%@localstatedir@%$localstatedir%g
-s%@libdir@%$libdir%g
-s%@includedir@%$includedir%g
-s%@oldincludedir@%$oldincludedir%g
-s%@infodir@%$infodir%g
-s%@mandir@%$mandir%g
-s%@CC@%$CC%g
-s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
-s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
-s%@INSTALL_DATA@%$INSTALL_DATA%g
-s%@host@%$host%g
-s%@host_alias@%$host_alias%g
-s%@host_cpu@%$host_cpu%g
-s%@host_vendor@%$host_vendor%g
-s%@host_os@%$host_os%g
-s%@build@%$build%g
-s%@build_alias@%$build_alias%g
-s%@build_cpu@%$build_cpu%g
-s%@build_vendor@%$build_vendor%g
-s%@build_os@%$build_os%g
-s%@AR@%$AR%g
-s%@RANLIB@%$RANLIB%g
-s%@CPP@%$CPP%g
-
-CEOF
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-
-# Split the substitutions into bite-sized pieces for seds with
-# small command number limits, like on Digital OSF/1 and HP-UX.
-ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
-ac_file=1 # Number of current file.
-ac_beg=1 # First line for current file.
-ac_end=$ac_max_sed_cmds # Line after last line for current file.
-ac_more_lines=:
-ac_sed_cmds=""
-while $ac_more_lines; do
-  if test $ac_beg -gt 1; then
-    sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
-  else
-    sed "${ac_end}q" conftest.subs > conftest.s$ac_file
-  fi
-  if test ! -s conftest.s$ac_file; then
-    ac_more_lines=false
-    rm -f conftest.s$ac_file
-  else
-    if test -z "$ac_sed_cmds"; then
-      ac_sed_cmds="sed -f conftest.s$ac_file"
-    else
-      ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
-    fi
-    ac_file=`expr $ac_file + 1`
-    ac_beg=$ac_end
-    ac_end=`expr $ac_end + $ac_max_sed_cmds`
-  fi
-done
-if test -z "$ac_sed_cmds"; then
-  ac_sed_cmds=cat
-fi
-EOF
-
-cat >> $CONFIG_STATUS <<EOF
-
-CONFIG_FILES=\${CONFIG_FILES-"Makefile"}
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case "$ac_file" in
-  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
-  esac
-
-  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
-
-  # Remove last slash and all that follows it.  Not all systems have dirname.
-  ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
-  if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
-    # The file is in a subdirectory.
-    test ! -d "$ac_dir" && mkdir "$ac_dir"
-    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dir_suffix.
-    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
-  else
-    ac_dir_suffix= ac_dots=
-  fi
-
-  case "$ac_given_srcdir" in
-  .)  srcdir=.
-      if test -z "$ac_dots"; then top_srcdir=.
-      else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
-  /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
-  *) # Relative path.
-    srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
-    top_srcdir="$ac_dots$ac_given_srcdir" ;;
-  esac
-
-  case "$ac_given_INSTALL" in
-  [/$]*) INSTALL="$ac_given_INSTALL" ;;
-  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
-  esac
-
-  echo creating "$ac_file"
-  rm -f "$ac_file"
-  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
-  case "$ac_file" in
-  *Makefile*) ac_comsub="1i\\
-# $configure_input" ;;
-  *) ac_comsub= ;;
-  esac
-
-  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
-  sed -e "$ac_comsub
-s%@configure_input@%$configure_input%g
-s%@srcdir@%$srcdir%g
-s%@top_srcdir@%$top_srcdir%g
-s%@INSTALL@%$INSTALL%g
-" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
-fi; done
-rm -f conftest.s*
-
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-
-exit 0
-EOF
-chmod +x $CONFIG_STATUS
-rm -fr confdefs* $ac_clean_files
-test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
-
diff --git a/mmalloc/configure.in b/mmalloc/configure.in
deleted file mode 100644
index db7a4c29792..00000000000
--- a/mmalloc/configure.in
+++ /dev/null
@@ -1,35 +0,0 @@
-dnl Autoconf configure script for MMALLOC, the GNU mmemory allocator.
-dnl Copyright 2000 Free Software Foundation, Inc.
-dnl
-dnl This file is part of GDB.
-dnl 
-dnl This program is free software; you can redistribute it and/or modify
-dnl it under the terms of the GNU General Public License as published by
-dnl the Free Software Foundation; either version 2 of the License, or
-dnl (at your option) any later version.
-dnl 
-dnl This program is distributed in the hope that it will be useful,
-dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
-dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-dnl GNU General Public License for more details.
-dnl 
-dnl You should have received a copy of the GNU General Public License
-dnl along with this program; if not, write to the Free Software
-dnl Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-dnl Process this file with autoconf to produce a configure script.
-
-AC_PREREQ(2.12.1)dnl
-AC_INIT(mmalloc.c)
-
-AC_PROG_CC
-AC_PROG_INSTALL
-AC_CHECK_TOOL(AR, ar)
-AC_CHECK_TOOL(RANLIB, ranlib, :)
-
-AC_FUNC_MMAP
-AC_CHECK_HEADERS(limits.h stddef.h unistd.h)
-
-BFD_NEED_DECLARATION(sbrk)
-BFD_NEED_DECLARATION(getpagesize)
-
-AC_OUTPUT(Makefile)
diff --git a/mmalloc/detach.c b/mmalloc/detach.c
deleted file mode 100644
index 1780679417d..00000000000
--- a/mmalloc/detach.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Finish access to a mmap'd malloc managed region.
-   Copyright 1992 Free Software Foundation, Inc.
-
-   Contributed by Fred Fish at Cygnus Support.   fnf@cygnus.com
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sys/types.h>
-#include "mmprivate.h"
-
-/* Terminate access to a mmalloc managed region by unmapping all memory pages
-   associated with the region, and closing the file descriptor if it is one
-   that we opened.
-
-   Returns NULL on success.
-
-   Returns the malloc descriptor on failure, which can subsequently be used
-   for further action, such as obtaining more information about the nature of
-   the failure by examining the preserved errno value.
-
-   Note that the malloc descriptor that we are using is currently located in
-   region we are about to unmap, so we first make a local copy of it on the
-   stack and use the copy. */
-
-PTR
-mmalloc_detach (md)
-     PTR md;
-{
-  struct mdesc mtemp;
-
-  if (md != NULL)
-    {
-
-      mtemp = *(struct mdesc *) md;
-      
-      /* Now unmap all the pages associated with this region by asking for a
-	 negative increment equal to the current size of the region. */
-      
-      if ((mtemp.morecore (&mtemp, mtemp.base - mtemp.breakval)) == NULL)
-	{
-	  /* Deallocating failed.  Update the original malloc descriptor
-	     with any changes */
-	  *(struct mdesc *) md = mtemp;
-	}
-      else
-	{
-	  if (mtemp.flags & MMALLOC_DEVZERO)
-	    {
-	      close (mtemp.fd);
-	    }
-	  md = NULL;
-	}
-    }
-
-  return (md);
-}
diff --git a/mmalloc/keys.c b/mmalloc/keys.c
deleted file mode 100644
index 35f00d19ba3..00000000000
--- a/mmalloc/keys.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* Access for application keys in mmap'd malloc managed region.
-   Copyright 1992 Free Software Foundation, Inc.
-
-   Contributed by Fred Fish at Cygnus Support.   fnf@cygnus.com
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This module provides access to some keys that the application can use to
-   provide persistent access to locations in the mapped memory section.
-   The intent is that these keys are to be used sparingly as sort of
-   persistent global variables which the application can use to reinitialize
-   access to data in the mapped region.
-
-   For the moment, these keys are simply stored in the malloc descriptor
-   itself, in an array of fixed length.  This should be fixed so that there
-   can be an unlimited number of keys, possibly using a multilevel access
-   scheme of some sort. */
-
-#include "mmprivate.h"
-
-int
-mmalloc_setkey (md, keynum, key)
-  PTR md;     
-  int keynum;
-  PTR key;
-{
-  struct mdesc *mdp = (struct mdesc *) md;
-  int result = 0;
-
-  if ((mdp != NULL) && (keynum >= 0) && (keynum < MMALLOC_KEYS))
-    {
-      mdp -> keys [keynum] = key;
-      result++;
-    }
-  return (result);
-}
-
-PTR
-mmalloc_getkey (md, keynum)
-  PTR md;     
-  int keynum;
-{
-  struct mdesc *mdp = (struct mdesc *) md;
-  PTR keyval = NULL;
-
-  if ((mdp != NULL) && (keynum >= 0) && (keynum < MMALLOC_KEYS))
-    {
-      keyval = mdp -> keys [keynum];
-    }
-  return (keyval);
-}
diff --git a/mmalloc/mcalloc.c b/mmalloc/mcalloc.c
deleted file mode 100644
index c9fcc07e894..00000000000
--- a/mmalloc/mcalloc.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright (C) 1991, 1992 Free Software Foundation, Inc.
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sys/types.h>  /* GCC on HP/UX needs this before string.h. */
-#include <string.h>	/* Prototypes for memcpy, memmove, memset, etc */
-
-#include "mmprivate.h"
-
-/* Allocate an array of NMEMB elements each SIZE bytes long.
-   The entire array is initialized to zeros.  */
-
-PTR
-mcalloc (md, nmemb, size)
-  PTR md;
-  register size_t nmemb;
-  register size_t size;
-{
-  register PTR result;
-
-  if ((result = mmalloc (md, nmemb * size)) != NULL)
-    {
-      memset (result, 0, nmemb * size);
-    }
-  return (result);
-}
-
-/* When using this package, provide a version of malloc/realloc/free built
-   on top of it, so that if we use the default sbrk() region we will not
-   collide with another malloc package trying to do the same thing, if
-   the application contains any "hidden" calls to malloc/realloc/free (such
-   as inside a system library). */
-
-PTR
-calloc (nmemb, size)
-  size_t nmemb;
-  size_t size;
-{
-  return (mcalloc ((PTR) NULL, nmemb, size));
-}
diff --git a/mmalloc/mfree.c b/mmalloc/mfree.c
deleted file mode 100644
index c509ac6e2a6..00000000000
--- a/mmalloc/mfree.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Free a block of memory allocated by `mmalloc'.
-   Copyright 1990, 1991, 1992 Free Software Foundation
-
-   Written May 1989 by Mike Haertel.
-   Heavily modified Mar 1992 by Fred Fish.  (fnf@cygnus.com)
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   The author may be reached (Email) at the address mike@ai.mit.edu,
-   or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-#include "mmprivate.h"
-
-/* Return memory to the heap.
-   Like `mfree' but don't call a mfree_hook if there is one.  */
-
-void
-__mmalloc_free (mdp, ptr)
-  struct mdesc *mdp;
-  PTR ptr;
-{
-  int type;
-  size_t block, blocks;
-  register size_t i;
-  struct list *prev, *next;
-
-  block = BLOCK (ptr);
-
-  type = mdp -> heapinfo[block].busy.type;
-  switch (type)
-    {
-    case 0:
-      /* Get as many statistics as early as we can.  */
-      mdp -> heapstats.chunks_used--;
-      mdp -> heapstats.bytes_used -=
-	  mdp -> heapinfo[block].busy.info.size * BLOCKSIZE;
-      mdp -> heapstats.bytes_free +=
-	  mdp -> heapinfo[block].busy.info.size * BLOCKSIZE;
-
-      /* Find the free cluster previous to this one in the free list.
-	 Start searching at the last block referenced; this may benefit
-	 programs with locality of allocation.  */
-      i = mdp -> heapindex;
-      if (i > block)
-	{
-	  while (i > block)
-	    {
-	      i = mdp -> heapinfo[i].free.prev;
-	    }
-	}
-      else
-	{
-	  do
-	    {
-	      i = mdp -> heapinfo[i].free.next;
-	    }
-	  while ((i != 0) && (i < block));
-	  i = mdp -> heapinfo[i].free.prev;
-	}
-
-      /* Determine how to link this block into the free list.  */
-      if (block == i + mdp -> heapinfo[i].free.size)
-	{
-	  /* Coalesce this block with its predecessor.  */
-	  mdp -> heapinfo[i].free.size +=
-	    mdp -> heapinfo[block].busy.info.size;
-	  block = i;
-	}
-      else
-	{
-	  /* Really link this block back into the free list.  */
-	  mdp -> heapinfo[block].free.size =
-	    mdp -> heapinfo[block].busy.info.size;
-	  mdp -> heapinfo[block].free.next = mdp -> heapinfo[i].free.next;
-	  mdp -> heapinfo[block].free.prev = i;
-	  mdp -> heapinfo[i].free.next = block;
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.prev = block;
-	  mdp -> heapstats.chunks_free++;
-	}
-
-      /* Now that the block is linked in, see if we can coalesce it
-	 with its successor (by deleting its successor from the list
-	 and adding in its size).  */
-      if (block + mdp -> heapinfo[block].free.size ==
-	  mdp -> heapinfo[block].free.next)
-	{
-	  mdp -> heapinfo[block].free.size
-	    += mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.size;
-	  mdp -> heapinfo[block].free.next
-	    = mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.next;
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.prev = block;
-	  mdp -> heapstats.chunks_free--;
-	}
-
-      /* Now see if we can return stuff to the system.  */
-      blocks = mdp -> heapinfo[block].free.size;
-      if (blocks >= FINAL_FREE_BLOCKS && block + blocks == mdp -> heaplimit
-	  && mdp -> morecore (mdp, 0) == ADDRESS (block + blocks))
-	{
-	  register size_t bytes = blocks * BLOCKSIZE;
-	  mdp -> heaplimit -= blocks;
-	  mdp -> morecore (mdp, -bytes);
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.prev].free.next
-	    = mdp -> heapinfo[block].free.next;
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.prev
-	    = mdp -> heapinfo[block].free.prev;
-	  block = mdp -> heapinfo[block].free.prev;
-	  mdp -> heapstats.chunks_free--;
-	  mdp -> heapstats.bytes_free -= bytes;
-	}
-
-      /* Set the next search to begin at this block.  */
-      mdp -> heapindex = block;
-      break;
-
-    default:
-      /* Do some of the statistics.  */
-      mdp -> heapstats.chunks_used--;
-      mdp -> heapstats.bytes_used -= 1 << type;
-      mdp -> heapstats.chunks_free++;
-      mdp -> heapstats.bytes_free += 1 << type;
-
-      /* Get the address of the first free fragment in this block.  */
-      prev = (struct list *)
-	((char *) ADDRESS(block) +
-	 (mdp -> heapinfo[block].busy.info.frag.first << type));
-
-      if (mdp -> heapinfo[block].busy.info.frag.nfree ==
-	  (BLOCKSIZE >> type) - 1)
-	{
-	  /* If all fragments of this block are free, remove them
-	     from the fragment list and free the whole block.  */
-	  next = prev;
-	  for (i = 1; i < (size_t) (BLOCKSIZE >> type); ++i)
-	    {
-	      next = next -> next;
-	    }
-	  prev -> prev -> next = next;
-	  if (next != NULL)
-	    {
-	      next -> prev = prev -> prev;
-	    }
-	  mdp -> heapinfo[block].busy.type = 0;
-	  mdp -> heapinfo[block].busy.info.size = 1;
-
-	  /* Keep the statistics accurate.  */
-	  mdp -> heapstats.chunks_used++;
-	  mdp -> heapstats.bytes_used += BLOCKSIZE;
-	  mdp -> heapstats.chunks_free -= BLOCKSIZE >> type;
-	  mdp -> heapstats.bytes_free -= BLOCKSIZE;
-
-	  mfree ((PTR) mdp, (PTR) ADDRESS(block));
-	}
-      else if (mdp -> heapinfo[block].busy.info.frag.nfree != 0)
-	{
-	  /* If some fragments of this block are free, link this
-	     fragment into the fragment list after the first free
-	     fragment of this block. */
-	  next = (struct list *) ptr;
-	  next -> next = prev -> next;
-	  next -> prev = prev;
-	  prev -> next = next;
-	  if (next -> next != NULL)
-	    {
-	      next -> next -> prev = next;
-	    }
-	  ++mdp -> heapinfo[block].busy.info.frag.nfree;
-	}
-      else
-	{
-	  /* No fragments of this block are free, so link this
-	     fragment into the fragment list and announce that
-	     it is the first free fragment of this block. */
-	  prev = (struct list *) ptr;
-	  mdp -> heapinfo[block].busy.info.frag.nfree = 1;
-	  mdp -> heapinfo[block].busy.info.frag.first =
-	    RESIDUAL (ptr, BLOCKSIZE) >> type;
-	  prev -> next = mdp -> fraghead[type].next;
-	  prev -> prev = &mdp -> fraghead[type];
-	  prev -> prev -> next = prev;
-	  if (prev -> next != NULL)
-	    {
-	      prev -> next -> prev = prev;
-	    }
-	}
-      break;
-    }
-}
-
-/* Return memory to the heap.  */
-
-void
-mfree (md, ptr)
-  PTR md;
-  PTR ptr;
-{
-  struct mdesc *mdp;
-  register struct alignlist *l;
-
-  if (ptr != NULL)
-    {
-      mdp = MD_TO_MDP (md);
-      for (l = mdp -> aligned_blocks; l != NULL; l = l -> next)
-	{
-	  if (l -> aligned == ptr)
-	    {
-	      l -> aligned = NULL;  /* Mark the slot in the list as free. */
-	      ptr = l -> exact;
-	      break;
-	    }
-	}      
-      if (mdp -> mfree_hook != NULL)
-	{
-	  (*mdp -> mfree_hook) (md, ptr);
-	}
-      else
-	{
-	  __mmalloc_free (mdp, ptr);
-	}
-    }
-}
-
-/* When using this package, provide a version of malloc/realloc/free built
-   on top of it, so that if we use the default sbrk() region we will not
-   collide with another malloc package trying to do the same thing, if
-   the application contains any "hidden" calls to malloc/realloc/free (such
-   as inside a system library). */
-
-void
-free (ptr)
-  PTR ptr;
-{
-  mfree ((PTR) NULL, ptr);
-}
diff --git a/mmalloc/mm.c b/mmalloc/mm.c
deleted file mode 100644
index d487e0cf518..00000000000
--- a/mmalloc/mm.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Build the entire mmalloc library as a single object module. This
-   avoids having clients pick up part of their allocation routines
-   from mmalloc and part from libc, which results in undefined
-   behavior.  It should also still be possible to build the library
-   as a standard library with multiple objects.
-
-   Copyright 1996, 2000 Free Software Foundation
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>	/* Prototypes for lseek, sbrk (maybe) */
-#endif
-#include "mcalloc.c"
-#include "mfree.c"
-#include "mmalloc.c"
-#include "mmcheck.c"
-#include "mmemalign.c"
-#include "mmstats.c"
-#include "mmtrace.c"
-#include "mrealloc.c"
-#include "mvalloc.c"
-#include "mmap-sup.c"
-#include "attach.c"
-#include "detach.c"
-#include "keys.c"
-#include "sbrk-sup.c"
diff --git a/mmalloc/mmalloc.c b/mmalloc/mmalloc.c
deleted file mode 100644
index 7c60fe2d57b..00000000000
--- a/mmalloc/mmalloc.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/* Memory allocator `malloc'.
-   Copyright 1990, 1991, 1992 Free Software Foundation
-
-   Written May 1989 by Mike Haertel.
-   Heavily modified Mar 1992 by Fred Fish for mmap'd version.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   The author may be reached (Email) at the address mike@ai.mit.edu,
-   or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-#include <string.h>	/* Prototypes for memcpy, memmove, memset, etc */
-
-#include "mmprivate.h"
-
-/* Prototypes for local functions */
-
-static int initialize PARAMS ((struct mdesc *));
-static PTR morecore PARAMS ((struct mdesc *, size_t));
-static PTR align PARAMS ((struct mdesc *, size_t));
-
-/* Aligned allocation.  */
-
-static PTR
-align (mdp, size)
-  struct mdesc *mdp;
-  size_t size;
-{
-  PTR result;
-  unsigned long int adj;
-
-  result = mdp -> morecore (mdp, size);
-  adj = RESIDUAL (result, BLOCKSIZE);
-  if (adj != 0)
-    {
-      adj = BLOCKSIZE - adj;
-      mdp -> morecore (mdp, adj);
-      result = (char *) result + adj;
-    }
-  return (result);
-}
-
-/* Set everything up and remember that we have.  */
-
-static int
-initialize (mdp)
-  struct mdesc *mdp;
-{
-  mdp -> heapsize = HEAP / BLOCKSIZE;
-  mdp -> heapinfo = (malloc_info *) 
-    align (mdp, mdp -> heapsize * sizeof (malloc_info));
-  if (mdp -> heapinfo == NULL)
-    {
-      return (0);
-    }
-  memset ((PTR)mdp -> heapinfo, 0, mdp -> heapsize * sizeof (malloc_info));
-  mdp -> heapinfo[0].free.size = 0;
-  mdp -> heapinfo[0].free.next = mdp -> heapinfo[0].free.prev = 0;
-  mdp -> heapindex = 0;
-  mdp -> heapbase = (char *) mdp -> heapinfo;
-  mdp -> flags |= MMALLOC_INITIALIZED;
-  return (1);
-}
-
-/* Get neatly aligned memory, initializing or
-   growing the heap info table as necessary. */
-
-static PTR
-morecore (mdp, size)
-  struct mdesc *mdp;
-  size_t size;
-{
-  PTR result;
-  malloc_info *newinfo, *oldinfo;
-  size_t newsize;
-
-  result = align (mdp, size);
-  if (result == NULL)
-    {
-      return (NULL);
-    }
-
-  /* Check if we need to grow the info table.  */
-  if ((size_t) BLOCK ((char *) result + size) > mdp -> heapsize)
-    {
-      newsize = mdp -> heapsize;
-      while ((size_t) BLOCK ((char *) result + size) > newsize)
-	{
-	  newsize *= 2;
-	}
-      newinfo = (malloc_info *) align (mdp, newsize * sizeof (malloc_info));
-      if (newinfo == NULL)
-	{
-	  mdp -> morecore (mdp, -size);
-	  return (NULL);
-	}
-      memset ((PTR) newinfo, 0, newsize * sizeof (malloc_info));
-      memcpy ((PTR) newinfo, (PTR) mdp -> heapinfo,
-	      mdp -> heapsize * sizeof (malloc_info));
-      oldinfo = mdp -> heapinfo;
-      newinfo[BLOCK (oldinfo)].busy.type = 0;
-      newinfo[BLOCK (oldinfo)].busy.info.size
-	= BLOCKIFY (mdp -> heapsize * sizeof (malloc_info));
-      mdp -> heapinfo = newinfo;
-      __mmalloc_free (mdp, (PTR)oldinfo);
-      mdp -> heapsize = newsize;
-    }
-
-  mdp -> heaplimit = BLOCK ((char *) result + size);
-  return (result);
-}
-
-/* Allocate memory from the heap.  */
-
-PTR
-mmalloc (md, size)
-  PTR md;
-  size_t size;
-{
-  struct mdesc *mdp;
-  PTR result;
-  size_t block, blocks, lastblocks, start;
-  register size_t i;
-  struct list *next;
-  register size_t log;
-
-  if (size == 0)
-    {
-      return (NULL);
-    }
-
-  mdp = MD_TO_MDP (md);
-      
-  if (mdp -> mmalloc_hook != NULL)
-    {
-      return ((*mdp -> mmalloc_hook) (md, size));
-    }
-
-  if (!(mdp -> flags & MMALLOC_INITIALIZED))
-    {
-      if (!initialize (mdp))
-	{
-	  return (NULL);
-	}
-    }
-
-  if (size < sizeof (struct list))
-    {
-      size = sizeof (struct list);
-    }
-
-  /* Determine the allocation policy based on the request size.  */
-  if (size <= BLOCKSIZE / 2)
-    {
-      /* Small allocation to receive a fragment of a block.
-	 Determine the logarithm to base two of the fragment size. */
-      log = 1;
-      --size;
-      while ((size /= 2) != 0)
-	{
-	  ++log;
-	}
-
-      /* Look in the fragment lists for a
-	 free fragment of the desired size. */
-      next = mdp -> fraghead[log].next;
-      if (next != NULL)
-	{
-	  /* There are free fragments of this size.
-	     Pop a fragment out of the fragment list and return it.
-	     Update the block's nfree and first counters. */
-	  result = (PTR) next;
-	  next -> prev -> next = next -> next;
-	  if (next -> next != NULL)
-	    {
-	      next -> next -> prev = next -> prev;
-	    }
-	  block = BLOCK (result);
-	  if (--mdp -> heapinfo[block].busy.info.frag.nfree != 0)
-	    {
-	      mdp -> heapinfo[block].busy.info.frag.first =
-		RESIDUAL (next -> next, BLOCKSIZE) >> log;
-	    }
-
-	  /* Update the statistics.  */
-	  mdp -> heapstats.chunks_used++;
-	  mdp -> heapstats.bytes_used += 1 << log;
-	  mdp -> heapstats.chunks_free--;
-	  mdp -> heapstats.bytes_free -= 1 << log;
-	}
-      else
-	{
-	  /* No free fragments of the desired size, so get a new block
-	     and break it into fragments, returning the first.  */
-	  result = mmalloc (md, BLOCKSIZE);
-	  if (result == NULL)
-	    {
-	      return (NULL);
-	    }
-
-	  /* Link all fragments but the first into the free list.  */
-	  for (i = 1; i < (size_t) (BLOCKSIZE >> log); ++i)
-	    {
-	      next = (struct list *) ((char *) result + (i << log));
-	      next -> next = mdp -> fraghead[log].next;
-	      next -> prev = &mdp -> fraghead[log];
-	      next -> prev -> next = next;
-	      if (next -> next != NULL)
-		{
-		  next -> next -> prev = next;
-		}
-	    }
-
-	  /* Initialize the nfree and first counters for this block.  */
-	  block = BLOCK (result);
-	  mdp -> heapinfo[block].busy.type = log;
-	  mdp -> heapinfo[block].busy.info.frag.nfree = i - 1;
-	  mdp -> heapinfo[block].busy.info.frag.first = i - 1;
-
-	  mdp -> heapstats.chunks_free += (BLOCKSIZE >> log) - 1;
-	  mdp -> heapstats.bytes_free += BLOCKSIZE - (1 << log);
- 	  mdp -> heapstats.bytes_used -= BLOCKSIZE - (1 << log);
-	}
-    }
-  else
-    {
-      /* Large allocation to receive one or more blocks.
-	 Search the free list in a circle starting at the last place visited.
-	 If we loop completely around without finding a large enough
-	 space we will have to get more memory from the system.  */
-      blocks = BLOCKIFY(size);
-      start = block = MALLOC_SEARCH_START;
-      while (mdp -> heapinfo[block].free.size < blocks)
-	{
-	  block = mdp -> heapinfo[block].free.next;
-	  if (block == start)
-	    {
-	      /* Need to get more from the system.  Check to see if
-		 the new core will be contiguous with the final free
-		 block; if so we don't need to get as much.  */
-	      block = mdp -> heapinfo[0].free.prev;
-	      lastblocks = mdp -> heapinfo[block].free.size;
-	      if (mdp -> heaplimit != 0 &&
-		  block + lastblocks == mdp -> heaplimit &&
-		  mdp -> morecore (mdp, 0) == ADDRESS(block + lastblocks) &&
-		  (morecore (mdp, (blocks - lastblocks) * BLOCKSIZE)) != NULL)
-		{
-		  /* Which block we are extending (the `final free
-		     block' referred to above) might have changed, if
-		     it got combined with a freed info table.  */
-		  block = mdp -> heapinfo[0].free.prev;
-
-		  mdp -> heapinfo[block].free.size += (blocks - lastblocks);
-		  mdp -> heapstats.bytes_free +=
-		      (blocks - lastblocks) * BLOCKSIZE;
-		  continue;
-		}
-	      result = morecore(mdp, blocks * BLOCKSIZE);
-	      if (result == NULL)
-		{
-		  return (NULL);
-		}
-	      block = BLOCK (result);
-	      mdp -> heapinfo[block].busy.type = 0;
-	      mdp -> heapinfo[block].busy.info.size = blocks;
-	      mdp -> heapstats.chunks_used++;
-	      mdp -> heapstats.bytes_used += blocks * BLOCKSIZE;
-	      return (result);
-	    }
-	}
-
-      /* At this point we have found a suitable free list entry.
-	 Figure out how to remove what we need from the list. */
-      result = ADDRESS(block);
-      if (mdp -> heapinfo[block].free.size > blocks)
-	{
-	  /* The block we found has a bit left over,
-	     so relink the tail end back into the free list. */
-	  mdp -> heapinfo[block + blocks].free.size
-	    = mdp -> heapinfo[block].free.size - blocks;
-	  mdp -> heapinfo[block + blocks].free.next
-	    = mdp -> heapinfo[block].free.next;
-	  mdp -> heapinfo[block + blocks].free.prev
-	    = mdp -> heapinfo[block].free.prev;
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.prev].free.next
-	    = mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.prev
-	      = mdp -> heapindex = block + blocks;
-	}
-      else
-	{
-	  /* The block exactly matches our requirements,
-	     so just remove it from the list. */
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.next].free.prev
-	    = mdp -> heapinfo[block].free.prev;
-	  mdp -> heapinfo[mdp -> heapinfo[block].free.prev].free.next
-	    = mdp -> heapindex = mdp -> heapinfo[block].free.next;
-	  mdp -> heapstats.chunks_free--;
-	}
-
-      mdp -> heapinfo[block].busy.type = 0;
-      mdp -> heapinfo[block].busy.info.size = blocks;
-      mdp -> heapstats.chunks_used++;
-      mdp -> heapstats.bytes_used += blocks * BLOCKSIZE;
-      mdp -> heapstats.bytes_free -= blocks * BLOCKSIZE;
-    }
-
-  return (result);
-}
-
-/* When using this package, provide a version of malloc/realloc/free built
-   on top of it, so that if we use the default sbrk() region we will not
-   collide with another malloc package trying to do the same thing, if
-   the application contains any "hidden" calls to malloc/realloc/free (such
-   as inside a system library). */
-
-PTR
-malloc (size)
-  size_t size;
-{
-  PTR result;
-
-  result = mmalloc ((PTR) NULL, size);
-  return (result);
-}
diff --git a/mmalloc/mmalloc.h b/mmalloc/mmalloc.h
deleted file mode 100644
index 082547ea504..00000000000
--- a/mmalloc/mmalloc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef MMALLOC_H
-#define MMALLOC_H 1
-
-#ifdef HAVE_STDDEF_H
-#  include <stddef.h>
-#else
-#  include <sys/types.h>   /* for size_t */
-#  include <stdio.h>       /* for NULL */
-#endif
-
-#include "ansidecl.h"
- 
-/* Allocate SIZE bytes of memory.  */
-
-extern PTR mmalloc PARAMS ((PTR, size_t));
-
-/* Re-allocate the previously allocated block in PTR, making the new block
-   SIZE bytes long.  */
-
-extern PTR mrealloc PARAMS ((PTR, PTR, size_t));
-
-/* Allocate NMEMB elements of SIZE bytes each, all initialized to 0.  */
-
-extern PTR mcalloc PARAMS ((PTR, size_t, size_t));
-
-/* Free a block allocated by `mmalloc', `mrealloc' or `mcalloc'.  */
-
-extern void mfree PARAMS ((PTR, PTR));
-
-/* Allocate SIZE bytes allocated to ALIGNMENT bytes.  */
-
-extern PTR mmemalign PARAMS ((PTR, size_t, size_t));
-
-/* Allocate SIZE bytes on a page boundary.  */
-
-extern PTR mvalloc PARAMS ((PTR, size_t));
-
-/* Activate a standard collection of debugging hooks.  */
-
-extern int mmcheck PARAMS ((PTR, void (*) (void)));
-
-extern int mmcheckf PARAMS ((PTR, void (*) (void), int));
-
-/* Pick up the current statistics. (see FIXME elsewhere) */
-
-extern struct mstats mmstats PARAMS ((PTR));
-
-extern PTR mmalloc_attach PARAMS ((int, PTR));
-
-extern PTR mmalloc_detach PARAMS ((PTR));
-
-extern int mmalloc_setkey PARAMS ((PTR, int, PTR));
-
-extern PTR mmalloc_getkey PARAMS ((PTR, int));
-
-extern int mmalloc_errno PARAMS ((PTR));
-
-extern int mmtrace PARAMS ((void));
-
-extern PTR mmalloc_findbase PARAMS ((int));
-
-#endif  /* MMALLOC_H */
diff --git a/mmalloc/mmalloc.texi b/mmalloc/mmalloc.texi
deleted file mode 100644
index c038f651b3a..00000000000
--- a/mmalloc/mmalloc.texi
+++ /dev/null
@@ -1,258 +0,0 @@
-\input texinfo  @c                                  -*- Texinfo -*-
-@setfilename mmalloc.info
-
-@ifinfo
-@format
-START-INFO-DIR-ENTRY
-* Mmalloc: (mmalloc).		The GNU mapped-malloc package.
-END-INFO-DIR-ENTRY
-@end format
-
-This file documents the GNU mmalloc (mapped-malloc) package, written by
-fnf@@cygnus.com, based on GNU malloc written by mike@@ai.mit.edu.
-
-Copyright (C) 1992 Free Software Foundation, Inc.
-
-Permission is granted to make and distribute verbatim copies of
-this manual provided the copyright notice and this permission notice
-are preserved on all copies.
-
-@ignore
-Permission is granted to process this file through Tex and print the
-results, provided the printed document carries copying permission
-notice identical to this one except for the removal of this paragraph
-(this paragraph not being relevant to the printed manual).
-
-@end ignore
-Permission is granted to copy and distribute modified versions of this
-manual under the conditions for verbatim copying, provided also that the
-entire resulting derived work is distributed under the terms of a
-permission notice identical to this one.
-
-Permission is granted to copy and distribute translations of this manual
-into another language, under the above conditions for modified versions.
-@end ifinfo
-@iftex
-@c @finalout
-@setchapternewpage odd
-@settitle MMALLOC, the GNU memory-mapped malloc package
-@titlepage
-@title mmalloc
-@subtitle The GNU memory-mapped malloc package
-@author Fred Fish
-@author Cygnus Support
-@author Mike Haertel
-@author Free Software Foundation
-@page
-
-@tex
-\def\$#1${{#1}}  % Kluge: collect RCS revision info without $...$
-\xdef\manvers{\$Revision$}  % For use in headers, footers too
-{\parskip=0pt
-\hfill Cygnus Support\par
-\hfill fnf\@cygnus.com\par
-\hfill {\it MMALLOC, the GNU memory-mapped malloc package}, \manvers\par
-\hfill \TeX{}info \texinfoversion\par
-}
-@end tex
-
-@vskip 0pt plus 1filll
-Copyright @copyright{} 1992 Free Software Foundation, Inc.
-
-Permission is granted to make and distribute verbatim copies of
-this manual provided the copyright notice and this permission notice
-are preserved on all copies.
-
-Permission is granted to copy and distribute modified versions of this
-manual under the conditions for verbatim copying, provided also that
-the entire resulting derived work is distributed under the terms of a
-permission notice identical to this one.
-
-Permission is granted to copy and distribute translations of this manual
-into another language, under the above conditions for modified versions.
-@end titlepage
-@end iftex
-
-@ifinfo
-@node Top, Overview, (dir), (dir)
-@top mmalloc
-This file documents the GNU memory-mapped malloc package mmalloc.
-
-@menu
-* Overview::                    Overall Description
-* Implementation::              Implementation
-
- --- The Detailed Node Listing ---
-
-Implementation
-
-* Compatibility::               Backwards Compatibility
-* Functions::                   Function Descriptions
-@end menu
-
-@end ifinfo
-
-@node Overview, Implementation, Top, Top
-@chapter Overall Description
-
-This is a heavily modified version of GNU @code{malloc}.  It uses
-@code{mmap} as the basic mechanism for obtaining memory from the
-system, rather than @code{sbrk}.  This gives it several advantages over the
-more traditional malloc:
-
-@itemize @bullet
-@item
-Several different heaps can be used, each of them growing
-or shinking under control of @code{mmap}, with the @code{mmalloc} functions
-using a specific heap on a call by call basis.
-
-@item
-By using @code{mmap}, it is easy to create heaps which are intended to
-be persistent and exist as a filesystem object after the creating
-process has gone away.
-
-@item
-Because multiple heaps can be managed, data used for a 
-specific purpose can be allocated into its own heap, making
-it easier to allow applications to ``dump'' and ``restore'' initialized
-malloc-managed memory regions.  For example, the ``unexec'' hack popularized
-by GNU Emacs could potentially go away.
-@end itemize
-
-@node Implementation,  , Overview, Top
-@chapter Implementation
-
-The @code{mmalloc} functions contain no internal static state.  All
-@code{mmalloc} internal data is allocated in the mapped in region, along
-with the user data that it manages.  This allows it to manage multiple
-such regions and to ``pick up where it left off'' when such regions are
-later dynamically mapped back in.
-
-In some sense, malloc has been ``purified'' to contain no internal state
-information and generalized to use multiple memory regions rather than a
-single region managed by @code{sbrk}.  However the new routines now need an
-extra parameter which informs @code{mmalloc} which memory region it is dealing
-with (along with other information).  This parameter is called the
-@dfn{malloc descriptor}.
-
-The functions initially provided by @code{mmalloc} are:
-
-@example
-void *mmalloc_attach (int fd, void *baseaddr);
-void *mmalloc_detach (void *md);
-int mmalloc_errno (void *md);
-int mmalloc_setkey (void *md, int keynum, void *key);
-void *mmalloc_getkey (void *md, int keynum);
-
-void *mmalloc (void *md, size_t size);
-void *mrealloc (void *md, void *ptr, size_t size);
-void *mvalloc (void *md, size_t size);
-void mfree (void *md, void *ptr);
-@end example
-
-@menu
-* Compatibility::               Backwards Compatibility
-* Functions::                   Function Descriptions
-@end menu
-
-@node Compatibility, Functions, Implementation, Implementation
-@section Backwards Compatibility
-
-To allow a single malloc package to be used in a given application,
-provision is made for the traditional @code{malloc}, @code{realloc}, and
-@code{free} functions to be implemented as special cases of the
-@code{mmalloc} functions.  In particular, if any of the functions that
-expect malloc descriptors are called with a @code{NULL} pointer rather than a
-valid malloc descriptor, then they default to using an @code{sbrk} managed
-region.
-The @code{mmalloc} package provides compatible @code{malloc}, @code{realloc},
-and @code{free} functions using this mechanism internally.
-Applications can avoid this extra interface layer by simply including the
-following defines:
-
-@example
-#define malloc(size)		mmalloc ((void *)0, (size))
-#define realloc(ptr,size)	mrealloc ((void *)0, (ptr), (size));
-#define free(ptr)		mfree ((void *)0, (ptr))
-@end example
-
-@noindent
-or replace the existing @code{malloc}, @code{realloc}, and @code{free}
-calls with the above patterns if using @code{#define} causes problems.
-
-@node Functions,  , Compatibility, Implementation
-@section Function Descriptions
-
-These are the details on the functions that make up the @code{mmalloc}
-package. 
-
-@table @code
-@item void *mmalloc_attach (int @var{fd}, void *@var{baseaddr});
-Initialize access to a @code{mmalloc} managed region.
-
-If @var{fd} is a valid file descriptor for an open file, then data for the
-@code{mmalloc} managed region is mapped to that file.   Otherwise
-@file{/dev/zero} is used and the data will not exist in any filesystem object.
-
-If the open file corresponding to @var{fd} is from a previous use of
-@code{mmalloc} and passes some basic sanity checks to ensure that it is
-compatible with the current @code{mmalloc} package, then its data is
-mapped in and is immediately accessible at the same addresses in
-the current process as the process that created the file.
-
-If @var{baseaddr} is not @code{NULL}, the mapping is established
-starting at the specified address in the process address space.  If
-@var{baseaddr} is @code{NULL}, the @code{mmalloc} package chooses a
-suitable address at which to start the mapped region, which will be the
-value of the previous mapping if opening an existing file which was
-previously built by @code{mmalloc}, or for new files will be a value
-chosen by @code{mmap}.
-
-Specifying @var{baseaddr} provides more control over where the regions
-start and how big they can be before bumping into existing mapped
-regions or future mapped regions.
-
-On success, returns a malloc descriptor which is used in subsequent
-calls to other @code{mmalloc} package functions.  It is explicitly
-@samp{void *} (@samp{char *} for systems that don't fully support
-@code{void}) so that users of the package don't have to worry about the
-actual implementation details.
-
-On failure returns @code{NULL}.
-
-@item void *mmalloc_detach (void *@var{md});
-Terminate access to a @code{mmalloc} managed region identified by the
-descriptor @var{md}, by closing the base file and unmapping all memory
-pages associated with the region. 
-
-Returns @code{NULL} on success.
-
-Returns the malloc descriptor on failure, which can subsequently
-be used for further action (such as obtaining more information about
-the nature of the failure).
-
-@item void *mmalloc (void *@var{md}, size_t @var{size});
-Given an @code{mmalloc} descriptor @var{md}, allocate additional memory of
-@var{size} bytes in the associated mapped region.
-
-@item *mrealloc (void *@var{md}, void *@var{ptr}, size_t @var{size});
-Given an @code{mmalloc} descriptor @var{md} and a pointer to memory
-previously allocated by @code{mmalloc} in @var{ptr}, reallocate the
-memory to be @var{size} bytes long, possibly moving the existing
-contents of memory if necessary.
-	
-@item void *mvalloc (void *@var{md}, size_t @var{size});
-Like @code{mmalloc} but the resulting memory is aligned on a page boundary.
-
-@item void mfree (void *@var{md}, void *@var{ptr});
-Given an @code{mmalloc} descriptor @var{md} and a pointer to memory previously
-allocated by @code{mmalloc} in @var{ptr}, free the previously allocated memory.
-
-@item int mmalloc_errno (void *@var{md});
-Given a @code{mmalloc} descriptor, if the last @code{mmalloc} operation
-failed for some reason due to a system call failure, then
-returns the associated @code{errno}.  Returns 0 otherwise.
-(This function is not yet implemented).
-@end table
-
-@bye
diff --git a/mmalloc/mmap-sup.c b/mmalloc/mmap-sup.c
deleted file mode 100644
index b12e43cf255..00000000000
--- a/mmalloc/mmap-sup.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Support for an sbrk-like function that uses mmap.
-   Copyright 1992, 2000 Free Software Foundation, Inc.
-
-   Contributed by Fred Fish at Cygnus Support.   fnf@cygnus.com
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#if defined(HAVE_MMAP)
-
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>	/* Prototypes for lseek */
-#endif
-#include <stdio.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#ifndef SEEK_SET
-#define SEEK_SET 0
-#endif
-
-#include "mmprivate.h"
-
-/* Cache the pagesize for the current host machine.  Note that if the host
-   does not readily provide a getpagesize() function, we need to emulate it
-   elsewhere, not clutter up this file with lots of kluges to try to figure
-   it out. */
-
-static size_t pagesize;
-#if NEED_DECLARATION_GETPAGESIZE
-extern int getpagesize PARAMS ((void));
-#endif
-
-#define PAGE_ALIGN(addr) (caddr_t) (((long)(addr) + pagesize - 1) & \
-				    ~(pagesize - 1))
-
-
-/* Return MAP_PRIVATE if MDP represents /dev/zero.  Otherwise, return
-   MAP_SHARED.  */
-
-#define MAP_PRIVATE_OR_SHARED(MDP) ((MDP -> flags & MMALLOC_DEVZERO) \
-                                    ? MAP_PRIVATE \
-                                    : MAP_SHARED)
-
-
-/*  Get core for the memory region specified by MDP, using SIZE as the
-    amount to either add to or subtract from the existing region.  Works
-    like sbrk(), but using mmap(). */
-
-PTR
-__mmalloc_mmap_morecore (mdp, size)
-  struct mdesc *mdp;
-  int size;
-{
-  PTR result = NULL;
-  off_t foffset;	/* File offset at which new mapping will start */
-  size_t mapbytes;	/* Number of bytes to map */
-  caddr_t moveto;	/* Address where we wish to move "break value" to */
-  caddr_t mapto;	/* Address we actually mapped to */
-  char buf = 0;		/* Single byte to write to extend mapped file */
-
-  if (pagesize == 0)
-    {
-      pagesize = getpagesize ();
-    }
-  if (size == 0)
-    {
-      /* Just return the current "break" value. */
-      result = mdp -> breakval;
-    }
-  else if (size < 0)
-    {
-      /* We are deallocating memory.  If the amount requested would cause
-	 us to try to deallocate back past the base of the mmap'd region
-	 then do nothing, and return NULL.  Otherwise, deallocate the
-	 memory and return the old break value. */
-      if (mdp -> breakval + size >= mdp -> base)
-	{
-	  result = (PTR) mdp -> breakval;
-	  mdp -> breakval += size;
-	  moveto = PAGE_ALIGN (mdp -> breakval);
-	  munmap (moveto, (size_t) (mdp -> top - moveto));
-	  mdp -> top = moveto;
-	}
-    }
-  else
-    {
-      /* We are allocating memory.  Make sure we have an open file
-	 descriptor and then go on to get the memory. */
-      if (mdp -> fd < 0)
-	{
-	  result = NULL;
-	}
-      else if (mdp -> breakval + size > mdp -> top)
-	{
-	  /* The request would move us past the end of the currently
-	     mapped memory, so map in enough more memory to satisfy
-	     the request.  This means we also have to grow the mapped-to
-	     file by an appropriate amount, since mmap cannot be used
-	     to extend a file. */
-	  moveto = PAGE_ALIGN (mdp -> breakval + size);
-	  mapbytes = moveto - mdp -> top;
-	  foffset = mdp -> top - mdp -> base;
-	  /* FIXME:  Test results of lseek() and write() */
-	  lseek (mdp -> fd, foffset + mapbytes - 1, SEEK_SET);
-	  write (mdp -> fd, &buf, 1);
-	  if (mdp -> base == 0)
-	    {
-	      /* Let mmap pick the map start address */
-	      mapto = mmap (0, mapbytes, PROT_READ | PROT_WRITE,
-			    MAP_PRIVATE_OR_SHARED (mdp), mdp -> fd, foffset);
-	      if (mapto != (caddr_t) -1)
-		{
-		  mdp -> base = mdp -> breakval = mapto;
-		  mdp -> top = mdp -> base + mapbytes;
-		  result = (PTR) mdp -> breakval;
-		  mdp -> breakval += size;
-		}
-	    }
-	  else
-	    {
-	      mapto = mmap (mdp -> top, mapbytes, PROT_READ | PROT_WRITE,
-			    MAP_PRIVATE_OR_SHARED (mdp) | MAP_FIXED, mdp -> fd,
-			    foffset);
-	      if (mapto == mdp -> top)
-		{
-		  mdp -> top = moveto;
-		  result = (PTR) mdp -> breakval;
-		  mdp -> breakval += size;
-		}
-	    }
-	}
-      else
-	{
-	  result = (PTR) mdp -> breakval;
-	  mdp -> breakval += size;
-	}
-    }
-  return (result);
-}
-
-PTR
-__mmalloc_remap_core (mdp)
-  struct mdesc *mdp;
-{
-  caddr_t base;
-
-  /* FIXME:  Quick hack, needs error checking and other attention. */
-
-  base = mmap (mdp -> base, mdp -> top - mdp -> base,
-	       PROT_READ | PROT_WRITE, MAP_PRIVATE_OR_SHARED (mdp) | MAP_FIXED,
-	       mdp -> fd, 0);
-  return ((PTR) base);
-}
-
-PTR
-mmalloc_findbase (size)
-  int size;
-{
-  int fd;
-  int flags;
-  caddr_t base = NULL;
-
-#ifdef MAP_ANONYMOUS
-  flags = MAP_PRIVATE | MAP_ANONYMOUS;
-  fd = -1;
-#else
-#ifdef MAP_FILE
-  flags = MAP_PRIVATE | MAP_FILE;
-#else
-  flags = MAP_PRIVATE;
-#endif
-  fd = open ("/dev/zero", O_RDWR);
-  if (fd != -1)
-    {
-      return ((PTR) NULL);
-    }
-#endif
-  base = mmap (0, size, PROT_READ | PROT_WRITE, flags, fd, 0);
-  if (base != (caddr_t) -1)
-    {
-      munmap (base, (size_t) size);
-    }
-  if (fd != -1)
-    {
-      close (fd);
-    }
-  if (base == 0)
-    {
-      /* Don't allow mapping at address zero.  We use that value
-	 to signal an error return, and besides, it is useful to
-	 catch NULL pointers if it is unmapped.  Instead start
-	 at the next page boundary. */
-      base = (caddr_t) getpagesize ();
-    }
-  else if (base == (caddr_t) -1)
-    {
-      base = NULL;
-    }
-  return ((PTR) base);
-}
-
-#else	/* defined(HAVE_MMAP) */
-/* Prevent "empty translation unit" warnings from the idiots at X3J11. */
-static char ansi_c_idiots = 69;
-#endif	/* defined(HAVE_MMAP) */
diff --git a/mmalloc/mmcheck.c b/mmalloc/mmcheck.c
deleted file mode 100644
index 48936b3e630..00000000000
--- a/mmalloc/mmcheck.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* Standard debugging hooks for `mmalloc'.
-   Copyright 1990, 1991, 1992 Free Software Foundation
-
-   Written May 1989 by Mike Haertel.
-   Heavily modified Mar 1992 by Fred Fish (fnf@cygnus.com)
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
- The author may be reached (Email) at the address mike@ai.mit.edu,
- or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-#include "mmprivate.h"
-
-/* Default function to call when something awful happens.  The application
-   can specify an alternate function to be called instead (and probably will
-   want to). */
-
-extern void abort PARAMS ((void));
-
-/* Arbitrary magical numbers.  */
-
-#define MAGICWORD	(unsigned int) 0xfedabeeb	/* Active chunk */
-#define MAGICWORDFREE	(unsigned int) 0xdeadbeef	/* Inactive chunk */
-#define MAGICBYTE	((char) 0xd7)
-
-/* Each memory allocation is bounded by a header structure and a trailer
-   byte.  I.E.
-
-	<size><magicword><user's allocation><magicbyte>
-
-   The pointer returned to the user points to the first byte in the
-   user's allocation area.  The magic word can be tested to detect
-   buffer underruns and the magic byte can be tested to detect overruns. */
-
-struct hdr
-  {
-    size_t size;		/* Exact size requested by user.  */
-    unsigned long int magic;	/* Magic number to check header integrity.  */
-  };
-
-static void checkhdr PARAMS ((struct mdesc *, CONST struct hdr *));
-static void mfree_check PARAMS ((PTR, PTR));
-static PTR mmalloc_check PARAMS ((PTR, size_t));
-static PTR mrealloc_check PARAMS ((PTR, PTR, size_t));
-
-/* Check the magicword and magicbyte, and if either is corrupted then
-   call the emergency abort function specified for the heap in use. */
-
-static void
-checkhdr (mdp, hdr)
-  struct mdesc *mdp;
-  CONST struct hdr *hdr;
-{
-  if (hdr -> magic != MAGICWORD ||
-      ((char *) &hdr[1])[hdr -> size] != MAGICBYTE)
-    {
-      (*mdp -> abortfunc)();
-    }
-}
-
-static void
-mfree_check (md, ptr)
-  PTR md;
-  PTR ptr;
-{
-  struct hdr *hdr = ((struct hdr *) ptr) - 1;
-  struct mdesc *mdp;
-
-  mdp = MD_TO_MDP (md);
-  checkhdr (mdp, hdr);
-  hdr -> magic = MAGICWORDFREE;
-  mdp -> mfree_hook = NULL;
-  mfree (md, (PTR)hdr);
-  mdp -> mfree_hook = mfree_check;
-}
-
-static PTR
-mmalloc_check (md, size)
-  PTR md;
-  size_t size;
-{
-  struct hdr *hdr;
-  struct mdesc *mdp;
-  size_t nbytes;
-
-  mdp = MD_TO_MDP (md);
-  mdp -> mmalloc_hook = NULL;
-  nbytes = sizeof (struct hdr) + size + 1;
-  hdr = (struct hdr *) mmalloc (md, nbytes);
-  mdp -> mmalloc_hook = mmalloc_check;
-  if (hdr != NULL)
-    {
-      hdr -> size = size;
-      hdr -> magic = MAGICWORD;
-      hdr++;
-      *((char *) hdr + size) = MAGICBYTE;
-    }
-  return ((PTR) hdr);
-}
-
-static PTR
-mrealloc_check (md, ptr, size)
-  PTR md;
-  PTR ptr;
-  size_t size;
-{
-  struct hdr *hdr = ((struct hdr *) ptr) - 1;
-  struct mdesc *mdp;
-  size_t nbytes;
-
-  mdp = MD_TO_MDP (md);
-  checkhdr (mdp, hdr);
-  mdp -> mfree_hook = NULL;
-  mdp -> mmalloc_hook = NULL;
-  mdp -> mrealloc_hook = NULL;
-  nbytes = sizeof (struct hdr) + size + 1;
-  hdr = (struct hdr *) mrealloc (md, (PTR) hdr, nbytes);
-  mdp -> mfree_hook = mfree_check;
-  mdp -> mmalloc_hook = mmalloc_check;
-  mdp -> mrealloc_hook = mrealloc_check;
-  if (hdr != NULL)
-    {
-      hdr -> size = size;
-      hdr++;
-      *((char *) hdr + size) = MAGICBYTE;
-    }
-  return ((PTR) hdr);
-}
-
-/* Turn on default checking for mmalloc/mrealloc/mfree, for the heap specified
-   by MD.  If FUNC is non-NULL, it is a pointer to the function to call
-   to abort whenever memory corruption is detected.  By default, this is the
-   standard library function abort().
-
-   Note that we disallow installation of initial checking hooks if mmalloc
-   has been called at any time for this particular heap, since if any region
-   that is allocated prior to installation of the hooks is subsequently
-   reallocated or freed after installation of the hooks, it is guaranteed
-   to trigger a memory corruption error.  We do this by checking the state
-   of the MMALLOC_INITIALIZED flag.  If the FORCE argument is non-zero, this
-   checking is disabled and it is allowed to install the checking hooks at any
-   time.  This is useful on systems where the C runtime makes one or more
-   malloc calls before the user code had a chance to call mmcheck or mmcheckf,
-   but never calls free with these values.  Thus if we are certain that only
-   values obtained from mallocs after an mmcheck/mmcheckf will ever be passed
-   to free(), we can go ahead and force installation of the useful checking
-   hooks.
-
-   However, we can call this function at any time after the initial call,
-   to update the function pointers to the checking routines and to the
-   user defined corruption handler routine, as long as these function pointers
-   have been previously extablished by the initial call.  Note that we
-   do this automatically when remapping a previously used heap, to ensure
-   that the hooks get updated to the correct values, although the corruption
-   handler pointer gets set back to the default.  The application can then
-   call mmcheck to use a different corruption handler if desired.
-
-   Returns non-zero if checking is successfully enabled, zero otherwise. */
-
-int
-mmcheckf (md, func, force)
-  PTR md;
-  void (*func) PARAMS ((void));
-  int force;
-{
-  struct mdesc *mdp;
-  int rtnval;
-
-  mdp = MD_TO_MDP (md);
-
-  /* We can safely set or update the abort function at any time, regardless
-     of whether or not we successfully do anything else. */
-
-  mdp -> abortfunc = (func != NULL ? func : abort);
-
-  /* If we haven't yet called mmalloc the first time for this heap, or if we
-     have hooks that were previously installed, then allow the hooks to be
-     initialized or updated. */
-
-  if (force ||
-      !(mdp -> flags & MMALLOC_INITIALIZED) ||
-      (mdp -> mfree_hook != NULL))
-    {
-      mdp -> mfree_hook = mfree_check;
-      mdp -> mmalloc_hook = mmalloc_check;
-      mdp -> mrealloc_hook = mrealloc_check;
-      mdp -> flags |= MMALLOC_MMCHECK_USED;
-      rtnval = 1;
-    }
-  else
-    {
-      rtnval = 0;
-    }
-
-  return (rtnval);
-}
-
-/* This routine is for backwards compatibility only, in case there are
-   still callers to the original mmcheck function. */
-
-int
-mmcheck (md, func)
-  PTR md;
-  void (*func) PARAMS ((void));
-{
-  int rtnval;
-
-  rtnval = mmcheckf (md, func, 0);
-  return (rtnval);
-}
diff --git a/mmalloc/mmemalign.c b/mmalloc/mmemalign.c
deleted file mode 100644
index 3ada02707d7..00000000000
--- a/mmalloc/mmemalign.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright (C) 1991, 1992 Free Software Foundation, Inc.
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "mmprivate.h"
-
-PTR
-mmemalign (md, alignment, size)
-  PTR md;
-  size_t alignment;
-  size_t size;
-{
-  PTR result;
-  unsigned long int adj;
-  struct alignlist *l;
-  struct mdesc *mdp;
-
-  if ((result = mmalloc (md, size + alignment - 1)) != NULL)
-    {
-      adj = RESIDUAL (result, alignment);
-      if (adj != 0)
-	{
-	  mdp = MD_TO_MDP (md);
-	  for (l = mdp -> aligned_blocks; l != NULL; l = l -> next)
-	    {
-	      if (l -> aligned == NULL)
-		{
-		  /* This slot is free.  Use it.  */
-		  break;
-		}
-	    }
-	  if (l == NULL)
-	    {
-	      l = (struct alignlist *) mmalloc (md, sizeof (struct alignlist));
-	      if (l == NULL)
-		{
-		  mfree (md, result);
-		  return (NULL);
-		}
-	      l -> next = mdp -> aligned_blocks;
-	      mdp -> aligned_blocks = l;
-	    }
-	  l -> exact = result;
-	  result = l -> aligned = (char *) result + alignment - adj;
-	}
-    }
-  return (result);
-}
diff --git a/mmalloc/mmprivate.h b/mmalloc/mmprivate.h
deleted file mode 100644
index 457626293b1..00000000000
--- a/mmalloc/mmprivate.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Declarations for `mmalloc' and friends.
-   Copyright 1990, 1991, 1992 Free Software Foundation
-
-   Written May 1989 by Mike Haertel.
-   Heavily modified Mar 1992 by Fred Fish. (fnf@cygnus.com)
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   The author may be reached (Email) at the address mike@ai.mit.edu,
-   or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-
-#ifndef __MMPRIVATE_H
-#define __MMPRIVATE_H 1
-
-#include "mmalloc.h"
-
-#ifdef HAVE_LIMITS_H
-#  include <limits.h>
-#else
-#  ifndef CHAR_BIT
-#    define CHAR_BIT 8
-#  endif
-#endif
-
-#ifndef MIN
-#  define MIN(A, B) ((A) < (B) ? (A) : (B))
-#endif
-
-#define MMALLOC_MAGIC		"mmalloc"	/* Mapped file magic number */
-#define MMALLOC_MAGIC_SIZE	8		/* Size of magic number buf */
-#define MMALLOC_VERSION		1		/* Current mmalloc version */
-#define MMALLOC_KEYS		16		/* Keys for application use */
-
-/* The allocator divides the heap into blocks of fixed size; large
-   requests receive one or more whole blocks, and small requests
-   receive a fragment of a block.  Fragment sizes are powers of two,
-   and all fragments of a block are the same size.  When all the
-   fragments in a block have been freed, the block itself is freed.  */
-
-#define INT_BIT		(CHAR_BIT * sizeof(int))
-#define BLOCKLOG	(INT_BIT > 16 ? 12 : 9)
-#define BLOCKSIZE	((unsigned int) 1 << BLOCKLOG)
-#define BLOCKIFY(SIZE)	(((SIZE) + BLOCKSIZE - 1) / BLOCKSIZE)
-
-/* The difference between two pointers is a signed int.  On machines where
-   the data addresses have the high bit set, we need to ensure that the
-   difference becomes an unsigned int when we are using the address as an
-   integral value.  In addition, when using with the '%' operator, the
-   sign of the result is machine dependent for negative values, so force
-   it to be treated as an unsigned int. */
-
-#define ADDR2UINT(addr)	((unsigned int) ((char *) (addr) - (char *) NULL))
-#define RESIDUAL(addr,bsize) ((unsigned int) (ADDR2UINT (addr) % (bsize)))
-
-/* Determine the amount of memory spanned by the initial heap table
-   (not an absolute limit).  */
-
-#define HEAP		(INT_BIT > 16 ? 4194304 : 65536)
-
-/* Number of contiguous free blocks allowed to build up at the end of
-   memory before they will be returned to the system.  */
-
-#define FINAL_FREE_BLOCKS	8
-
-/* Where to start searching the free list when looking for new memory.
-   The two possible values are 0 and heapindex.  Starting at 0 seems
-   to reduce total memory usage, while starting at heapindex seems to
-   run faster.  */
-
-#define MALLOC_SEARCH_START	mdp -> heapindex
-
-/* Address to block number and vice versa.  */
-
-#define BLOCK(A) (((char *) (A) - mdp -> heapbase) / BLOCKSIZE + 1)
-
-#define ADDRESS(B) ((PTR) (((B) - 1) * BLOCKSIZE + mdp -> heapbase))
-
-/* Data structure giving per-block information.  */
-
-typedef union
-  {
-    /* Heap information for a busy block.  */
-    struct
-      {
-	/* Zero for a large block, or positive giving the
-	   logarithm to the base two of the fragment size.  */
-	int type;
-	union
-	  {
-	    struct
-	      {
-		size_t nfree;	/* Free fragments in a fragmented block.  */
-		size_t first;	/* First free fragment of the block.  */
-	      } frag;
-	    /* Size (in blocks) of a large cluster.  */
-	    size_t size;
-	  } info;
-      } busy;
-    /* Heap information for a free block (that may be the first of
-       a free cluster).  */
-    struct
-      {
-	size_t size;		/* Size (in blocks) of a free cluster.  */
-	size_t next;		/* Index of next free cluster.  */
-	size_t prev;		/* Index of previous free cluster.  */
-      } free;
-  } malloc_info;
-
-/* List of blocks allocated with `mmemalign' (or `mvalloc').  */
-
-struct alignlist
-  {
-    struct alignlist *next;
-    PTR aligned;		/* The address that mmemaligned returned.  */
-    PTR exact;			/* The address that malloc returned.  */
-  };
-
-/* Doubly linked lists of free fragments.  */
-
-struct list
-  {
-    struct list *next;
-    struct list *prev;
-  };
-
-/* Statistics available to the user.
-   FIXME:  By design, the internals of the malloc package are no longer
-   exported to the user via an include file, so access to this data needs
-   to be via some other mechanism, such as mmstat_<something> where the
-   return value is the <something> the user is interested in. */
-
-struct mstats
-  {
-    size_t bytes_total;		/* Total size of the heap. */
-    size_t chunks_used;		/* Chunks allocated by the user. */
-    size_t bytes_used;		/* Byte total of user-allocated chunks. */
-    size_t chunks_free;		/* Chunks in the free list. */
-    size_t bytes_free;		/* Byte total of chunks in the free list. */
-  };
-
-/* Internal structure that defines the format of the malloc-descriptor.
-   This gets written to the base address of the region that mmalloc is
-   managing, and thus also becomes the file header for the mapped file,
-   if such a file exists. */
-
-struct mdesc
-{
-  /* The "magic number" for an mmalloc file. */
-
-  char magic[MMALLOC_MAGIC_SIZE];
-
-  /* The size in bytes of this structure, used as a sanity check when reusing
-     a previously created mapped file. */
-
-  unsigned int headersize;
-
-  /* The version number of the mmalloc package that created this file. */
-
-  unsigned char version;
-
-  /* Some flag bits to keep track of various internal things. */
-
-  unsigned int flags;
-
-  /* If a system call made by the mmalloc package fails, the errno is
-     preserved for future examination. */
-
-  int saved_errno;
-
-  /* Pointer to the function that is used to get more core, or return core
-     to the system, for requests using this malloc descriptor.  For memory
-     mapped regions, this is the mmap() based routine.  There may also be
-     a single malloc descriptor that points to an sbrk() based routine
-     for systems without mmap() or for applications that call the mmalloc()
-     package with a NULL malloc descriptor.
-
-     FIXME:  For mapped regions shared by more than one process, this
-     needs to be maintained on a per-process basis. */
-
-  PTR (*morecore) PARAMS ((struct mdesc *, int));
-     
-  /* Pointer to the function that causes an abort when the memory checking
-     features are activated.  By default this is set to abort(), but can
-     be set to another function by the application using mmalloc().
-
-     FIXME:  For mapped regions shared by more than one process, this
-     needs to be maintained on a per-process basis. */
-
-  void (*abortfunc) PARAMS ((void));
-
-  /* Debugging hook for free.
-
-     FIXME:  For mapped regions shared by more than one process, this
-     needs to be maintained on a per-process basis. */
-
-  void (*mfree_hook) PARAMS ((PTR, PTR));
-
-  /* Debugging hook for `malloc'.
-
-     FIXME:  For mapped regions shared by more than one process, this
-     needs to be maintained on a per-process basis. */
-
-  PTR (*mmalloc_hook) PARAMS ((PTR, size_t));
-
-  /* Debugging hook for realloc.
-
-     FIXME:  For mapped regions shared by more than one process, this
-     needs to be maintained on a per-process basis. */
-
-  PTR (*mrealloc_hook) PARAMS ((PTR, PTR, size_t));
-
-  /* Number of info entries.  */
-
-  size_t heapsize;
-
-  /* Pointer to first block of the heap (base of the first block).  */
-
-  char *heapbase;
-
-  /* Current search index for the heap table.  */
-  /* Search index in the info table.  */
-
-  size_t heapindex;
-
-  /* Limit of valid info table indices.  */
-
-  size_t heaplimit;
-
-  /* Block information table.
-     Allocated with malign/__mmalloc_free (not mmalloc/mfree).  */
-  /* Table indexed by block number giving per-block information.  */
-
-  malloc_info *heapinfo;
-
-  /* Instrumentation.  */
-
-  struct mstats heapstats;
-
-  /* Free list headers for each fragment size.  */
-  /* Free lists for each fragment size.  */
-
-  struct list fraghead[BLOCKLOG];
-
-  /* List of blocks allocated by memalign.  */
-
-  struct alignlist *aligned_blocks;
-
-  /* The base address of the memory region for this malloc heap.  This
-     is the location where the bookkeeping data for mmap and for malloc
-     begins. */
-
-  char *base;
-
-  /* The current location in the memory region for this malloc heap which
-     represents the end of memory in use. */
-
-  char *breakval;
-
-  /* The end of the current memory region for this malloc heap.  This is
-     the first location past the end of mapped memory. */
-
-  char *top;
-
-  /* Open file descriptor for the file to which this malloc heap is mapped.
-     This will always be a valid file descriptor, since /dev/zero is used
-     by default if no open file is supplied by the client.  Also note that
-     it may change each time the region is mapped and unmapped. */
-
-  int fd;
-
-  /* An array of keys to data within the mapped region, for use by the
-     application.  */
-
-  PTR keys[MMALLOC_KEYS];
-
-};
-
-/* Bits to look at in the malloc descriptor flags word */
-
-#define MMALLOC_DEVZERO		(1 << 0)	/* Have mapped to /dev/zero */
-#define MMALLOC_INITIALIZED	(1 << 1)	/* Initialized mmalloc */
-#define MMALLOC_MMCHECK_USED	(1 << 2)	/* mmcheckf() called already */
-
-/* Internal version of `mfree' used in `morecore'. */
-
-extern void __mmalloc_free PARAMS ((struct mdesc *, PTR));
-
-/* Hooks for debugging versions.  */
-
-extern void (*__mfree_hook) PARAMS ((PTR, PTR));
-extern PTR (*__mmalloc_hook) PARAMS ((PTR, size_t));
-extern PTR (*__mrealloc_hook) PARAMS ((PTR, PTR, size_t));
-
-/* A default malloc descriptor for the single sbrk() managed region. */
-
-extern struct mdesc *__mmalloc_default_mdp;
-
-/* Initialize the first use of the default malloc descriptor, which uses
-   an sbrk() region. */
-
-extern struct mdesc *__mmalloc_sbrk_init PARAMS ((void));
-
-/* Grow or shrink a contiguous mapped region using mmap().
-   Works much like sbrk() */
-
-#if defined(HAVE_MMAP)
-
-extern PTR __mmalloc_mmap_morecore PARAMS ((struct mdesc *, int));
-
-#endif
-
-/* Remap a mmalloc region that was previously mapped. */
-
-extern PTR __mmalloc_remap_core PARAMS ((struct mdesc *));
-
-/* Macro to convert from a user supplied malloc descriptor to pointer to the
-   internal malloc descriptor.  If the user supplied descriptor is NULL, then
-   use the default internal version, initializing it if necessary.  Otherwise
-   just cast the user supplied version (which is void *) to the proper type
-   (struct mdesc *). */
-
-#define MD_TO_MDP(md) \
-  ((md) == NULL \
-   ? (__mmalloc_default_mdp == NULL \
-      ? __mmalloc_sbrk_init () \
-      : __mmalloc_default_mdp) \
-   : (struct mdesc *) (md))
-
-#endif  /* __MMPRIVATE_H */
diff --git a/mmalloc/mmstats.c b/mmalloc/mmstats.c
deleted file mode 100644
index ed17323ee5f..00000000000
--- a/mmalloc/mmstats.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Access the statistics maintained by `mmalloc'.
-   Copyright 1990, 1991, 1992 Free Software Foundation
-
-   Written May 1989 by Mike Haertel.
-   Modified Mar 1992 by Fred Fish.  (fnf@cygnus.com)
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   The author may be reached (Email) at the address mike@ai.mit.edu,
-   or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-#include "mmprivate.h"
-
-/* FIXME:  See the comment in mmprivate.h where struct mstats is defined.
-   None of the internal mmalloc structures should be externally visible
-   outside the library. */
-
-struct mstats
-mmstats (md)
-  PTR md;
-{
-  struct mstats result;
-  struct mdesc *mdp;
-
-  mdp = MD_TO_MDP (md);
-  result.bytes_total =
-      (char *) mdp -> morecore (mdp, 0) - mdp -> heapbase;
-  result.chunks_used = mdp -> heapstats.chunks_used;
-  result.bytes_used = mdp -> heapstats.bytes_used;
-  result.chunks_free = mdp -> heapstats.chunks_free;
-  result.bytes_free = mdp -> heapstats.bytes_free;
-  return (result);
-}
diff --git a/mmalloc/mmtrace.awk b/mmalloc/mmtrace.awk
deleted file mode 100644
index d7689cec3ff..00000000000
--- a/mmalloc/mmtrace.awk
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-#  Awk program to analyze mtrace.c output.
-#
-$1 == "+"	{ if (allocated[$2] != "")
-		    print "+", $2, "Alloc", NR, "duplicate:", allocated[$2];
-		  else
-		    allocated[$2] = $3;
-		}
-$1 == "-"	{ if (allocated[$2] != "") {
-		    allocated[$2] = "";
-		    if (allocated[$2] != "")
-			print "DELETE FAILED", $2, allocated[$2];
-		  } else
-		    print "-", $2, "Free", NR, "was never alloc'd";
-		}
-$1 == "<"	{ if (allocated[$2] != "")
-		    allocated[$2] = "";
-		  else
-		    print "-", $2, "Realloc", NR, "was never alloc'd";
-		}
-$1 == ">"	{ if (allocated[$2] != "")
-		    print "+", $2, "Realloc", NR, "duplicate:", allocated[$2];
-		  else
-		    allocated[$2] = $3;
-		}
-
-# Ignore "= Start"
-$1 == "="	{ }
-# Ignore failed realloc attempts for now
-$1 == "!"	{ }
-
-
-END		{ for (x in allocated) 
-		    if (allocated[x] != "")
-		      print "+", x, allocated[x];
-		}
diff --git a/mmalloc/mmtrace.c b/mmalloc/mmtrace.c
deleted file mode 100644
index 563c860aff0..00000000000
--- a/mmalloc/mmtrace.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* More debugging hooks for `mmalloc'.
-   Copyright 1991, 1992, 1994 Free Software Foundation
-
-   Written April 2, 1991 by John Gilmore of Cygnus Support
-   Based on mcheck.c by Mike Haertel.
-   Modified Mar 1992 by Fred Fish.  (fnf@cygnus.com)
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <stdio.h>
-#include "mmprivate.h"
-
-static void tr_break PARAMS ((void));
-static void tr_freehook PARAMS ((PTR, PTR));
-static PTR tr_mallochook PARAMS ((PTR, size_t));
-static PTR tr_reallochook PARAMS ((PTR, PTR, size_t));
-
-#ifndef	__GNU_LIBRARY__
-extern char *getenv ();
-#endif
-
-static FILE *mallstream;
-
-#if 0	/* FIXME:  Disabled for now. */
-static char mallenv[] = "MALLOC_TRACE";
-static char mallbuf[BUFSIZ];	/* Buffer for the output.  */
-#endif
-
-/* Address to breakpoint on accesses to... */
-static PTR mallwatch;
-
-/* Old hook values.  */
-
-static void (*old_mfree_hook) PARAMS ((PTR, PTR));
-static PTR (*old_mmalloc_hook) PARAMS ((PTR, size_t));
-static PTR (*old_mrealloc_hook) PARAMS ((PTR, PTR, size_t));
-
-/* This function is called when the block being alloc'd, realloc'd, or
-   freed has an address matching the variable "mallwatch".  In a debugger,
-   set "mallwatch" to the address of interest, then put a breakpoint on
-   tr_break.  */
-
-static void
-tr_break ()
-{
-}
-
-static void
-tr_freehook (md, ptr)
-  PTR md;
-  PTR ptr;
-{
-  struct mdesc *mdp;
-
-  mdp = MD_TO_MDP (md);
-  /* Be sure to print it first.  */
-  fprintf (mallstream, "- %08lx\n", (unsigned long) ptr);
-  if (ptr == mallwatch)
-    tr_break ();
-  mdp -> mfree_hook = old_mfree_hook;
-  mfree (md, ptr);
-  mdp -> mfree_hook = tr_freehook;
-}
-
-static PTR
-tr_mallochook (md, size)
-  PTR md;
-  size_t size;
-{
-  PTR hdr;
-  struct mdesc *mdp;
-
-  mdp = MD_TO_MDP (md);
-  mdp -> mmalloc_hook = old_mmalloc_hook;
-  hdr = (PTR) mmalloc (md, size);
-  mdp -> mmalloc_hook = tr_mallochook;
-
-  /* We could be printing a NULL here; that's OK.  */
-  fprintf (mallstream, "+ %08lx %x\n", (unsigned long) hdr, size);
-
-  if (hdr == mallwatch)
-    tr_break ();
-
-  return (hdr);
-}
-
-static PTR
-tr_reallochook (md, ptr, size)
-  PTR md;
-  PTR ptr;
-  size_t size;
-{
-  PTR hdr;
-  struct mdesc *mdp;
-
-  mdp = MD_TO_MDP (md);
-
-  if (ptr == mallwatch)
-    tr_break ();
-
-  mdp -> mfree_hook = old_mfree_hook;
-  mdp -> mmalloc_hook = old_mmalloc_hook;
-  mdp -> mrealloc_hook = old_mrealloc_hook;
-  hdr = (PTR) mrealloc (md, ptr, size);
-  mdp -> mfree_hook = tr_freehook;
-  mdp -> mmalloc_hook = tr_mallochook;
-  mdp -> mrealloc_hook = tr_reallochook;
-  if (hdr == NULL)
-    /* Failed realloc.  */
-    fprintf (mallstream, "! %08lx %x\n", (unsigned long) ptr, size);
-  else
-    fprintf (mallstream, "< %08lx\n> %08lx %x\n", (unsigned long) ptr,
-	     (unsigned long) hdr, size);
-
-  if (hdr == mallwatch)
-    tr_break ();
-
-  return hdr;
-}
-
-/* We enable tracing if either the environment variable MALLOC_TRACE
-   is set, or if the variable mallwatch has been patched to an address
-   that the debugging user wants us to stop on.  When patching mallwatch,
-   don't forget to set a breakpoint on tr_break!  */
-
-int
-mmtrace ()
-{
-#if 0	/* FIXME!  This is disabled for now until we figure out how to
-	   maintain a stack of hooks per heap, since we might have other
-	   hooks (such as set by mmcheck/mmcheckf) active also. */
-  char *mallfile;
-
-  mallfile = getenv (mallenv);
-  if (mallfile  != NULL || mallwatch != NULL)
-    {
-      mallstream = fopen (mallfile != NULL ? mallfile : "/dev/null", "w");
-      if (mallstream != NULL)
-	{
-	  /* Be sure it doesn't mmalloc its buffer!  */
-	  setbuf (mallstream, mallbuf);
-	  fprintf (mallstream, "= Start\n");
-	  old_mfree_hook = mdp -> mfree_hook;
-	  mdp -> mfree_hook = tr_freehook;
-	  old_mmalloc_hook = mdp -> mmalloc_hook;
-	  mdp -> mmalloc_hook = tr_mallochook;
-	  old_mrealloc_hook = mdp -> mrealloc_hook;
-	  mdp -> mrealloc_hook = tr_reallochook;
-	}
-    }
-
-#endif	/* 0 */
-
-  return (1);
-}
-
diff --git a/mmalloc/mrealloc.c b/mmalloc/mrealloc.c
deleted file mode 100644
index e2004aaf47b..00000000000
--- a/mmalloc/mrealloc.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Change the size of a block allocated by `mmalloc'.
-   Copyright 1990, 1991 Free Software Foundation
-		  Written May 1989 by Mike Haertel.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   The author may be reached (Email) at the address mike@ai.mit.edu,
-   or (US mail) as Mike Haertel c/o Free Software Foundation. */
-
-#include <string.h>	/* Prototypes for memcpy, memmove, memset, etc */
-
-#include "mmprivate.h"
-
-/* Resize the given region to the new size, returning a pointer
-   to the (possibly moved) region.  This is optimized for speed;
-   some benchmarks seem to indicate that greater compactness is
-   achieved by unconditionally allocating and copying to a
-   new region.  This module has incestuous knowledge of the
-   internals of both mfree and mmalloc. */
-
-PTR
-mrealloc (md, ptr, size)
-  PTR md;
-  PTR ptr;
-  size_t size;
-{
-  struct mdesc *mdp;
-  PTR result;
-  int type;
-  size_t block, blocks, oldlimit;
-
-  if (size == 0)
-    {
-      mfree (md, ptr);
-      return (mmalloc (md, 0));
-    }
-  else if (ptr == NULL)
-    {
-      return (mmalloc (md, size));
-    }
-
-  mdp = MD_TO_MDP (md);
-
-  if (mdp -> mrealloc_hook != NULL)
-    {
-      return ((*mdp -> mrealloc_hook) (md, ptr, size));
-    }
-
-  block = BLOCK (ptr);
-
-  type = mdp -> heapinfo[block].busy.type;
-  switch (type)
-    {
-    case 0:
-      /* Maybe reallocate a large block to a small fragment.  */
-      if (size <= BLOCKSIZE / 2)
-	{
-	  result = mmalloc (md, size);
-	  if (result != NULL)
-	    {
-	      memcpy (result, ptr, size);
-	      mfree (md, ptr);
-	      return (result);
-	    }
-	}
-
-      /* The new size is a large allocation as well;
-	 see if we can hold it in place. */
-      blocks = BLOCKIFY (size);
-      if (blocks < mdp -> heapinfo[block].busy.info.size)
-	{
-	  /* The new size is smaller; return excess memory to the free list. */
-	  mdp -> heapinfo[block + blocks].busy.type = 0;
-	  mdp -> heapinfo[block + blocks].busy.info.size
-	    = mdp -> heapinfo[block].busy.info.size - blocks;
-	  mdp -> heapinfo[block].busy.info.size = blocks;
-	  mfree (md, ADDRESS (block + blocks));
-	  result = ptr;
-	}
-      else if (blocks == mdp -> heapinfo[block].busy.info.size)
-	{
-	  /* No size change necessary.  */
-	  result = ptr;
-	}
-      else
-	{
-	  /* Won't fit, so allocate a new region that will.
-	     Free the old region first in case there is sufficient
-	     adjacent free space to grow without moving. */
-	  blocks = mdp -> heapinfo[block].busy.info.size;
-	  /* Prevent free from actually returning memory to the system.  */
-	  oldlimit = mdp -> heaplimit;
-	  mdp -> heaplimit = 0;
-	  mfree (md, ptr);
-	  mdp -> heaplimit = oldlimit;
-	  result = mmalloc (md, size);
-	  if (result == NULL)
-	    {
-	      mmalloc (md, blocks * BLOCKSIZE);
-	      return (NULL);
-	    }
-	  if (ptr != result)
-	    {
-	      memmove (result, ptr, blocks * BLOCKSIZE);
-	    }
-	}
-      break;
-
-    default:
-      /* Old size is a fragment; type is logarithm
-	 to base two of the fragment size.  */
-      if (size > (size_t) (1 << (type - 1)) && size <= (size_t) (1 << type))
-	{
-	  /* The new size is the same kind of fragment.  */
-	  result = ptr;
-	}
-      else
-	{
-	  /* The new size is different; allocate a new space,
-	     and copy the lesser of the new size and the old. */
-	  result = mmalloc (md, size);
-	  if (result == NULL)
-	    {
-	      return (NULL);
-	    }
-	  memcpy (result, ptr, MIN (size, (size_t) 1 << type));
-	  mfree (md, ptr);
-	}
-      break;
-    }
-
-  return (result);
-}
-
-/* When using this package, provide a version of malloc/realloc/free built
-   on top of it, so that if we use the default sbrk() region we will not
-   collide with another malloc package trying to do the same thing, if
-   the application contains any "hidden" calls to malloc/realloc/free (such
-   as inside a system library). */
-
-PTR
-realloc (ptr, size)
-  PTR ptr;
-  size_t size;
-{
-  PTR result;
-
-  result = mrealloc ((PTR) NULL, ptr, size);
-  return (result);
-}
diff --git a/mmalloc/mvalloc.c b/mmalloc/mvalloc.c
deleted file mode 100644
index e44942f5bb5..00000000000
--- a/mmalloc/mvalloc.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Allocate memory on a page boundary.
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "mmprivate.h"
-
-/* Cache the pagesize for the current host machine.  Note that if the host
-   does not readily provide a getpagesize() function, we need to emulate it
-   elsewhere, not clutter up this file with lots of kluges to try to figure
-   it out. */
-
-static size_t cache_pagesize;
-#if NEED_DECLARATION_GETPAGESIZE
-extern int getpagesize PARAMS ((void));
-#endif
-
-PTR
-mvalloc (md, size)
-  PTR md;
-  size_t size;
-{
-  if (cache_pagesize == 0)
-    {
-      cache_pagesize = getpagesize ();
-    }
-
-  return (mmemalign (md, cache_pagesize, size));
-}
-
-
-PTR
-valloc (size)
-  size_t size;
-{
-  return mvalloc ((PTR) NULL, size);
-}
diff --git a/mmalloc/sbrk-sup.c b/mmalloc/sbrk-sup.c
deleted file mode 100644
index 93c078bb2d0..00000000000
--- a/mmalloc/sbrk-sup.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Support for sbrk() regions.
-   Copyright 1992, 2000 Free Software Foundation, Inc.
-   Contributed by Fred Fish at Cygnus Support.   fnf@cygnus.com
-
-This file is part of the GNU C Library.
-
-The GNU C Library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Library General Public License as
-published by the Free Software Foundation; either version 2 of the
-License, or (at your option) any later version.
-
-The GNU C Library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Library General Public License for more details.
-
-You should have received a copy of the GNU Library General Public
-License along with the GNU C Library; see the file COPYING.LIB.  If
-not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>	/* Prototypes for sbrk (maybe) */
-#endif
-#include <string.h>	/* Prototypes for memcpy, memmove, memset, etc */
-
-#include "mmprivate.h"
-
-static PTR sbrk_morecore PARAMS ((struct mdesc *, int));
-#if NEED_DECLARATION_SBRK
-extern PTR sbrk PARAMS ((int));
-#endif
-
-/* The mmalloc() package can use a single implicit malloc descriptor
-   for mmalloc/mrealloc/mfree operations which do not supply an explicit
-   descriptor.  For these operations, sbrk() is used to obtain more core
-   from the system, or return core.  This allows mmalloc() to provide
-   backwards compatibility with the non-mmap'd version. */
-
-struct mdesc *__mmalloc_default_mdp;
-
-/* Use sbrk() to get more core. */
-
-static PTR
-sbrk_morecore (mdp, size)
-  struct mdesc *mdp;
-  int size;
-{
-  PTR result;
-
-  if ((result = sbrk (size)) == (PTR) -1)
-    {
-      result = NULL;
-    }
-  else
-    {
-      mdp -> breakval += size;
-      mdp -> top += size;
-    }
-  return (result);
-}
-
-/* Initialize the default malloc descriptor if this is the first time
-   a request has been made to use the default sbrk'd region.
-
-   Since no alignment guarantees are made about the initial value returned
-   by sbrk, test the initial value and (if necessary) sbrk enough additional
-   memory to start off with alignment to BLOCKSIZE.  We actually only need
-   it aligned to an alignment suitable for any object, so this is overkill.
-   But at most it wastes just part of one BLOCKSIZE chunk of memory and
-   minimizes portability problems by avoiding us having to figure out
-   what the actual minimal alignment is.  The rest of the malloc code
-   avoids this as well, by always aligning to the minimum of the requested
-   size rounded up to a power of two, or to BLOCKSIZE.
-
-   Note that we are going to use some memory starting at this initial sbrk
-   address for the sbrk region malloc descriptor, which is a struct, so the
-   base address must be suitably aligned. */
-
-struct mdesc *
-__mmalloc_sbrk_init ()
-{
-  PTR base;
-  unsigned int adj;
-
-  base = sbrk (0);
-  adj = RESIDUAL (base, BLOCKSIZE);
-  if (adj != 0)
-    {
-      sbrk (BLOCKSIZE - adj);
-      base = sbrk (0);
-    }
-  __mmalloc_default_mdp = (struct mdesc *) sbrk (sizeof (struct mdesc));
-  memset ((char *) __mmalloc_default_mdp, 0, sizeof (struct mdesc));
-  __mmalloc_default_mdp -> morecore = sbrk_morecore;
-  __mmalloc_default_mdp -> base = base;
-  __mmalloc_default_mdp -> breakval = __mmalloc_default_mdp -> top = sbrk (0);
-  __mmalloc_default_mdp -> fd = -1;
-  return (__mmalloc_default_mdp);
-}
-
-
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 915105dd5f1..5bf79149aff 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,130 @@
+2005-10-31  Alan Modra  <amodra@bigpond.net.au>
+
+	* arm-dis.c (print_insn): Warning fix.
+
+2005-10-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerated.
+
+	* dep-in.sed: Replace " ./" with " ".
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	* All CGEN-generated sources: Regenerate.
+
+	Contribute the following changes:
+	2005-09-19  Dave Brolley  <brolley@redhat.com>
+
+	* disassemble.c (disassemble_init_for_target): Add 'break' to case for
+	bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
+	bfd_arch_m32c case.
+
+	2005-02-16  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
+	cgen_isa_mask_* to cgen_bitset_*.
+	* cgen-opc.c: Likewise.
+
+	2003-11-28  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
+	* *-dis.c: Regenerate.
+
+	2003-06-05  DJ Delorie	<dj@redhat.com>
+
+	* cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
+	it, as it may point to a reused buffer.	Set prev_isas when we
+	change cpus.
+
+	2002-12-13  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-opc.c (cgen_isa_mask_create): New support function for
+	CGEN_ISA_MASK.
+	(cgen_isa_mask_init): Ditto.
+	(cgen_isa_mask_clear): Ditto.
+	(cgen_isa_mask_add): Ditto.
+	(cgen_isa_mask_set): Ditto.
+	(cgen_isa_supported): Ditto.
+	(cgen_isa_mask_compare): Ditto.
+	(cgen_isa_mask_intersection): Ditto.
+	(cgen_isa_mask_copy): Ditto.
+	(cgen_isa_mask_combine): Ditto.
+	* cgen-dis.in (libiberty.h): #include it.
+	(isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
+	(print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
+	* Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
+	* Makefile.in: Regenerated.
+
+2005-10-27  DJ Delorie  <dj@redhat.com>
+
+	* m32c-asm.c: Regenerate.
+	* m32c-desc.c: Regenerate.
+	* m32c-desc.h: Regenerate.
+	* m32c-dis.c: Regenerate.
+	* m32c-ibld.c: Regenerate.
+	* m32c-opc.c: Regenerate.
+	* m32c-opc.h: Regenerate.
+
+2005-10-26  DJ Delorie  <dj@redhat.com>
+
+	* m32c-asm.c: Regenerate.
+	* m32c-desc.c: Regenerate.
+	* m32c-desc.h: Regenerate.
+	* m32c-dis.c: Regenerate.
+	* m32c-ibld.c: Regenerate.
+	* m32c-opc.c: Regenerate.
+	* m32c-opc.h: Regenerate.
+
+2005-10-26  Paul Brook  <paul@codesourcery.com>
+
+	* arm-dis.c (arm_opcodes): Correct "sel" entry.
+
+2005-10-26  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* m32r-asm.c: Regenerate.
+
+2005-10-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c-asm.c: Regenerate.
+	* m32c-desc.c: Regenerate.
+	* m32c-desc.h: Regenerate.
+	* m32c-dis.c: Regenerate.
+	* m32c-ibld.c: Regenerate.
+	* m32c-opc.c: Regenerate.
+	* m32c-opc.h: Regenerate.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* configure.in: Add target architecture bfd_arch_z80.
+	* configure: Regenerated.
+	* disassemble.c (disassembler)<ARCH_z80>: Add case  
+	bfd_arch_z80.
+	* z80-dis.c: New file.
+
+2005-10-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+	* po/opcodes.pot: Regenerate.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* ia64-asmtab.c: Regenerate.
+
+2005-10-21  DJ Delorie  <dj@redhat.com>
+
+	* m32c-asm.c: Regenerate.
+	* m32c-desc.c: Regenerate.
+	* m32c-desc.h: Regenerate.
+	* m32c-dis.c: Regenerate.
+	* m32c-ibld.c: Regenerate.
+	* m32c-opc.c: Regenerate.
+	* m32c-opc.h: Regenerate.
+
+2005-10-21  Nick Clifton  <nickc@redhat.com>
+
+	* bfin-dis.c: Tidy up code, removing redundant constructs.
+
 2005-10-19  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 
 	* s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 5ac0ffe2b84..4a7b3c92992 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -178,6 +178,7 @@ CFILES = \
 	xstormy16-ibld.c \
 	xstormy16-opc.c \
 	xtensa-dis.c \
+	z80-dis.c \
 	z8k-dis.c \
 	z8kgen.c
 
@@ -302,6 +303,7 @@ ALL_MACHINES = \
 	xstormy16-ibld.lo \
 	xstormy16-opc.lo \
 	xtensa-dis.lo \
+	z80-dis.lo \
 	z8k-dis.lo
 
 OFILES = @BFD_MACHINES@
@@ -574,10 +576,10 @@ dep-am: DEP
 
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
-alpha-dis.lo: alpha-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/alpha.h
-alpha-opc.lo: alpha-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h opintl.h
 arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
@@ -586,133 +588,147 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
   opintl.h arc-dis.h arc-ext.h
-arc-opc.lo: arc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
   opintl.h
-arc-ext.lo: arc-ext.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
-arm-dis.lo: arm-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h \
   $(INCDIR)/elf/reloc-macros.h
-avr-dis.lo: avr-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/avr.h
 bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-cgen-asm.lo: cgen-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h opintl.h
-cgen-dis.lo: cgen-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+  opintl.h
+cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h
-cgen-opc.lo: cgen-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
+cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
 cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h
 crx-dis.lo: crx-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/crx.h
 crx-opc.lo: crx-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/crx.h
-d10v-dis.lo: d10v-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-d10v-opc.lo: d10v-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h
-d30v-dis.lo: d30v-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-d30v-opc.lo: d30v-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h
-dlx-dis.lo: dlx-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/dlx.h
-dis-buf.lo: dis-buf.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   opintl.h
-dis-init.lo: dis-init.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H)
-disassemble.lo: disassemble.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-fr30-asm.lo: fr30-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-fr30-desc.lo: fr30-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-fr30-dis.lo: fr30-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h
-fr30-ibld.lo: fr30-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h
+fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h
-fr30-opc.lo: fr30-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
-frv-asm.lo: frv-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-frv-desc.lo: frv-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-frv-dis.lo: frv-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h
-frv-ibld.lo: frv-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h
+frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   frv-opc.h opintl.h $(INCDIR)/safe-ctype.h
-frv-opc.lo: frv-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-h8300-dis.lo: h8300-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h \
+  $(INCDIR)/elf/reloc-macros.h
+h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
-h8500-dis.lo: h8500-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h opintl.h
-hppa-dis.lo: hppa-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-i370-dis.lo: i370-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/i370.h
-i370-opc.lo: i370-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/i370.h
 i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h opintl.h
 i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
-i960-dis.lo: i960-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h \
@@ -729,308 +745,351 @@ ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h sysdep.h \
-  ./config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   ia64-asmtab.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h sysdep.h \
-  ./config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h ia64-opc-a.c \
   ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c \
   ia64-opc-x.c ia64-opc-d.c
 ia64-asmtab.lo: ia64-asmtab.c
-ip2k-asm.lo: ip2k-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ip2k-desc.lo: ip2k-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-ip2k-dis.lo: ip2k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h
-ip2k-ibld.lo: ip2k-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h
+ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h
-ip2k-opc.lo: ip2k-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-iq2000-asm.lo: iq2000-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \
-  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-iq2000-desc.lo: iq2000-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \
-  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-iq2000-dis.lo: iq2000-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
+iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \
-  opintl.h
-iq2000-ibld.lo: iq2000-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h
+iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \
-  iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h
-iq2000-opc.lo: iq2000-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
+iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
-m32c-asm.lo: m32c-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
+m32c-asm.lo: m32c-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32c-desc.h $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h \
-  cgen-ops.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-m32c-desc.lo: m32c-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/safe-ctype.h
+m32c-desc.lo: m32c-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32c-desc.h $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h \
-  cgen-ops.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-m32c-dis.lo: m32c-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
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-  cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h
-m32c-ibld.lo: m32c-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h
+m32c-ibld.lo: m32c-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/safe-ctype.h
-m32c-opc.lo: m32c-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m32c-opc.lo: m32c-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32c-desc.h $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h \
-  cgen-ops.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
-m32r-asm.lo: m32r-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-m32r-desc.lo: m32r-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-m32r-dis.lo: m32r-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h
-m32r-ibld.lo: m32r-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h \
+  opintl.h
+m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h
-m32r-opc.lo: m32r-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
-m32r-opinst.lo: m32r-opinst.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h
 m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h
-m68k-dis.lo: m68k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/floatformat.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   opintl.h $(INCDIR)/opcode/m68k.h
-m68k-opc.lo: m68k-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68k.h
-m88k-dis.lo: m88k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/m88k.h opintl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
-maxq-dis.lo: maxq-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/maxq.h
-mcore-dis.lo: mcore-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-mips-dis.lo: mips-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h \
   opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
-mips-opc.lo: mips-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mips.h
-mips16-opc.lo: mips16-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mips.h
-m10200-dis.lo: m10200-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-m10200-opc.lo: m10200-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10200.h
-m10300-dis.lo: m10300-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-m10300-opc.lo: m10300-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10300.h
 mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(BFD_H) opintl.h
 mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
-ms1-asm.lo: ms1-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ms1-desc.lo: ms1-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-ms1-dis.lo: ms1-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h
-ms1-ibld.lo: ms1-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h
+ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h
-ms1-opc.lo: ms1-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ns32k.h \
   opintl.h
-openrisc-asm.lo: openrisc-asm.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/safe-ctype.h
-openrisc-desc.lo: openrisc-desc.c sysdep.h ./config.h \
+openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-openrisc-dis.lo: openrisc-dis.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \
-  openrisc-opc.h opintl.h
-openrisc-ibld.lo: openrisc-ibld.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h
+openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/safe-ctype.h
-openrisc-opc.lo: openrisc-opc.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
+openrisc-opc.lo: openrisc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 or32-dis.lo: or32-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/or32.h \
   $(INCDIR)/safe-ctype.h
 or32-opc.lo: or32-opc.c $(INCDIR)/safe-ctype.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/or32.h
-pdp11-dis.lo: pdp11-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pdp11-dis.lo: pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/pdp11.h
 pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
-pj-dis.lo: pj-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-pj-opc.lo: pj-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h
-ppc-dis.lo: ppc-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/ppc.h
-ppc-opc.lo: ppc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/ppc.h opintl.h
 s390-mkopc.lo: s390-mkopc.c
 s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \
-  ./s390-opc.tab
+  s390-opc.tab
 s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  ./config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/s390.h
-sh-dis.lo: sh-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   sh-opc.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
 sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h sh64-opc.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 sh64-opc.lo: sh64-opc.c sh64-opc.h
-sparc-dis.lo: sparc-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h opintl.h
-sparc-opc.lo: sparc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/ansidecl.h
-tic30-dis.lo: tic30-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic30.h
 tic4x-dis.lo: tic4x-dis.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic4x.h
-tic54x-dis.lo: tic54x-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic54x.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h
-tic54x-opc.lo: tic54x-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic54x.h
-tic80-dis.lo: tic80-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-tic80-opc.lo: tic80-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/tic80.h
-v850-dis.lo: v850-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-v850-opc.lo: v850-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/v850.h opintl.h
-vax-dis.lo: vax-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-w65-dis.lo: w65-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-xstormy16-asm.lo: xstormy16-asm.c sysdep.h ./config.h \
+xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/safe-ctype.h
-xstormy16-desc.lo: xstormy16-desc.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-xstormy16-dis.lo: xstormy16-dis.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   xstormy16-opc.h opintl.h
-xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h ./config.h \
+xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/safe-ctype.h
-xstormy16-opc.lo: xstormy16-opc.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
+xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  sysdep.h ./config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  sysdep.h config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-z8k-dis.lo: z8k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+z80-dis.lo: z80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   z8k-opc.h
-z8kgen.lo: z8kgen.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index f2e8ccddbf5..718250e8588 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -400,6 +400,7 @@ CFILES = \
 	xstormy16-ibld.c \
 	xstormy16-opc.c \
 	xtensa-dis.c \
+	z80-dis.c \
 	z8k-dis.c \
 	z8kgen.c
 
@@ -524,6 +525,7 @@ ALL_MACHINES = \
 	xstormy16-ibld.lo \
 	xstormy16-opc.lo \
 	xtensa-dis.lo \
+	z80-dis.lo \
 	z8k-dis.lo
 
 OFILES = @BFD_MACHINES@
@@ -1116,10 +1118,10 @@ dep-am: DEP
 
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
-alpha-dis.lo: alpha-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/alpha.h
-alpha-opc.lo: alpha-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h opintl.h
 arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
@@ -1128,133 +1130,147 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
   opintl.h arc-dis.h arc-ext.h
-arc-opc.lo: arc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
   opintl.h
-arc-ext.lo: arc-ext.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
-arm-dis.lo: arm-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h \
   $(INCDIR)/elf/reloc-macros.h
-avr-dis.lo: avr-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/avr.h
 bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-cgen-asm.lo: cgen-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h opintl.h
-cgen-dis.lo: cgen-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+  opintl.h
+cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h
-cgen-opc.lo: cgen-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
+cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  $(INCDIR)/opcode/cgen.h
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
 cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h
 crx-dis.lo: crx-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/crx.h
 crx-opc.lo: crx-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/crx.h
-d10v-dis.lo: d10v-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-d10v-opc.lo: d10v-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h
-d30v-dis.lo: d30v-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-d30v-opc.lo: d30v-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h
-dlx-dis.lo: dlx-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/dlx.h
-dis-buf.lo: dis-buf.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   opintl.h
-dis-init.lo: dis-init.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H)
-disassemble.lo: disassemble.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-fr30-asm.lo: fr30-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-fr30-desc.lo: fr30-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-fr30-dis.lo: fr30-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h
-fr30-ibld.lo: fr30-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h
+fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h
-fr30-opc.lo: fr30-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
-frv-asm.lo: frv-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
+frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-frv-desc.lo: frv-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-frv-dis.lo: frv-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h
-frv-ibld.lo: frv-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h
+frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   frv-opc.h opintl.h $(INCDIR)/safe-ctype.h
-frv-opc.lo: frv-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-h8300-dis.lo: h8300-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h \
+  $(INCDIR)/elf/reloc-macros.h
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   $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
-h8500-dis.lo: h8500-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h opintl.h
-hppa-dis.lo: hppa-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-i370-dis.lo: i370-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/i370.h
-i370-opc.lo: i370-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/i370.h
 i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h opintl.h
 i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
-i960-dis.lo: i960-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h \
@@ -1271,309 +1287,352 @@ ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h sysdep.h \
-  ./config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   ia64-asmtab.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h sysdep.h \
-  ./config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h ia64-opc-a.c \
   ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c \
   ia64-opc-x.c ia64-opc-d.c
 ia64-asmtab.lo: ia64-asmtab.c
-ip2k-asm.lo: ip2k-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ip2k-desc.lo: ip2k-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-ip2k-dis.lo: ip2k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
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-ip2k-ibld.lo: ip2k-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h
+ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
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-ip2k-opc.lo: ip2k-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-iq2000-asm.lo: iq2000-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-iq2000-desc.lo: iq2000-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-iq2000-dis.lo: iq2000-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
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-  opintl.h
-iq2000-ibld.lo: iq2000-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h opintl.h
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \
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-iq2000-opc.lo: iq2000-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
-m32c-asm.lo: m32c-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-m32c-desc.lo: m32c-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
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+  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-m32c-dis.lo: m32c-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h
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+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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+  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
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-m32c-opc.lo: m32c-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
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   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-m32r-desc.lo: m32r-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  $(INCDIR)/xregex2.h
-m32r-dis.lo: m32r-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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 m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68hc11.h
-m68k-dis.lo: m68k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
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   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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+m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/m68k.h
-m88k-dis.lo: m88k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/m88k.h opintl.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h
-maxq-dis.lo: maxq-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/maxq.h
-mcore-dis.lo: mcore-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-mips-dis.lo: mips-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h \
   opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
-mips-opc.lo: mips-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mips.h
-mips16-opc.lo: mips16-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mips.h
-m10200-dis.lo: m10200-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-m10200-opc.lo: m10200-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10200.h
-m10300-dis.lo: m10300-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-m10300-opc.lo: m10300-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/mn10300.h
 mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(BFD_H) opintl.h
 mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
-ms1-asm.lo: ms1-asm.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h \
-  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
-ms1-desc.lo: ms1-desc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
-ms1-dis.lo: ms1-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h
-ms1-ibld.lo: ms1-ibld.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  opintl.h
+ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
-  $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \
+  $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h
-ms1-opc.lo: ms1-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
-  ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+  ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ns32k.h \
   opintl.h
-openrisc-asm.lo: openrisc-asm.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/safe-ctype.h
-openrisc-desc.lo: openrisc-desc.c sysdep.h ./config.h \
+openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-openrisc-dis.lo: openrisc-dis.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \
-  openrisc-opc.h opintl.h
-openrisc-ibld.lo: openrisc-ibld.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h
+openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/safe-ctype.h
-openrisc-opc.lo: openrisc-opc.c sysdep.h ./config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
-  $(INCDIR)/symcat.h $(INCDIR)/symcat.h openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h openrisc-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
+openrisc-opc.lo: openrisc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h openrisc-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 or32-dis.lo: or32-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/or32.h \
   $(INCDIR)/safe-ctype.h
 or32-opc.lo: or32-opc.c $(INCDIR)/safe-ctype.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/or32.h
-pdp11-dis.lo: pdp11-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pdp11-dis.lo: pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/pdp11.h
 pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
-pj-dis.lo: pj-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-pj-opc.lo: pj-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h
-ppc-dis.lo: ppc-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/ppc.h
-ppc-opc.lo: ppc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/ppc.h opintl.h
 s390-mkopc.lo: s390-mkopc.c
 s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \
-  ./s390-opc.tab
+  s390-opc.tab
 s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \
-  ./config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/s390.h
-sh-dis.lo: sh-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   sh-opc.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
 sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h ./config.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
   $(INCDIR)/ansidecl.h sh64-opc.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 sh64-opc.lo: sh64-opc.c sh64-opc.h
-sparc-dis.lo: sparc-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h opintl.h
-sparc-opc.lo: sparc-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/sparc.h $(INCDIR)/ansidecl.h
-tic30-dis.lo: tic30-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic30.h
 tic4x-dis.lo: tic4x-dis.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic4x.h
-tic54x-dis.lo: tic54x-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic54x.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h
-tic54x-opc.lo: tic54x-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   $(INCDIR)/opcode/tic54x.h
-tic80-dis.lo: tic80-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-tic80-opc.lo: tic80-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/tic80.h
-v850-dis.lo: v850-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
-v850-opc.lo: v850-opc.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/v850.h opintl.h
-vax-dis.lo: vax-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
-w65-dis.lo: w65-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-xstormy16-asm.lo: xstormy16-asm.c sysdep.h ./config.h \
+xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/safe-ctype.h
-xstormy16-desc.lo: xstormy16-desc.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
+xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
-xstormy16-dis.lo: xstormy16-dis.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   xstormy16-opc.h opintl.h
-xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h ./config.h \
+xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/safe-ctype.h
-xstormy16-opc.lo: xstormy16-opc.c sysdep.h ./config.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
+xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/ansidecl.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
-  sysdep.h ./config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  sysdep.h config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h
-z8k-dis.lo: z8k-dis.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+z80-dis.lo: z80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
+z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
   z8k-opc.h
-z8kgen.lo: z8kgen.c sysdep.h ./config.h $(INCDIR)/ansidecl.h \
+z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index e5c3742b15a..a19c077c067 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -557,7 +557,7 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
-  {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
+  {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
@@ -2854,13 +2854,13 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
       size = 2;
 
       status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
+      if (little)
+	given = (b[0]) | (b[1] << 8);
+      else
+	given = (b[1]) | (b[0] << 8);
+
       if (!status)
 	{
-	  if (little)
-	    given = (b[0]) | (b[1] << 8);
-	  else
-	    given = (b[1]) | (b[0] << 8);
-
 	  /* These bit patterns signal a four-byte Thumb
 	     instruction.  */
 	  if ((given & 0xF800) == 0xF800
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index 08f9d23c5b8..adeb7d072da 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -42,15 +42,13 @@
 
 typedef long TIword;
 
-#define HOST_LONG_WORD_SIZE (sizeof(long)*8)
-
-#define XFIELD(w,p,s) (((w)&((1<<(s))-1)<<(p))>>(p))
-
-#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
-#define MASKBITS(val, bits) (val & (( 1 << bits)-1))
-
+#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
+#define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
+#define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
+#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
 
 #include "dis-asm.h"
+
 typedef enum
 {
   c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
@@ -132,6 +130,7 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
   if (constant_formats[cf].negative)
     {
       int nb = constant_formats[cf].nbits + 1;
+
       x = x | (1 << constant_formats[cf].nbits);
       x = SIGNEXTEND (x, nb);
     }
@@ -152,13 +151,6 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
   return buf;
 }
 
-#undef SIGNEXTEND
-#undef MASKBITS
-#undef HOST_LONG_WORD_SIZE
-#define HOST_LONG_WORD_SIZE (sizeof(long)*8)
-#define SIGNEXTEND(v, n) (((long)(v) << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
-#define MASKBITS(val, bits) (val & (( 1 << bits)-1))
-
 enum machine_registers
 {
   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
@@ -228,7 +220,7 @@ static enum machine_registers decode_dregs_lo[] =
   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
 };
 
-#define dregs_lo(x) REGNAME(decode_dregs_lo[(x) & 7])
+#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
 
 /* RH(0..7).  */
 static enum machine_registers decode_dregs_hi[] =
@@ -236,7 +228,7 @@ static enum machine_registers decode_dregs_hi[] =
   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
 };
 
-#define dregs_hi(x) REGNAME(decode_dregs_hi[(x) & 7])
+#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
 
 /* R(0..7).  */
 static enum machine_registers decode_dregs[] =
@@ -244,7 +236,7 @@ static enum machine_registers decode_dregs[] =
   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
 };
 
-#define dregs(x) REGNAME(decode_dregs[(x) & 7])
+#define dregs(x) REGNAME (decode_dregs[(x) & 7])
 
 /* R BYTE(0..7).  */
 static enum machine_registers decode_dregs_byte[] =
@@ -252,8 +244,8 @@ static enum machine_registers decode_dregs_byte[] =
   REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
 };
 
-#define dregs_byte(x) REGNAME(decode_dregs_byte[(x) & 7])
-#define dregs_pair(x) REGNAME(decode_dregs_pair[(x) & 7])
+#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
+#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
 
 /* P(0..5) SP FP.  */
 static enum machine_registers decode_pregs[] =
@@ -261,12 +253,12 @@ static enum machine_registers decode_pregs[] =
   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
 };
 
-#define pregs(x)	REGNAME(decode_pregs[(x) & 7])
-#define spfp(x)		REGNAME(decode_spfp[(x) & 1])
-#define dregs_hilo(x,i)	REGNAME(decode_dregs_hilo[((i)<<3)|x])
-#define accum_ext(x)	REGNAME(decode_accum_ext[(x) & 1])
-#define accum_word(x)	REGNAME(decode_accum_word[(x) & 1])
-#define accum(x)	REGNAME(decode_accum[(x) & 1])
+#define pregs(x)	REGNAME (decode_pregs[(x) & 7])
+#define spfp(x)		REGNAME (decode_spfp[(x) & 1])
+#define dregs_hilo(x,i)	REGNAME (decode_dregs_hilo[((i) << 3)|x])
+#define accum_ext(x)	REGNAME (decode_accum_ext[(x) & 1])
+#define accum_word(x)	REGNAME (decode_accum_word[(x) & 1])
+#define accum(x)	REGNAME (decode_accum[(x) & 1])
 
 /* I(0..3).  */
 static enum machine_registers decode_iregs[] =
@@ -274,7 +266,7 @@ static enum machine_registers decode_iregs[] =
   REG_I0, REG_I1, REG_I2, REG_I3,
 };
 
-#define iregs(x) REGNAME(decode_iregs[(x) & 3])
+#define iregs(x) REGNAME (decode_iregs[(x) & 3])
 
 /* M(0..3).  */
 static enum machine_registers decode_mregs[] =
@@ -282,9 +274,9 @@ static enum machine_registers decode_mregs[] =
   REG_M0, REG_M1, REG_M2, REG_M3,
 };
 
-#define mregs(x) REGNAME(decode_mregs[(x) & 3])
-#define bregs(x) REGNAME(decode_bregs[(x) & 3])
-#define lregs(x) REGNAME(decode_lregs[(x) & 3])
+#define mregs(x) REGNAME (decode_mregs[(x) & 3])
+#define bregs(x) REGNAME (decode_bregs[(x) & 3])
+#define lregs(x) REGNAME (decode_lregs[(x) & 3])
 
 /* dregs pregs.  */
 static enum machine_registers decode_dpregs[] =
@@ -293,7 +285,7 @@ static enum machine_registers decode_dpregs[] =
   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
 };
 
-#define dpregs(x) REGNAME(decode_dpregs[(x) & 15])
+#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
 
 /* [dregs pregs].  */
 static enum machine_registers decode_gregs[] =
@@ -302,7 +294,7 @@ static enum machine_registers decode_gregs[] =
   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
 };
 
-#define gregs(x,i) REGNAME(decode_gregs[((i)<<3)|x])
+#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
 
 /* [dregs pregs (iregs mregs) (bregs lregs)].  */
 static enum machine_registers decode_regs[] =
@@ -313,7 +305,7 @@ static enum machine_registers decode_regs[] =
   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
 };
 
-#define regs(x,i) REGNAME(decode_regs[((i)<<3)|x])
+#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
 
 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
 static enum machine_registers decode_regs_lo[] =
@@ -324,7 +316,7 @@ static enum machine_registers decode_regs_lo[] =
   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
 };
 
-#define regs_lo(x,i) REGNAME(decode_regs_lo[((i)<<3)|x])
+#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
 /* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
 static enum machine_registers decode_regs_hi[] =
 {
@@ -334,7 +326,7 @@ static enum machine_registers decode_regs_hi[] =
   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
 };
 
-#define regs_hi(x,i) REGNAME(decode_regs_hi[((i)<<3)|x])
+#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
 
 static enum machine_registers decode_statbits[] =
 {
@@ -344,9 +336,9 @@ static enum machine_registers decode_statbits[] =
   REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
 };
 
-#define statbits(x)	REGNAME(decode_statbits[(x) & 31])
-#define ignore_bits(x)	REGNAME(decode_ignore_bits[(x) & 7])
-#define ccstat(x)	REGNAME(decode_ccstat[(x) & 0])
+#define statbits(x)	REGNAME (decode_statbits[(x) & 31])
+#define ignore_bits(x)	REGNAME (decode_ignore_bits[(x) & 7])
+#define ccstat(x)	REGNAME (decode_ccstat[(x) & 0])
 
 /* LC0 LC1.  */
 static enum machine_registers decode_counters[] =
@@ -354,8 +346,8 @@ static enum machine_registers decode_counters[] =
   REG_LC0, REG_LC1,
 };
 
-#define counters(x) REGNAME(decode_counters[(x) & 1])
-#define dregs2_sysregs1(x) REGNAME(decode_dregs2_sysregs1[(x) & 7])
+#define counters(x)        REGNAME (decode_counters[(x) & 1])
+#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
 
 /* [dregs pregs (iregs mregs) (bregs lregs)
    dregs2_sysregs1 open sysregs2 sysregs3].  */
@@ -371,230 +363,108 @@ static enum machine_registers decode_allregs[] =
   REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
 };
 
-#define allregs(x,i)	REGNAME(decode_allregs[((i) << 3) | x])
-#define uimm16s4(x)	fmtconst(c_uimm16s4, x, 0, outf)
-#define pcrel4(x)	fmtconst(c_pcrel4, x, pc, outf)
-#define pcrel8(x)	fmtconst(c_pcrel8, x, pc, outf)
-#define pcrel8s4(x)	fmtconst(c_pcrel8s4, x, pc, outf)
-#define pcrel10(x)	fmtconst(c_pcrel10, x, pc, outf)
-#define pcrel12(x)	fmtconst(c_pcrel12, x, pc, outf)
-#define negimm5s4(x)	fmtconst(c_negimm5s4, x, 0, outf)
-#define rimm16(x)	fmtconst(c_rimm16, x, 0, outf)
-#define huimm16(x)	fmtconst(c_huimm16, x, 0, outf)
-#define imm16(x)	fmtconst(c_imm16, x, 0, outf)
-#define uimm2(x)	fmtconst(c_uimm2, x, 0, outf)
-#define uimm3(x)	fmtconst(c_uimm3, x, 0, outf)
-#define luimm16(x)	fmtconst(c_luimm16, x, 0, outf)
-#define uimm4(x)	fmtconst(c_uimm4, x, 0, outf)
-#define uimm5(x)	fmtconst(c_uimm5, x, 0, outf)
-#define imm16s2(x)	fmtconst(c_imm16s2, x, 0, outf)
-#define uimm8(x)	fmtconst(c_uimm8, x, 0, outf)
-#define imm16s4(x)	fmtconst(c_imm16s4, x, 0, outf)
-#define uimm4s2(x)	fmtconst(c_uimm4s2, x, 0, outf)
-#define uimm4s4(x)	fmtconst(c_uimm4s4, x, 0, outf)
-#define lppcrel10(x)	fmtconst(c_lppcrel10, x, pc, outf)
-#define imm3(x)		fmtconst(c_imm3, x, 0, outf)
-#define imm4(x)		fmtconst(c_imm4, x, 0, outf)
-#define uimm8s4(x)	fmtconst(c_uimm8s4, x, 0, outf)
-#define imm5(x)		fmtconst(c_imm5, x, 0, outf)
-#define imm6(x)		fmtconst(c_imm6, x, 0, outf)
-#define imm7(x)		fmtconst(c_imm7, x, 0, outf)
-#define imm8(x)		fmtconst(c_imm8, x, 0, outf)
-#define pcrel24(x)	fmtconst(c_pcrel24, x, pc, outf)
-#define uimm16(x)	fmtconst(c_uimm16, x, 0, outf)
+#define allregs(x,i)	REGNAME (decode_allregs[((i) << 3) | x])
+#define uimm16s4(x)	fmtconst (c_uimm16s4, x, 0, outf)
+#define pcrel4(x)	fmtconst (c_pcrel4, x, pc, outf)
+#define pcrel8(x)	fmtconst (c_pcrel8, x, pc, outf)
+#define pcrel8s4(x)	fmtconst (c_pcrel8s4, x, pc, outf)
+#define pcrel10(x)	fmtconst (c_pcrel10, x, pc, outf)
+#define pcrel12(x)	fmtconst (c_pcrel12, x, pc, outf)
+#define negimm5s4(x)	fmtconst (c_negimm5s4, x, 0, outf)
+#define rimm16(x)	fmtconst (c_rimm16, x, 0, outf)
+#define huimm16(x)	fmtconst (c_huimm16, x, 0, outf)
+#define imm16(x)	fmtconst (c_imm16, x, 0, outf)
+#define uimm2(x)	fmtconst (c_uimm2, x, 0, outf)
+#define uimm3(x)	fmtconst (c_uimm3, x, 0, outf)
+#define luimm16(x)	fmtconst (c_luimm16, x, 0, outf)
+#define uimm4(x)	fmtconst (c_uimm4, x, 0, outf)
+#define uimm5(x)	fmtconst (c_uimm5, x, 0, outf)
+#define imm16s2(x)	fmtconst (c_imm16s2, x, 0, outf)
+#define uimm8(x)	fmtconst (c_uimm8, x, 0, outf)
+#define imm16s4(x)	fmtconst (c_imm16s4, x, 0, outf)
+#define uimm4s2(x)	fmtconst (c_uimm4s2, x, 0, outf)
+#define uimm4s4(x)	fmtconst (c_uimm4s4, x, 0, outf)
+#define lppcrel10(x)	fmtconst (c_lppcrel10, x, pc, outf)
+#define imm3(x)		fmtconst (c_imm3, x, 0, outf)
+#define imm4(x)		fmtconst (c_imm4, x, 0, outf)
+#define uimm8s4(x)	fmtconst (c_uimm8s4, x, 0, outf)
+#define imm5(x)		fmtconst (c_imm5, x, 0, outf)
+#define imm6(x)		fmtconst (c_imm6, x, 0, outf)
+#define imm7(x)		fmtconst (c_imm7, x, 0, outf)
+#define imm8(x)		fmtconst (c_imm8, x, 0, outf)
+#define pcrel24(x)	fmtconst (c_pcrel24, x, pc, outf)
+#define uimm16(x)	fmtconst (c_uimm16, x, 0, outf)
 
 /* (arch.pm)arch_disassembler_functions.  */
-#define notethat(x)
-
 #ifndef OUTS
-#define OUTS(p,txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
+#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
 #endif
 
-
 static void
 amod0 (int s0, int x0, disassemble_info *outf)
 {
-  if (s0 == 0 && x0 == 0)
-    {
-      notethat ("(NS)");
-      return;
-    }
-  else if (s0 == 1 && x0 == 0)
-    {
-      notethat ("(S)");
-      OUTS (outf, "(S)");
-      return;
-    }
+  if (s0 == 1 && x0 == 0)
+    OUTS (outf, "(S)");
   else if (s0 == 0 && x0 == 1)
-    {
-      notethat ("(CO)");
-      OUTS (outf, "(CO)");
-      return;
-    }
+    OUTS (outf, "(CO)");
   else if (s0 == 1 && x0 == 1)
-    {
-      notethat ("(SCO)");
-      OUTS (outf, "(SCO)");
-      return;
-    }
-  else
-    goto illegal_instruction;
-illegal_instruction:
-  return;
+    OUTS (outf, "(SCO)");
 }
 
 static void
 amod1 (int s0, int x0, disassemble_info *outf)
 {
   if (s0 == 0 && x0 == 0)
-    {
-      notethat ("(NS)");
-      OUTS (outf, "(NS)");
-      return;
-    }
+    OUTS (outf, "(NS)");
   else if (s0 == 1 && x0 == 0)
-    {
-      notethat ("(S)");
-      OUTS (outf, "(S)");
-      return;
-    }
-  else
-    goto illegal_instruction;
-illegal_instruction:
-  return;
+    OUTS (outf, "(S)");
 }
 
 static void
 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
 {
-  if (s0 == 0 && x0 == 0 && aop0 == 0)
-    {
-      notethat ("(NS)");
-      return;
-    }
-  else if (s0 == 1 && x0 == 0 && aop0 == 0)
-    {
-      notethat ("(S)");
-      OUTS (outf, "(S)");
-      return;
-    }
+  if (s0 == 1 && x0 == 0 && aop0 == 0)
+    OUTS (outf, "(S)");
   else if (s0 == 0 && x0 == 1 && aop0 == 0)
-    {
-      notethat ("(CO)");
-      OUTS (outf, "(CO)");
-      return;
-    }
+    OUTS (outf, "(CO)");
   else if (s0 == 1 && x0 == 1 && aop0 == 0)
-    {
-      notethat ("(SCO)");
-      OUTS (outf, "(SCO)");
-      return;
-    }
+    OUTS (outf, "(SCO)");
   else if (s0 == 0 && x0 == 0 && aop0 == 2)
-    {
-      notethat ("(ASR)");
-      OUTS (outf, "(ASR)");
-      return;
-    }
+    OUTS (outf, "(ASR)");
   else if (s0 == 1 && x0 == 0 && aop0 == 2)
-    {
-      notethat ("(S,ASR)");
-      OUTS (outf, "(S,ASR)");
-      return;
-    }
+    OUTS (outf, "(S,ASR)");
   else if (s0 == 0 && x0 == 1 && aop0 == 2)
-    {
-      notethat ("(CO,ASR)");
-      OUTS (outf, "(CO,ASR)");
-      return;
-    }
+    OUTS (outf, "(CO,ASR)");
   else if (s0 == 1 && x0 == 1 && aop0 == 2)
-    {
-      notethat ("(SCO,ASR)");
-      OUTS (outf, "(SCO,ASR)");
-      return;
-    }
+    OUTS (outf, "(SCO,ASR)");
   else if (s0 == 0 && x0 == 0 && aop0 == 3)
-    {
-      notethat ("(ASL)");
-      OUTS (outf, "(ASL)");
-      return;
-    }
+    OUTS (outf, "(ASL)");
   else if (s0 == 1 && x0 == 0 && aop0 == 3)
-    {
-      notethat ("(S,ASL)");
-      OUTS (outf, "(S,ASL)");
-      return;
-    }
+    OUTS (outf, "(S,ASL)");
   else if (s0 == 0 && x0 == 1 && aop0 == 3)
-    {
-      notethat ("(CO,ASL)");
-      OUTS (outf, "(CO,ASL)");
-      return;
-    }
+    OUTS (outf, "(CO,ASL)");
   else if (s0 == 1 && x0 == 1 && aop0 == 3)
-    {
-      notethat ("(SCO,ASL)");
-      OUTS (outf, "(SCO,ASL)");
-      return;
-    }
-  else
-    goto illegal_instruction;
-illegal_instruction:
-  return;
+    OUTS (outf, "(SCO,ASL)");
 }
 
 static void
 searchmod (int r0, disassemble_info *outf)
 {
-  if ((r0 == 0))
-    {
-      notethat ("GT");
-      OUTS (outf, "GT");
-      return;
-    }
-  else if ((r0 == 1))
-    {
-      notethat ("GE");
-      OUTS (outf, "GE");
-      return;
-    }
-  else if ((r0 == 2))
-    {
-      notethat ("LT");
-      OUTS (outf, "LT");
-      return;
-    }
-  else if ((r0 == 3))
-    {
-      notethat ("LE");
-      OUTS (outf, "LE");
-      return;
-    }
-  else
-    goto illegal_instruction;
-illegal_instruction:
-  return;
+  if (r0 == 0)
+    OUTS (outf, "GT");
+  else if (r0 == 1)
+    OUTS (outf, "GE");
+  else if (r0 == 2)
+    OUTS (outf, "LT");
+  else if (r0 == 3)
+    OUTS (outf, "LE");
 }
 
 static void
 aligndir (int r0, disassemble_info *outf)
 {
-  if ((r0 == 0))
-    {
-      notethat ("");
-      return;
-    }
-  else if ((r0 == 1))
-    {
-      notethat ("(R)");
-      OUTS (outf, "(R)");
-      return;
-    }
-  else
-    goto illegal_instruction;
-illegal_instruction:
-  return;
+  if (r0 == 1)
+    OUTS (outf, "(R)");
 }
 
 static int
@@ -637,15 +507,10 @@ decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemb
 
   switch (op)
     {
-    case 0:
-      sop = "=";
-      break;
-    case 1:
-      sop = "+=";
-      break;
-    case 2:
-      sop = "-=";
-      break;
+    case 0: sop = "=";   break;
+    case 1: sop = "+=";  break;
+    case 2: sop = "-=";  break;
+    default: break;
     }
 
   OUTS (outf, a);
@@ -673,7 +538,7 @@ decode_optmode (int mod, int MM, disassemble_info *outf)
 
   if (MM)
     OUTS (outf, "M, ");
-  
+
   if (mod == M_S2RND)
     OUTS (outf, "S2RND");
   else if (mod == M_T)
@@ -697,350 +562,251 @@ decode_optmode (int mod, int MM, disassemble_info *outf)
 
   OUTS (outf, ")");
 }
+
 static int
 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
 {
-/* ProgCtrl
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* ProgCtrl
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
   int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
 
   if (prgfunc == 0 && poprnd == 0)
-    {
-      notethat ("NOP");
-      OUTS (outf, "NOP");
-      return 1 * 2;
-    }
+    OUTS (outf, "NOP");
   else if (prgfunc == 1 && poprnd == 0)
-    {
-      notethat ("RTS");
-      OUTS (outf, "RTS");
-      return 1 * 2;
-    }
+    OUTS (outf, "RTS");
   else if (prgfunc == 1 && poprnd == 1)
-    {
-      notethat ("RTI");
-      OUTS (outf, "RTI");
-      return 1 * 2;
-    }
+    OUTS (outf, "RTI");
   else if (prgfunc == 1 && poprnd == 2)
-    {
-      notethat ("RTX");
-      OUTS (outf, "RTX");
-      return 1 * 2;
-    }
+    OUTS (outf, "RTX");
   else if (prgfunc == 1 && poprnd == 3)
-    {
-      notethat ("RTN");
-      OUTS (outf, "RTN");
-      return 1 * 2;
-    }
+    OUTS (outf, "RTN");
   else if (prgfunc == 1 && poprnd == 4)
-    {
-      notethat ("RTE");
-      OUTS (outf, "RTE");
-      return 1 * 2;
-    }
+    OUTS (outf, "RTE");
   else if (prgfunc == 2 && poprnd == 0)
-    {
-      notethat ("IDLE");
-      OUTS (outf, "IDLE");
-      return 1 * 2;
-    }
+    OUTS (outf, "IDLE");
   else if (prgfunc == 2 && poprnd == 3)
-    {
-      notethat ("CSYNC");
-      OUTS (outf, "CSYNC");
-      return 1 * 2;
-    }
+    OUTS (outf, "CSYNC");
   else if (prgfunc == 2 && poprnd == 4)
-    {
-      notethat ("SSYNC");
-      OUTS (outf, "SSYNC");
-      return 1 * 2;
-    }
+    OUTS (outf, "SSYNC");
   else if (prgfunc == 2 && poprnd == 5)
-    {
-      notethat ("EMUEXCPT");
-      OUTS (outf, "EMUEXCPT");
-      return 1 * 2;
-    }
+    OUTS (outf, "EMUEXCPT");
   else if (prgfunc == 3)
     {
-      notethat ("CLI dregs");
       OUTS (outf, "CLI  ");
       OUTS (outf, dregs (poprnd));
-      return 1 * 2;
     }
   else if (prgfunc == 4)
     {
-      notethat ("STI dregs");
       OUTS (outf, "STI  ");
       OUTS (outf, dregs (poprnd));
-      return 1 * 2;
     }
   else if (prgfunc == 5)
     {
-      notethat ("JUMP ( pregs )");
       OUTS (outf, "JUMP  (");
       OUTS (outf, pregs (poprnd));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (prgfunc == 6)
     {
-      notethat ("CALL ( pregs )");
       OUTS (outf, "CALL  (");
       OUTS (outf, pregs (poprnd));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (prgfunc == 7)
     {
-      notethat ("CALL ( PC + pregs )");
       OUTS (outf, "CALL  (PC+");
       OUTS (outf, pregs (poprnd));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (prgfunc == 8)
     {
-      notethat ("JUMP ( PC + pregs )");
       OUTS (outf, "JUMP  (PC+");
       OUTS (outf, pregs (poprnd));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (prgfunc == 9)
     {
-      notethat ("RAISE uimm4");
       OUTS (outf, "RAISE  ");
       OUTS (outf, uimm4 (poprnd));
-      return 1 * 2;
     }
   else if (prgfunc == 10)
     {
-      notethat ("EXCPT uimm4");
       OUTS (outf, "EXCPT  ");
       OUTS (outf, uimm4 (poprnd));
-      return 1 * 2;
     }
   else if (prgfunc == 11)
     {
-      notethat ("TESTSET ( pregs )");
       OUTS (outf, "TESTSET  (");
       OUTS (outf, pregs (poprnd));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
 {
-/* CaCTRL
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* CaCTRL
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
   int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
   int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
 
   if (a == 0 && op == 0)
     {
-      notethat ("PREFETCH [ pregs ]");
       OUTS (outf, "PREFETCH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (a == 0 && op == 1)
     {
-      notethat ("FLUSHINV [ pregs ]");
       OUTS (outf, "FLUSHINV[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (a == 0 && op == 2)
     {
-      notethat ("FLUSH [ pregs ]");
       OUTS (outf, "FLUSH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (a == 0 && op == 3)
     {
-      notethat ("IFLUSH [ pregs ]");
       OUTS (outf, "IFLUSH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (a == 1 && op == 0)
     {
-      notethat ("PREFETCH [ pregs ++ ]");
       OUTS (outf, "PREFETCH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (a == 1 && op == 1)
     {
-      notethat ("FLUSHINV [ pregs ++ ]");
       OUTS (outf, "FLUSHINV[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (a == 1 && op == 2)
     {
-      notethat ("FLUSH [ pregs ++ ]");
       OUTS (outf, "FLUSH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (a == 1 && op == 3)
     {
-      notethat ("IFLUSH [ pregs ++ ]");
       OUTS (outf, "IFLUSH[");
       OUTS (outf, pregs (reg));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
 {
-
-/* PushPopReg
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* PushPopReg
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
   int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
   int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
 
   if (W == 0)
     {
-      notethat ("allregs = [ SP ++ ]");
       OUTS (outf, allregs (reg, grp));
       OUTS (outf, " = [SP++]");
-      return 1 * 2;
     }
   else if (W == 1)
     {
-      notethat ("[ -- SP ] = allregs");
       OUTS (outf, "[--SP] = ");
       OUTS (outf, allregs (reg, grp));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
 {
-/* PushPopMultiple
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* PushPopMultiple
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
   int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
   int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
   int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
   int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
-
   char ps[5], ds[5];
+
   sprintf (ps, "%d", pr);
   sprintf (ds, "%d", dr);
 
   if (W == 1 && d == 1 && p == 1)
     {
-      notethat ("[ -- SP ] = ( R7 : reglim , P5 : reglim )");
       OUTS (outf, "[--SP] = (R7:");
       OUTS (outf, ds);
       OUTS (outf, ", P5:");
       OUTS (outf, ps);
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (W == 1 && d == 1 && p == 0)
     {
-      notethat ("[ -- SP ] = ( R7 : reglim )");
       OUTS (outf, "[--SP] = (R7:");
       OUTS (outf, ds);
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (W == 1 && d == 0 && p == 1)
     {
-      notethat ("[ -- SP ] = ( P5 : reglim )");
       OUTS (outf, "[--SP] = (P5:");
       OUTS (outf, ps);
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (W == 0 && d == 1 && p == 1)
     {
-      notethat ("( R7 : reglim , P5 : reglim ) = [ SP ++ ]");
       OUTS (outf, "(R7:");
       OUTS (outf, ds);
       OUTS (outf, ", P5:");
       OUTS (outf, ps);
       OUTS (outf, ") = [SP++]");
-      return 1 * 2;
     }
   else if (W == 0 && d == 1 && p == 0)
     {
-      notethat ("( R7 : reglim ) = [ SP ++ ]");
       OUTS (outf, "(R7:");
       OUTS (outf, ds);
       OUTS (outf, ") = [SP++]");
-      return 1 * 2;
     }
   else if (W == 0 && d == 0 && p == 1)
     {
-      notethat ("( P5 : reglim ) = [ SP ++ ]");
       OUTS (outf, "(P5:");
       OUTS (outf, ps);
       OUTS (outf, ") = [SP++]");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
 {
-/* ccMV
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* ccMV
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
   int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
   int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
@@ -1049,36 +815,30 @@ decode_ccMV_0 (TIword iw0, disassemble_info *outf)
 
   if (T == 1)
     {
-      notethat ("IF CC gregs = gregs");
       OUTS (outf, "IF CC ");
       OUTS (outf, gregs (dst, d));
       OUTS (outf, " = ");
       OUTS (outf, gregs (src, s));
-      return 1 * 2;
     }
   else if (T == 0)
     {
-      notethat ("IF ! CC gregs = gregs");
       OUTS (outf, "IF ! CC ");
       OUTS (outf, gregs (dst, d));
       OUTS (outf, " = ");
       OUTS (outf, gregs (src, s));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
 {
-/* CCflag
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* CCflag
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
   int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
   int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
@@ -1087,739 +847,588 @@ decode_CCflag_0 (TIword iw0, disassemble_info *outf)
 
   if (opc == 0 && I == 0 && G == 0)
     {
-      notethat ("CC = dregs == dregs");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "==");
       OUTS (outf, dregs (y));
-      return 1 * 2;
     }
   else if (opc == 1 && I == 0 && G == 0)
     {
-      notethat ("CC = dregs < dregs");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<");
       OUTS (outf, dregs (y));
-      return 1 * 2;
     }
   else if (opc == 2 && I == 0 && G == 0)
     {
-      notethat ("CC = dregs <= dregs");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<=");
       OUTS (outf, dregs (y));
-      return 1 * 2;
     }
   else if (opc == 3 && I == 0 && G == 0)
     {
-      notethat ("CC = dregs < dregs ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<");
       OUTS (outf, dregs (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 4 && I == 0 && G == 0)
     {
-      notethat ("CC = dregs <= dregs ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<=");
       OUTS (outf, dregs (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 0 && I == 1 && G == 0)
     {
-      notethat ("CC = dregs == imm3");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "==");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 1 && I == 1 && G == 0)
     {
-      notethat ("CC = dregs < imm3");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 2 && I == 1 && G == 0)
     {
-      notethat ("CC = dregs <= imm3");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<=");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 3 && I == 1 && G == 0)
     {
-      notethat ("CC = dregs < uimm3 ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<");
       OUTS (outf, uimm3 (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 4 && I == 1 && G == 0)
     {
-      notethat ("CC = dregs <= uimm3 ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (x));
       OUTS (outf, "<=");
       OUTS (outf, uimm3 (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 0 && I == 0 && G == 1)
     {
-      notethat ("CC = pregs == pregs");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "==");
       OUTS (outf, pregs (y));
-      return 1 * 2;
     }
   else if (opc == 1 && I == 0 && G == 1)
     {
-      notethat ("CC = pregs < pregs");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<");
       OUTS (outf, pregs (y));
-      return 1 * 2;
     }
   else if (opc == 2 && I == 0 && G == 1)
     {
-      notethat ("CC = pregs <= pregs");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<=");
       OUTS (outf, pregs (y));
-      return 1 * 2;
     }
   else if (opc == 3 && I == 0 && G == 1)
     {
-      notethat ("CC = pregs < pregs ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<");
       OUTS (outf, pregs (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 4 && I == 0 && G == 1)
     {
-      notethat ("CC = pregs <= pregs ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<=");
       OUTS (outf, pregs (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 0 && I == 1 && G == 1)
     {
-      notethat ("CC = pregs == imm3");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "==");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 1 && I == 1 && G == 1)
     {
-      notethat ("CC = pregs < imm3");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 2 && I == 1 && G == 1)
     {
-      notethat ("CC = pregs <= imm3");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<=");
       OUTS (outf, imm3 (y));
-      return 1 * 2;
     }
   else if (opc == 3 && I == 1 && G == 1)
     {
-      notethat ("CC = pregs < uimm3 ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<");
       OUTS (outf, uimm3 (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 4 && I == 1 && G == 1)
     {
-      notethat ("CC = pregs <= uimm3 ( IU )");
       OUTS (outf, "CC=");
       OUTS (outf, pregs (x));
       OUTS (outf, "<=");
       OUTS (outf, uimm3 (y));
       OUTS (outf, "(IU)");
-      return 1 * 2;
     }
   else if (opc == 5 && I == 0 && G == 0)
-    {
-      notethat ("CC = A0 == A1");
-      OUTS (outf, "CC=A0==A1");
-      return 1 * 2;
-    }
+    OUTS (outf, "CC=A0==A1");
+
   else if (opc == 6 && I == 0 && G == 0)
-    {
-      notethat ("CC = A0 < A1");
-      OUTS (outf, "CC=A0<A1");
-      return 1 * 2;
-    }
+    OUTS (outf, "CC=A0<A1");
+
   else if (opc == 7 && I == 0 && G == 0)
-    {
-      notethat ("CC = A0 <= A1");
-      OUTS (outf, "CC=A0<=A1");
-      return 1 * 2;
-    }
+    OUTS (outf, "CC=A0<=A1");
+
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 2;
 }
 
 static int
 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
 {
-/* CC2dreg
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* CC2dreg
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
   int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
 
   if (op == 0)
     {
-      notethat ("dregs = CC");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=CC");
-      return 1 * 2;
     }
   else if (op == 1)
     {
-      notethat ("CC = dregs");
       OUTS (outf, "CC=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (op == 3)
-    {
-      notethat ("CC =! CC");
-      OUTS (outf, "CC=!CC");
-      return 1 * 2;
-    }
+    OUTS (outf, "CC=!CC");
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
 {
-/* CC2stat
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* CC2stat
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
   int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
   int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
 
   if (op == 0 && D == 0)
     {
-      notethat ("CC = statbits");
       OUTS (outf, "CC = ");
       OUTS (outf, statbits (cbit));
-      return 1 * 2;
     }
   else if (op == 1 && D == 0)
     {
-      notethat ("CC |= statbits");
       OUTS (outf, "CC|=");
       OUTS (outf, statbits (cbit));
-      return 1 * 2;
     }
   else if (op == 2 && D == 0)
     {
-      notethat ("CC &= statbits");
       OUTS (outf, "CC&=");
       OUTS (outf, statbits (cbit));
-      return 1 * 2;
     }
   else if (op == 3 && D == 0)
     {
-      notethat ("CC ^= statbits");
       OUTS (outf, "CC^=");
       OUTS (outf, statbits (cbit));
-      return 1 * 2;
     }
   else if (op == 0 && D == 1)
     {
-      notethat ("statbits = CC");
       OUTS (outf, statbits (cbit));
       OUTS (outf, "=CC");
-      return 1 * 2;
     }
   else if (op == 1 && D == 1)
     {
-      notethat ("statbits |= CC");
       OUTS (outf, statbits (cbit));
       OUTS (outf, "|=CC");
-      return 1 * 2;
     }
   else if (op == 2 && D == 1)
     {
-      notethat ("statbits &= CC");
       OUTS (outf, statbits (cbit));
       OUTS (outf, "&=CC");
-      return 1 * 2;
     }
   else if (op == 3 && D == 1)
     {
-      notethat ("statbits ^= CC");
       OUTS (outf, statbits (cbit));
       OUTS (outf, "^=CC");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
 {
-/* BRCC
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* BRCC
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
   int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
   int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
 
   if (T == 1 && B == 1)
     {
-      notethat ("IF CC JUMP pcrel10 ( BP )");
       OUTS (outf, "IF CC JUMP ");
       OUTS (outf, pcrel10 (offset));
       OUTS (outf, "(BP)");
-      return 1 * 2;
     }
   else if (T == 0 && B == 1)
     {
-      notethat ("IF !CC JUMP pcrel10 ( BP )");
       OUTS (outf, "IF ! CC JUMP ");
       OUTS (outf, pcrel10 (offset));
       OUTS (outf, "(BP)");
-      return 1 * 2;
     }
   else if (T == 1)
     {
-      notethat ("IF CC JUMP pcrel10");
       OUTS (outf, "IF CC JUMP ");
       OUTS (outf, pcrel10 (offset));
-      return 1 * 2;
     }
   else if (T == 0)
     {
-      notethat ("IF !CC JUMP pcrel10");
       OUTS (outf, "IF ! CC JUMP ");
       OUTS (outf, pcrel10 (offset));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
 {
-/* UJUMP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 1 | 0 |.offset........................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* UJUMP
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 1 | 0 |.offset........................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
 
-  notethat ("JUMP.S pcrel12");
   OUTS (outf, "JUMP.S  ");
   OUTS (outf, pcrel12 (offset));
-  return 1 * 2;
+  return 2;
 }
 
 static int
 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
 {
-/* REGMV
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* REGMV
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
   int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
   int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
   int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
 
-  notethat ("allregs = allregs");
   OUTS (outf, allregs (dst, gd));
   OUTS (outf, "=");
   OUTS (outf, allregs (src, gs));
-  return 1 * 2;
+  return 2;
 }
 
 static int
 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
 {
-/* ALU2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* ALU2op
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
   int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
   int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
 
   if (opc == 0)
     {
-      notethat ("dregs >>>= dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, ">>>=");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else if (opc == 1)
     {
-      notethat ("dregs >>= dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, ">>=");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else if (opc == 2)
     {
-      notethat ("dregs <<= dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "<<=");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else if (opc == 3)
     {
-      notethat ("dregs *= dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "*=");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else if (opc == 4)
     {
-      notethat ("dregs = (dregs + dregs) << 1");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=(");
       OUTS (outf, dregs (dst));
       OUTS (outf, "+");
       OUTS (outf, dregs (src));
       OUTS (outf, ")<<1");
-      return 1 * 2;
     }
   else if (opc == 5)
     {
-      notethat ("dregs = (dregs + dregs) << 2");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=(");
       OUTS (outf, dregs (dst));
       OUTS (outf, "+");
       OUTS (outf, dregs (src));
       OUTS (outf, ")<<2");
-      return 1 * 2;
     }
   else if (opc == 8)
     {
-      notethat ("DIVQ (dregs , dregs)");
       OUTS (outf, "DIVQ(");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, dregs (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 9)
     {
-      notethat ("DIVS (dregs , dregs)");
       OUTS (outf, "DIVS(");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, dregs (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 10)
     {
-      notethat ("dregs = dregs_lo (X)");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src));
       OUTS (outf, "(X)");
-      return 1 * 2;
     }
   else if (opc == 11)
     {
-      notethat ("dregs = dregs_lo (Z)");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src));
       OUTS (outf, "(Z)");
-      return 1 * 2;
     }
   else if (opc == 12)
     {
-      notethat ("dregs = dregs_byte (X)");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs_byte (src));
       OUTS (outf, "(X)");
-      return 1 * 2;
     }
   else if (opc == 13)
     {
-      notethat ("dregs = dregs_byte (Z)");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs_byte (src));
       OUTS (outf, "(Z)");
-      return 1 * 2;
     }
   else if (opc == 14)
     {
-      notethat ("dregs = - dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=-");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else if (opc == 15)
     {
-      notethat ("dregs = ~ dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=~");
       OUTS (outf, dregs (src));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
 {
-/* PTR2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* PTR2op
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
   int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
   int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
 
   if (opc == 0)
     {
-      notethat ("pregs -= pregs");
       OUTS (outf, pregs (dst));
       OUTS (outf, "-=");
       OUTS (outf, pregs (src));
-      return 1 * 2;
     }
   else if (opc == 1)
     {
-      notethat ("pregs = pregs << 2");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src));
       OUTS (outf, "<<2");
-      return 1 * 2;
     }
   else if (opc == 3)
     {
-      notethat ("pregs = pregs >> 2");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src));
       OUTS (outf, ">>2");
-      return 1 * 2;
     }
   else if (opc == 4)
     {
-      notethat ("pregs = pregs >> 1");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src));
       OUTS (outf, ">>1");
-      return 1 * 2;
     }
   else if (opc == 5)
     {
-      notethat ("pregs += pregs ( BREV )");
       OUTS (outf, pregs (dst));
       OUTS (outf, "+=");
       OUTS (outf, pregs (src));
       OUTS (outf, "(BREV)");
-      return 1 * 2;
     }
   else if (opc == 6)
     {
-      notethat ("pregs = (pregs + pregs) << 1");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=(");
       OUTS (outf, pregs (dst));
       OUTS (outf, "+");
       OUTS (outf, pregs (src));
       OUTS (outf, ")<<1");
-      return 1 * 2;
     }
   else if (opc == 7)
     {
-      notethat ("pregs = (pregs + pregs) << 2");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=(");
       OUTS (outf, pregs (dst));
       OUTS (outf, "+");
       OUTS (outf, pregs (src));
       OUTS (outf, ")<<2");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
 {
-/* LOGI2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LOGI2op
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
   int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
   int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
 
   if (opc == 0)
     {
-      notethat ("CC = ! BITTST ( dregs , uimm5 )");
       OUTS (outf, "CC = ! BITTST (");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, uimm5 (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 1)
     {
-      notethat ("CC = BITTST ( dregs , uimm5 )");
       OUTS (outf, "CC = BITTST (");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, uimm5 (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 2)
     {
-      notethat ("BITSET ( dregs , uimm5 )");
       OUTS (outf, "BITSET (");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, uimm5 (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 3)
     {
-      notethat ("BITTGL ( dregs , uimm5 )");
       OUTS (outf, "BITTGL (");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, uimm5 (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 4)
     {
-      notethat ("BITCLR ( dregs , uimm5 )");
       OUTS (outf, "BITCLR (");
       OUTS (outf, dregs (dst));
       OUTS (outf, ",");
       OUTS (outf, uimm5 (src));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (opc == 5)
     {
-      notethat ("dregs >>>= uimm5");
       OUTS (outf, dregs (dst));
       OUTS (outf, ">>>=");
       OUTS (outf, uimm5 (src));
-      return 1 * 2;
     }
   else if (opc == 6)
     {
-      notethat ("dregs >>= uimm5");
       OUTS (outf, dregs (dst));
       OUTS (outf, ">>=");
       OUTS (outf, uimm5 (src));
-      return 1 * 2;
     }
   else if (opc == 7)
     {
-      notethat ("dregs <<= uimm5");
       OUTS (outf, dregs (dst));
       OUTS (outf, "<<=");
       OUTS (outf, uimm5 (src));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
 {
-/* COMP3op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* COMP3op
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
   int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
   int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
@@ -1827,178 +1436,149 @@ decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
 
   if (opc == 5 && src1 == src0)
     {
-      notethat ("pregs = pregs << 1");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src0));
       OUTS (outf, "<<1");
-      return 1 * 2;
     }
   else if (opc == 1)
     {
-      notethat ("dregs = dregs - dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "-");
       OUTS (outf, dregs (src1));
-      return 1 * 2;
     }
   else if (opc == 2)
     {
-      notethat ("dregs = dregs & dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "&");
       OUTS (outf, dregs (src1));
-      return 1 * 2;
     }
   else if (opc == 3)
     {
-      notethat ("dregs = dregs | dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "|");
       OUTS (outf, dregs (src1));
-      return 1 * 2;
     }
   else if (opc == 4)
     {
-      notethat ("dregs = dregs ^ dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "^");
       OUTS (outf, dregs (src1));
-      return 1 * 2;
     }
   else if (opc == 5)
     {
-      notethat ("pregs = pregs + pregs");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src0));
       OUTS (outf, "+");
       OUTS (outf, pregs (src1));
-      return 1 * 2;
     }
   else if (opc == 6)
     {
-      notethat ("pregs = pregs + (pregs << 1)");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src0));
       OUTS (outf, "+(");
       OUTS (outf, pregs (src1));
       OUTS (outf, "<<1)");
-      return 1 * 2;
     }
   else if (opc == 7)
     {
-      notethat ("pregs = pregs + (pregs << 2)");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, pregs (src0));
       OUTS (outf, "+(");
       OUTS (outf, pregs (src1));
       OUTS (outf, "<<2)");
-      return 1 * 2;
     }
   else if (opc == 0)
     {
-      notethat ("dregs = dregs + dregs");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "+");
       OUTS (outf, dregs (src1));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
 {
-/* COMPI2opD
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* COMPI2opD
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
   int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
   int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
 
   if (op == 0)
     {
-      notethat ("dregs = imm7 (x)");
       OUTS (outf, dregs (dst));
       OUTS (outf, "=");
       OUTS (outf, imm7 (src));
       OUTS (outf, "(x)");
-      return 1 * 2;
     }
   else if (op == 1)
     {
-      notethat ("dregs += imm7");
       OUTS (outf, dregs (dst));
       OUTS (outf, "+=");
       OUTS (outf, imm7 (src));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
 {
-/* COMPI2opP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* COMPI2opP
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
   int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
   int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
 
   if (op == 0)
     {
-      notethat ("pregs = imm7");
       OUTS (outf, pregs (dst));
       OUTS (outf, "=");
       OUTS (outf, imm7 (src));
-      return 1 * 2;
     }
   else if (op == 1)
     {
-      notethat ("pregs += imm7");
       OUTS (outf, pregs (dst));
       OUTS (outf, "+=");
       OUTS (outf, imm7 (src));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
 {
-/* LDSTpmod
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDSTpmod
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
   int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
   int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
@@ -2007,142 +1587,117 @@ decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
 
   if (aop == 1 && W == 0 && idx == ptr)
     {
-      notethat ("dregs_lo = W [ pregs ]");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && W == 0 && idx == ptr)
     {
-      notethat ("dregs_hi = W [ pregs ]");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 1 && W == 1 && idx == ptr)
     {
-      notethat ("W [ pregs ] = dregs_lo");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, dregs_lo (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && W == 1 && idx == ptr)
     {
-      notethat ("W [ pregs ] = dregs_hi");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, dregs_hi (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && W == 0)
     {
-      notethat ("dregs = [ pregs ++ pregs ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 1 && W == 0)
     {
-      notethat ("dregs_lo = W [ pregs ++ pregs ]");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && W == 0)
     {
-      notethat ("dregs_hi = W [ pregs ++ pregs ]");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 3 && W == 0)
     {
-      notethat ("dregs = W [ pregs ++ pregs ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "] (Z)");
-      return 1 * 2;
     }
   else if (aop == 3 && W == 1)
     {
-      notethat ("dregs = W [ pregs ++ pregs ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "](X)");
-      return 1 * 2;
     }
   else if (aop == 0 && W == 1)
     {
-      notethat ("[ pregs ++ pregs ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && W == 1)
     {
-      notethat (" W [ pregs ++ pregs ] = dregs_lo");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]=");
       OUTS (outf, dregs_lo (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && W == 1)
     {
-      notethat (" W[ pregs ++ pregs ] = dregs_hi");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++");
       OUTS (outf, pregs (idx));
       OUTS (outf, "]=");
       OUTS (outf, dregs_hi (reg));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
 {
-/* dagMODim
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* dagMODim
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
   int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
   int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
@@ -2150,88 +1705,72 @@ decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
 
   if (op == 0 && br == 1)
     {
-      notethat ("iregs += mregs ( BREV )");
       OUTS (outf, iregs (i));
       OUTS (outf, "+=");
       OUTS (outf, mregs (m));
       OUTS (outf, "(BREV)");
-      return 1 * 2;
     }
   else if (op == 0)
     {
-      notethat ("iregs += mregs");
       OUTS (outf, iregs (i));
       OUTS (outf, "+=");
       OUTS (outf, mregs (m));
-      return 1 * 2;
     }
   else if (op == 1)
     {
-      notethat ("iregs -= mregs");
       OUTS (outf, iregs (i));
       OUTS (outf, "-=");
       OUTS (outf, mregs (m));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
 {
-/* dagMODik
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* dagMODik
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
   int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
 
   if (op == 0)
     {
-      notethat ("iregs += 2");
       OUTS (outf, iregs (i));
       OUTS (outf, "+=2");
-      return 1 * 2;
     }
   else if (op == 1)
     {
-      notethat ("iregs -= 2");
       OUTS (outf, iregs (i));
       OUTS (outf, "-=2");
-      return 1 * 2;
     }
   else if (op == 2)
     {
-      notethat ("iregs += 4");
       OUTS (outf, iregs (i));
       OUTS (outf, "+=4");
-      return 1 * 2;
     }
   else if (op == 3)
     {
-      notethat ("iregs -= 4");
       OUTS (outf, iregs (i));
       OUTS (outf, "-=4");
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
 {
-/* dspLDST
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* dspLDST
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
   int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
   int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
@@ -2240,202 +1779,161 @@ decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
 
   if (aop == 0 && W == 0 && m == 0)
     {
-      notethat ("dregs = [ iregs ++ ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (aop == 0 && W == 0 && m == 1)
     {
-      notethat ("dregs_lo = W [ iregs ++ ]");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (aop == 0 && W == 0 && m == 2)
     {
-      notethat ("dregs_hi = W [ iregs ++ ]");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (aop == 1 && W == 0 && m == 0)
     {
-      notethat ("dregs = [ iregs -- ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]");
-      return 1 * 2;
     }
   else if (aop == 1 && W == 0 && m == 1)
     {
-      notethat ("dregs_lo = W [ iregs -- ]");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]");
-      return 1 * 2;
     }
   else if (aop == 1 && W == 0 && m == 2)
     {
-      notethat ("dregs_hi = W [ iregs -- ]");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]");
-      return 1 * 2;
     }
   else if (aop == 2 && W == 0 && m == 0)
     {
-      notethat ("dregs = [ iregs ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && W == 0 && m == 1)
     {
-      notethat ("dregs_lo = W [ iregs ]");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && W == 0 && m == 2)
     {
-      notethat ("dregs_hi = W [ iregs ]");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 0 && W == 1 && m == 0)
     {
-      notethat ("[ iregs ++ ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && W == 1 && m == 1)
     {
-      notethat ("W [ iregs ++ ] = dregs_lo");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]=");
       OUTS (outf, dregs_lo (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && W == 1 && m == 2)
     {
-      notethat ("W [ iregs ++ ] = dregs_hi");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++]=");
       OUTS (outf, dregs_hi (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && W == 1 && m == 0)
     {
-      notethat ("[ iregs -- ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && W == 1 && m == 1)
     {
-      notethat ("W [ iregs -- ] = dregs_lo");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]=");
       OUTS (outf, dregs_lo (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && W == 1 && m == 2)
     {
-      notethat ("W [ iregs -- ] = dregs_hi");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "--]=");
       OUTS (outf, dregs_hi (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && W == 1 && m == 0)
     {
-      notethat ("[ iregs ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && W == 1 && m == 1)
     {
-      notethat (" W [ iregs ] = dregs_lo");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]=");
       OUTS (outf, dregs_lo (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && W == 1 && m == 2)
     {
-      notethat (" W [ iregs ] = dregs_hi");
       OUTS (outf, "W[");
       OUTS (outf, iregs (i));
       OUTS (outf, "]=");
       OUTS (outf, dregs_hi (reg));
-      return 1 * 2;
     }
   else if (aop == 3 && W == 0)
     {
-      notethat ("dregs = [ iregs ++ mregs ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++");
       OUTS (outf, mregs (m));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 3 && W == 1)
     {
-      notethat ("[ iregs ++ mregs ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, iregs (i));
       OUTS (outf, "++");
       OUTS (outf, mregs (m));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LDST_0 (TIword iw0, disassemble_info *outf)
 {
-/* LDST
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDST
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
   int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
   int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
@@ -2445,324 +1943,258 @@ decode_LDST_0 (TIword iw0, disassemble_info *outf)
 
   if (aop == 0 && sz == 0 && Z == 0 && W == 0)
     {
-      notethat ("dregs = [ pregs ++ ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
     {
-      notethat ("pregs = [ pregs ++ ]");
       OUTS (outf, pregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
     {
-      notethat ("dregs = W [ pregs ++ ] (z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++] (Z)");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
     {
-      notethat ("dregs = W [ pregs ++ ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++](X)");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
     {
-      notethat ("dregs = B [ pregs ++ ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++] (Z)");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
     {
-      notethat ("dregs = B [ pregs ++ ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++](X)");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
     {
-      notethat ("dregs = [ pregs -- ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
     {
-      notethat ("pregs = [ pregs -- ]");
       OUTS (outf, pregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
     {
-      notethat ("dregs = W [ pregs -- ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--] (Z)");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
     {
-      notethat ("dregs = W [ pregs -- ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--](X)");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
     {
-      notethat ("dregs = B [ pregs -- ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--] (Z)");
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
     {
-      notethat ("dregs = B [ pregs -- ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--](X)");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
     {
-      notethat ("dregs = [ pregs ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
     {
-      notethat ("pregs = [ pregs ]");
       OUTS (outf, pregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
     {
-      notethat ("dregs = W [ pregs ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "] (Z)");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
     {
-      notethat ("dregs = W [ pregs ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "](X)");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
     {
-      notethat ("dregs = B [ pregs ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "] (Z)");
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
     {
-      notethat ("dregs = B [ pregs ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "](X)");
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
     {
-      notethat ("[ pregs ++ ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
     {
-      notethat ("[ pregs ++ ] = pregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]=");
       OUTS (outf, pregs (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
     {
-      notethat ("W [ pregs ++ ] = dregs");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
     {
-      notethat ("B [ pregs ++ ] = dregs");
       OUTS (outf, "B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "++]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
     {
-      notethat ("[ pregs -- ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
     {
-      notethat ("[ pregs -- ] = pregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]=");
       OUTS (outf, pregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
     {
-      notethat ("W [ pregs -- ] = dregs");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
     {
-      notethat ("B [ pregs -- ] = dregs");
       OUTS (outf, "B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "--]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
     {
-      notethat ("[ pregs ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
     {
-      notethat ("[ pregs ] = pregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, pregs (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
     {
-      notethat ("W [ pregs ] = dregs");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
     {
-      notethat ("B [ pregs ] = dregs");
       OUTS (outf, "B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
 {
-/* LDSTiiFP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDSTiiFP
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
   int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
   int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
 
   if (W == 0)
     {
-      notethat ("dpregs = [ FP - negimm5s4 ]");
       OUTS (outf, dpregs (reg));
       OUTS (outf, "=[FP");
       OUTS (outf, negimm5s4 (offset));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (W == 1)
     {
-      notethat ("[ FP - negimm5s4 ] = dpregs");
       OUTS (outf, "[FP");
       OUTS (outf, negimm5s4 (offset));
       OUTS (outf, "]=");
       OUTS (outf, dpregs (reg));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
 {
-/* LDSTii
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDSTii
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
   int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
   int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
@@ -2771,62 +2203,51 @@ decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
 
   if (W == 0 && op == 0)
     {
-      notethat ("dregs = [ pregs + uimm4s4 ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s4 (offset));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (W == 0 && op == 1)
     {
-      notethat ("dregs = W [ pregs + uimm4s2 ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s2 (offset));
       OUTS (outf, "] (Z)");
-      return 1 * 2;
     }
   else if (W == 0 && op == 2)
     {
-      notethat ("dregs = W [ pregs + uimm4s2 ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s2 (offset));
       OUTS (outf, "](X)");
-      return 1 * 2;
     }
   else if (W == 0 && op == 3)
     {
-      notethat ("pregs = [ pregs + uimm4s4 ]");
       OUTS (outf, pregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s4 (offset));
       OUTS (outf, "]");
-      return 1 * 2;
     }
   else if (W == 1 && op == 0)
     {
-      notethat ("[ pregs + uimm4s4 ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s4 (offset));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (W == 1 && op == 1)
     {
-      notethat ("W [ pregs + uimm4s2 ] = dregs");
       OUTS (outf, "W");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
@@ -2835,34 +2256,30 @@ decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
       OUTS (outf, "]");
       OUTS (outf, "=");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (W == 1 && op == 3)
     {
-      notethat ("[ pregs + uimm4s4 ] = pregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, uimm4s4 (offset));
       OUTS (outf, "]=");
       OUTS (outf, pregs (reg));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
 {
-/* LoopSetup
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
-|.reg...........| - | - |.eoffset...............................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LoopSetup
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
+     |.reg...........| - | - |.eoffset...............................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
   int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
   int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
@@ -2871,7 +2288,6 @@ decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
 
   if (rop == 0)
     {
-      notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters");
       OUTS (outf, "LSETUP");
       OUTS (outf, "(");
       OUTS (outf, pcrel4 (soffset));
@@ -2879,11 +2295,9 @@ decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
       OUTS (outf, lppcrel10 (eoffset));
       OUTS (outf, ")");
       OUTS (outf, counters (c));
-      return 2 * 2;
     }
   else if (rop == 1)
     {
-      notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters = pregs");
       OUTS (outf, "LSETUP");
       OUTS (outf, "(");
       OUTS (outf, pcrel4 (soffset));
@@ -2893,11 +2307,9 @@ decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
       OUTS (outf, counters (c));
       OUTS (outf, "=");
       OUTS (outf, pregs (reg));
-      return 2 * 2;
     }
   else if (rop == 3)
     {
-      notethat ("LSETUP ( pcrel4 , lppcrel10 ) counters = pregs >> 1");
       OUTS (outf, "LSETUP");
       OUTS (outf, "(");
       OUTS (outf, pcrel4 (soffset));
@@ -2908,23 +2320,21 @@ decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
       OUTS (outf, "=");
       OUTS (outf, pregs (reg));
       OUTS (outf, ">>1");
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* LDIMMhalf
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
-|.hword.........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDIMMhalf
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
+     |.hword.........................................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
   int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
   int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
@@ -2934,111 +2344,86 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 
   if (grp == 0 && H == 0 && S == 0 && Z == 0)
     {
-      notethat ("dregs_lo = imm16");
       OUTS (outf, dregs_lo (reg));
       OUTS (outf, "=");
       OUTS (outf, imm16 (hword));
-      return 2 * 2;
     }
   else if (grp == 0 && H == 1 && S == 0 && Z == 0)
     {
-      notethat ("dregs_hi = imm16");
       OUTS (outf, dregs_hi (reg));
       OUTS (outf, "=");
       OUTS (outf, imm16 (hword));
-      return 2 * 2;
     }
   else if (grp == 0 && H == 0 && S == 1 && Z == 0)
     {
-      notethat ("dregs = imm16 (x)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=");
       OUTS (outf, imm16 (hword));
       OUTS (outf, " (X)");
-      return 2 * 2;
     }
   else if (H == 0 && S == 1 && Z == 0)
     {
-      notethat ("regs = imm16 (x)");
       OUTS (outf, regs (reg, grp));
       OUTS (outf, "=");
       OUTS (outf, imm16 (hword));
       OUTS (outf, " (X)");
-      return 2 * 2;
     }
   else if (H == 0 && S == 0 && Z == 1)
     {
-      notethat ("regs = luimm16 (Z)");
       OUTS (outf, regs (reg, grp));
       OUTS (outf, "=");
       OUTS (outf, luimm16 (hword));
       OUTS (outf, "(Z)");
-      return 2 * 2;
     }
   else if (H == 0 && S == 0 && Z == 0)
     {
-      notethat ("regs_lo = luimm16");
       OUTS (outf, regs_lo (reg, grp));
       OUTS (outf, "=");
       OUTS (outf, luimm16 (hword));
-      return 2 * 2;
     }
   else if (H == 1 && S == 0 && Z == 0)
     {
-      notethat ("regs_hi = huimm16");
       OUTS (outf, regs_hi (reg, grp));
       OUTS (outf, "=");
       OUTS (outf, huimm16 (hword));
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
 {
-/* CALLa
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
-|.lsw...........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* CALLa
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
+     |.lsw...........................................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
   int lsw = ((iw1 >> 0) & 0xffff);
   int msw = ((iw0 >> 0) & 0xff);
 
   if (S == 1)
-    {
-      notethat ("CALL  pcrel24");
-      OUTS (outf, "CALL  ");
-      OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
-      return 2 * 2;
-    }
+    OUTS (outf, "CALL  ");
   else if (S == 0)
-    {
-      notethat ("JUMP.L  pcrel24");
-      OUTS (outf, "JUMP.L  ");
-      OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
-      return 2 * 2;
-    }
+    OUTS (outf, "JUMP.L  ");
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
+  return 4;
 }
 
 static int
 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* LDSTidxI
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
-|.offset........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* LDSTidxI
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
+     |.offset........................................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
   int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
   int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
@@ -3048,174 +2433,146 @@ decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 
   if (W == 0 && sz == 0 && Z == 0)
     {
-      notethat ("dregs = [ pregs + imm16s4 ]");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s4 (offset));
       OUTS (outf, "]");
-      return 2 * 2;
     }
   else if (W == 0 && sz == 0 && Z == 1)
     {
-      notethat ("pregs = [ pregs + imm16s4 ]");
       OUTS (outf, pregs (reg));
       OUTS (outf, "=[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s4 (offset));
       OUTS (outf, "]");
-      return 2 * 2;
     }
   else if (W == 0 && sz == 1 && Z == 0)
     {
-      notethat ("dregs = W [ pregs + imm16s2 ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s2 (offset));
       OUTS (outf, "] (Z)");
-      return 2 * 2;
     }
   else if (W == 0 && sz == 1 && Z == 1)
     {
-      notethat ("dregs = W [ pregs + imm16s2 ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s2 (offset));
       OUTS (outf, "](X)");
-      return 2 * 2;
     }
   else if (W == 0 && sz == 2 && Z == 0)
     {
-      notethat ("dregs = B [ pregs + imm16 ] (Z)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16 (offset));
       OUTS (outf, "] (Z)");
-      return 2 * 2;
     }
   else if (W == 0 && sz == 2 && Z == 1)
     {
-      notethat ("dregs = B [ pregs + imm16 ] (X)");
       OUTS (outf, dregs (reg));
       OUTS (outf, "=B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16 (offset));
       OUTS (outf, "](X)");
-      return 2 * 2;
     }
   else if (W == 1 && sz == 0 && Z == 0)
     {
-      notethat ("[ pregs + imm16s4 ] = dregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s4 (offset));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 2 * 2;
     }
   else if (W == 1 && sz == 0 && Z == 1)
     {
-      notethat ("[ pregs + imm16s4 ] = pregs");
       OUTS (outf, "[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s4 (offset));
       OUTS (outf, "]=");
       OUTS (outf, pregs (reg));
-      return 2 * 2;
     }
   else if (W == 1 && sz == 1 && Z == 0)
     {
-      notethat ("W [ pregs + imm16s2 ] = dregs");
       OUTS (outf, "W[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16s2 (offset));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 2 * 2;
     }
   else if (W == 1 && sz == 2 && Z == 0)
     {
-      notethat ("B [ pregs + imm16 ] = dregs");
       OUTS (outf, "B[");
       OUTS (outf, pregs (ptr));
       OUTS (outf, "+");
       OUTS (outf, imm16 (offset));
       OUTS (outf, "]=");
       OUTS (outf, dregs (reg));
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* linkage
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
-|.framesize.....................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* linkage
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
+     |.framesize.....................................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
   int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
 
   if (R == 0)
     {
-      notethat ("LINK uimm16s4");
       OUTS (outf, "LINK ");
       OUTS (outf, uimm16s4 (framesize));
-      return 2 * 2;
     }
   else if (R == 1)
-    {
-      notethat ("UNLINK");
-      OUTS (outf, "UNLINK");
-      return 2 * 2;
-    }
+    OUTS (outf, "UNLINK");
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* dsp32mac
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
-|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-  int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
-  int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
-  int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
-  int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
+  /* dsp32mac
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
+     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
+  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
+  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
+  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
+  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
-  int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
+  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
-  int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
-  int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
-  int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
-  int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
-  int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
-  int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
+  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
+  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
+  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
+  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
+  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
+  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
 
   if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
     return 0;
@@ -3279,30 +2636,30 @@ decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 static int
 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* dsp32mult
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
-|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-  int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
-  int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
-  int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
+  /* dsp32mult
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
+     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
+  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
+  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
+  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
-  int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
+  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
-  int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
-  int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
-  int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
-  int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
-  int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
+  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
+  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
+  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
+  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
+  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
 
   if (w1 == 0 && w0 == 0)
     return 0;
+
   if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
     return 0;
-  
+
   if (w1)
     {
       OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
@@ -3332,12 +2689,11 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 static int
 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* dsp32alu
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
-|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* dsp32alu
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
+     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
   int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
   int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
@@ -3350,123 +2706,98 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 
   if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
     {
-      notethat ("A0.L = dregs_lo");
       OUTS (outf, "A0.L=");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
     {
-      notethat ("A1.H = dregs_hi");
       OUTS (outf, "A1.H=");
       OUTS (outf, dregs_hi (src0));
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
     {
-      notethat ("A1.L = dregs_lo");
       OUTS (outf, "A1.L=");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
     {
-      notethat ("A0.H = dregs_hi");
       OUTS (outf, "A0.H=");
       OUTS (outf, dregs_hi (src0));
-      return 2 * 2;
     }
   else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
     {
-      notethat ("dregs_hi = dregs - dregs (RND20)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "-");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND20)");
-      return 2 * 2;
     }
   else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
     {
-      notethat ("dregs_hi = dregs + dregs (RND20)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "+");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND20)");
-      return 2 * 2;
     }
   else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
     {
-      notethat ("dregs_lo = dregs - dregs (RND12)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "-");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND12)");
-      return 2 * 2;
     }
   else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
     {
-      notethat ("dregs_lo = dregs + dregs (RND12)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "+");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND12)");
-      return 2 * 2;
     }
   else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
     {
-      notethat ("dregs_lo = dregs - dregs (RND20)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "-");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND20)");
-      return 2 * 2;
     }
   else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
     {
-      notethat ("dregs_hi = dregs + dregs (RND12)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "+");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND12)");
-      return 2 * 2;
     }
   else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
     {
-      notethat ("dregs_lo = dregs + dregs (RND20)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "+");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND20)");
-      return 2 * 2;
     }
   else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
     {
-      notethat ("dregs_hi = dregs - dregs (RND12)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "-");
       OUTS (outf, dregs (src1));
       OUTS (outf, "(RND12)");
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 0 && aopcde == 2)
     {
-      notethat ("dregs_hi = dregs_lo + dregs_lo amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3474,11 +2805,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 1 && aopcde == 2)
     {
-      notethat ("dregs_hi = dregs_lo + dregs_hi amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3486,11 +2815,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 2 && aopcde == 2)
     {
-      notethat ("dregs_hi = dregs_hi + dregs_lo amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3498,11 +2825,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 3 && aopcde == 2)
     {
-      notethat ("dregs_hi = dregs_hi + dregs_hi amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3510,11 +2835,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 0 && aopcde == 3)
     {
-      notethat ("dregs_lo = dregs_lo - dregs_lo amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3522,11 +2845,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 1 && aopcde == 3)
     {
-      notethat ("dregs_lo = dregs_lo - dregs_hi amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3534,11 +2855,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 3 && aopcde == 2)
     {
-      notethat ("dregs_lo = dregs_hi + dregs_hi amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3546,11 +2865,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 0 && aopcde == 3)
     {
-      notethat ("dregs_hi = dregs_lo - dregs_lo amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3558,11 +2875,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 1 && aopcde == 3)
     {
-      notethat ("dregs_hi = dregs_lo - dregs_hi amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3570,11 +2885,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 2 && aopcde == 3)
     {
-      notethat ("dregs_hi = dregs_hi - dregs_lo amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3582,11 +2895,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 1 && aop == 3 && aopcde == 3)
     {
-      notethat ("dregs_hi = dregs_hi - dregs_hi amod1");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3594,11 +2905,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 2 && aopcde == 2)
     {
-      notethat ("dregs_lo = dregs_hi + dregs_lo amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3606,11 +2915,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 1 && aopcde == 2)
     {
-      notethat ("dregs_lo = dregs_lo + dregs_hi amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3618,11 +2925,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 2 && aopcde == 3)
     {
-      notethat ("dregs_lo = dregs_hi - dregs_lo amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3630,11 +2935,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 3 && aopcde == 3)
     {
-      notethat ("dregs_lo = dregs_hi - dregs_hi amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src0));
@@ -3642,11 +2945,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 0 && aopcde == 2)
     {
-      notethat ("dregs_lo = dregs_lo + dregs_lo amod1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src0));
@@ -3654,30 +2955,20 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 9 && s == 1)
     {
-      notethat ("A0 = dregs");
       OUTS (outf, "A0=");
       OUTS (outf, dregs (src0));
-      return 2 * 2;
     }
   else if (aop == 3 && aopcde == 11 && s == 0)
-    {
-      notethat ("A0 -= A1");
-      OUTS (outf, "A0-=A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0-=A1");
+
   else if (aop == 3 && aopcde == 11 && s == 1)
-    {
-      notethat ("A0 -= A1 (W32)");
-      OUTS (outf, "A0-=A1(W32)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0-=A1(W32)");
+
   else if (aop == 3 && aopcde == 22 && HL == 1)
     {
-      notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (TH , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2M(");
       OUTS (outf, dregs (src0 + 1));
@@ -3692,11 +2983,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 3 && aopcde == 22 && HL == 0)
     {
-      notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (TL , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2M(");
       OUTS (outf, dregs (src0 + 1));
@@ -3711,11 +3000,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 22 && HL == 1)
     {
-      notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (RNDH , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2M(");
       OUTS (outf, dregs (src0 + 1));
@@ -3730,11 +3017,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 22 && HL == 0)
     {
-      notethat ("dregs = BYTEOP2M ( dregs_pair , dregs_pair ) (RNDL , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2M(");
       OUTS (outf, dregs (src0 + 1));
@@ -3749,11 +3034,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 22 && HL == 1)
     {
-      notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (TH , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2P(");
       OUTS (outf, dregs (src0 + 1));
@@ -3768,11 +3051,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 22 && HL == 0)
     {
-      notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (TL , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2P(");
       OUTS (outf, dregs (src0 + 1));
@@ -3787,11 +3068,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 22 && HL == 1)
     {
-      notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (RNDH , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2P(");
       OUTS (outf, dregs (src0 + 1));
@@ -3806,11 +3085,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 22 && HL == 0)
     {
-      notethat ("dregs = BYTEOP2P ( dregs_pair , dregs_pair ) (RNDL , aligndir)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP2P(");
       OUTS (outf, dregs (src0 + 1));
@@ -3825,79 +3102,46 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && s == 0 && aopcde == 8)
-    {
-      notethat ("A0 = 0");
-      OUTS (outf, "A0=0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=0");
+
   else if (aop == 0 && s == 1 && aopcde == 8)
-    {
-      notethat ("A0 = A0 (S)");
-      OUTS (outf, "A0=A0(S)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=A0(S)");
+
   else if (aop == 1 && s == 0 && aopcde == 8)
-    {
-      notethat ("A1 = 0");
-      OUTS (outf, "A1=0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=0");
+
   else if (aop == 1 && s == 1 && aopcde == 8)
-    {
-      notethat ("A1 = A1 (S)");
-      OUTS (outf, "A1=A1(S)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=A1(S)");
+
   else if (aop == 2 && s == 0 && aopcde == 8)
-    {
-      notethat ("A1 = A0 = 0");
-      OUTS (outf, "A1=A0=0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=A0=0");
+
   else if (aop == 2 && s == 1 && aopcde == 8)
-    {
-      notethat ("A1 = A1 (S) , A0 = A0 (S)");
-      OUTS (outf, "A1=A1(S),A0=A0(S)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=A1(S),A0=A0(S)");
+
   else if (aop == 3 && s == 0 && aopcde == 8)
-    {
-      notethat ("A0 = A1");
-      OUTS (outf, "A0=A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=A1");
+
   else if (aop == 3 && s == 1 && aopcde == 8)
-    {
-      notethat ("A1 = A0");
-      OUTS (outf, "A1=A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=A0");
+
   else if (aop == 1 && aopcde == 9 && s == 0)
     {
-      notethat ("A0.x = dregs_lo");
       OUTS (outf, "A0.x=");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (aop == 1 && HL == 0 && aopcde == 11)
     {
-      notethat ("dregs_lo = ( A0 += A1 )");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=(A0+=A1)");
-      return 2 * 2;
     }
   else if (aop == 3 && HL == 0 && aopcde == 16)
-    {
-      notethat ("A1 = ABS A1, A0 = ABS A0");
-      OUTS (outf, "A1= ABS A0,A0= ABS A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1= ABS A0,A0= ABS A0");
+
   else if (aop == 0 && aopcde == 23 && HL == 1)
     {
-      notethat ("dregs = BYTEOP3P ( dregs_pair , dregs_pair ) (HI , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP3P(");
       OUTS (outf, dregs (src0 + 1));
@@ -3912,119 +3156,80 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 3 && aopcde == 9 && s == 0)
     {
-      notethat ("A1.x = dregs_lo");
       OUTS (outf, "A1.x=");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (aop == 1 && HL == 1 && aopcde == 16)
-    {
-      notethat ("A1 = ABS A1");
-      OUTS (outf, "A1= ABS A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1= ABS A1");
+
   else if (aop == 0 && HL == 1 && aopcde == 16)
-    {
-      notethat ("A1 = ABS A0");
-      OUTS (outf, "A1= ABS A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1= ABS A0");
+
   else if (aop == 2 && aopcde == 9 && s == 1)
     {
-      notethat ("A1 = dregs");
       OUTS (outf, "A1=");
       OUTS (outf, dregs (src0));
-      return 2 * 2;
     }
   else if (HL == 0 && aop == 3 && aopcde == 12)
     {
-      notethat ("dregs_lo = dregs (RND)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(RND)");
-      return 2 * 2;
     }
   else if (aop == 1 && HL == 0 && aopcde == 16)
-    {
-      notethat ("A0 = ABS A1");
-      OUTS (outf, "A0= ABS A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0= ABS A1");
+
   else if (aop == 0 && HL == 0 && aopcde == 16)
-    {
-      notethat ("A0 = ABS A0");
-      OUTS (outf, "A0= ABS A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0= ABS A0");
+
   else if (aop == 3 && HL == 0 && aopcde == 15)
     {
-      notethat ("dregs = - dregs (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=-");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(V)");
-      return 2 * 2;
     }
   else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
     {
-      notethat ("dregs = - dregs (S)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=-");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
     {
-      notethat ("dregs = - dregs (NS)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=-");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(NS)");
-      return 2 * 2;
     }
   else if (aop == 1 && HL == 1 && aopcde == 11)
     {
-      notethat ("dregs_hi = ( A0 += A1 )");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=(A0+=A1)");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 11 && s == 0)
-    {
-      notethat ("A0 += A1");
-      OUTS (outf, "A0+=A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0+=A1");
+
   else if (aop == 2 && aopcde == 11 && s == 1)
-    {
-      notethat ("A0 += A1 (W32)");
-      OUTS (outf, "A0+=A1(W32)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0+=A1(W32)");
+
   else if (aop == 3 && HL == 0 && aopcde == 14)
-    {
-      notethat ("A1 = - A1 , A0 = - A0");
-      OUTS (outf, "A1=-A1,A0=-A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=-A1,A0=-A0");
+
   else if (HL == 1 && aop == 3 && aopcde == 12)
     {
-      notethat ("dregs_hi = dregs (RND)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(RND)");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 23 && HL == 0)
     {
-      notethat ("dregs = BYTEOP3P ( dregs_pair , dregs_pair ) (LO , R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP3P(");
       OUTS (outf, dregs (src0 + 1));
@@ -4039,35 +3244,21 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && HL == 0 && aopcde == 14)
-    {
-      notethat ("A0 = - A0");
-      OUTS (outf, "A0=-A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=-A0");
+
   else if (aop == 1 && HL == 0 && aopcde == 14)
-    {
-      notethat ("A0 = - A1");
-      OUTS (outf, "A0=-A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=-A1");
+
   else if (aop == 0 && HL == 1 && aopcde == 14)
-    {
-      notethat ("A1 = - A0");
-      OUTS (outf, "A1=-A0");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=-A0");
+
   else if (aop == 1 && HL == 1 && aopcde == 14)
-    {
-      notethat ("A1 = - A1");
-      OUTS (outf, "A1=-A1");
-      return 2 * 2;
-    }
+    OUTS (outf, "A1=-A1");
+
   else if (aop == 0 && aopcde == 12)
     {
-      notethat ("dregs_hi=dregs_lo=SIGN(dregs_hi)*dregs_hi + SIGN(dregs_lo)*dregs_lo)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (dst0));
@@ -4080,11 +3271,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, ")*");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 0)
     {
-      notethat ("dregs = dregs -|+ dregs amod0");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4092,20 +3281,16 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod0 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 12)
     {
-      notethat ("dregs = A1.L + A1.H , dregs = A0.L + A0.H");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=A1.L+A1.H,");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=A0.L+A0.H");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 4)
     {
-      notethat ("dregs = dregs + dregs , dregs = dregs - dregs amod1");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4119,11 +3304,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (HL == 0 && aopcde == 1)
     {
-      notethat ("dregs = dregs +|+ dregs , dregs = dregs -|- dregs (amod0, amod2)");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4136,32 +3319,24 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, "-|-");
       OUTS (outf, dregs (src1));
       amod0amod2 (s, x, aop, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 11)
     {
-      notethat ("dregs = ( A0 += A1 )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=(A0+=A1)");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 10)
     {
-      notethat ("dregs_lo = A0.x");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=A0.x");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 10)
     {
-      notethat ("dregs_lo = A1.x");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=A1.x");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 0)
     {
-      notethat ("dregs = dregs +|- dregs amod0");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4169,11 +3344,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod0 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 3 && aopcde == 0)
     {
-      notethat ("dregs = dregs -|- dregs amod0");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4181,11 +3354,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod0 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 4)
     {
-      notethat ("dregs = dregs - dregs amod1");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4193,31 +3364,25 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 17)
     {
-      notethat ("dregs = A1 + A0, dregs = A1 - A0 amod1");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=A1+A0,");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=A1-A0 ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 17)
     {
-      notethat ("dregs = A0 + A1, dregs = A0 - A1 amod1");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=A0+A1,");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=A0-A1 ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 18)
     {
-      notethat ("SAA ( dregs_pair , dregs_pair ) aligndir");
       OUTS (outf, "SAA(");
       OUTS (outf, dregs (src0 + 1));
       OUTS (outf, ":");
@@ -4228,17 +3393,12 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, imm5 (src1));
       OUTS (outf, ") ");
       aligndir (s, outf);
-      return 2 * 2;
     }
   else if (aop == 3 && aopcde == 18)
-    {
-      notethat ("DISALGNEXCPT");
-      OUTS (outf, "DISALGNEXCPT");
-      return 2 * 2;
-    }
+    OUTS (outf, "DISALGNEXCPT");
+
   else if (aop == 0 && aopcde == 20)
     {
-      notethat ("dregs = BYTEOP1P ( dregs_pair , dregs_pair ) aligndir");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP1P(");
       OUTS (outf, dregs (src0 + 1));
@@ -4250,11 +3410,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, imm5 (src1));
       OUTS (outf, ")");
       aligndir (s, outf);
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 20)
     {
-      notethat ("dregs = BYTEOP1P ( dregs_pair , dregs_pair ) (T, R)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEOP1P(");
       OUTS (outf, dregs (src0 + 1));
@@ -4269,11 +3427,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	OUTS (outf, ", R)");
       else
 	OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 21)
     {
-      notethat ("( dregs , dregs ) = BYTEOP16P ( dregs_pair , dregs_pair ) aligndir");
       OUTS (outf, "(");
       OUTS (outf, dregs (dst1));
       OUTS (outf, ",");
@@ -4288,11 +3444,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, imm5 (src1));
       OUTS (outf, ") ");
       aligndir (s, outf);
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 21)
     {
-      notethat ("( dregs , dregs ) = BYTEOP16M ( dregs_pair , dregs_pair ) aligndir");
       OUTS (outf, "(");
       OUTS (outf, dregs (dst1));
       OUTS (outf, ",");
@@ -4307,72 +3461,58 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, imm5 (src1));
       OUTS (outf, ") ");
       aligndir (s, outf);
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 7)
     {
-      notethat ("dregs = ABS dregs");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ABS ");
       OUTS (outf, dregs (src0));
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 7)
     {
-      notethat ("dregs = MIN ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=MIN(");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 7)
     {
-      notethat ("dregs = MAX ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=MAX(");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 2 && aopcde == 6)
     {
-      notethat ("dregs = ABS dregs (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ABS ");
       OUTS (outf, dregs (src0));
       OUTS (outf, "(V)");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 6)
     {
-      notethat ("dregs = MIN ( dregs , dregs ) (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=MIN(");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ")(V)");
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 6)
     {
-      notethat ("dregs = MAX ( dregs , dregs ) (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=MAX(");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ")(V)");
-      return 2 * 2;
     }
   else if (HL == 1 && aopcde == 1)
     {
-      notethat ("dregs = dregs +|- dregs, dregs = dregs -|+ dregs (amod0, amod2)");
       OUTS (outf, dregs (dst1));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4385,11 +3525,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, "-|+");
       OUTS (outf, dregs (src1));
       amod0amod2 (s, x, aop, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 4)
     {
-      notethat ("dregs = dregs + dregs amod1");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4397,11 +3535,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod1 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 0)
     {
-      notethat ("dregs = dregs +|+ dregs amod0");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src0));
@@ -4409,22 +3545,18 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, dregs (src1));
       OUTS (outf, " ");
       amod0 (s, x, outf);
-      return 2 * 2;
     }
   else if (aop == 0 && aopcde == 24)
     {
-      notethat ("dregs = BYTEPACK ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=BYTEPACK(");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (aop == 1 && aopcde == 24)
     {
-      notethat ("( dregs , dregs ) = BYTEUNPACK dregs_pair aligndir");
       OUTS (outf, "(");
       OUTS (outf, dregs (dst1));
       OUTS (outf, ",");
@@ -4435,11 +3567,9 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, imm5 (src0));
       OUTS (outf, " ");
       aligndir (s, outf);
-      return 2 * 2;
     }
   else if (aopcde == 13)
     {
-      notethat ("( dregs , dregs ) = SEARCH dregs (searchmod)");
       OUTS (outf, "(");
       OUTS (outf, dregs (dst1));
       OUTS (outf, ",");
@@ -4449,23 +3579,21 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, "(");
       searchmod (aop, outf);
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* dsp32shift
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
-|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* dsp32shift
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
+     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
   int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
   int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
@@ -4474,218 +3602,176 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
   int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
   const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
 
-
   if (HLs == 0 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_lo = ASHIFT dregs_lo BY dregs_lo");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (HLs == 1 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_lo = ASHIFT dregs_hi BY dregs_lo");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_hi = ASHIFT dregs_lo BY dregs_lo");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_hi = ASHIFT dregs_hi BY dregs_lo");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (HLs == 0 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_lo = ASHIFT dregs_lo BY dregs_lo (S)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 1 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_lo = ASHIFT dregs_hi BY dregs_lo (S)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_hi = ASHIFT dregs_lo BY dregs_lo (S)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_hi = ASHIFT dregs_hi BY dregs_lo (S)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 0)
     {
-      notethat ("dregs_hilo = LSHIFT dregs_hilo BY dregs_lo");
       OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
       OUTS (outf, "= LSHIFT ");
       OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 3)
     {
-      notethat ("An = ASHIFT An BY dregs_lo");
       OUTS (outf, acc01);
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, acc01);
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 3)
     {
-      notethat ("An = LSHIFT An BY dregs_lo");
       OUTS (outf, acc01);
       OUTS (outf, "= LSHIFT ");
       OUTS (outf, acc01);
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 3)
     {
-      notethat ("An = ROT An BY dregs_lo");
       OUTS (outf, acc01);
       OUTS (outf, "= ROT ");
       OUTS (outf, acc01);
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 3)
     {
-      notethat ("dregs = ROT dregs BY dregs_lo");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ROT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 1)
     {
-      notethat ("dregs = ASHIFT dregs BY dregs_lo (V, S)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(V,S)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 1)
     {
-      notethat ("dregs = ASHIFT dregs BY dregs_lo (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(V)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 2)
     {
-      notethat ("dregs = ASHIFT dregs BY dregs_lo");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 2)
     {
-      notethat ("dregs = ASHIFT dregs BY dregs_lo (S)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ASHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 2)
     {
-      notethat ("dregs = SHIFT dregs BY dregs_lo");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=SHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 2)
     {
-      notethat ("dregs = ROT dregs BY dregs_lo");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ROT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 1)
     {
-      notethat ("dregs = SHIFT dregs BY dregs_lo (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=SHIFT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, "(V)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 4)
     {
-      notethat ("dregs = PACK ( dregs_lo , dregs_lo )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=PACK");
       OUTS (outf, "(");
@@ -4693,796 +3779,631 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 4)
     {
-      notethat ("dregs = PACK ( dregs_lo , dregs_hi )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=PACK(");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_hi (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 4)
     {
-      notethat ("dregs = PACK ( dregs_hi , dregs_lo )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=PACK(");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 4)
     {
-      notethat ("dregs = PACK ( dregs_hi , dregs_hi )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=PACK(");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_hi (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 5)
     {
-      notethat ("dregs_lo = SIGNBITS dregs");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=SIGNBITS ");
       OUTS (outf, dregs (src1));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 5)
     {
-      notethat ("dregs_lo = SIGNBITS dregs_lo");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=SIGNBITS ");
       OUTS (outf, dregs_lo (src1));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 5)
     {
-      notethat ("dregs_lo = SIGNBITS dregs_hi");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=SIGNBITS ");
       OUTS (outf, dregs_hi (src1));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 6)
     {
-      notethat ("dregs_lo = SIGNBITS A0");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=SIGNBITS A0");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 6)
     {
-      notethat ("dregs_lo = SIGNBITS A1");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=SIGNBITS A1");
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 6)
     {
-      notethat ("dregs_lo = ONES dregs");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=ONES ");
       OUTS (outf, dregs (src1));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 7)
     {
-      notethat ("dregs_lo = EXPADJ (dregs , dregs_lo)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=EXPADJ (");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 7)
     {
-      notethat ("dregs_lo = EXPADJ (dregs , dregs_lo) (V)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=EXPADJ (");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ") (V)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 7)
     {
-      notethat ("dregs_lo = EXPADJ (dregs_lo , dregs_lo)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=EXPADJ (");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 7)
     {
-      notethat ("dregs_lo = EXPADJ (dregs_hi , dregs_lo)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=EXPADJ (");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 8)
     {
-      notethat ("BITMUX (dregs , dregs , A0) (ASR)");
       OUTS (outf, "BITMUX (");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",A0 )(ASR)");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 8)
     {
-      notethat ("BITMUX (dregs , dregs , A0) (ASL)");
       OUTS (outf, "BITMUX (");
       OUTS (outf, dregs (src0));
       OUTS (outf, ",");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",A0 )(ASL)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 9)
     {
-      notethat ("dregs_lo = VIT_MAX (dregs) (ASL)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=VIT_MAX (");
       OUTS (outf, dregs (src1));
       OUTS (outf, ") (ASL)");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 9)
     {
-      notethat ("dregs_lo = VIT_MAX (dregs) (ASR)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=VIT_MAX (");
       OUTS (outf, dregs (src1));
       OUTS (outf, ") (ASR)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 9)
     {
-      notethat ("dregs = VIT_MAX ( dregs , dregs ) (ASL)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=VIT_MAX(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")(ASL)");
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 9)
     {
-      notethat ("dregs = VIT_MAX ( dregs , dregs ) (ASR)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=VIT_MAX(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")(ASR)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 10)
     {
-      notethat ("dregs = EXTRACT ( dregs , dregs_lo ) (Z)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=EXTRACT(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ") (Z)");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 10)
     {
-      notethat ("dregs = EXTRACT ( dregs , dregs_lo ) (X)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=EXTRACT(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs_lo (src0));
       OUTS (outf, ")(X)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 10)
     {
-      notethat ("dregs = DEPOSIT ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=DEPOSIT(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 10)
     {
-      notethat ("dregs = DEPOSIT ( dregs , dregs ) (X)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=DEPOSIT(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")(X)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 11)
     {
-      notethat ("dregs_lo = CC = BXORSHIFT ( A0 , dregs )");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=CC=BXORSHIFT(A0,");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 11)
     {
-      notethat ("dregs_lo = CC = BXOR (A0 , dregs)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=CC=BXOR(A0,");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 12)
-    {
-      notethat ("A0 = BXORSHIFT ( A0 , A1 , CC )");
-      OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)");
-      return 2 * 2;
-    }
+    OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)");
+
   else if (sop == 1 && sopcde == 12)
     {
-      notethat ("dregs_lo = CC = BXOR (A0 , A1 , CC)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=CC=BXOR( A0,A1 ,CC )");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 13)
     {
-      notethat ("dregs = ALIGN8 ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=ALIGN8(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 13)
     {
-      notethat ("dregs = ALIGN16 ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=ALIGN16(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 13)
     {
-      notethat ("dregs = ALIGN24 ( dregs , dregs )");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=ALIGN24(");
       OUTS (outf, dregs (src1));
       OUTS (outf, ",");
       OUTS (outf, dregs (src0));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* dsp32shiftimm
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
-|.sop...|.HLs...|.dst0......|.immag.................|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-  int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
-  int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
-  int bit8 = ((iw1 >> 8) & 0x1);
-  int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
+  /* dsp32shiftimm
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
+     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
+  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
+  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
+  int bit8     = ((iw1 >> 8) & 0x1);
+  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
   int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
-  int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
-  int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
-  int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
+  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
+  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
+  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
 
 
   if (HLs == 0 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_lo = dregs_lo >>> uimm4");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 1 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_lo = dregs_hi >>> uimm4");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_hi = dregs_lo >>> uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 0 && sopcde == 0)
     {
-      notethat ("dregs_hi = dregs_hi >>> uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 0 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_lo = dregs_lo << uimm4 (S)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 1 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_lo = dregs_hi << uimm4 (S)");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_hi = dregs_lo << uimm4 (S)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 1 && sopcde == 0)
     {
-      notethat ("dregs_hi = dregs_hi << uimm4 (S)");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 0)
     {
-      notethat ("dregs_lo = dregs_lo << uimm4");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
-      return 2 * 2;
     }
   else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 1)
     {
-      notethat ("dregs_lo = dregs_lo >> uimm4");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ">>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 1 && sop == 2 && sopcde == 0)
     {
-      notethat ("dregs_lo = dregs_hi >> uimm4");
       OUTS (outf, dregs_lo (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ">>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 1)
     {
-      notethat ("dregs_hi = dregs_lo >> uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, ">>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 0)
     {
-      notethat ("dregs_hi = dregs_lo << uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_lo (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 1)
     {
-      notethat ("dregs_hi = dregs_hi >> uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, ">>");
       OUTS (outf, uimm4 (newimmag));
-      return 2 * 2;
     }
   else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 0)
     {
-      notethat ("dregs_hi = dregs_hi << uimm4");
       OUTS (outf, dregs_hi (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs_hi (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm4 (immag));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 3 && HLs == 1)
     {
-      notethat ("A1 = ROT A1 BY imm6");
       OUTS (outf, "A1= ROT A1 BY ");
       OUTS (outf, imm6 (immag));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
     {
-      notethat ("A0 = A0 << uimm5");
       OUTS (outf, "A0=A0<<");
       OUTS (outf, uimm5 (immag));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
     {
-      notethat ("A0 = A0 >>> uimm5");
       OUTS (outf, "A0=A0>>>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
     {
-      notethat ("A1 = A1 << uimm5");
       OUTS (outf, "A1=A1<<");
       OUTS (outf, uimm5 (immag));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
     {
-      notethat ("A1 = A1 >>> uimm5");
       OUTS (outf, "A1=A1>>>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 3 && HLs == 0)
     {
-      notethat ("A0 = A0 >> uimm5");
       OUTS (outf, "A0=A0>>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 3 && HLs == 1)
     {
-      notethat ("A1 = A1 >> uimm5");
       OUTS (outf, "A1=A1>>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 3 && HLs == 0)
     {
-      notethat ("A0 = ROT A0 BY imm6");
       OUTS (outf, "A0= ROT A0 BY ");
       OUTS (outf, imm6 (immag));
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 1 && bit8 == 0)
     {
-      notethat ("dregs = dregs << uimm5 (V, S)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm5 (immag));
       OUTS (outf, " (V, S)");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 1 && bit8 == 1)
     {
-      notethat ("dregs = dregs >>> uimm5 (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, ">>>");
       OUTS (outf, imm5 (-immag));
       OUTS (outf, " (V)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 1 && bit8 == 1)
     {
-      notethat ("dregs = dregs >> uimm5 (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, " >> ");
       OUTS (outf, uimm5 (newimmag));
       OUTS (outf, " (V)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 1 && bit8 == 0)
     {
-      notethat ("dregs = dregs << imm5 (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, "<<");
       OUTS (outf, imm5 (immag));
       OUTS (outf, " (V)");
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 1)
     {
-      notethat ("dregs = dregs >>> uimm5 (V)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm5 (newimmag));
       OUTS (outf, " (V)");
-      return 2 * 2;
     }
   else if (sop == 1 && sopcde == 2)
     {
-      notethat ("dregs = dregs << uimm5 (S)");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm5 (immag));
       OUTS (outf, "(S)");
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 2 && bit8 == 1)
     {
-      notethat ("dregs = dregs >> uimm5");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, ">>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else if (sop == 2 && sopcde == 2 && bit8 == 0)
     {
-      notethat ("dregs = dregs << uimm5");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, "<<");
       OUTS (outf, uimm5 (immag));
-      return 2 * 2;
     }
   else if (sop == 3 && sopcde == 2)
     {
-      notethat ("dregs = ROT dregs BY imm6");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "= ROT ");
       OUTS (outf, dregs (src1));
       OUTS (outf, " BY ");
       OUTS (outf, imm6 (immag));
-      return 2 * 2;
     }
   else if (sop == 0 && sopcde == 2)
     {
-      notethat ("dregs = dregs >>> uimm5");
       OUTS (outf, dregs (dst0));
       OUTS (outf, "=");
       OUTS (outf, dregs (src1));
       OUTS (outf, ">>>");
       OUTS (outf, uimm5 (newimmag));
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 4;
 }
 
 static int
 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
 {
-/* pseudoDEBUG
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* pseudoDEBUG
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
   int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
   int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
 
   if (reg == 0 && fn == 3)
-    {
-      notethat ("DBG A0");
-      OUTS (outf, "DBG A0");
-      return 1 * 2;
-    }
+    OUTS (outf, "DBG A0");
+
   else if (reg == 1 && fn == 3)
-    {
-      notethat ("DBG A1");
-      OUTS (outf, "DBG A1");
-      return 1 * 2;
-    }
+    OUTS (outf, "DBG A1");
+
   else if (reg == 3 && fn == 3)
-    {
-      notethat ("ABORT");
-      OUTS (outf, "ABORT");
-      return 1 * 2;
-    }
+    OUTS (outf, "ABORT");
+
   else if (reg == 4 && fn == 3)
-    {
-      notethat ("HLT");
-      OUTS (outf, "HLT");
-      return 1 * 2;
-    }
+    OUTS (outf, "HLT");
+
   else if (reg == 5 && fn == 3)
-    {
-      notethat ("DBGHALT");
-      OUTS (outf, "DBGHALT");
-      return 1 * 2;
-    }
+    OUTS (outf, "DBGHALT");
+
   else if (reg == 6 && fn == 3)
     {
-      notethat ("DBGCMPLX ( dregs )");
       OUTS (outf, "DBGCMPLX(");
       OUTS (outf, dregs (grp));
       OUTS (outf, ")");
-      return 1 * 2;
     }
   else if (reg == 7 && fn == 3)
-    {
-      notethat ("DBG");
-      OUTS (outf, "DBG");
-      return 1 * 2;
-    }
+    OUTS (outf, "DBG");
+
   else if (grp == 0 && fn == 2)
     {
-      notethat ("OUTC dregs");
       OUTS (outf, "OUTC");
       OUTS (outf, dregs (reg));
-      return 1 * 2;
     }
   else if (fn == 0)
     {
-      notethat ("DBG allregs");
       OUTS (outf, "DBG");
       OUTS (outf, allregs (reg, grp));
-      return 1 * 2;
     }
   else if (fn == 1)
     {
-      notethat ("PRNT allregs");
       OUTS (outf, "PRNT");
       OUTS (outf, allregs (reg, grp));
-      return 1 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+
+  return 2;
 }
 
 static int
 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
-/* pseudodbg_assert
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
-|.expected......................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
+  /* pseudodbg_assert
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
+     |.expected......................................................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
-  int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
-  int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
+  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
+  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
 
   if (dbgop == 0)
     {
-      notethat ("DBGA ( dregs_lo , uimm16 )");
       OUTS (outf, "DBGA(");
       OUTS (outf, dregs_lo (regtest));
       OUTS (outf, ",");
       OUTS (outf, uimm16 (expected));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (dbgop == 1)
     {
-      notethat ("DBGA ( dregs_hi , uimm16 )");
       OUTS (outf, "DBGA(");
       OUTS (outf, dregs_hi (regtest));
       OUTS (outf, ",");
       OUTS (outf, uimm16 (expected));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (dbgop == 2)
     {
-      notethat ("DBGAL ( dregs , uimm16 )");
       OUTS (outf, "DBGAL(");
       OUTS (outf, dregs (regtest));
       OUTS (outf, ",");
       OUTS (outf, uimm16 (expected));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else if (dbgop == 3)
     {
-      notethat ("DBGAH ( dregs , uimm16 )");
       OUTS (outf, "DBGAH(");
       OUTS (outf, dregs (regtest));
       OUTS (outf, ",");
       OUTS (outf, uimm16 (expected));
       OUTS (outf, ")");
-      return 2 * 2;
     }
   else
-    goto illegal_instruction;
-illegal_instruction:
-  return 0;
+    return 0;
+  return 4;
 }
 
 int
 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
 {
-
   bfd_byte buf[4];
   TIword iw0;
   TIword iw1;
   int status;
+  int rv = 0;
+
   status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
   status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
 
@@ -5495,270 +4416,83 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
       return 4;
     }
   else if ((iw0 & 0xff00) == 0x0000)
-    {
-      int rv = decode_ProgCtrl_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_ProgCtrl_0 (iw0, outf);
   else if ((iw0 & 0xffc0) == 0x0240)
-    {
-      int rv = decode_CaCTRL_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_CaCTRL_0 (iw0, outf);
   else if ((iw0 & 0xff80) == 0x0100)
-    {
-      int rv = decode_PushPopReg_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_PushPopReg_0 (iw0, outf);
   else if ((iw0 & 0xfe00) == 0x0400)
-    {
-      int rv = decode_PushPopMultiple_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_PushPopMultiple_0 (iw0, outf);
   else if ((iw0 & 0xfe00) == 0x0600)
-    {
-      int rv = decode_ccMV_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_ccMV_0 (iw0, outf);
   else if ((iw0 & 0xf800) == 0x0800)
-    {
-      int rv = decode_CCflag_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_CCflag_0 (iw0, outf);
   else if ((iw0 & 0xffe0) == 0x0200)
-    {
-      int rv = decode_CC2dreg_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_CC2dreg_0 (iw0, outf);
   else if ((iw0 & 0xff00) == 0x0300)
-    {
-      int rv = decode_CC2stat_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_CC2stat_0 (iw0, outf);
   else if ((iw0 & 0xf000) == 0x1000)
-    {
-      int rv = decode_BRCC_0 (iw0, pc, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_BRCC_0 (iw0, pc, outf);
   else if ((iw0 & 0xf000) == 0x2000)
-    {
-      int rv = decode_UJUMP_0 (iw0, pc, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_UJUMP_0 (iw0, pc, outf);
   else if ((iw0 & 0xf000) == 0x3000)
-    {
-      int rv = decode_REGMV_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_REGMV_0 (iw0, outf);
   else if ((iw0 & 0xfc00) == 0x4000)
-    {
-      int rv = decode_ALU2op_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_ALU2op_0 (iw0, outf);
   else if ((iw0 & 0xfe00) == 0x4400)
-    {
-      int rv = decode_PTR2op_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_PTR2op_0 (iw0, outf);
   else if ((iw0 & 0xf800) == 0x4800)
-    {
-      int rv = decode_LOGI2op_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LOGI2op_0 (iw0, outf);
   else if ((iw0 & 0xf000) == 0x5000)
-    {
-      int rv = decode_COMP3op_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_COMP3op_0 (iw0, outf);
   else if ((iw0 & 0xf800) == 0x6000)
-    {
-      int rv = decode_COMPI2opD_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_COMPI2opD_0 (iw0, outf);
   else if ((iw0 & 0xf800) == 0x6800)
-    {
-      int rv = decode_COMPI2opP_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_COMPI2opP_0 (iw0, outf);
   else if ((iw0 & 0xf000) == 0x8000)
-    {
-      int rv = decode_LDSTpmod_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDSTpmod_0 (iw0, outf);
   else if ((iw0 & 0xff60) == 0x9e60)
-    {
-      int rv = decode_dagMODim_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dagMODim_0 (iw0, outf);
   else if ((iw0 & 0xfff0) == 0x9f60)
-    {
-      int rv = decode_dagMODik_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dagMODik_0 (iw0, outf);
   else if ((iw0 & 0xfc00) == 0x9c00)
-    {
-      int rv = decode_dspLDST_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dspLDST_0 (iw0, outf);
   else if ((iw0 & 0xf000) == 0x9000)
-    {
-      int rv = decode_LDST_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDST_0 (iw0, outf);
   else if ((iw0 & 0xfc00) == 0xb800)
-    {
-      int rv = decode_LDSTiiFP_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDSTiiFP_0 (iw0, outf);
   else if ((iw0 & 0xe000) == 0xA000)
-    {
-      int rv = decode_LDSTii_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDSTii_0 (iw0, outf);
   else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
-    {
-      int rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
   else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
   else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_CALLa_0 (iw0, iw1, pc, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
   else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_LDSTidxI_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
   else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_linkage_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_linkage_0 (iw0, iw1, outf);
   else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_dsp32mac_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dsp32mac_0 (iw0, iw1, outf);
   else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_dsp32mult_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dsp32mult_0 (iw0, iw1, outf);
   else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_dsp32alu_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dsp32alu_0 (iw0, iw1, outf);
   else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
-    {
-      int rv = decode_dsp32shift_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dsp32shift_0 (iw0, iw1, outf);
   else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
   else if ((iw0 & 0xff00) == 0xf800)
-    {
-      int rv = decode_pseudoDEBUG_0 (iw0, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
+    rv = decode_pseudoDEBUG_0 (iw0, outf);
 #if 0
-    }
   else if ((iw0 & 0xFF00) == 0xF900)
-    {
-
-      int rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
+    rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
 #endif
-    }
   else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
-    {
-      int rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
-      if (rv)
-	return rv;
-      goto illegal_instruction;
-    }
+    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
 
-illegal_instruction:
-  return 0;
+  return rv;
 }
 
 
@@ -5778,7 +4512,7 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
   /* Proper display of multiple issue instructions.  */
 
   if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
-      && ((iw0 & 0xe800) != 0xe800 /* not Linkage */ ))
+      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
     {
       outf->fprintf_func (outf->stream, " || ");
       count += _print_insn_bfin (pc + 4, outf);
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index bc2a7d3e668..5f29e2852f8 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -347,7 +347,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -359,11 +359,12 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -386,25 +387,34 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -420,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -433,7 +443,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c
index d34aac826cf..dbc51751a05 100644
--- a/opcodes/cgen-opc.c
+++ b/opcodes/cgen-opc.c
@@ -613,3 +613,151 @@ cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd)
 {
   return cd->signed_overflow_ok_p;
 }
+/* Functions for manipulating CGEN_BITSET.  */
+
+/* Create a bit mask.  */
+CGEN_BITSET *
+cgen_bitset_create (unsigned bit_count)
+{
+  CGEN_BITSET * mask = xmalloc (sizeof (* mask));
+  cgen_bitset_init (mask, bit_count);
+  return mask;
+}
+
+/* Initialize an existing bit mask.  */
+
+void
+cgen_bitset_init (CGEN_BITSET * mask, unsigned bit_count)
+{
+  if (! mask)
+    return;
+  mask->length = (bit_count / 8) + 1;
+  mask->bits = xmalloc (mask->length);
+  cgen_bitset_clear (mask);
+}
+
+/* Clear the bits of a bit mask.  */
+
+void
+cgen_bitset_clear (CGEN_BITSET * mask)
+{
+  unsigned i;
+
+  if (! mask)
+    return;
+
+  for (i = 0; i < mask->length; ++i)
+    mask->bits[i] = 0;
+}
+
+/* Add a bit to a bit mask.  */
+
+void
+cgen_bitset_add (CGEN_BITSET * mask, unsigned bit_num)
+{
+  int byte_ix, bit_ix;
+  int bit_mask;
+
+  if (! mask)
+    return;
+  byte_ix = bit_num / 8;
+  bit_ix = bit_num % 8;
+  bit_mask = 1 << (7 - bit_ix);
+  mask->bits[byte_ix] |= bit_mask;
+}
+
+/* Set a bit mask.  */
+
+void
+cgen_bitset_set (CGEN_BITSET * mask, unsigned bit_num)
+{
+  if (! mask)
+    return;
+  cgen_bitset_clear (mask);
+  cgen_bitset_add (mask, bit_num);
+}
+
+/* Test for a bit in a bit mask.
+   Returns 1 if the bit is found  */
+
+int
+cgen_bitset_contains (CGEN_BITSET * mask, unsigned bit_num)
+{
+  int byte_ix, bit_ix;
+  int bit_mask;
+
+  if (! mask)
+    return 1; /* No bit restrictions.  */
+
+  byte_ix = bit_num / 8;
+  bit_ix = 7 - (bit_num % 8);
+  bit_mask = 1 << bit_ix;
+  return (mask->bits[byte_ix] & bit_mask) >> bit_ix;
+}
+
+/* Compare two bit masks for equality.
+   Returns 0 if they are equal.  */
+
+int
+cgen_bitset_compare (CGEN_BITSET * mask1, CGEN_BITSET * mask2)
+{
+  if (mask1 == mask2)
+    return 0;
+  if (! mask1 || ! mask2)
+    return 1;
+  if (mask1->length != mask2->length)
+    return 1;
+  return memcmp (mask1->bits, mask2->bits, mask1->length);
+}
+
+/* Test two bit masks for common bits.
+   Returns 1 if a common bit is found.  */
+
+int
+cgen_bitset_intersect_p (CGEN_BITSET * mask1, CGEN_BITSET * mask2)
+{
+  unsigned i, limit;
+
+  if (mask1 == mask2)
+    return 1;
+  if (! mask1 || ! mask2)
+    return 0;
+  limit = mask1->length < mask2->length ? mask1->length : mask2->length;
+
+  for (i = 0; i < limit; ++i)
+    if ((mask1->bits[i] & mask2->bits[i]))
+      return 1;
+
+  return 0;
+}
+
+/* Make a copy of a bit mask.  */
+
+CGEN_BITSET *
+cgen_bitset_copy (CGEN_BITSET * mask)
+{
+  CGEN_BITSET* newmask;
+
+  if (! mask)
+    return NULL;
+  newmask = cgen_bitset_create ((mask->length * 8) - 1);
+  memcpy (newmask->bits, mask->bits, mask->length);
+  return newmask;
+}
+
+/* Combine two bit masks.  */
+
+void
+cgen_bitset_union (CGEN_BITSET * mask1, CGEN_BITSET * mask2,
+		   CGEN_BITSET * result)
+{
+  unsigned i;
+
+  if (! mask1 || ! mask2 || ! result
+      || mask1->length != mask2->length
+      || mask1->length != result->length)
+    return;
+
+  for (i = 0; i < result->length; ++i)
+    result->bits[i] = mask1->bits[i] | mask2->bits[i];
+}
diff --git a/opcodes/configure b/opcodes/configure
index a9c0ac64569..34c9ced1d03 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -8769,6 +8769,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_we32k_arch)		;;
 	bfd_xstormy16_arch)	ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
+	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
 	bfd_z8k_arch)		ta="$ta z8k-dis.lo" ;;
 
 	"")			;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 5156685e8cb..ad02c3e3d16 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -229,6 +229,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_we32k_arch)		;;
 	bfd_xstormy16_arch)	ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
+	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
 	bfd_z8k_arch)		ta="$ta z8k-dis.lo" ;;
 
 	"")			;;
diff --git a/opcodes/dep-in.sed b/opcodes/dep-in.sed
index 94da2adc340..081f99c1e08 100644
--- a/opcodes/dep-in.sed
+++ b/opcodes/dep-in.sed
@@ -4,6 +4,7 @@ s/\\\n */ /g
 t loop
 
 s!\.o:!.lo:!
+s! \./! !g
 s! @BFD_H@! $(BFD_H)!g
 s!@INCDIR@!$(INCDIR)!g
 s!@TOPDIR@/include!$(INCDIR)!g
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 9304e083806..007731a7ef2 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -75,6 +75,7 @@
 #define ARCH_w65
 #define ARCH_xstormy16
 #define ARCH_xtensa
+#define ARCH_z80
 #define ARCH_z8k
 #define INCLUDE_SHMEDIA
 #endif
@@ -374,6 +375,11 @@ disassembler (abfd)
       disassemble = print_insn_xtensa;
       break;
 #endif
+#ifdef ARCH_z80
+    case bfd_arch_z80:
+      disassemble = print_insn_z80;
+      break;
+#endif
 #ifdef ARCH_z8k
     case bfd_arch_z8k:
       if (bfd_get_mach(abfd) == bfd_mach_z8001)
@@ -446,14 +452,19 @@ disassemble_init_for_target (struct disassemble_info * info)
 #ifdef ARCH_tic4x
     case bfd_arch_tic4x:
       info->skip_zeroes = 32;
+      break;
 #endif
 #ifdef ARCH_m32c
     case bfd_arch_m32c:
       info->endian = BFD_ENDIAN_BIG;
-      if (info->mach == bfd_mach_m16c)
-	info->insn_sets = 1 << ISA_M16C;
-      else
-	info->insn_sets = 1 << ISA_M32C;
+      if (! info->insn_sets)
+	{
+	  info->insn_sets = cgen_bitset_create (ISA_MAX);
+	  if (info->mach == bfd_mach_m16c)
+	    cgen_bitset_set (info->insn_sets, ISA_M16C);
+	  else
+	    cgen_bitset_set (info->insn_sets, ISA_M32C);
+	}
       break;
 #endif
     default:
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index 768fce6ebc0..a8c2a357b6c 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -128,25 +128,25 @@ static const CGEN_MACH fr30_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 },
-  { "ac", 13, {0, {0}}, 0, 0 },
-  { "fp", 14, {0, {0}}, 0, 0 },
-  { "sp", 15, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "ac", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_gr_names =
@@ -158,22 +158,22 @@ CGEN_KEYWORD fr30_cgen_opval_gr_names =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
 {
-  { "cr0", 0, {0, {0}}, 0, 0 },
-  { "cr1", 1, {0, {0}}, 0, 0 },
-  { "cr2", 2, {0, {0}}, 0, 0 },
-  { "cr3", 3, {0, {0}}, 0, 0 },
-  { "cr4", 4, {0, {0}}, 0, 0 },
-  { "cr5", 5, {0, {0}}, 0, 0 },
-  { "cr6", 6, {0, {0}}, 0, 0 },
-  { "cr7", 7, {0, {0}}, 0, 0 },
-  { "cr8", 8, {0, {0}}, 0, 0 },
-  { "cr9", 9, {0, {0}}, 0, 0 },
-  { "cr10", 10, {0, {0}}, 0, 0 },
-  { "cr11", 11, {0, {0}}, 0, 0 },
-  { "cr12", 12, {0, {0}}, 0, 0 },
-  { "cr13", 13, {0, {0}}, 0, 0 },
-  { "cr14", 14, {0, {0}}, 0, 0 },
-  { "cr15", 15, {0, {0}}, 0, 0 }
+  { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_cr_names =
@@ -185,12 +185,12 @@ CGEN_KEYWORD fr30_cgen_opval_cr_names =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
 {
-  { "tbr", 0, {0, {0}}, 0, 0 },
-  { "rp", 1, {0, {0}}, 0, 0 },
-  { "ssp", 2, {0, {0}}, 0, 0 },
-  { "usp", 3, {0, {0}}, 0, 0 },
-  { "mdh", 4, {0, {0}}, 0, 0 },
-  { "mdl", 5, {0, {0}}, 0, 0 }
+  { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "rp", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "usp", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_dr_names =
@@ -202,7 +202,7 @@ CGEN_KEYWORD fr30_cgen_opval_dr_names =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
 {
-  { "ps", 0, {0, {0}}, 0, 0 }
+  { "ps", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_h_ps =
@@ -214,7 +214,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_ps =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
 {
-  { "r13", 0, {0, {0}}, 0, 0 }
+  { "r13", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
@@ -226,7 +226,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r13 =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
 {
-  { "r14", 0, {0, {0}}, 0, 0 }
+  { "r14", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
@@ -238,7 +238,7 @@ CGEN_KEYWORD fr30_cgen_opval_h_r14 =
 
 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
 {
-  { "r15", 0, {0, {0}}, 0, 0 }
+  { "r15", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
@@ -259,32 +259,32 @@ CGEN_KEYWORD fr30_cgen_opval_h_r15 =
 
 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
-  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
-  { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
-  { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
-  { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
-  { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
-  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -300,49 +300,49 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
 
 const CGEN_IFLD fr30_cgen_ifld_table[] =
 {
-  { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
-  { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -381,203 +381,203 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* Ri: destination register */
   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rj: source register */
   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Ric: target register coproc insn */
   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rjc: source register coproc insn */
   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRi: coprocessor register */
   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRj: coprocessor register */
   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rs1: dedicated register */
   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rs2: dedicated register */
   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* R13: General Register 13 */
   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* R14: General Register 14 */
   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* R15: General Register 15 */
   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ps: Program Status register */
   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* u4: 4  bit unsigned immediate */
   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u4c: 4  bit unsigned immediate */
   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u8: 8  bit unsigned immediate */
   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* i8: 8  bit unsigned immediate */
   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* udisp6: 6  bit unsigned immediate */
   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp8: 8  bit signed   immediate */
   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp9: 9  bit signed   immediate */
   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp10: 10 bit signed   immediate */
   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* s10: 10 bit signed   immediate */
   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u10: 10 bit unsigned immediate */
   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* i32: 32 bit immediate */
   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } }, 
-    { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 /* m4: 4  bit negative immediate */
   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* i20: 20 bit immediate */
   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
     { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } }, 
-    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* dir8: 8  bit direct address */
   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dir9: 9  bit direct address */
   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dir10: 10 bit direct address */
   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* label9: 9  bit pc relative address */
   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* label12: 12 bit pc relative address */
   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* reglist_low_ld: 8 bit low register mask for ldm */
   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* reglist_hi_ld: 8 bit high register mask for ldm */
   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* reglist_low_st: 8 bit low register mask for stm */
   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* reglist_hi_st: 8 bit high register mask for stm */
   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cc: condition codes */
   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ccc: coprocessor calc */
   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* nbit: negative   bit */
   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* vbit: overflow   bit */
   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* zbit: zero       bit */
   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbit: carry      bit */
   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ibit: interrupt  bit */
   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sbit: stack      bit */
   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* tbit: trace trap bit */
   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* d0bit: division 0 bit */
   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* d1bit: division 1 bit */
   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ccr: condition code bits */
   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* scr: system condition bits */
   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ilm: interrupt level mask */
   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -597,831 +597,831 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 /* add $Rj,$Ri */
   {
     FR30_INSN_ADD, "add", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $u4,$Ri */
   {
     FR30_INSN_ADDI, "addi", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add2 $m4,$Ri */
   {
     FR30_INSN_ADD2, "add2", "add2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addc $Rj,$Ri */
   {
     FR30_INSN_ADDC, "addc", "addc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addn $Rj,$Ri */
   {
     FR30_INSN_ADDN, "addn", "addn", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addn $u4,$Ri */
   {
     FR30_INSN_ADDNI, "addni", "addn", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addn2 $m4,$Ri */
   {
     FR30_INSN_ADDN2, "addn2", "addn2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $Rj,$Ri */
   {
     FR30_INSN_SUB, "sub", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subc $Rj,$Ri */
   {
     FR30_INSN_SUBC, "subc", "subc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subn $Rj,$Ri */
   {
     FR30_INSN_SUBN, "subn", "subn", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cmp $Rj,$Ri */
   {
     FR30_INSN_CMP, "cmp", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cmp $u4,$Ri */
   {
     FR30_INSN_CMPI, "cmpi", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cmp2 $m4,$Ri */
   {
     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and $Rj,$Ri */
   {
     FR30_INSN_AND, "and", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $Rj,$Ri */
   {
     FR30_INSN_OR, "or", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* eor $Rj,$Ri */
   {
     FR30_INSN_EOR, "eor", "eor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and $Rj,@$Ri */
   {
     FR30_INSN_ANDM, "andm", "and", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* andh $Rj,@$Ri */
   {
     FR30_INSN_ANDH, "andh", "andh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* andb $Rj,@$Ri */
   {
     FR30_INSN_ANDB, "andb", "andb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $Rj,@$Ri */
   {
     FR30_INSN_ORM, "orm", "or", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* orh $Rj,@$Ri */
   {
     FR30_INSN_ORH, "orh", "orh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* orb $Rj,@$Ri */
   {
     FR30_INSN_ORB, "orb", "orb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* eor $Rj,@$Ri */
   {
     FR30_INSN_EORM, "eorm", "eor", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* eorh $Rj,@$Ri */
   {
     FR30_INSN_EORH, "eorh", "eorh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* eorb $Rj,@$Ri */
   {
     FR30_INSN_EORB, "eorb", "eorb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bandl $u4,@$Ri */
   {
     FR30_INSN_BANDL, "bandl", "bandl", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* borl $u4,@$Ri */
   {
     FR30_INSN_BORL, "borl", "borl", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* beorl $u4,@$Ri */
   {
     FR30_INSN_BEORL, "beorl", "beorl", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bandh $u4,@$Ri */
   {
     FR30_INSN_BANDH, "bandh", "bandh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* borh $u4,@$Ri */
   {
     FR30_INSN_BORH, "borh", "borh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* beorh $u4,@$Ri */
   {
     FR30_INSN_BEORH, "beorh", "beorh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* btstl $u4,@$Ri */
   {
     FR30_INSN_BTSTL, "btstl", "btstl", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* btsth $u4,@$Ri */
   {
     FR30_INSN_BTSTH, "btsth", "btsth", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mul $Rj,$Ri */
   {
     FR30_INSN_MUL, "mul", "mul", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mulu $Rj,$Ri */
   {
     FR30_INSN_MULU, "mulu", "mulu", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mulh $Rj,$Ri */
   {
     FR30_INSN_MULH, "mulh", "mulh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* muluh $Rj,$Ri */
   {
     FR30_INSN_MULUH, "muluh", "muluh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div0s $Ri */
   {
     FR30_INSN_DIV0S, "div0s", "div0s", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div0u $Ri */
   {
     FR30_INSN_DIV0U, "div0u", "div0u", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div1 $Ri */
   {
     FR30_INSN_DIV1, "div1", "div1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div2 $Ri */
   {
     FR30_INSN_DIV2, "div2", "div2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div3 */
   {
     FR30_INSN_DIV3, "div3", "div3", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div4s */
   {
     FR30_INSN_DIV4S, "div4s", "div4s", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl $Rj,$Ri */
   {
     FR30_INSN_LSL, "lsl", "lsl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl $u4,$Ri */
   {
     FR30_INSN_LSLI, "lsli", "lsl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl2 $u4,$Ri */
   {
     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr $Rj,$Ri */
   {
     FR30_INSN_LSR, "lsr", "lsr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr $u4,$Ri */
   {
     FR30_INSN_LSRI, "lsri", "lsr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr2 $u4,$Ri */
   {
     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr $Rj,$Ri */
   {
     FR30_INSN_ASR, "asr", "asr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr $u4,$Ri */
   {
     FR30_INSN_ASRI, "asri", "asr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr2 $u4,$Ri */
   {
     FR30_INSN_ASR2, "asr2", "asr2", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldi:8 $i8,$Ri */
   {
     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldi:20 $i20,$Ri */
   {
     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldi:32 $i32,$Ri */
   {
     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @$Rj,$Ri */
   {
     FR30_INSN_LD, "ld", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lduh @$Rj,$Ri */
   {
     FR30_INSN_LDUH, "lduh", "lduh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldub @$Rj,$Ri */
   {
     FR30_INSN_LDUB, "ldub", "ldub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @($R13,$Rj),$Ri */
   {
     FR30_INSN_LDR13, "ldr13", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lduh @($R13,$Rj),$Ri */
   {
     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldub @($R13,$Rj),$Ri */
   {
     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @($R14,$disp10),$Ri */
   {
     FR30_INSN_LDR14, "ldr14", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lduh @($R14,$disp9),$Ri */
   {
     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldub @($R14,$disp8),$Ri */
   {
     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @($R15,$udisp6),$Ri */
   {
     FR30_INSN_LDR15, "ldr15", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @$R15+,$Ri */
   {
     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @$R15+,$Rs2 */
   {
     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ld @$R15+,$ps */
   {
     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Ri,@$Rj */
   {
     FR30_INSN_ST, "st", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sth $Ri,@$Rj */
   {
     FR30_INSN_STH, "sth", "sth", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stb $Ri,@$Rj */
   {
     FR30_INSN_STB, "stb", "stb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Ri,@($R13,$Rj) */
   {
     FR30_INSN_STR13, "str13", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sth $Ri,@($R13,$Rj) */
   {
     FR30_INSN_STR13H, "str13h", "sth", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stb $Ri,@($R13,$Rj) */
   {
     FR30_INSN_STR13B, "str13b", "stb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Ri,@($R14,$disp10) */
   {
     FR30_INSN_STR14, "str14", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sth $Ri,@($R14,$disp9) */
   {
     FR30_INSN_STR14H, "str14h", "sth", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stb $Ri,@($R14,$disp8) */
   {
     FR30_INSN_STR14B, "str14b", "stb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Ri,@($R15,$udisp6) */
   {
     FR30_INSN_STR15, "str15", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Ri,@-$R15 */
   {
     FR30_INSN_STR15GR, "str15gr", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $Rs2,@-$R15 */
   {
     FR30_INSN_STR15DR, "str15dr", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* st $ps,@-$R15 */
   {
     FR30_INSN_STR15PS, "str15ps", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Rj,$Ri */
   {
     FR30_INSN_MOV, "mov", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Rs1,$Ri */
   {
     FR30_INSN_MOVDR, "movdr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $ps,$Ri */
   {
     FR30_INSN_MOVPS, "movps", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Ri,$Rs1 */
   {
     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Ri,$ps */
   {
     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jmp @$Ri */
   {
     FR30_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jmp:d @$Ri */
   {
     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call @$Ri */
   {
     FR30_INSN_CALLR, "callr", "call", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call:d @$Ri */
   {
     FR30_INSN_CALLRD, "callrd", "call:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call $label12 */
   {
     FR30_INSN_CALL, "call", "call", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call:d $label12 */
   {
     FR30_INSN_CALLD, "calld", "call:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ret */
   {
     FR30_INSN_RET, "ret", "ret", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ret:d */
   {
     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* int $u8 */
   {
     FR30_INSN_INT, "int", "int", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* inte */
   {
     FR30_INSN_INTE, "inte", "inte", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* reti */
   {
     FR30_INSN_RETI, "reti", "reti", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bra:d $label9 */
   {
     FR30_INSN_BRAD, "brad", "bra:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bra $label9 */
   {
     FR30_INSN_BRA, "bra", "bra", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bno:d $label9 */
   {
     FR30_INSN_BNOD, "bnod", "bno:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bno $label9 */
   {
     FR30_INSN_BNO, "bno", "bno", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* beq:d $label9 */
   {
     FR30_INSN_BEQD, "beqd", "beq:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* beq $label9 */
   {
     FR30_INSN_BEQ, "beq", "beq", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bne:d $label9 */
   {
     FR30_INSN_BNED, "bned", "bne:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bne $label9 */
   {
     FR30_INSN_BNE, "bne", "bne", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bc:d $label9 */
   {
     FR30_INSN_BCD, "bcd", "bc:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bc $label9 */
   {
     FR30_INSN_BC, "bc", "bc", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bnc:d $label9 */
   {
     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bnc $label9 */
   {
     FR30_INSN_BNC, "bnc", "bnc", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn:d $label9 */
   {
     FR30_INSN_BND, "bnd", "bn:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn $label9 */
   {
     FR30_INSN_BN, "bn", "bn", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp:d $label9 */
   {
     FR30_INSN_BPD, "bpd", "bp:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp $label9 */
   {
     FR30_INSN_BP, "bp", "bp", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bv:d $label9 */
   {
     FR30_INSN_BVD, "bvd", "bv:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bv $label9 */
   {
     FR30_INSN_BV, "bv", "bv", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bnv:d $label9 */
   {
     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bnv $label9 */
   {
     FR30_INSN_BNV, "bnv", "bnv", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* blt:d $label9 */
   {
     FR30_INSN_BLTD, "bltd", "blt:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* blt $label9 */
   {
     FR30_INSN_BLT, "blt", "blt", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bge:d $label9 */
   {
     FR30_INSN_BGED, "bged", "bge:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bge $label9 */
   {
     FR30_INSN_BGE, "bge", "bge", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ble:d $label9 */
   {
     FR30_INSN_BLED, "bled", "ble:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ble $label9 */
   {
     FR30_INSN_BLE, "ble", "ble", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bgt:d $label9 */
   {
     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bgt $label9 */
   {
     FR30_INSN_BGT, "bgt", "bgt", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bls:d $label9 */
   {
     FR30_INSN_BLSD, "blsd", "bls:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bls $label9 */
   {
     FR30_INSN_BLS, "bls", "bls", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bhi:d $label9 */
   {
     FR30_INSN_BHID, "bhid", "bhi:d", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bhi $label9 */
   {
     FR30_INSN_BHI, "bhi", "bhi", 16,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov $R13,@$dir10 */
   {
     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovh $R13,@$dir9 */
   {
     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovb $R13,@$dir8 */
   {
     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov @$R13+,@$dir10 */
   {
     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovh @$R13+,@$dir9 */
   {
     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovb @$R13+,@$dir8 */
   {
     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov @$R15+,@$dir10 */
   {
     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov @$dir10,$R13 */
   {
     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovh @$dir9,$R13 */
   {
     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovb @$dir8,$R13 */
   {
     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov @$dir10,@$R13+ */
   {
     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovh @$dir9,@$R13+ */
   {
     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmovb @$dir8,@$R13+ */
   {
     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dmov @$dir10,@-$R15 */
   {
     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldres @$Ri+,$u4 */
   {
     FR30_INSN_LDRES, "ldres", "ldres", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stres $u4,@$Ri+ */
   {
     FR30_INSN_STRES, "stres", "stres", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* copop $u4c,$ccc,$CRj,$CRi */
   {
     FR30_INSN_COPOP, "copop", "copop", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* copld $u4c,$ccc,$Rjc,$CRi */
   {
     FR30_INSN_COPLD, "copld", "copld", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* copst $u4c,$ccc,$CRj,$Ric */
   {
     FR30_INSN_COPST, "copst", "copst", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* copsv $u4c,$ccc,$CRj,$Ric */
   {
     FR30_INSN_COPSV, "copsv", "copsv", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nop */
   {
     FR30_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* andccr $u8 */
   {
     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* orccr $u8 */
   {
     FR30_INSN_ORCCR, "orccr", "orccr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stilm $u8 */
   {
     FR30_INSN_STILM, "stilm", "stilm", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addsp $s10 */
   {
     FR30_INSN_ADDSP, "addsp", "addsp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* extsb $Ri */
   {
     FR30_INSN_EXTSB, "extsb", "extsb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* extub $Ri */
   {
     FR30_INSN_EXTUB, "extub", "extub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* extsh $Ri */
   {
     FR30_INSN_EXTSH, "extsh", "extsh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* extuh $Ri */
   {
     FR30_INSN_EXTUH, "extuh", "extuh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldm0 ($reglist_low_ld) */
   {
     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldm1 ($reglist_hi_ld) */
   {
     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stm0 ($reglist_low_st) */
   {
     FR30_INSN_STM0, "stm0", "stm0", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stm1 ($reglist_hi_st) */
   {
     FR30_INSN_STM1, "stm1", "stm1", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* enter $u10 */
   {
     FR30_INSN_ENTER, "enter", "enter", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* leave */
   {
     FR30_INSN_LEAVE, "leave", "leave", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xchb @$Rj,$Ri */
   {
     FR30_INSN_XCHB, "xchb", "xchb", 16,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
@@ -1544,7 +1544,7 @@ static void
 fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1556,7 +1556,7 @@ fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
 
@@ -1641,7 +1641,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -1660,7 +1660,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -1691,9 +1691,6 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -1701,7 +1698,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h
index 7741fafcb2e..509a69b88e5 100644
--- a/opcodes/fr30-desc.h
+++ b/opcodes/fr30-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef FR30_CPU_H
 #define FR30_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH fr30
 
 /* Given symbol S, return fr30_cgen_<S>.  */
@@ -156,6 +158,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for fr30 ifield types.  */
 typedef enum ifield_type {
   FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
@@ -184,6 +195,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for fr30 hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -210,6 +228,18 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
+
 /* Enum declaration for fr30 operand types.  */
 typedef enum cgen_operand_type {
   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
@@ -246,6 +276,20 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 0f7c8e895f5..740e4f4bfcd 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -607,7 +607,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -619,11 +619,12 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -646,25 +647,34 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -680,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -693,7 +703,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 0eefb4693a7..be92c6d77bf 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -1228,17 +1228,17 @@ static const CGEN_IBASE fr30_cgen_macro_insn_table[] =
 /* ldi8 $i8,$Ri */
   {
     -1, "ldi8m", "ldi8", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldi20 $i20,$Ri */
   {
     -1, "ldi20m", "ldi20", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldi32 $i32,$Ri */
   {
     -1, "ldi32m", "ldi32", 48,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c
index bff97d83ed1..39235a6a164 100644
--- a/opcodes/frv-desc.c
+++ b/opcodes/frv-desc.c
@@ -296,72 +296,72 @@ static const CGEN_MACH frv_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
 {
-  { "sp", 1, {0, {0}}, 0, 0 },
-  { "fp", 2, {0, {0}}, 0, 0 },
-  { "gr0", 0, {0, {0}}, 0, 0 },
-  { "gr1", 1, {0, {0}}, 0, 0 },
-  { "gr2", 2, {0, {0}}, 0, 0 },
-  { "gr3", 3, {0, {0}}, 0, 0 },
-  { "gr4", 4, {0, {0}}, 0, 0 },
-  { "gr5", 5, {0, {0}}, 0, 0 },
-  { "gr6", 6, {0, {0}}, 0, 0 },
-  { "gr7", 7, {0, {0}}, 0, 0 },
-  { "gr8", 8, {0, {0}}, 0, 0 },
-  { "gr9", 9, {0, {0}}, 0, 0 },
-  { "gr10", 10, {0, {0}}, 0, 0 },
-  { "gr11", 11, {0, {0}}, 0, 0 },
-  { "gr12", 12, {0, {0}}, 0, 0 },
-  { "gr13", 13, {0, {0}}, 0, 0 },
-  { "gr14", 14, {0, {0}}, 0, 0 },
-  { "gr15", 15, {0, {0}}, 0, 0 },
-  { "gr16", 16, {0, {0}}, 0, 0 },
-  { "gr17", 17, {0, {0}}, 0, 0 },
-  { "gr18", 18, {0, {0}}, 0, 0 },
-  { "gr19", 19, {0, {0}}, 0, 0 },
-  { "gr20", 20, {0, {0}}, 0, 0 },
-  { "gr21", 21, {0, {0}}, 0, 0 },
-  { "gr22", 22, {0, {0}}, 0, 0 },
-  { "gr23", 23, {0, {0}}, 0, 0 },
-  { "gr24", 24, {0, {0}}, 0, 0 },
-  { "gr25", 25, {0, {0}}, 0, 0 },
-  { "gr26", 26, {0, {0}}, 0, 0 },
-  { "gr27", 27, {0, {0}}, 0, 0 },
-  { "gr28", 28, {0, {0}}, 0, 0 },
-  { "gr29", 29, {0, {0}}, 0, 0 },
-  { "gr30", 30, {0, {0}}, 0, 0 },
-  { "gr31", 31, {0, {0}}, 0, 0 },
-  { "gr32", 32, {0, {0}}, 0, 0 },
-  { "gr33", 33, {0, {0}}, 0, 0 },
-  { "gr34", 34, {0, {0}}, 0, 0 },
-  { "gr35", 35, {0, {0}}, 0, 0 },
-  { "gr36", 36, {0, {0}}, 0, 0 },
-  { "gr37", 37, {0, {0}}, 0, 0 },
-  { "gr38", 38, {0, {0}}, 0, 0 },
-  { "gr39", 39, {0, {0}}, 0, 0 },
-  { "gr40", 40, {0, {0}}, 0, 0 },
-  { "gr41", 41, {0, {0}}, 0, 0 },
-  { "gr42", 42, {0, {0}}, 0, 0 },
-  { "gr43", 43, {0, {0}}, 0, 0 },
-  { "gr44", 44, {0, {0}}, 0, 0 },
-  { "gr45", 45, {0, {0}}, 0, 0 },
-  { "gr46", 46, {0, {0}}, 0, 0 },
-  { "gr47", 47, {0, {0}}, 0, 0 },
-  { "gr48", 48, {0, {0}}, 0, 0 },
-  { "gr49", 49, {0, {0}}, 0, 0 },
-  { "gr50", 50, {0, {0}}, 0, 0 },
-  { "gr51", 51, {0, {0}}, 0, 0 },
-  { "gr52", 52, {0, {0}}, 0, 0 },
-  { "gr53", 53, {0, {0}}, 0, 0 },
-  { "gr54", 54, {0, {0}}, 0, 0 },
-  { "gr55", 55, {0, {0}}, 0, 0 },
-  { "gr56", 56, {0, {0}}, 0, 0 },
-  { "gr57", 57, {0, {0}}, 0, 0 },
-  { "gr58", 58, {0, {0}}, 0, 0 },
-  { "gr59", 59, {0, {0}}, 0, 0 },
-  { "gr60", 60, {0, {0}}, 0, 0 },
-  { "gr61", 61, {0, {0}}, 0, 0 },
-  { "gr62", 62, {0, {0}}, 0, 0 },
-  { "gr63", 63, {0, {0}}, 0, 0 }
+  { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "gr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_gr_names =
@@ -373,70 +373,70 @@ CGEN_KEYWORD frv_cgen_opval_gr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
 {
-  { "fr0", 0, {0, {0}}, 0, 0 },
-  { "fr1", 1, {0, {0}}, 0, 0 },
-  { "fr2", 2, {0, {0}}, 0, 0 },
-  { "fr3", 3, {0, {0}}, 0, 0 },
-  { "fr4", 4, {0, {0}}, 0, 0 },
-  { "fr5", 5, {0, {0}}, 0, 0 },
-  { "fr6", 6, {0, {0}}, 0, 0 },
-  { "fr7", 7, {0, {0}}, 0, 0 },
-  { "fr8", 8, {0, {0}}, 0, 0 },
-  { "fr9", 9, {0, {0}}, 0, 0 },
-  { "fr10", 10, {0, {0}}, 0, 0 },
-  { "fr11", 11, {0, {0}}, 0, 0 },
-  { "fr12", 12, {0, {0}}, 0, 0 },
-  { "fr13", 13, {0, {0}}, 0, 0 },
-  { "fr14", 14, {0, {0}}, 0, 0 },
-  { "fr15", 15, {0, {0}}, 0, 0 },
-  { "fr16", 16, {0, {0}}, 0, 0 },
-  { "fr17", 17, {0, {0}}, 0, 0 },
-  { "fr18", 18, {0, {0}}, 0, 0 },
-  { "fr19", 19, {0, {0}}, 0, 0 },
-  { "fr20", 20, {0, {0}}, 0, 0 },
-  { "fr21", 21, {0, {0}}, 0, 0 },
-  { "fr22", 22, {0, {0}}, 0, 0 },
-  { "fr23", 23, {0, {0}}, 0, 0 },
-  { "fr24", 24, {0, {0}}, 0, 0 },
-  { "fr25", 25, {0, {0}}, 0, 0 },
-  { "fr26", 26, {0, {0}}, 0, 0 },
-  { "fr27", 27, {0, {0}}, 0, 0 },
-  { "fr28", 28, {0, {0}}, 0, 0 },
-  { "fr29", 29, {0, {0}}, 0, 0 },
-  { "fr30", 30, {0, {0}}, 0, 0 },
-  { "fr31", 31, {0, {0}}, 0, 0 },
-  { "fr32", 32, {0, {0}}, 0, 0 },
-  { "fr33", 33, {0, {0}}, 0, 0 },
-  { "fr34", 34, {0, {0}}, 0, 0 },
-  { "fr35", 35, {0, {0}}, 0, 0 },
-  { "fr36", 36, {0, {0}}, 0, 0 },
-  { "fr37", 37, {0, {0}}, 0, 0 },
-  { "fr38", 38, {0, {0}}, 0, 0 },
-  { "fr39", 39, {0, {0}}, 0, 0 },
-  { "fr40", 40, {0, {0}}, 0, 0 },
-  { "fr41", 41, {0, {0}}, 0, 0 },
-  { "fr42", 42, {0, {0}}, 0, 0 },
-  { "fr43", 43, {0, {0}}, 0, 0 },
-  { "fr44", 44, {0, {0}}, 0, 0 },
-  { "fr45", 45, {0, {0}}, 0, 0 },
-  { "fr46", 46, {0, {0}}, 0, 0 },
-  { "fr47", 47, {0, {0}}, 0, 0 },
-  { "fr48", 48, {0, {0}}, 0, 0 },
-  { "fr49", 49, {0, {0}}, 0, 0 },
-  { "fr50", 50, {0, {0}}, 0, 0 },
-  { "fr51", 51, {0, {0}}, 0, 0 },
-  { "fr52", 52, {0, {0}}, 0, 0 },
-  { "fr53", 53, {0, {0}}, 0, 0 },
-  { "fr54", 54, {0, {0}}, 0, 0 },
-  { "fr55", 55, {0, {0}}, 0, 0 },
-  { "fr56", 56, {0, {0}}, 0, 0 },
-  { "fr57", 57, {0, {0}}, 0, 0 },
-  { "fr58", 58, {0, {0}}, 0, 0 },
-  { "fr59", 59, {0, {0}}, 0, 0 },
-  { "fr60", 60, {0, {0}}, 0, 0 },
-  { "fr61", 61, {0, {0}}, 0, 0 },
-  { "fr62", 62, {0, {0}}, 0, 0 },
-  { "fr63", 63, {0, {0}}, 0, 0 }
+  { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "fr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_fr_names =
@@ -448,70 +448,70 @@ CGEN_KEYWORD frv_cgen_opval_fr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
 {
-  { "cpr0", 0, {0, {0}}, 0, 0 },
-  { "cpr1", 1, {0, {0}}, 0, 0 },
-  { "cpr2", 2, {0, {0}}, 0, 0 },
-  { "cpr3", 3, {0, {0}}, 0, 0 },
-  { "cpr4", 4, {0, {0}}, 0, 0 },
-  { "cpr5", 5, {0, {0}}, 0, 0 },
-  { "cpr6", 6, {0, {0}}, 0, 0 },
-  { "cpr7", 7, {0, {0}}, 0, 0 },
-  { "cpr8", 8, {0, {0}}, 0, 0 },
-  { "cpr9", 9, {0, {0}}, 0, 0 },
-  { "cpr10", 10, {0, {0}}, 0, 0 },
-  { "cpr11", 11, {0, {0}}, 0, 0 },
-  { "cpr12", 12, {0, {0}}, 0, 0 },
-  { "cpr13", 13, {0, {0}}, 0, 0 },
-  { "cpr14", 14, {0, {0}}, 0, 0 },
-  { "cpr15", 15, {0, {0}}, 0, 0 },
-  { "cpr16", 16, {0, {0}}, 0, 0 },
-  { "cpr17", 17, {0, {0}}, 0, 0 },
-  { "cpr18", 18, {0, {0}}, 0, 0 },
-  { "cpr19", 19, {0, {0}}, 0, 0 },
-  { "cpr20", 20, {0, {0}}, 0, 0 },
-  { "cpr21", 21, {0, {0}}, 0, 0 },
-  { "cpr22", 22, {0, {0}}, 0, 0 },
-  { "cpr23", 23, {0, {0}}, 0, 0 },
-  { "cpr24", 24, {0, {0}}, 0, 0 },
-  { "cpr25", 25, {0, {0}}, 0, 0 },
-  { "cpr26", 26, {0, {0}}, 0, 0 },
-  { "cpr27", 27, {0, {0}}, 0, 0 },
-  { "cpr28", 28, {0, {0}}, 0, 0 },
-  { "cpr29", 29, {0, {0}}, 0, 0 },
-  { "cpr30", 30, {0, {0}}, 0, 0 },
-  { "cpr31", 31, {0, {0}}, 0, 0 },
-  { "cpr32", 32, {0, {0}}, 0, 0 },
-  { "cpr33", 33, {0, {0}}, 0, 0 },
-  { "cpr34", 34, {0, {0}}, 0, 0 },
-  { "cpr35", 35, {0, {0}}, 0, 0 },
-  { "cpr36", 36, {0, {0}}, 0, 0 },
-  { "cpr37", 37, {0, {0}}, 0, 0 },
-  { "cpr38", 38, {0, {0}}, 0, 0 },
-  { "cpr39", 39, {0, {0}}, 0, 0 },
-  { "cpr40", 40, {0, {0}}, 0, 0 },
-  { "cpr41", 41, {0, {0}}, 0, 0 },
-  { "cpr42", 42, {0, {0}}, 0, 0 },
-  { "cpr43", 43, {0, {0}}, 0, 0 },
-  { "cpr44", 44, {0, {0}}, 0, 0 },
-  { "cpr45", 45, {0, {0}}, 0, 0 },
-  { "cpr46", 46, {0, {0}}, 0, 0 },
-  { "cpr47", 47, {0, {0}}, 0, 0 },
-  { "cpr48", 48, {0, {0}}, 0, 0 },
-  { "cpr49", 49, {0, {0}}, 0, 0 },
-  { "cpr50", 50, {0, {0}}, 0, 0 },
-  { "cpr51", 51, {0, {0}}, 0, 0 },
-  { "cpr52", 52, {0, {0}}, 0, 0 },
-  { "cpr53", 53, {0, {0}}, 0, 0 },
-  { "cpr54", 54, {0, {0}}, 0, 0 },
-  { "cpr55", 55, {0, {0}}, 0, 0 },
-  { "cpr56", 56, {0, {0}}, 0, 0 },
-  { "cpr57", 57, {0, {0}}, 0, 0 },
-  { "cpr58", 58, {0, {0}}, 0, 0 },
-  { "cpr59", 59, {0, {0}}, 0, 0 },
-  { "cpr60", 60, {0, {0}}, 0, 0 },
-  { "cpr61", 61, {0, {0}}, 0, 0 },
-  { "cpr62", 62, {0, {0}}, 0, 0 },
-  { "cpr63", 63, {0, {0}}, 0, 0 }
+  { "cpr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_cpr_names =
@@ -523,1028 +523,1028 @@ CGEN_KEYWORD frv_cgen_opval_cpr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 {
-  { "psr", 0, {0, {0}}, 0, 0 },
-  { "pcsr", 1, {0, {0}}, 0, 0 },
-  { "bpcsr", 2, {0, {0}}, 0, 0 },
-  { "tbr", 3, {0, {0}}, 0, 0 },
-  { "bpsr", 4, {0, {0}}, 0, 0 },
-  { "hsr0", 16, {0, {0}}, 0, 0 },
-  { "hsr1", 17, {0, {0}}, 0, 0 },
-  { "hsr2", 18, {0, {0}}, 0, 0 },
-  { "hsr3", 19, {0, {0}}, 0, 0 },
-  { "hsr4", 20, {0, {0}}, 0, 0 },
-  { "hsr5", 21, {0, {0}}, 0, 0 },
-  { "hsr6", 22, {0, {0}}, 0, 0 },
-  { "hsr7", 23, {0, {0}}, 0, 0 },
-  { "hsr8", 24, {0, {0}}, 0, 0 },
-  { "hsr9", 25, {0, {0}}, 0, 0 },
-  { "hsr10", 26, {0, {0}}, 0, 0 },
-  { "hsr11", 27, {0, {0}}, 0, 0 },
-  { "hsr12", 28, {0, {0}}, 0, 0 },
-  { "hsr13", 29, {0, {0}}, 0, 0 },
-  { "hsr14", 30, {0, {0}}, 0, 0 },
-  { "hsr15", 31, {0, {0}}, 0, 0 },
-  { "hsr16", 32, {0, {0}}, 0, 0 },
-  { "hsr17", 33, {0, {0}}, 0, 0 },
-  { "hsr18", 34, {0, {0}}, 0, 0 },
-  { "hsr19", 35, {0, {0}}, 0, 0 },
-  { "hsr20", 36, {0, {0}}, 0, 0 },
-  { "hsr21", 37, {0, {0}}, 0, 0 },
-  { "hsr22", 38, {0, {0}}, 0, 0 },
-  { "hsr23", 39, {0, {0}}, 0, 0 },
-  { "hsr24", 40, {0, {0}}, 0, 0 },
-  { "hsr25", 41, {0, {0}}, 0, 0 },
-  { "hsr26", 42, {0, {0}}, 0, 0 },
-  { "hsr27", 43, {0, {0}}, 0, 0 },
-  { "hsr28", 44, {0, {0}}, 0, 0 },
-  { "hsr29", 45, {0, {0}}, 0, 0 },
-  { "hsr30", 46, {0, {0}}, 0, 0 },
-  { "hsr31", 47, {0, {0}}, 0, 0 },
-  { "hsr32", 48, {0, {0}}, 0, 0 },
-  { "hsr33", 49, {0, {0}}, 0, 0 },
-  { "hsr34", 50, {0, {0}}, 0, 0 },
-  { "hsr35", 51, {0, {0}}, 0, 0 },
-  { "hsr36", 52, {0, {0}}, 0, 0 },
-  { "hsr37", 53, {0, {0}}, 0, 0 },
-  { "hsr38", 54, {0, {0}}, 0, 0 },
-  { "hsr39", 55, {0, {0}}, 0, 0 },
-  { "hsr40", 56, {0, {0}}, 0, 0 },
-  { "hsr41", 57, {0, {0}}, 0, 0 },
-  { "hsr42", 58, {0, {0}}, 0, 0 },
-  { "hsr43", 59, {0, {0}}, 0, 0 },
-  { "hsr44", 60, {0, {0}}, 0, 0 },
-  { "hsr45", 61, {0, {0}}, 0, 0 },
-  { "hsr46", 62, {0, {0}}, 0, 0 },
-  { "hsr47", 63, {0, {0}}, 0, 0 },
-  { "hsr48", 64, {0, {0}}, 0, 0 },
-  { "hsr49", 65, {0, {0}}, 0, 0 },
-  { "hsr50", 66, {0, {0}}, 0, 0 },
-  { "hsr51", 67, {0, {0}}, 0, 0 },
-  { "hsr52", 68, {0, {0}}, 0, 0 },
-  { "hsr53", 69, {0, {0}}, 0, 0 },
-  { "hsr54", 70, {0, {0}}, 0, 0 },
-  { "hsr55", 71, {0, {0}}, 0, 0 },
-  { "hsr56", 72, {0, {0}}, 0, 0 },
-  { "hsr57", 73, {0, {0}}, 0, 0 },
-  { "hsr58", 74, {0, {0}}, 0, 0 },
-  { "hsr59", 75, {0, {0}}, 0, 0 },
-  { "hsr60", 76, {0, {0}}, 0, 0 },
-  { "hsr61", 77, {0, {0}}, 0, 0 },
-  { "hsr62", 78, {0, {0}}, 0, 0 },
-  { "hsr63", 79, {0, {0}}, 0, 0 },
-  { "ccr", 256, {0, {0}}, 0, 0 },
-  { "cccr", 263, {0, {0}}, 0, 0 },
-  { "lr", 272, {0, {0}}, 0, 0 },
-  { "lcr", 273, {0, {0}}, 0, 0 },
-  { "iacc0h", 280, {0, {0}}, 0, 0 },
-  { "iacc0l", 281, {0, {0}}, 0, 0 },
-  { "isr", 288, {0, {0}}, 0, 0 },
-  { "neear0", 352, {0, {0}}, 0, 0 },
-  { "neear1", 353, {0, {0}}, 0, 0 },
-  { "neear2", 354, {0, {0}}, 0, 0 },
-  { "neear3", 355, {0, {0}}, 0, 0 },
-  { "neear4", 356, {0, {0}}, 0, 0 },
-  { "neear5", 357, {0, {0}}, 0, 0 },
-  { "neear6", 358, {0, {0}}, 0, 0 },
-  { "neear7", 359, {0, {0}}, 0, 0 },
-  { "neear8", 360, {0, {0}}, 0, 0 },
-  { "neear9", 361, {0, {0}}, 0, 0 },
-  { "neear10", 362, {0, {0}}, 0, 0 },
-  { "neear11", 363, {0, {0}}, 0, 0 },
-  { "neear12", 364, {0, {0}}, 0, 0 },
-  { "neear13", 365, {0, {0}}, 0, 0 },
-  { "neear14", 366, {0, {0}}, 0, 0 },
-  { "neear15", 367, {0, {0}}, 0, 0 },
-  { "neear16", 368, {0, {0}}, 0, 0 },
-  { "neear17", 369, {0, {0}}, 0, 0 },
-  { "neear18", 370, {0, {0}}, 0, 0 },
-  { "neear19", 371, {0, {0}}, 0, 0 },
-  { "neear20", 372, {0, {0}}, 0, 0 },
-  { "neear21", 373, {0, {0}}, 0, 0 },
-  { "neear22", 374, {0, {0}}, 0, 0 },
-  { "neear23", 375, {0, {0}}, 0, 0 },
-  { "neear24", 376, {0, {0}}, 0, 0 },
-  { "neear25", 377, {0, {0}}, 0, 0 },
-  { "neear26", 378, {0, {0}}, 0, 0 },
-  { "neear27", 379, {0, {0}}, 0, 0 },
-  { "neear28", 380, {0, {0}}, 0, 0 },
-  { "neear29", 381, {0, {0}}, 0, 0 },
-  { "neear30", 382, {0, {0}}, 0, 0 },
-  { "neear31", 383, {0, {0}}, 0, 0 },
-  { "nesr0", 384, {0, {0}}, 0, 0 },
-  { "nesr1", 385, {0, {0}}, 0, 0 },
-  { "nesr2", 386, {0, {0}}, 0, 0 },
-  { "nesr3", 387, {0, {0}}, 0, 0 },
-  { "nesr4", 388, {0, {0}}, 0, 0 },
-  { "nesr5", 389, {0, {0}}, 0, 0 },
-  { "nesr6", 390, {0, {0}}, 0, 0 },
-  { "nesr7", 391, {0, {0}}, 0, 0 },
-  { "nesr8", 392, {0, {0}}, 0, 0 },
-  { "nesr9", 393, {0, {0}}, 0, 0 },
-  { "nesr10", 394, {0, {0}}, 0, 0 },
-  { "nesr11", 395, {0, {0}}, 0, 0 },
-  { "nesr12", 396, {0, {0}}, 0, 0 },
-  { "nesr13", 397, {0, {0}}, 0, 0 },
-  { "nesr14", 398, {0, {0}}, 0, 0 },
-  { "nesr15", 399, {0, {0}}, 0, 0 },
-  { "nesr16", 400, {0, {0}}, 0, 0 },
-  { "nesr17", 401, {0, {0}}, 0, 0 },
-  { "nesr18", 402, {0, {0}}, 0, 0 },
-  { "nesr19", 403, {0, {0}}, 0, 0 },
-  { "nesr20", 404, {0, {0}}, 0, 0 },
-  { "nesr21", 405, {0, {0}}, 0, 0 },
-  { "nesr22", 406, {0, {0}}, 0, 0 },
-  { "nesr23", 407, {0, {0}}, 0, 0 },
-  { "nesr24", 408, {0, {0}}, 0, 0 },
-  { "nesr25", 409, {0, {0}}, 0, 0 },
-  { "nesr26", 410, {0, {0}}, 0, 0 },
-  { "nesr27", 411, {0, {0}}, 0, 0 },
-  { "nesr28", 412, {0, {0}}, 0, 0 },
-  { "nesr29", 413, {0, {0}}, 0, 0 },
-  { "nesr30", 414, {0, {0}}, 0, 0 },
-  { "nesr31", 415, {0, {0}}, 0, 0 },
-  { "necr", 416, {0, {0}}, 0, 0 },
-  { "gner0", 432, {0, {0}}, 0, 0 },
-  { "gner1", 433, {0, {0}}, 0, 0 },
-  { "fner0", 434, {0, {0}}, 0, 0 },
-  { "fner1", 435, {0, {0}}, 0, 0 },
-  { "epcr0", 512, {0, {0}}, 0, 0 },
-  { "epcr1", 513, {0, {0}}, 0, 0 },
-  { "epcr2", 514, {0, {0}}, 0, 0 },
-  { "epcr3", 515, {0, {0}}, 0, 0 },
-  { "epcr4", 516, {0, {0}}, 0, 0 },
-  { "epcr5", 517, {0, {0}}, 0, 0 },
-  { "epcr6", 518, {0, {0}}, 0, 0 },
-  { "epcr7", 519, {0, {0}}, 0, 0 },
-  { "epcr8", 520, {0, {0}}, 0, 0 },
-  { "epcr9", 521, {0, {0}}, 0, 0 },
-  { "epcr10", 522, {0, {0}}, 0, 0 },
-  { "epcr11", 523, {0, {0}}, 0, 0 },
-  { "epcr12", 524, {0, {0}}, 0, 0 },
-  { "epcr13", 525, {0, {0}}, 0, 0 },
-  { "epcr14", 526, {0, {0}}, 0, 0 },
-  { "epcr15", 527, {0, {0}}, 0, 0 },
-  { "epcr16", 528, {0, {0}}, 0, 0 },
-  { "epcr17", 529, {0, {0}}, 0, 0 },
-  { "epcr18", 530, {0, {0}}, 0, 0 },
-  { "epcr19", 531, {0, {0}}, 0, 0 },
-  { "epcr20", 532, {0, {0}}, 0, 0 },
-  { "epcr21", 533, {0, {0}}, 0, 0 },
-  { "epcr22", 534, {0, {0}}, 0, 0 },
-  { "epcr23", 535, {0, {0}}, 0, 0 },
-  { "epcr24", 536, {0, {0}}, 0, 0 },
-  { "epcr25", 537, {0, {0}}, 0, 0 },
-  { "epcr26", 538, {0, {0}}, 0, 0 },
-  { "epcr27", 539, {0, {0}}, 0, 0 },
-  { "epcr28", 540, {0, {0}}, 0, 0 },
-  { "epcr29", 541, {0, {0}}, 0, 0 },
-  { "epcr30", 542, {0, {0}}, 0, 0 },
-  { "epcr31", 543, {0, {0}}, 0, 0 },
-  { "epcr32", 544, {0, {0}}, 0, 0 },
-  { "epcr33", 545, {0, {0}}, 0, 0 },
-  { "epcr34", 546, {0, {0}}, 0, 0 },
-  { "epcr35", 547, {0, {0}}, 0, 0 },
-  { "epcr36", 548, {0, {0}}, 0, 0 },
-  { "epcr37", 549, {0, {0}}, 0, 0 },
-  { "epcr38", 550, {0, {0}}, 0, 0 },
-  { "epcr39", 551, {0, {0}}, 0, 0 },
-  { "epcr40", 552, {0, {0}}, 0, 0 },
-  { "epcr41", 553, {0, {0}}, 0, 0 },
-  { "epcr42", 554, {0, {0}}, 0, 0 },
-  { "epcr43", 555, {0, {0}}, 0, 0 },
-  { "epcr44", 556, {0, {0}}, 0, 0 },
-  { "epcr45", 557, {0, {0}}, 0, 0 },
-  { "epcr46", 558, {0, {0}}, 0, 0 },
-  { "epcr47", 559, {0, {0}}, 0, 0 },
-  { "epcr48", 560, {0, {0}}, 0, 0 },
-  { "epcr49", 561, {0, {0}}, 0, 0 },
-  { "epcr50", 562, {0, {0}}, 0, 0 },
-  { "epcr51", 563, {0, {0}}, 0, 0 },
-  { "epcr52", 564, {0, {0}}, 0, 0 },
-  { "epcr53", 565, {0, {0}}, 0, 0 },
-  { "epcr54", 566, {0, {0}}, 0, 0 },
-  { "epcr55", 567, {0, {0}}, 0, 0 },
-  { "epcr56", 568, {0, {0}}, 0, 0 },
-  { "epcr57", 569, {0, {0}}, 0, 0 },
-  { "epcr58", 570, {0, {0}}, 0, 0 },
-  { "epcr59", 571, {0, {0}}, 0, 0 },
-  { "epcr60", 572, {0, {0}}, 0, 0 },
-  { "epcr61", 573, {0, {0}}, 0, 0 },
-  { "epcr62", 574, {0, {0}}, 0, 0 },
-  { "epcr63", 575, {0, {0}}, 0, 0 },
-  { "esr0", 576, {0, {0}}, 0, 0 },
-  { "esr1", 577, {0, {0}}, 0, 0 },
-  { "esr2", 578, {0, {0}}, 0, 0 },
-  { "esr3", 579, {0, {0}}, 0, 0 },
-  { "esr4", 580, {0, {0}}, 0, 0 },
-  { "esr5", 581, {0, {0}}, 0, 0 },
-  { "esr6", 582, {0, {0}}, 0, 0 },
-  { "esr7", 583, {0, {0}}, 0, 0 },
-  { "esr8", 584, {0, {0}}, 0, 0 },
-  { "esr9", 585, {0, {0}}, 0, 0 },
-  { "esr10", 586, {0, {0}}, 0, 0 },
-  { "esr11", 587, {0, {0}}, 0, 0 },
-  { "esr12", 588, {0, {0}}, 0, 0 },
-  { "esr13", 589, {0, {0}}, 0, 0 },
-  { "esr14", 590, {0, {0}}, 0, 0 },
-  { "esr15", 591, {0, {0}}, 0, 0 },
-  { "esr16", 592, {0, {0}}, 0, 0 },
-  { "esr17", 593, {0, {0}}, 0, 0 },
-  { "esr18", 594, {0, {0}}, 0, 0 },
-  { "esr19", 595, {0, {0}}, 0, 0 },
-  { "esr20", 596, {0, {0}}, 0, 0 },
-  { "esr21", 597, {0, {0}}, 0, 0 },
-  { "esr22", 598, {0, {0}}, 0, 0 },
-  { "esr23", 599, {0, {0}}, 0, 0 },
-  { "esr24", 600, {0, {0}}, 0, 0 },
-  { "esr25", 601, {0, {0}}, 0, 0 },
-  { "esr26", 602, {0, {0}}, 0, 0 },
-  { "esr27", 603, {0, {0}}, 0, 0 },
-  { "esr28", 604, {0, {0}}, 0, 0 },
-  { "esr29", 605, {0, {0}}, 0, 0 },
-  { "esr30", 606, {0, {0}}, 0, 0 },
-  { "esr31", 607, {0, {0}}, 0, 0 },
-  { "esr32", 608, {0, {0}}, 0, 0 },
-  { "esr33", 609, {0, {0}}, 0, 0 },
-  { "esr34", 610, {0, {0}}, 0, 0 },
-  { "esr35", 611, {0, {0}}, 0, 0 },
-  { "esr36", 612, {0, {0}}, 0, 0 },
-  { "esr37", 613, {0, {0}}, 0, 0 },
-  { "esr38", 614, {0, {0}}, 0, 0 },
-  { "esr39", 615, {0, {0}}, 0, 0 },
-  { "esr40", 616, {0, {0}}, 0, 0 },
-  { "esr41", 617, {0, {0}}, 0, 0 },
-  { "esr42", 618, {0, {0}}, 0, 0 },
-  { "esr43", 619, {0, {0}}, 0, 0 },
-  { "esr44", 620, {0, {0}}, 0, 0 },
-  { "esr45", 621, {0, {0}}, 0, 0 },
-  { "esr46", 622, {0, {0}}, 0, 0 },
-  { "esr47", 623, {0, {0}}, 0, 0 },
-  { "esr48", 624, {0, {0}}, 0, 0 },
-  { "esr49", 625, {0, {0}}, 0, 0 },
-  { "esr50", 626, {0, {0}}, 0, 0 },
-  { "esr51", 627, {0, {0}}, 0, 0 },
-  { "esr52", 628, {0, {0}}, 0, 0 },
-  { "esr53", 629, {0, {0}}, 0, 0 },
-  { "esr54", 630, {0, {0}}, 0, 0 },
-  { "esr55", 631, {0, {0}}, 0, 0 },
-  { "esr56", 632, {0, {0}}, 0, 0 },
-  { "esr57", 633, {0, {0}}, 0, 0 },
-  { "esr58", 634, {0, {0}}, 0, 0 },
-  { "esr59", 635, {0, {0}}, 0, 0 },
-  { "esr60", 636, {0, {0}}, 0, 0 },
-  { "esr61", 637, {0, {0}}, 0, 0 },
-  { "esr62", 638, {0, {0}}, 0, 0 },
-  { "esr63", 639, {0, {0}}, 0, 0 },
-  { "eir0", 640, {0, {0}}, 0, 0 },
-  { "eir1", 641, {0, {0}}, 0, 0 },
-  { "eir2", 642, {0, {0}}, 0, 0 },
-  { "eir3", 643, {0, {0}}, 0, 0 },
-  { "eir4", 644, {0, {0}}, 0, 0 },
-  { "eir5", 645, {0, {0}}, 0, 0 },
-  { "eir6", 646, {0, {0}}, 0, 0 },
-  { "eir7", 647, {0, {0}}, 0, 0 },
-  { "eir8", 648, {0, {0}}, 0, 0 },
-  { "eir9", 649, {0, {0}}, 0, 0 },
-  { "eir10", 650, {0, {0}}, 0, 0 },
-  { "eir11", 651, {0, {0}}, 0, 0 },
-  { "eir12", 652, {0, {0}}, 0, 0 },
-  { "eir13", 653, {0, {0}}, 0, 0 },
-  { "eir14", 654, {0, {0}}, 0, 0 },
-  { "eir15", 655, {0, {0}}, 0, 0 },
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-  { "dbmr00", 2076, {0, {0}}, 0, 0 },
-  { "dbmr01", 2077, {0, {0}}, 0, 0 },
-  { "dbmr02", 2078, {0, {0}}, 0, 0 },
-  { "dbmr03", 2079, {0, {0}}, 0, 0 },
-  { "dbmr10", 2080, {0, {0}}, 0, 0 },
-  { "dbmr11", 2081, {0, {0}}, 0, 0 },
-  { "dbmr12", 2082, {0, {0}}, 0, 0 },
-  { "dbmr13", 2083, {0, {0}}, 0, 0 },
-  { "dbmr20", 2084, {0, {0}}, 0, 0 },
-  { "dbmr21", 2085, {0, {0}}, 0, 0 },
-  { "dbmr22", 2086, {0, {0}}, 0, 0 },
-  { "dbmr23", 2087, {0, {0}}, 0, 0 },
-  { "dbmr30", 2088, {0, {0}}, 0, 0 },
-  { "dbmr31", 2089, {0, {0}}, 0, 0 },
-  { "dbmr32", 2090, {0, {0}}, 0, 0 },
-  { "dbmr33", 2091, {0, {0}}, 0, 0 },
-  { "cpcfr", 2092, {0, {0}}, 0, 0 },
-  { "cpcr", 2093, {0, {0}}, 0, 0 },
-  { "cpsr", 2094, {0, {0}}, 0, 0 },
-  { "cpesr0", 2096, {0, {0}}, 0, 0 },
-  { "cpesr1", 2097, {0, {0}}, 0, 0 },
-  { "cpemr0", 2098, {0, {0}}, 0, 0 },
-  { "cpemr1", 2099, {0, {0}}, 0, 0 },
-  { "ihsr8", 3848, {0, {0}}, 0, 0 }
+  { "psr", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "pcsr", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "bpcsr", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "tbr", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "bpsr", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr0", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr1", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr2", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr3", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr4", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr5", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr6", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr7", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr8", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr9", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr10", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr11", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr12", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr13", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr14", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr15", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr16", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr17", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr18", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr19", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr20", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr21", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr22", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr23", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr24", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr25", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr26", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr27", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr28", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr29", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr30", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr31", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr32", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr33", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr34", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr35", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr36", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr37", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr38", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr39", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr40", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr41", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr42", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr43", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr44", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr45", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr46", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr47", 63, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr48", 64, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr49", 65, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr50", 66, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr51", 67, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr52", 68, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr53", 69, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr54", 70, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr55", 71, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr56", 72, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr57", 73, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr58", 74, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr59", 75, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr60", 76, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr61", 77, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr62", 78, {0, {{{0, 0}}}}, 0, 0 },
+  { "hsr63", 79, {0, {{{0, 0}}}}, 0, 0 },
+  { "ccr", 256, {0, {{{0, 0}}}}, 0, 0 },
+  { "cccr", 263, {0, {{{0, 0}}}}, 0, 0 },
+  { "lr", 272, {0, {{{0, 0}}}}, 0, 0 },
+  { "lcr", 273, {0, {{{0, 0}}}}, 0, 0 },
+  { "iacc0h", 280, {0, {{{0, 0}}}}, 0, 0 },
+  { "iacc0l", 281, {0, {{{0, 0}}}}, 0, 0 },
+  { "isr", 288, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear0", 352, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear1", 353, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear2", 354, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear3", 355, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear4", 356, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear5", 357, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear6", 358, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear7", 359, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear8", 360, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear9", 361, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear10", 362, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear11", 363, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear12", 364, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear13", 365, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear14", 366, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear15", 367, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear16", 368, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear17", 369, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear18", 370, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear19", 371, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear20", 372, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear21", 373, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear22", 374, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear23", 375, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear24", 376, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear25", 377, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear26", 378, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear27", 379, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear28", 380, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear29", 381, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear30", 382, {0, {{{0, 0}}}}, 0, 0 },
+  { "neear31", 383, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr0", 384, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr1", 385, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr2", 386, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr3", 387, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr4", 388, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr5", 389, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr6", 390, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr7", 391, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr8", 392, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr9", 393, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr10", 394, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr11", 395, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr12", 396, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr13", 397, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr14", 398, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr15", 399, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr16", 400, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr17", 401, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr18", 402, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr19", 403, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr20", 404, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr21", 405, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr22", 406, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr23", 407, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr24", 408, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr25", 409, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr26", 410, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr27", 411, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr28", 412, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr29", 413, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr30", 414, {0, {{{0, 0}}}}, 0, 0 },
+  { "nesr31", 415, {0, {{{0, 0}}}}, 0, 0 },
+  { "necr", 416, {0, {{{0, 0}}}}, 0, 0 },
+  { "gner0", 432, {0, {{{0, 0}}}}, 0, 0 },
+  { "gner1", 433, {0, {{{0, 0}}}}, 0, 0 },
+  { "fner0", 434, {0, {{{0, 0}}}}, 0, 0 },
+  { "fner1", 435, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr0", 512, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr1", 513, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr2", 514, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr3", 515, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr4", 516, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr5", 517, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr6", 518, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr7", 519, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr8", 520, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr9", 521, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr10", 522, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr11", 523, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr12", 524, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr13", 525, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr14", 526, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr15", 527, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr16", 528, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr17", 529, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr18", 530, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr19", 531, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr20", 532, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr21", 533, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr22", 534, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr23", 535, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr24", 536, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr25", 537, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr26", 538, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr27", 539, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr28", 540, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr29", 541, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr30", 542, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr31", 543, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr32", 544, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr33", 545, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr34", 546, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr35", 547, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr36", 548, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr37", 549, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr38", 550, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr39", 551, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr40", 552, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr41", 553, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr42", 554, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr43", 555, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr44", 556, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr45", 557, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr46", 558, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr47", 559, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr48", 560, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr49", 561, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr50", 562, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr51", 563, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr52", 564, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr53", 565, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr54", 566, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr55", 567, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr56", 568, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr57", 569, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr58", 570, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr59", 571, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr60", 572, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr61", 573, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr62", 574, {0, {{{0, 0}}}}, 0, 0 },
+  { "epcr63", 575, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr0", 576, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr1", 577, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr2", 578, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr3", 579, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr4", 580, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr5", 581, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr6", 582, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr7", 583, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr8", 584, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr9", 585, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr10", 586, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr11", 587, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr12", 588, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr13", 589, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr14", 590, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr15", 591, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr16", 592, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr17", 593, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr18", 594, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr19", 595, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr20", 596, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr21", 597, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr22", 598, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr23", 599, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr24", 600, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr25", 601, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr26", 602, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr27", 603, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr28", 604, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr29", 605, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr30", 606, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr31", 607, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr32", 608, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr33", 609, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr34", 610, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr35", 611, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr36", 612, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr37", 613, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr38", 614, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr39", 615, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr40", 616, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr41", 617, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr42", 618, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr43", 619, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr44", 620, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr45", 621, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr46", 622, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr47", 623, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr48", 624, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr49", 625, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr50", 626, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr51", 627, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr52", 628, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr53", 629, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr54", 630, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr55", 631, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr56", 632, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr57", 633, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr58", 634, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr59", 635, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr60", 636, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr61", 637, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr62", 638, {0, {{{0, 0}}}}, 0, 0 },
+  { "esr63", 639, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir0", 640, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir1", 641, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir2", 642, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir3", 643, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir4", 644, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir5", 645, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir6", 646, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir7", 647, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir8", 648, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir9", 649, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir10", 650, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir11", 651, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir12", 652, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir13", 653, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir14", 654, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir15", 655, {0, {{{0, 0}}}}, 0, 0 },
+  { "eir16", 656, {0, {{{0, 0}}}}, 0, 0 },
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+  { "dampr0", 1856, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr1", 1857, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr2", 1858, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr3", 1859, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr4", 1860, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr5", 1861, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr6", 1862, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr7", 1863, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr8", 1864, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr9", 1865, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr10", 1866, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr11", 1867, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr12", 1868, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr13", 1869, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr14", 1870, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr15", 1871, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr16", 1872, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr17", 1873, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr18", 1874, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr19", 1875, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr20", 1876, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr21", 1877, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr22", 1878, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr23", 1879, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr24", 1880, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr25", 1881, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr26", 1882, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr27", 1883, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr28", 1884, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr29", 1885, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr30", 1886, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr31", 1887, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr32", 1888, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr33", 1889, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr34", 1890, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr35", 1891, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr36", 1892, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr37", 1893, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr38", 1894, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr39", 1895, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr40", 1896, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr41", 1897, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr42", 1898, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr43", 1899, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr44", 1900, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr45", 1901, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr46", 1902, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr47", 1903, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr48", 1904, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr49", 1905, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr50", 1906, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr51", 1907, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr52", 1908, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr53", 1909, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr54", 1910, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr55", 1911, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr56", 1912, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr57", 1913, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr58", 1914, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr59", 1915, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr60", 1916, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr61", 1917, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr62", 1918, {0, {{{0, 0}}}}, 0, 0 },
+  { "dampr63", 1919, {0, {{{0, 0}}}}, 0, 0 },
+  { "amcr", 1920, {0, {{{0, 0}}}}, 0, 0 },
+  { "stbar", 1921, {0, {{{0, 0}}}}, 0, 0 },
+  { "mmcr", 1922, {0, {{{0, 0}}}}, 0, 0 },
+  { "iamvr1", 1925, {0, {{{0, 0}}}}, 0, 0 },
+  { "damvr1", 1927, {0, {{{0, 0}}}}, 0, 0 },
+  { "cxnr", 1936, {0, {{{0, 0}}}}, 0, 0 },
+  { "ttbr", 1937, {0, {{{0, 0}}}}, 0, 0 },
+  { "tplr", 1938, {0, {{{0, 0}}}}, 0, 0 },
+  { "tppr", 1939, {0, {{{0, 0}}}}, 0, 0 },
+  { "tpxr", 1940, {0, {{{0, 0}}}}, 0, 0 },
+  { "timerh", 1952, {0, {{{0, 0}}}}, 0, 0 },
+  { "timerl", 1953, {0, {{{0, 0}}}}, 0, 0 },
+  { "timerd", 1954, {0, {{{0, 0}}}}, 0, 0 },
+  { "dcr", 2048, {0, {{{0, 0}}}}, 0, 0 },
+  { "brr", 2049, {0, {{{0, 0}}}}, 0, 0 },
+  { "nmar", 2050, {0, {{{0, 0}}}}, 0, 0 },
+  { "btbr", 2051, {0, {{{0, 0}}}}, 0, 0 },
+  { "ibar0", 2052, {0, {{{0, 0}}}}, 0, 0 },
+  { "ibar1", 2053, {0, {{{0, 0}}}}, 0, 0 },
+  { "ibar2", 2054, {0, {{{0, 0}}}}, 0, 0 },
+  { "ibar3", 2055, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbar0", 2056, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbar1", 2057, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbar2", 2058, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbar3", 2059, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr00", 2060, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr01", 2061, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr02", 2062, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr03", 2063, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr10", 2064, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr11", 2065, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr12", 2066, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr13", 2067, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr20", 2068, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr21", 2069, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr22", 2070, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr23", 2071, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr30", 2072, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr31", 2073, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr32", 2074, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbdr33", 2075, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr00", 2076, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr01", 2077, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr02", 2078, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr03", 2079, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr10", 2080, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr11", 2081, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr12", 2082, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr13", 2083, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr20", 2084, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr21", 2085, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr22", 2086, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr23", 2087, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr30", 2088, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 },
+  { "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpcfr", 2092, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpcr", 2093, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpsr", 2094, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpesr0", 2096, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpesr1", 2097, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpemr0", 2098, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpemr1", 2099, {0, {{{0, 0}}}}, 0, 0 },
+  { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_spr_names =
@@ -1556,70 +1556,70 @@ CGEN_KEYWORD frv_cgen_opval_spr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
 {
-  { "accg0", 0, {0, {0}}, 0, 0 },
-  { "accg1", 1, {0, {0}}, 0, 0 },
-  { "accg2", 2, {0, {0}}, 0, 0 },
-  { "accg3", 3, {0, {0}}, 0, 0 },
-  { "accg4", 4, {0, {0}}, 0, 0 },
-  { "accg5", 5, {0, {0}}, 0, 0 },
-  { "accg6", 6, {0, {0}}, 0, 0 },
-  { "accg7", 7, {0, {0}}, 0, 0 },
-  { "accg8", 8, {0, {0}}, 0, 0 },
-  { "accg9", 9, {0, {0}}, 0, 0 },
-  { "accg10", 10, {0, {0}}, 0, 0 },
-  { "accg11", 11, {0, {0}}, 0, 0 },
-  { "accg12", 12, {0, {0}}, 0, 0 },
-  { "accg13", 13, {0, {0}}, 0, 0 },
-  { "accg14", 14, {0, {0}}, 0, 0 },
-  { "accg15", 15, {0, {0}}, 0, 0 },
-  { "accg16", 16, {0, {0}}, 0, 0 },
-  { "accg17", 17, {0, {0}}, 0, 0 },
-  { "accg18", 18, {0, {0}}, 0, 0 },
-  { "accg19", 19, {0, {0}}, 0, 0 },
-  { "accg20", 20, {0, {0}}, 0, 0 },
-  { "accg21", 21, {0, {0}}, 0, 0 },
-  { "accg22", 22, {0, {0}}, 0, 0 },
-  { "accg23", 23, {0, {0}}, 0, 0 },
-  { "accg24", 24, {0, {0}}, 0, 0 },
-  { "accg25", 25, {0, {0}}, 0, 0 },
-  { "accg26", 26, {0, {0}}, 0, 0 },
-  { "accg27", 27, {0, {0}}, 0, 0 },
-  { "accg28", 28, {0, {0}}, 0, 0 },
-  { "accg29", 29, {0, {0}}, 0, 0 },
-  { "accg30", 30, {0, {0}}, 0, 0 },
-  { "accg31", 31, {0, {0}}, 0, 0 },
-  { "accg32", 32, {0, {0}}, 0, 0 },
-  { "accg33", 33, {0, {0}}, 0, 0 },
-  { "accg34", 34, {0, {0}}, 0, 0 },
-  { "accg35", 35, {0, {0}}, 0, 0 },
-  { "accg36", 36, {0, {0}}, 0, 0 },
-  { "accg37", 37, {0, {0}}, 0, 0 },
-  { "accg38", 38, {0, {0}}, 0, 0 },
-  { "accg39", 39, {0, {0}}, 0, 0 },
-  { "accg40", 40, {0, {0}}, 0, 0 },
-  { "accg41", 41, {0, {0}}, 0, 0 },
-  { "accg42", 42, {0, {0}}, 0, 0 },
-  { "accg43", 43, {0, {0}}, 0, 0 },
-  { "accg44", 44, {0, {0}}, 0, 0 },
-  { "accg45", 45, {0, {0}}, 0, 0 },
-  { "accg46", 46, {0, {0}}, 0, 0 },
-  { "accg47", 47, {0, {0}}, 0, 0 },
-  { "accg48", 48, {0, {0}}, 0, 0 },
-  { "accg49", 49, {0, {0}}, 0, 0 },
-  { "accg50", 50, {0, {0}}, 0, 0 },
-  { "accg51", 51, {0, {0}}, 0, 0 },
-  { "accg52", 52, {0, {0}}, 0, 0 },
-  { "accg53", 53, {0, {0}}, 0, 0 },
-  { "accg54", 54, {0, {0}}, 0, 0 },
-  { "accg55", 55, {0, {0}}, 0, 0 },
-  { "accg56", 56, {0, {0}}, 0, 0 },
-  { "accg57", 57, {0, {0}}, 0, 0 },
-  { "accg58", 58, {0, {0}}, 0, 0 },
-  { "accg59", 59, {0, {0}}, 0, 0 },
-  { "accg60", 60, {0, {0}}, 0, 0 },
-  { "accg61", 61, {0, {0}}, 0, 0 },
-  { "accg62", 62, {0, {0}}, 0, 0 },
-  { "accg63", 63, {0, {0}}, 0, 0 }
+  { "accg0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "accg63", 63, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_accg_names =
@@ -1631,70 +1631,70 @@ CGEN_KEYWORD frv_cgen_opval_accg_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
 {
-  { "acc0", 0, {0, {0}}, 0, 0 },
-  { "acc1", 1, {0, {0}}, 0, 0 },
-  { "acc2", 2, {0, {0}}, 0, 0 },
-  { "acc3", 3, {0, {0}}, 0, 0 },
-  { "acc4", 4, {0, {0}}, 0, 0 },
-  { "acc5", 5, {0, {0}}, 0, 0 },
-  { "acc6", 6, {0, {0}}, 0, 0 },
-  { "acc7", 7, {0, {0}}, 0, 0 },
-  { "acc8", 8, {0, {0}}, 0, 0 },
-  { "acc9", 9, {0, {0}}, 0, 0 },
-  { "acc10", 10, {0, {0}}, 0, 0 },
-  { "acc11", 11, {0, {0}}, 0, 0 },
-  { "acc12", 12, {0, {0}}, 0, 0 },
-  { "acc13", 13, {0, {0}}, 0, 0 },
-  { "acc14", 14, {0, {0}}, 0, 0 },
-  { "acc15", 15, {0, {0}}, 0, 0 },
-  { "acc16", 16, {0, {0}}, 0, 0 },
-  { "acc17", 17, {0, {0}}, 0, 0 },
-  { "acc18", 18, {0, {0}}, 0, 0 },
-  { "acc19", 19, {0, {0}}, 0, 0 },
-  { "acc20", 20, {0, {0}}, 0, 0 },
-  { "acc21", 21, {0, {0}}, 0, 0 },
-  { "acc22", 22, {0, {0}}, 0, 0 },
-  { "acc23", 23, {0, {0}}, 0, 0 },
-  { "acc24", 24, {0, {0}}, 0, 0 },
-  { "acc25", 25, {0, {0}}, 0, 0 },
-  { "acc26", 26, {0, {0}}, 0, 0 },
-  { "acc27", 27, {0, {0}}, 0, 0 },
-  { "acc28", 28, {0, {0}}, 0, 0 },
-  { "acc29", 29, {0, {0}}, 0, 0 },
-  { "acc30", 30, {0, {0}}, 0, 0 },
-  { "acc31", 31, {0, {0}}, 0, 0 },
-  { "acc32", 32, {0, {0}}, 0, 0 },
-  { "acc33", 33, {0, {0}}, 0, 0 },
-  { "acc34", 34, {0, {0}}, 0, 0 },
-  { "acc35", 35, {0, {0}}, 0, 0 },
-  { "acc36", 36, {0, {0}}, 0, 0 },
-  { "acc37", 37, {0, {0}}, 0, 0 },
-  { "acc38", 38, {0, {0}}, 0, 0 },
-  { "acc39", 39, {0, {0}}, 0, 0 },
-  { "acc40", 40, {0, {0}}, 0, 0 },
-  { "acc41", 41, {0, {0}}, 0, 0 },
-  { "acc42", 42, {0, {0}}, 0, 0 },
-  { "acc43", 43, {0, {0}}, 0, 0 },
-  { "acc44", 44, {0, {0}}, 0, 0 },
-  { "acc45", 45, {0, {0}}, 0, 0 },
-  { "acc46", 46, {0, {0}}, 0, 0 },
-  { "acc47", 47, {0, {0}}, 0, 0 },
-  { "acc48", 48, {0, {0}}, 0, 0 },
-  { "acc49", 49, {0, {0}}, 0, 0 },
-  { "acc50", 50, {0, {0}}, 0, 0 },
-  { "acc51", 51, {0, {0}}, 0, 0 },
-  { "acc52", 52, {0, {0}}, 0, 0 },
-  { "acc53", 53, {0, {0}}, 0, 0 },
-  { "acc54", 54, {0, {0}}, 0, 0 },
-  { "acc55", 55, {0, {0}}, 0, 0 },
-  { "acc56", 56, {0, {0}}, 0, 0 },
-  { "acc57", 57, {0, {0}}, 0, 0 },
-  { "acc58", 58, {0, {0}}, 0, 0 },
-  { "acc59", 59, {0, {0}}, 0, 0 },
-  { "acc60", 60, {0, {0}}, 0, 0 },
-  { "acc61", 61, {0, {0}}, 0, 0 },
-  { "acc62", 62, {0, {0}}, 0, 0 },
-  { "acc63", 63, {0, {0}}, 0, 0 }
+  { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc60", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc61", 61, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc62", 62, {0, {{{0, 0}}}}, 0, 0 },
+  { "acc63", 63, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_acc_names =
@@ -1706,7 +1706,7 @@ CGEN_KEYWORD frv_cgen_opval_acc_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] =
 {
-  { "iacc0", 0, {0, {0}}, 0, 0 }
+  { "iacc0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_iacc0_names =
@@ -1718,10 +1718,10 @@ CGEN_KEYWORD frv_cgen_opval_iacc0_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
 {
-  { "icc0", 0, {0, {0}}, 0, 0 },
-  { "icc1", 1, {0, {0}}, 0, 0 },
-  { "icc2", 2, {0, {0}}, 0, 0 },
-  { "icc3", 3, {0, {0}}, 0, 0 }
+  { "icc0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "icc1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "icc2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "icc3", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_iccr_names =
@@ -1733,10 +1733,10 @@ CGEN_KEYWORD frv_cgen_opval_iccr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
 {
-  { "fcc0", 0, {0, {0}}, 0, 0 },
-  { "fcc1", 1, {0, {0}}, 0, 0 },
-  { "fcc2", 2, {0, {0}}, 0, 0 },
-  { "fcc3", 3, {0, {0}}, 0, 0 }
+  { "fcc0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "fcc1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "fcc2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "fcc3", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_fccr_names =
@@ -1748,14 +1748,14 @@ CGEN_KEYWORD frv_cgen_opval_fccr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
 {
-  { "cc0", 0, {0, {0}}, 0, 0 },
-  { "cc1", 1, {0, {0}}, 0, 0 },
-  { "cc2", 2, {0, {0}}, 0, 0 },
-  { "cc3", 3, {0, {0}}, 0, 0 },
-  { "cc4", 4, {0, {0}}, 0, 0 },
-  { "cc5", 5, {0, {0}}, 0, 0 },
-  { "cc6", 6, {0, {0}}, 0, 0 },
-  { "cc7", 7, {0, {0}}, 0, 0 }
+  { "cc0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc7", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_cccr_names =
@@ -1767,9 +1767,9 @@ CGEN_KEYWORD frv_cgen_opval_cccr_names =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
 {
-  { "", 1, {0, {0}}, 0, 0 },
-  { ".p", 0, {0, {0}}, 0, 0 },
-  { ".P", 0, {0, {0}}, 0, 0 }
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { ".p", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".P", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_h_pack =
@@ -1781,10 +1781,10 @@ CGEN_KEYWORD frv_cgen_opval_h_pack =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
 {
-  { "", 2, {0, {0}}, 0, 0 },
-  { "", 0, {0, {0}}, 0, 0 },
-  { "", 1, {0, {0}}, 0, 0 },
-  { "", 3, {0, {0}}, 0, 0 }
+  { "", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
@@ -1796,10 +1796,10 @@ CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
 
 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
 {
-  { "", 0, {0, {0}}, 0, 0 },
-  { "", 1, {0, {0}}, 0, 0 },
-  { "", 2, {0, {0}}, 0, 0 },
-  { "", 3, {0, {0}}, 0, 0 }
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
@@ -1820,57 +1820,57 @@ CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
 
 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-reloc-ann", HW_H_RELOC_ANN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
-  { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
-  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400)|(1<<MACH_FR450) } } },
-  { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
-  { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
-  { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-reloc-ann", HW_H_RELOC_ANN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
+  { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FRV), 0 } } } } },
+  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } } } } },
+  { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -1886,112 +1886,112 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] =
 
 const CGEN_IFLD frv_cgen_ifld_table[] =
 {
-  { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { FRV_F_RELOC_ANN, "f-reloc-ann", 0, 32, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { FRV_F_RELOC_ANN, "f-reloc-ann", 0, 32, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -2044,363 +2044,363 @@ const CGEN_OPERAND frv_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* pack: packing bit */
   { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRi: source register 1 */
   { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRj: source register 2 */
   { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRk: destination register */
   { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRkhi: destination register */
   { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRklo: destination register */
   { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* GRdoublek: destination register */
   { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACC40Si: signed accumulator */
   { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACC40Ui: unsigned accumulator */
   { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACC40Sk: target accumulator */
   { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACC40Uk: target accumulator */
   { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACCGi: source register */
   { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ACCGk: target register */
   { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CPRi: source register */
   { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } }, 
-    { 0, { (1<<MACH_FRV) } }  },
+    { 0, { { { (1<<MACH_FRV), 0 } } } }  },
 /* CPRj: source register */
   { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } }, 
-    { 0, { (1<<MACH_FRV) } }  },
+    { 0, { { { (1<<MACH_FRV), 0 } } } }  },
 /* CPRk: destination register */
   { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, 
-    { 0, { (1<<MACH_FRV) } }  },
+    { 0, { { { (1<<MACH_FRV), 0 } } } }  },
 /* CPRdoublek: destination register */
   { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, 
-    { 0, { (1<<MACH_FRV) } }  },
+    { 0, { { { (1<<MACH_FRV), 0 } } } }  },
 /* FRinti: source register 1 */
   { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRintj: source register 2 */
   { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRintk: target register */
   { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRi: source register 1 */
   { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRj: source register 2 */
   { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRk: destination register */
   { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRkhi: destination register */
   { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRklo: destination register */
   { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRdoublei: source register 1 */
   { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRdoublej: source register 2 */
   { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRdoublek: target register */
   { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRi: source register 1 */
   { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRj: source register 2 */
   { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRj_int: destination register */
   { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRj_float: destination register */
   { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CRk: destination register */
   { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* CCi: condition   register */
   { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ICCi_1: condition   register */
   { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ICCi_2: condition   register */
   { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ICCi_3: condition   register */
   { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FCCi_1: condition   register */
   { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FCCi_2: condition   register */
   { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FCCi_3: condition   register */
   { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FCCk: condition   register */
   { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* eir: exception insn reg */
   { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* s10: 10 bit signed immediate */
   { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u16: 16 bit unsigned immediate */
   { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* s16: 16 bit signed   immediate */
   { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* s6: 6  bit signed   immediate */
   { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* s6_1: 6  bit signed   immediate */
   { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u6: 6  bit unsigned immediate */
   { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* s5: 5  bit signed   immediate */
   { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* cond: conditional arithmetic */
   { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ccond: lr branch condition */
   { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* hint: 2 bit branch predictor */
   { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* hint_taken: 2 bit branch predictor */
   { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* hint_not_taken: 2 bit branch predictor */
   { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* LI: link indicator */
   { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* lock: cache lock indicator */
   { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* debug: debug mode indicator */
   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ae: all entries indicator */
   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* label16: 18 bit pc relative address */
   { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* LRAE: Load Real Address E flag */
   { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* LRAD: Load Real Address D flag */
   { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* LRAS: Load Real Address S flag */
   { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* TLBPRopx: TLB Probe operation number */
   { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* TLBPRL: TLB Probe L flag */
   { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* A0: A==0 operand of mclracc */
   { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* A1: A==1 operand of mclracc */
   { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRintieven: (even) source register 1 */
   { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRintjeven: (even) source register 2 */
   { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* FRintkeven: (even) target register */
   { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* d12: 12 bit signed immediate */
   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* s12: 12 bit signed immediate */
   { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* u12: 12 bit signed immediate */
   { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
     { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } }, 
-    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* spr: special purpose register */
   { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
     { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ulo16: 16 bit unsigned immediate, for #lo() */
   { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* slo16: 16 bit unsigned immediate, for #lo() */
   { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* uhi16: 16 bit unsigned immediate, for #hi() */
   { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* label24: 26 bit pc relative address */
   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, 
-    { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psr_esr: PSR.ESR bit */
   { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psr_s: PSR.S   bit */
   { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psr_ps: PSR.PS  bit */
   { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psr_et: PSR.ET  bit */
   { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* bpsr_bs: BPSR.BS  bit */
   { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* bpsr_bet: BPSR.BET bit */
   { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* tbr_tba: TBR.TBA */
   { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* tbr_tt: TBR.TT */
   { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ldann: ld annotation */
   { "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* lddann: ldd annotation */
   { "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* callann: call annotation */
   { "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0,
     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -2420,3721 +2420,3721 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_NIL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } } },
 /* add$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_ADD, "add", "add", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sub$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SUB, "sub", "sub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* and$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_AND, "and", "and", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* or$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_OR, "or", "or", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* xor$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_XOR, "xor", "xor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* not$pack $GRj,$GRk */
   {
     FRV_INSN_NOT, "not", "not", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* nsdiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* udiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_UDIV, "udiv", "udiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* nudiv$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* smul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_SMUL, "smul", "smul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* umul$pack $GRi,$GRj,$GRdoublek */
   {
     FRV_INSN_UMUL, "umul", "umul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* smu$pack $GRi,$GRj */
   {
     FRV_INSN_SMU, "smu", "smu", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* smass$pack $GRi,$GRj */
   {
     FRV_INSN_SMASS, "smass", "smass", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* smsss$pack $GRi,$GRj */
   {
     FRV_INSN_SMSSS, "smsss", "smsss", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IACC, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* sll$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SLL, "sll", "sll", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* srl$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRL, "srl", "srl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sra$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SRA, "sra", "sra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* slass$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SLASS, "slass", "slass", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* scutss$pack $GRj,$GRk */
   {
     FRV_INSN_SCUTSS, "scutss", "scutss", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_I0, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* scan$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SCAN, "scan", "scan", 32,
-    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADD, "cadd", "cadd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUB, "csub", "csub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CAND, "cand", "cand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_COR, "cor", "cor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXOR, "cxor", "cxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cnot$pack $GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CNOT, "cnot", "cnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMUL, "csmul", "csmul", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLL, "csll", "csll", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRL, "csrl", "csrl", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRA, "csra", "csra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSCAN, "cscan", "cscan", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDCC, "addcc", "addcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBCC, "subcc", "subcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDCC, "andcc", "andcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORCC, "orcc", "orcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRACC, "sracc", "sracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CANDCC, "candcc", "candcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CORCC, "corcc", "corcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
   {
     FRV_INSN_CSRACC, "csracc", "csracc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDX, "addx", "addx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBX, "subx", "subx", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addss$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_ADDSS, "addss", "addss", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* subss$pack $GRi,$GRj,$GRk */
   {
     FRV_INSN_SUBSS, "subss", "subss", 32,
-    { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0|A(AUDIO), { { { (1<<MACH_FR400)|(1<<MACH_FR450), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* addi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ADDI, "addi", "addi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SUBI, "subi", "subi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* andi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ANDI, "andi", "andi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* ori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_ORI, "ori", "ori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* xori$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_XORI, "xori", "xori", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* nsdivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* udivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_UDIVI, "udivi", "udivi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* nudivi$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* smuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_SMULI, "smuli", "smuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* umuli$pack $GRi,$s12,$GRdoublek */
   {
     FRV_INSN_UMULI, "umuli", "umuli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* slli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SLLI, "slli", "slli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* srli$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRLI, "srli", "srli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* srai$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SRAI, "srai", "srai", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* scani$pack $GRi,$s12,$GRk */
   {
     FRV_INSN_SCANI, "scani", "scani", 32,
-    { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_SCAN, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDICC, "addicc", "addicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBICC, "subicc", "subicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ANDICC, "andicc", "andicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ORICC, "oricc", "oricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
   {
     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MULT_DIV, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_2, 0 } } } }
   },
 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXI, "addxi", "addxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXI, "subxi", "subxi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
   {
     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
   {
     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* setlo$pack $ulo16,$GRklo */
   {
     FRV_INSN_SETLO, "setlo", "setlo", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* sethi$pack $uhi16,$GRkhi */
   {
     FRV_INSN_SETHI, "sethi", "sethi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* setlos$pack $slo16,$GRk */
   {
     FRV_INSN_SETLOS, "setlos", "setlos", 32,
-    { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_I_1, 0 } } } }
   },
 /* ldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUB, "ldub", "ldub", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUH, "lduh", "lduh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ld$pack $ldann($GRi,$GRj),$GRk */
   {
     FRV_INSN_LD, "ld", "ld", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDF, "ldf", "ldf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDC, "ldc", "ldc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldsb$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldub$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUB, "nldub", "nldub", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldsh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlduh$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nld$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLD, "nld", "nld", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldbf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldhf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDF, "nldf", "nldf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldd$pack $lddann($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDD, "ldd", "ldd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDF, "lddf", "lddf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDC, "lddc", "lddc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldd$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDD, "nldd", "nldd", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQ, "ldq", "ldq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldqc$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldq$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQ, "nldq", "nldq", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldqf$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDU, "ldu", "ldu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldsbu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldubu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldshu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlduhu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDU, "nldu", "nldu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldbfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldhfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_LDDU, "lddu", "lddu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
   {
     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
   {
     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
   {
     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldqu$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldqcu$pack @($GRi,$GRj),$CPRk */
   {
     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldqfu$pack @($GRi,$GRj),$FRintk */
   {
     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDI, "ldi", "ldi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldsbi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldubi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldshi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlduhi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_NLDI, "nldi", "nldi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldbfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldhfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nldfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_LDDI, "lddi", "lddi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* lddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlddi$pack @($GRi,$d12),$GRdoublek */
   {
     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
   {
     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* ldqi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nldqfi$pack @($GRi,$d12),$FRintk */
   {
     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
-    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STB, "stb", "stb", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sth$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STH, "sth", "sth", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* st$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_ST, "st", "st", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stbf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBF, "stbf", "stbf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sthf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHF, "sthf", "sthf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STF, "stf", "stf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STC, "stc", "stc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* std$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STD, "std", "std", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdf$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDF, "stdf", "stdf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdc$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDC, "stdc", "stdc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stq$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQ, "stq", "stq", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stqf$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQF, "stqf", "stqf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stqc$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQC, "stqc", "stqc", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stbu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STBU, "stbu", "stbu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sthu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STHU, "sthu", "sthu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STU, "stu", "stu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stbfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sthfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STFU, "stfu", "stfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STCU, "stcu", "stcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdu$pack $GRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDU, "stdu", "stdu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdfu$pack $FRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
   {
     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stqu$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQU, "stqu", "stqu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stqfu$pack $FRintk,@($GRi,$GRj) */
   {
     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stqcu$pack $CPRk,@($GRi,$GRj) */
   {
     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUB, "cldub", "cldub", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUH, "clduh", "clduh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLD, "cld", "cld", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDF, "cldf", "cldf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDD, "cldd", "cldd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDF, "clddf", "clddf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQ, "cldq", "cldq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDU, "cldu", "cldu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
   {
     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDU, "clddu", "clddu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
   {
     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_I_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_I_3, 0 } } } }
   },
 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_LOAD, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTB, "cstb", "cstb", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTH, "csth", "csth", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CST, "cst", "cst", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHF, "csthf", "csthf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTF, "cstf", "cstf", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTD, "cstd", "cstd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTQ, "cstq", "cstq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHU, "csthu", "csthu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTU, "cstu", "cstu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stbi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STBI, "stbi", "stbi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sthi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STHI, "sthi", "sthi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sti$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STI, "sti", "sti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stbfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* sthfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STFI, "stfi", "stfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdi$pack $GRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDI, "stdi", "stdi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stdfi$pack $FRdoublek,@($GRi,$d12) */
   {
     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_I_3, 0 } }, { { FR450_MAJOR_I_3, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_I_4, 0 } } } }
   },
 /* stqi$pack $GRk,@($GRi,$d12) */
   {
     FRV_INSN_STQI, "stqi", "stqi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* stqfi$pack $FRintk,@($GRi,$d12) */
   {
     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_STORE, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* swap$pack @($GRi,$GRj),$GRk */
   {
     FRV_INSN_SWAP, "swap", "swap", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* swapi$pack @($GRi,$d12),$GRk */
   {
     FRV_INSN_SWAPI, "swapi", "swapi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
   {
     FRV_INSN_CSWAP, "cswap", "cswap", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* movgf$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGF, "movgf", "movgf", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* movfg$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFG, "movfg", "movfg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* movgfd$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* movfgd$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* movgfq$pack $GRj,$FRintk */
   {
     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* movfgq$pack $FRintk,$GRj */
   {
     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
   {
     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_4, 0 } }, { { FR450_MAJOR_I_4, 0 } }, { { FR500_MAJOR_I_4, 0 } }, { { FR550_MAJOR_I_5, 0 } } } }
   },
 /* movgs$pack $GRj,$spr */
   {
     FRV_INSN_MOVGS, "movgs", "movgs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* movsg$pack $spr,$GRj */
   {
     FRV_INSN_MOVSG, "movsg", "movsg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* bra$pack $hint_taken$label16 */
   {
     FRV_INSN_BRA, "bra", "bra", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bno$pack$hint_not_taken */
   {
     FRV_INSN_BNO, "bno", "bno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* beq$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bne$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* ble$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLE, "ble", "ble", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bgt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGT, "bgt", "bgt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* blt$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLT, "blt", "blt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bge$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BGE, "bge", "bge", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bls$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BLS, "bls", "bls", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bhi$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BHI, "bhi", "bhi", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BC, "bc", "bc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bnc$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNC, "bnc", "bnc", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bn$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BN, "bn", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bp$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BP, "bp", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BV, "bv", "bv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bnv$pack $ICCi_2,$hint,$label16 */
   {
     FRV_INSN_BNV, "bnv", "bnv", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbra$pack $hint_taken$label16 */
   {
     FRV_INSN_FBRA, "fbra", "fbra", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbno$pack$hint_not_taken */
   {
     FRV_INSN_FBNO, "fbno", "fbno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbne$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBNE, "fbne", "fbne", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbeq$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fblg$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLG, "fblg", "fblg", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbue$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUE, "fbue", "fbue", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbul$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUL, "fbul", "fbul", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGE, "fbge", "fbge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fblt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLT, "fblt", "fblt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbuge$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbug$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBUG, "fbug", "fbug", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fble$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBLE, "fble", "fble", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbgt$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbule$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBULE, "fbule", "fbule", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbu$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBU, "fbu", "fbu", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* fbo$pack $FCCi_2,$hint,$label16 */
   {
     FRV_INSN_FBO, "fbo", "fbo", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_1, 0 } }, { { FR450_MAJOR_B_1, 0 } }, { { FR500_MAJOR_B_1, 0 } }, { { FR550_MAJOR_B_1, 0 } } } }
   },
 /* bctrlr$pack $ccond,$hint */
   {
     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bralr$pack$hint_taken */
   {
     FRV_INSN_BRALR, "bralr", "bralr", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bnolr$pack$hint_not_taken */
   {
     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* beqlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bnelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* blelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLELR, "blelr", "blelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bgtlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bltlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bgelr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* blslr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BLSLR, "blslr", "blslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bhilr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BCLR, "bclr", "bclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bnclr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bnlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bplr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BPLR, "bplr", "bplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bnvlr$pack $ICCi_2,$hint */
   {
     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbralr$pack$hint_taken */
   {
     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
-    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbeqlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbnelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fblglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbuelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbullr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbgelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbltlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbugelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbuglr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fblelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbgtlr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbulelr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbulr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* fbolr$pack $FCCi_2,$hint */
   {
     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_B_3, 0 } } } }
   },
 /* bcralr$pack $ccond$hint_taken */
   {
     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcnolr$pack$hint_not_taken */
   {
     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bceqlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcnelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bclelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcltlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcgelr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bclslr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bchilr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcnclr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcnlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcplr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
   {
     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbralr$pack $ccond$hint_taken */
   {
     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbnolr$pack$hint_not_taken */
   {
     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcblglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbullr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcblelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbulr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* fcbolr$pack $FCCi_2,$ccond,$hint */
   {
     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
-    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+    { 0|A(FR_ACCESS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_2, 0 } }, { { FR450_MAJOR_B_2, 0 } }, { { FR500_MAJOR_B_2, 0 } }, { { FR550_MAJOR_B_2, 0 } } } }
   },
 /* jmpl$pack @($GRi,$GRj) */
   {
     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* calll$pack $callann($GRi,$GRj) */
   {
     FRV_INSN_CALLL, "calll", "calll", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* jmpil$pack @($GRi,$s12) */
   {
     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* callil$pack @($GRi,$s12) */
   {
     FRV_INSN_CALLIL, "callil", "callil", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* call$pack $label24 */
   {
     FRV_INSN_CALL, "call", "call", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR450_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B0, 0 } }, { { FR400_MAJOR_B_4, 0 } }, { { FR450_MAJOR_B_4, 0 } }, { { FR500_MAJOR_B_4, 0 } }, { { FR550_MAJOR_B_4, 0 } } } }
   },
 /* rett$pack $debug */
   {
     FRV_INSN_RETT, "rett", "rett", 32,
-    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* rei$pack $eir */
   {
     FRV_INSN_REI, "rei", "rei", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* tra$pack $GRi,$GRj */
   {
     FRV_INSN_TRA, "tra", "tra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tno$pack */
   {
     FRV_INSN_TNO, "tno", "tno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* teq$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TEQ, "teq", "teq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tne$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNE, "tne", "tne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tle$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLE, "tle", "tle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tgt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGT, "tgt", "tgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tlt$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLT, "tlt", "tlt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tge$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TGE, "tge", "tge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tls$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TLS, "tls", "tls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* thi$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_THI, "thi", "thi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TC, "tc", "tc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tnc$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNC, "tnc", "tnc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tn$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TN, "tn", "tn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tp$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TP, "tp", "tp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TV, "tv", "tv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tnv$pack $ICCi_2,$GRi,$GRj */
   {
     FRV_INSN_TNV, "tnv", "tnv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftra$pack $GRi,$GRj */
   {
     FRV_INSN_FTRA, "ftra", "ftra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftno$pack */
   {
     FRV_INSN_FTNO, "ftno", "ftno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftne$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTNE, "ftne", "ftne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* fteq$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTEQ, "fteq", "fteq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftlg$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftue$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUE, "ftue", "ftue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftul$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUL, "ftul", "ftul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGE, "ftge", "ftge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftlt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftuge$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftug$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTUG, "ftug", "ftug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftle$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTLE, "ftle", "ftle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftgt$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftule$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTULE, "ftule", "ftule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftu$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTU, "ftu", "ftu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* fto$pack $FCCi_2,$GRi,$GRj */
   {
     FRV_INSN_FTO, "fto", "fto", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tira$pack $GRi,$s12 */
   {
     FRV_INSN_TIRA, "tira", "tira", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tino$pack */
   {
     FRV_INSN_TINO, "tino", "tino", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tieq$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIEQ, "tieq", "tieq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tine$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINE, "tine", "tine", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tile$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILE, "tile", "tile", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tigt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGT, "tigt", "tigt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tilt$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILT, "tilt", "tilt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tige$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIGE, "tige", "tige", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tils$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TILS, "tils", "tils", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tihi$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIHI, "tihi", "tihi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tic$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIC, "tic", "tic", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tinc$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINC, "tinc", "tinc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tin$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIN, "tin", "tin", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tip$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIP, "tip", "tip", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tiv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TIV, "tiv", "tiv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* tinv$pack $ICCi_2,$GRi,$s12 */
   {
     FRV_INSN_TINV, "tinv", "tinv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftira$pack $GRi,$s12 */
   {
     FRV_INSN_FTIRA, "ftira", "ftira", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftino$pack */
   {
     FRV_INSN_FTINO, "ftino", "ftino", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftine$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTINE, "ftine", "ftine", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftieq$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftilg$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiue$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiul$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftige$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGE, "ftige", "ftige", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftilt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiug$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftile$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTILE, "ftile", "ftile", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftigt$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiule$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftiu$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* ftio$pack $FCCi_2,$GRi,$s12 */
   {
     FRV_INSN_FTIO, "ftio", "ftio", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* break$pack */
   {
     FRV_INSN_BREAK, "break", "break", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* mtrap$pack */
   {
     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_1, 0 } }, { { FR450_MAJOR_C_1, 0 } }, { { FR500_MAJOR_C_1, 0 } }, { { FR550_MAJOR_C_1, 0 } } } }
   },
 /* andcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDCR, "andcr", "andcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* orcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORCR, "orcr", "orcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* xorcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* nandcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* norcr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORCR, "norcr", "norcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* andncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* orncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_ORNCR, "orncr", "orncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* nandncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* norncr$pack $CRi,$CRj,$CRk */
   {
     FRV_INSN_NORNCR, "norncr", "norncr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* notcr$pack $CRj,$CRk */
   {
     FRV_INSN_NOTCR, "notcr", "notcr", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_6, 0 } }, { { FR450_MAJOR_B_6, 0 } }, { { FR500_MAJOR_B_6, 0 } }, { { FR550_MAJOR_B_6, 0 } } } }
   },
 /* ckra$pack $CRj_int */
   {
     FRV_INSN_CKRA, "ckra", "ckra", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckno$pack $CRj_int */
   {
     FRV_INSN_CKNO, "ckno", "ckno", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckeq$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckne$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNE, "ckne", "ckne", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckle$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLE, "ckle", "ckle", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckgt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cklt$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLT, "cklt", "cklt", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckge$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKGE, "ckge", "ckge", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckls$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKLS, "ckls", "ckls", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckhi$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKC, "ckc", "ckc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cknc$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNC, "cknc", "cknc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckn$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKN, "ckn", "ckn", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckp$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKP, "ckp", "ckp", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ckv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKV, "ckv", "ckv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cknv$pack $ICCi_3,$CRj_int */
   {
     FRV_INSN_CKNV, "cknv", "cknv", 32,
-    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckra$pack $CRj_float */
   {
     FRV_INSN_FCKRA, "fckra", "fckra", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckno$pack $CRj_float */
   {
     FRV_INSN_FCKNO, "fckno", "fckno", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckne$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKNE, "fckne", "fckne", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckeq$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fcklg$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckue$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUE, "fckue", "fckue", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckul$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUL, "fckul", "fckul", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGE, "fckge", "fckge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fcklt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckuge$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckug$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKUG, "fckug", "fckug", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckle$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKLE, "fckle", "fckle", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckgt$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fckule$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKULE, "fckule", "fckule", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fcku$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKU, "fcku", "fcku", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* fcko$pack $FCCi_3,$CRj_float */
   {
     FRV_INSN_FCKO, "fcko", "fcko", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckra$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKRA, "cckra", "cckra", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckno$pack $CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNO, "cckno", "cckno", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNE, "cckne", "cckne", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLE, "cckle", "cckle", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKGE, "cckge", "cckge", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKLS, "cckls", "cckls", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKC, "cckc", "cckc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKN, "cckn", "cckn", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKP, "cckp", "cckp", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKV, "cckv", "cckv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
   {
     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckra$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckno$pack $CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
   {
     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_5, 0 } }, { { FR450_MAJOR_B_5, 0 } }, { { FR500_MAJOR_B_5, 0 } }, { { FR550_MAJOR_B_5, 0 } } } }
   },
 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
   {
     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
-    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+    { 0|A(CONDITIONAL)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { UNIT_I0, 0 } }, { { FR400_MAJOR_I_5, 0 } }, { { FR450_MAJOR_I_5, 0 } }, { { FR500_MAJOR_I_5, 0 } }, { { FR550_MAJOR_I_6, 0 } } } }
   },
 /* ici$pack @($GRi,$GRj) */
   {
     FRV_INSN_ICI, "ici", "ici", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dci$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCI, "dci", "dci", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* icei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_ICEI, "icei", "icei", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dcei$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEI, "dcei", "dcei", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dcf$pack @($GRi,$GRj) */
   {
     FRV_INSN_DCF, "dcf", "dcf", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dcef$pack @($GRi,$GRj),$ae */
   {
     FRV_INSN_DCEF, "dcef", "dcef", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* witlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WITLB, "witlb", "witlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* wdtlb$pack $GRk,@($GRi,$GRj) */
   {
     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* itlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* dtlbi$pack @($GRi,$GRj) */
   {
     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
-    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0|A(PRIVILEGED), { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* icpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_ICPL, "icpl", "icpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dcpl$pack $GRi,$GRj,$lock */
   {
     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
-    { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR450_MAJOR_I_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_DCPL, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_I_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_I_8, 0 } } } }
   },
 /* icul$pack $GRi */
   {
     FRV_INSN_ICUL, "icul", "icul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* dcul$pack $GRi */
   {
     FRV_INSN_DCUL, "dcul", "dcul", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* bar$pack */
   {
     FRV_INSN_BAR, "bar", "bar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* membar$pack */
   {
     FRV_INSN_MEMBAR, "membar", "membar", 32,
-    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_C_2, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_C_2, 0 } } } }
   },
 /* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
   {
     FRV_INSN_LRAI, "lrai", "lrai", 32,
-    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
   {
     FRV_INSN_LRAD, "lrad", "lrad", 32,
-    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
   {
     FRV_INSN_TLBPR, "tlbpr", "tlbpr", 32,
-    { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_C_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP1, "cop1", "cop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
   {
     FRV_INSN_COP2, "cop2", "cop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_C, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_C_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* clrgr$pack $GRk */
   {
     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* clrfr$pack $FRk */
   {
     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* clrga$pack */
   {
     FRV_INSN_CLRGA, "clrga", "clrga", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* clrfa$pack */
   {
     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* commitgr$pack $GRk */
   {
     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* commitfr$pack $FRk */
   {
     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* commitga$pack */
   {
     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
-    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0, { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* commitfa$pack */
   {
     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
-    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+    { 0|A(FR_ACCESS), { { { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), 0 } }, { { UNIT_I01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_I_6, 0 } }, { { FR550_MAJOR_I_7, 0 } } } }
   },
 /* fitos$pack $FRintj,$FRk */
   {
     FRV_INSN_FITOS, "fitos", "fitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fitod$pack $FRintj,$FRdoublek */
   {
     FRV_INSN_FITOD, "fitod", "fitod", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdtoi$pack $FRdoublej,$FRintk */
   {
     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fditos$pack $FRintj,$FRk */
   {
     FRV_INSN_FDITOS, "fditos", "fditos", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfditos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* nfitos$pack $FRintj,$FRk */
   {
     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* nfstoi$pack $FRj,$FRintk */
   {
     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fmovd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdmovs$pack $FRj,$FRk */
   {
     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
-    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fnegd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdnegs$pack $FRj,$FRk */
   {
     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fabss$pack $FRj,$FRk */
   {
     FRV_INSN_FABSS, "fabss", "fabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fabsd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdabss$pack $FRj,$FRk */
   {
     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_1, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* fdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fsqrtd$pack $FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* nfsqrts$pack $FRj,$FRk */
   {
     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* fadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FADDS, "fadds", "fadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* fdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FADDD, "faddd", "faddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* nfadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* nfsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* nfmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_3, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* nfdivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_4, 0 } }, { { FR550_MAJOR_F_3, 0 } } } }
   },
 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
   {
     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
   {
     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_2, 0 } }, { { FR550_MAJOR_F_2, 0 } } } }
   },
 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
   {
     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfmadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfmsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
-    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0|A(NON_EXCEPTING), { { { (1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAS, "fmas", "fmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSS, "fmss", "fmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
   {
     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fmad$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMAD, "fmad", "fmad", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fmsd$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfmas$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfmss$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_5, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* fdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfdmulcs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfdadds$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfdsubs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfdmuls$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfddivs$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* nfdsads$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_F_4, 0 } } } }
   },
 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
   {
     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_6, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mhsetlos$pack $u12,$FRklo */
   {
     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mhsethis$pack $u12,$FRkhi */
   {
     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mhdsets$pack $u12,$FRintk */
   {
     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mhsetloh$pack $s5,$FRklo */
   {
     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mhsethih$pack $s5,$FRkhi */
   {
     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mhdseth$pack $s5,$FRintk */
   {
     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_5, 0 } } } }
   },
 /* mand$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAND, "mand", "mand", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MOR, "mor", "mor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mxor$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MXOR, "mxor", "mxor", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMAND, "cmand", "cmand", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMOR, "cmor", "cmor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mnot$pack $FRintj,$FRintk */
   {
     FRV_INSN_MNOT, "mnot", "mnot", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mrotli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mrotri$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mwcut$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mwcuti$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUT, "mcut", "mcut", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcuti$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
   {
     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
   {
     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
   {
     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDCUTSSI, FR400_MAJOR_M_2, FR450_MAJOR_M_6, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDCUTSSI, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_6, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* maveh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MAVEH, "maveh", "maveh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* msllhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* msrlhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* msrahi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mdrotli$pack $FRintieven,$s6,$FRintkeven */
   {
     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcplhi$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcpli$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMLOW, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* msaths$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHS, "msaths", "msaths", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* msathu$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSATHU, "msathu", "msathu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
   {
     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mabshs$pack $FRintj,$FRintk */
   {
     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* maddhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* maddhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* msubhss$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* msubhus$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_2, 0 } } } }
   },
 /* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQLCLRHS, "mqlclrhs", "mqlclrhs", 32,
-    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MQLMTHS, "mqlmths", "mqlmths", 32,
-    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
   {
     FRV_INSN_MQSLLHI, "mqsllhi", "mqsllhi", 32,
-    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
   {
     FRV_INSN_MQSRAHI, "mqsrahi", "mqsrahi", 32,
-    { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FR450), 0 } }, { { UNIT_FM0, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* maddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* msubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* masaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
   {
     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_MDUALACC, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
-    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
-    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
   {
     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
   {
     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
   {
     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
-    { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_NONE, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
   {
     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
   {
     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
   {
     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_4, 0 } }, { { FR550_MAJOR_M_4, 0 } } } }
   },
 /* mexpdhw$pack $FRinti,$u6,$FRintk */
   {
     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mexpdhd$pack $FRinti,$u6,$FRintkeven */
   {
     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mpackh$pack $FRinti,$FRintj,$FRintk */
   {
     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
   {
     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_5, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* munpackh$pack $FRinti,$FRintkeven */
   {
     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mdunpackh$pack $FRintieven,$FRintk */
   {
     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mbtoh$pack $FRintj,$FRintkeven */
   {
     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
   {
     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mhtob$pack $FRintjeven,$FRintk */
   {
     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_2, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mbtohe$pack $FRintj,$FRintk */
   {
     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
   {
     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
-    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL), { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_7, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mnop$pack */
   {
     FRV_INSN_MNOP, "mnop", "mnop", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_1, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_M_1, 0 } } } }
   },
 /* mclracc$pack $ACC40Sk,$A0 */
   {
     FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mclracc$pack $ACC40Sk,$A1 */
   {
     FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_MCLRACC_1, 0 } }, { { FR400_MAJOR_M_2, 0 } }, { { FR450_MAJOR_M_4, 0 } }, { { FR500_MAJOR_M_6, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mrdacc$pack $ACC40Si,$FRintk */
   {
     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mrdaccg$pack $ACCGi,$FRintk */
   {
     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_5, 0 } }, { { FR500_MAJOR_M_2, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mwtacc$pack $FRinti,$ACC40Sk */
   {
     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mwtaccg$pack $FRinti,$ACCGk */
   {
     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
-    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_M_1, 0 } }, { { FR450_MAJOR_M_3, 0 } }, { { FR500_MAJOR_M_3, 0 } }, { { FR550_MAJOR_M_3, 0 } } } }
   },
 /* mcop1$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mcop2$pack $FRi,$FRj,$FRk */
   {
     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
-    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+    { 0, { { { (1<<MACH_FRV), 0 } }, { { UNIT_FM01, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_M_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* fnop$pack */
   {
     FRV_INSN_FNOP, "fnop", "fnop", 32,
-    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
+    { 0, { { { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), 0 } }, { { UNIT_FMALL, 0 } }, { { FR400_MAJOR_NONE, 0 } }, { { FR450_MAJOR_NONE, 0 } }, { { FR500_MAJOR_F_8, 0 } }, { { FR550_MAJOR_F_1, 0 } } } }
   },
 };
 
@@ -6257,7 +6257,7 @@ static void
 frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -6269,7 +6269,7 @@ frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & frv_cgen_isa_table[i];
 
@@ -6354,7 +6354,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -6373,7 +6373,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -6404,9 +6404,6 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -6414,7 +6411,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h
index 8b506dc2a16..d94447f9fdb 100644
--- a/opcodes/frv-desc.h
+++ b/opcodes/frv-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef FRV_CPU_H
 #define FRV_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH frv
 
 /* Given symbol S, return frv_cgen_<S>.  */
@@ -617,6 +619,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for frv ifield types.  */
 typedef enum ifield_type {
   FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP
@@ -661,6 +672,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for frv hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -693,6 +711,18 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
+
 /* Enum declaration for frv operand types.  */
 typedef enum cgen_operand_type {
   FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ
@@ -742,6 +772,30 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRIVILEGED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NON_EXCEPTING)) != 0)
+#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_CONDITIONAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FR_ACCESS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PRESERVE_OVF)) != 0)
+#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AUDIO)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index a82fe2b6846..f74eb6251cc 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -704,7 +704,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -716,11 +716,12 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -743,25 +744,34 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -777,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -790,7 +800,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c
index 293ae61f6e9..d3e2b351e1a 100644
--- a/opcodes/frv-opc.c
+++ b/opcodes/frv-opc.c
@@ -38,7 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    development tree.  */
 
 bfd_boolean
-frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -62,7 +62,7 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 /* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
 
 bfd_boolean
-frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -81,7 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
 /* Returns TRUE if {MAJOR,MACH} supports media insns.  */
 
 bfd_boolean
-frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
 {
   switch (mach)
     {
@@ -225,7 +225,7 @@ static VLIW_COMBO fr550_allowed_vliw[] =
 /* Some insns are assigned specialized implementation units which map to
    different actual implementation units on different machines.  These
    tables perform that mapping.  */
-static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -260,7 +260,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
 /* Some insns are assigned specialized implementation units which map to
    different actual implementation units on different machines.  These
    tables perform that mapping.  */
-static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -292,7 +292,7 @@ static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
 /* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
 };
 
-static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -324,7 +324,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
 /* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
 };
 
-static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
+static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
 {
 /* unit in insn    actual unit */
 /* NIL      */     UNIT_NIL,
@@ -390,7 +390,7 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
    *_allowed_vliw tables above.  */
 static bfd_boolean
 match_unit (FRV_VLIW *vliw,
-	    CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
+	    CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
 {
   /* Map any specialized implementation units to actual ones.  */
   unit1 = vliw->unit_mapping[unit1];
@@ -442,7 +442,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
    If one is found then return it. Otherwise return NULL.  */
 
 static VLIW_COMBO *
-add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
+add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
 {
   int           next    = vliw->next_slot;
   VLIW_COMBO    *current = vliw->current_vliw;
@@ -473,7 +473,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
    Returns TRUE if found, FALSE otherwise.  */
 
 static bfd_boolean
-find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   int i;
 
@@ -488,7 +488,7 @@ find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
    types.  */
 
 static bfd_boolean
-fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   /* In the cpu file, all media insns are represented as being allowed in
      both media units. This makes it easier since this is the case for fr500.
@@ -508,9 +508,9 @@ fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 }
 
 static bfd_boolean
-fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
-  CGEN_ATTR_VALUE_TYPE other_major;
+  CGEN_ATTR_VALUE_ENUM_TYPE other_major;
 
   /* Our caller guarantees there's at least one other instruction.  */
   other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
@@ -543,7 +543,7 @@ fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 }
 
 static bfd_boolean
-find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
+find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
 {
   int i;
 
@@ -556,8 +556,8 @@ find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
 
 static bfd_boolean
 find_major_in_slot (FRV_VLIW *vliw,
-		    CGEN_ATTR_VALUE_TYPE major,
-		    CGEN_ATTR_VALUE_TYPE slot)
+		    CGEN_ATTR_VALUE_ENUM_TYPE major,
+		    CGEN_ATTR_VALUE_ENUM_TYPE slot)
 {
   int i;
 
@@ -612,11 +612,11 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw)
 
 static bfd_boolean
 fr550_check_insn_major_constraints (FRV_VLIW *vliw,
-				    CGEN_ATTR_VALUE_TYPE major,
+				    CGEN_ATTR_VALUE_ENUM_TYPE major,
 				    const CGEN_INSN *insn)
 {
-  CGEN_ATTR_VALUE_TYPE unit;
-  CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
+  CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
   switch (slot)
     {
     case UNIT_I2:
@@ -662,7 +662,7 @@ fr550_check_insn_major_constraints (FRV_VLIW *vliw,
 }
 
 static bfd_boolean
-fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
 {
   /* TODO: A table might be faster for some of the more complex instances
      here.  */
@@ -770,7 +770,7 @@ fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
 
 static bfd_boolean
 check_insn_major_constraints (FRV_VLIW *vliw,
-			      CGEN_ATTR_VALUE_TYPE major,
+			      CGEN_ATTR_VALUE_ENUM_TYPE major,
 			      const CGEN_INSN *insn)
 {
   switch (vliw->mach)
@@ -796,8 +796,8 @@ int
 frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 {
   int index;
-  CGEN_ATTR_VALUE_TYPE major;
-  CGEN_ATTR_VALUE_TYPE unit;
+  CGEN_ATTR_VALUE_ENUM_TYPE major;
+  CGEN_ATTR_VALUE_ENUM_TYPE unit;
   VLIW_COMBO *new_vliw;
 
   if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
@@ -6046,37 +6046,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
 /* nop$pack */
   {
     -1, "nop", "nop", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ret$pack */
   {
     -1, "ret", "ret", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_B01, 0 } }, { { FR400_MAJOR_B_3, 0 } }, { { FR450_MAJOR_B_3, 0 } }, { { FR500_MAJOR_B_3, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cmp$pack $GRi,$GRj,$ICCi_1 */
   {
     -1, "cmp", "cmp", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cmpi$pack $GRi,$s10,$ICCi_1 */
   {
     -1, "cmpi", "cmpi", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* ccmp$pack $GRi,$GRj,$CCi,$cond */
   {
     -1, "ccmp", "ccmp", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* mov$pack $GRi,$GRk */
   {
     -1, "mov", "mov", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 /* cmov$pack $GRi,$GRk,$CCi,$cond */
   {
     -1, "cmov", "cmov", 32,
-    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+    { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { UNIT_IALL, 0 } }, { { FR400_MAJOR_I_1, 0 } }, { { FR450_MAJOR_I_1, 0 } }, { { FR500_MAJOR_I_1, 0 } }, { { FR550_MAJOR_NONE, 0 } } } }
   },
 };
 
diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h
index 50e1041851f..fb04b95f2f4 100644
--- a/opcodes/frv-opc.h
+++ b/opcodes/frv-opc.h
@@ -39,7 +39,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
 #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
 
-typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
+typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
 typedef struct
 {
@@ -47,15 +47,15 @@ typedef struct
   int                    constraint_violation;
   unsigned long          mach;
   unsigned long          elf_flags;
-  CGEN_ATTR_VALUE_TYPE * unit_mapping;
+  CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping;
   VLIW_COMBO *           current_vliw;
-  CGEN_ATTR_VALUE_TYPE   major[FRV_VLIW_SIZE];
+  CGEN_ATTR_VALUE_ENUM_TYPE   major[FRV_VLIW_SIZE];
   const CGEN_INSN *      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
-int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
-int frv_is_float_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
-int frv_is_media_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
+int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
 int frv_is_branch_insn  (const CGEN_INSN *);
 int frv_is_float_insn   (const CGEN_INSN *);
 int frv_is_media_insn   (const CGEN_INSN *);
diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c
index 2264164ba86..b12a728a88e 100644
--- a/opcodes/ia64-asmtab.c
+++ b/opcodes/ia64-asmtab.c
@@ -4939,16 +4939,16 @@ main_table[] = {
   { 27, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 22, 26, 7, 0 }, 0x40, 1058, },
   { 27, 1, 1, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 26, 7, 0, 0 }, 0x40, 1059, },
   { 27, 1, 2, 0x000001ce00000000ull, 0x000001ee00001000ull, { 23, 22, 55, 26, 0 }, 0x40, 1377, },
-  { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 33, 25, 1, 2 }, 0x0, 257, },
-  { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x40, 258, },
-  { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 33, 25, 2, 0 }, 0x0, 259, },
-  { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x40, 260, },
-  { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 33, 25, 2, 0 }, 0x0, 261, },
-  { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x40, 262, },
-  { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 33, 25, 2, 0 }, 0x0, 263, },
-  { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x40, 264, },
-  { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 33, 25, 2, 0 }, 0x0, 265, },
-  { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x40, 266, },
+  { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 28, 25, 1, 2 }, 0x0, 257, },
+  { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 258, },
+  { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 259, },
+  { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 260, },
+  { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 261, },
+  { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 262, },
+  { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 263, },
+  { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 264, },
+  { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 265, },
+  { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 266, },
   { 34, 4, 0, 0x0000000010000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 19, },
   { 36, 2, 1, 0x00000000c0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 1149, },
   { 37, 2, 1, 0x00000000c8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 1150, },
@@ -4991,8 +4991,8 @@ main_table[] = {
   { 62, 5, 1, 0x00000000c0000000ull, 0x000001eff8000000ull, { 18, 19, 0, 0, 0 }, 0x40, 1025, },
   { 62, 5, 1, 0x00000000e0000000ull, 0x000001e3f8000000ull, { 18, 19, 0, 0, 0 }, 0x0, 2998, },
   { 62, 5, 1, 0x0000010008000000ull, 0x000001fff80fe000ull, { 18, 20, 0, 0, 0 }, 0x40, 2999, },
-  { 63, 3, 1, 0x0000008488000000ull, 0x000001fff8000000ull, { 24, 33, 71, 0, 0 }, 0x0, 267, },
-  { 64, 3, 1, 0x00000084c8000000ull, 0x000001fff8000000ull, { 24, 33, 71, 0, 0 }, 0x0, 268, },
+  { 63, 3, 1, 0x0000008488000000ull, 0x000001fff8000000ull, { 24, 28, 71, 0, 0 }, 0x0, 267, },
+  { 64, 3, 1, 0x00000084c8000000ull, 0x000001fff8000000ull, { 24, 28, 71, 0, 0 }, 0x0, 268, },
   { 67, 3, 0, 0x0000000060000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 33, },
   { 68, 5, 1, 0x0000010000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 2319, },
   { 68, 5, 1, 0x0000010000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 34, },
@@ -5065,47 +5065,47 @@ main_table[] = {
   { 123, 3, 0, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 0, 0, 0, 0 }, 0x0, 902, },
   { 123, 3, 0, 0x0000000098000000ull, 0x000001eff8000000ull, { 18, 0, 0, 0, 0 }, 0x0, 903, },
   { 124, 3, 0, 0x0000002170000000ull, 0x000001eff8000000ull, { 25, 0, 0, 0, 0 }, 0xc, 828, },
-  { 125, 3, 1, 0x0000002070000000ull, 0x000001eff8000000ull, { 30, 25, 0, 0, 0 }, 0x8, 829, },
-  { 125, 3, 1, 0x0000002078000000ull, 0x000001eff8000000ull, { 31, 25, 0, 0, 0 }, 0x8, 1125, },
-  { 127, 3, 1, 0x0000008000000000ull, 0x000001fff8000000ull, { 24, 33, 0, 0, 0 }, 0x0, 70, },
-  { 127, 3, 1, 0x0000009000000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x400, 71, },
-  { 127, 3, 1, 0x000000a000000000ull, 0x000001eff0000000ull, { 24, 33, 62, 0, 0 }, 0x400, 72, },
-  { 128, 3, 2, 0x0000008a08000000ull, 0x000001fff8000000ull, { 24, 1, 33, 0, 0 }, 0x0, 73, },
-  { 128, 3, 1, 0x0000008a08000000ull, 0x000001fff8000000ull, { 24, 33, 0, 0, 0 }, 0x40, 74, },
-  { 129, 3, 1, 0x0000008040000000ull, 0x000001fff8000000ull, { 24, 33, 0, 0, 0 }, 0x0, 75, },
-  { 129, 3, 1, 0x0000009040000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x400, 76, },
-  { 129, 3, 1, 0x000000a040000000ull, 0x000001eff0000000ull, { 24, 33, 62, 0, 0 }, 0x400, 77, },
-  { 130, 3, 1, 0x0000008080000000ull, 0x000001fff8000000ull, { 24, 33, 0, 0, 0 }, 0x0, 78, },
-  { 130, 3, 1, 0x0000009080000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x400, 79, },
-  { 130, 3, 1, 0x000000a080000000ull, 0x000001eff0000000ull, { 24, 33, 62, 0, 0 }, 0x400, 80, },
-  { 131, 3, 1, 0x00000080c0000000ull, 0x000001fff8000000ull, { 24, 33, 0, 0, 0 }, 0x0, 81, },
-  { 131, 3, 1, 0x00000080c0000000ull, 0x000001fff8000000ull, { 24, 33, 83, 0, 0 }, 0x0, 1321, },
-  { 131, 3, 1, 0x00000090c0000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x400, 82, },
-  { 131, 3, 1, 0x000000a0c0000000ull, 0x000001eff0000000ull, { 24, 33, 62, 0, 0 }, 0x400, 83, },
-  { 132, 3, 1, 0x000000c6c0000000ull, 0x000001fff8000000ull, { 18, 33, 0, 0, 0 }, 0x0, 1021, },
-  { 132, 3, 1, 0x000000d6c0000000ull, 0x000001fff8000000ull, { 18, 33, 25, 0, 0 }, 0x400, 1022, },
-  { 132, 3, 1, 0x000000e6c0000000ull, 0x000001eff0000000ull, { 18, 33, 62, 0, 0 }, 0x400, 1023, },
-  { 133, 3, 1, 0x000000c040000000ull, 0x000001fff8000000ull, { 18, 33, 0, 0, 0 }, 0x0, 84, },
-  { 133, 3, 1, 0x000000d040000000ull, 0x000001fff8000000ull, { 18, 33, 25, 0, 0 }, 0x400, 85, },
-  { 133, 3, 1, 0x000000e040000000ull, 0x000001eff0000000ull, { 18, 33, 62, 0, 0 }, 0x400, 86, },
-  { 134, 3, 1, 0x000000c0c0000000ull, 0x000001fff8000000ull, { 18, 33, 0, 0, 0 }, 0x0, 87, },
-  { 134, 3, 1, 0x000000d0c0000000ull, 0x000001fff8000000ull, { 18, 33, 25, 0, 0 }, 0x400, 88, },
-  { 134, 3, 1, 0x000000e0c0000000ull, 0x000001eff0000000ull, { 18, 33, 62, 0, 0 }, 0x400, 89, },
-  { 135, 3, 1, 0x000000c000000000ull, 0x000001fff8000000ull, { 18, 33, 0, 0, 0 }, 0x0, 90, },
-  { 135, 3, 1, 0x000000d000000000ull, 0x000001fff8000000ull, { 18, 33, 25, 0, 0 }, 0x400, 91, },
-  { 135, 3, 1, 0x000000e000000000ull, 0x000001eff0000000ull, { 18, 33, 62, 0, 0 }, 0x400, 92, },
-  { 136, 3, 2, 0x000000c048000000ull, 0x000001fff8000000ull, { 18, 19, 33, 0, 0 }, 0x0, 93, },
-  { 136, 3, 2, 0x000000d048000000ull, 0x000001fff8000000ull, { 18, 19, 33, 6, 0 }, 0x400, 94, },
-  { 137, 3, 2, 0x000000c0c8000000ull, 0x000001fff8000000ull, { 18, 19, 33, 0, 0 }, 0x0, 95, },
-  { 137, 3, 2, 0x000000d0c8000000ull, 0x000001fff8000000ull, { 18, 19, 33, 6, 0 }, 0x400, 96, },
-  { 138, 3, 2, 0x000000c088000000ull, 0x000001fff8000000ull, { 18, 19, 33, 0, 0 }, 0x0, 97, },
-  { 138, 3, 2, 0x000000d088000000ull, 0x000001fff8000000ull, { 18, 19, 33, 5, 0 }, 0x400, 98, },
-  { 139, 3, 1, 0x000000c080000000ull, 0x000001fff8000000ull, { 18, 33, 0, 0, 0 }, 0x0, 99, },
-  { 139, 3, 1, 0x000000d080000000ull, 0x000001fff8000000ull, { 18, 33, 25, 0, 0 }, 0x400, 100, },
-  { 139, 3, 1, 0x000000e080000000ull, 0x000001eff0000000ull, { 18, 33, 62, 0, 0 }, 0x400, 101, },
-  { 142, 3, 0, 0x000000cb00000000ull, 0x000001fff8000000ull, { 33, 0, 0, 0, 0 }, 0x0, 102, },
-  { 142, 3, 0, 0x000000db00000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x400, 103, },
-  { 142, 3, 0, 0x000000eb00000000ull, 0x000001eff0000000ull, { 33, 62, 0, 0, 0 }, 0x400, 104, },
+  { 125, 3, 1, 0x0000002070000000ull, 0x000001eff8000000ull, { 31, 25, 0, 0, 0 }, 0x8, 829, },
+  { 125, 3, 1, 0x0000002078000000ull, 0x000001eff8000000ull, { 32, 25, 0, 0, 0 }, 0x8, 1125, },
+  { 127, 3, 1, 0x0000008000000000ull, 0x000001fff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 70, },
+  { 127, 3, 1, 0x0000009000000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x400, 71, },
+  { 127, 3, 1, 0x000000a000000000ull, 0x000001eff0000000ull, { 24, 28, 62, 0, 0 }, 0x400, 72, },
+  { 128, 3, 2, 0x0000008a08000000ull, 0x000001fff8000000ull, { 24, 1, 28, 0, 0 }, 0x0, 73, },
+  { 128, 3, 1, 0x0000008a08000000ull, 0x000001fff8000000ull, { 24, 28, 0, 0, 0 }, 0x40, 74, },
+  { 129, 3, 1, 0x0000008040000000ull, 0x000001fff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 75, },
+  { 129, 3, 1, 0x0000009040000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x400, 76, },
+  { 129, 3, 1, 0x000000a040000000ull, 0x000001eff0000000ull, { 24, 28, 62, 0, 0 }, 0x400, 77, },
+  { 130, 3, 1, 0x0000008080000000ull, 0x000001fff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 78, },
+  { 130, 3, 1, 0x0000009080000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x400, 79, },
+  { 130, 3, 1, 0x000000a080000000ull, 0x000001eff0000000ull, { 24, 28, 62, 0, 0 }, 0x400, 80, },
+  { 131, 3, 1, 0x00000080c0000000ull, 0x000001fff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 81, },
+  { 131, 3, 1, 0x00000080c0000000ull, 0x000001fff8000000ull, { 24, 28, 83, 0, 0 }, 0x0, 1321, },
+  { 131, 3, 1, 0x00000090c0000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x400, 82, },
+  { 131, 3, 1, 0x000000a0c0000000ull, 0x000001eff0000000ull, { 24, 28, 62, 0, 0 }, 0x400, 83, },
+  { 132, 3, 1, 0x000000c6c0000000ull, 0x000001fff8000000ull, { 18, 28, 0, 0, 0 }, 0x0, 1021, },
+  { 132, 3, 1, 0x000000d6c0000000ull, 0x000001fff8000000ull, { 18, 28, 25, 0, 0 }, 0x400, 1022, },
+  { 132, 3, 1, 0x000000e6c0000000ull, 0x000001eff0000000ull, { 18, 28, 62, 0, 0 }, 0x400, 1023, },
+  { 133, 3, 1, 0x000000c040000000ull, 0x000001fff8000000ull, { 18, 28, 0, 0, 0 }, 0x0, 84, },
+  { 133, 3, 1, 0x000000d040000000ull, 0x000001fff8000000ull, { 18, 28, 25, 0, 0 }, 0x400, 85, },
+  { 133, 3, 1, 0x000000e040000000ull, 0x000001eff0000000ull, { 18, 28, 62, 0, 0 }, 0x400, 86, },
+  { 134, 3, 1, 0x000000c0c0000000ull, 0x000001fff8000000ull, { 18, 28, 0, 0, 0 }, 0x0, 87, },
+  { 134, 3, 1, 0x000000d0c0000000ull, 0x000001fff8000000ull, { 18, 28, 25, 0, 0 }, 0x400, 88, },
+  { 134, 3, 1, 0x000000e0c0000000ull, 0x000001eff0000000ull, { 18, 28, 62, 0, 0 }, 0x400, 89, },
+  { 135, 3, 1, 0x000000c000000000ull, 0x000001fff8000000ull, { 18, 28, 0, 0, 0 }, 0x0, 90, },
+  { 135, 3, 1, 0x000000d000000000ull, 0x000001fff8000000ull, { 18, 28, 25, 0, 0 }, 0x400, 91, },
+  { 135, 3, 1, 0x000000e000000000ull, 0x000001eff0000000ull, { 18, 28, 62, 0, 0 }, 0x400, 92, },
+  { 136, 3, 2, 0x000000c048000000ull, 0x000001fff8000000ull, { 18, 19, 28, 0, 0 }, 0x0, 93, },
+  { 136, 3, 2, 0x000000d048000000ull, 0x000001fff8000000ull, { 18, 19, 28, 6, 0 }, 0x400, 94, },
+  { 137, 3, 2, 0x000000c0c8000000ull, 0x000001fff8000000ull, { 18, 19, 28, 0, 0 }, 0x0, 95, },
+  { 137, 3, 2, 0x000000d0c8000000ull, 0x000001fff8000000ull, { 18, 19, 28, 6, 0 }, 0x400, 96, },
+  { 138, 3, 2, 0x000000c088000000ull, 0x000001fff8000000ull, { 18, 19, 28, 0, 0 }, 0x0, 97, },
+  { 138, 3, 2, 0x000000d088000000ull, 0x000001fff8000000ull, { 18, 19, 28, 5, 0 }, 0x400, 98, },
+  { 139, 3, 1, 0x000000c080000000ull, 0x000001fff8000000ull, { 18, 28, 0, 0, 0 }, 0x0, 99, },
+  { 139, 3, 1, 0x000000d080000000ull, 0x000001fff8000000ull, { 18, 28, 25, 0, 0 }, 0x400, 100, },
+  { 139, 3, 1, 0x000000e080000000ull, 0x000001eff0000000ull, { 18, 28, 62, 0, 0 }, 0x400, 101, },
+  { 142, 3, 0, 0x000000cb00000000ull, 0x000001fff8000000ull, { 28, 0, 0, 0, 0 }, 0x0, 102, },
+  { 142, 3, 0, 0x000000db00000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x400, 103, },
+  { 142, 3, 0, 0x000000eb00000000ull, 0x000001eff0000000ull, { 28, 62, 0, 0, 0 }, 0x400, 104, },
   { 143, 3, 0, 0x0000000050000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 105, },
   { 151, 3, 0, 0x0000000110000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 106, },
   { 152, 2, 1, 0x000000e880000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2169, },
@@ -5135,20 +5135,20 @@ main_table[] = {
   { 155, 3, 1, 0x0000002128000000ull, 0x000001eff8000000ull, { 24, 11, 0, 0, 0 }, 0x8, 122, },
   { 155, 3, 1, 0x0000002108000000ull, 0x000001eff8000000ull, { 24, 13, 0, 0, 0 }, 0x0, 123, },
   { 155, 3, 1, 0x0000002000000000ull, 0x000001eff8000000ull, { 38, 25, 0, 0, 0 }, 0x8, 124, },
-  { 155, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 29, 25, 0, 0, 0 }, 0x8, 125, },
-  { 155, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 32, 25, 0, 0, 0 }, 0x8, 126, },
+  { 155, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 30, 25, 0, 0, 0 }, 0x8, 125, },
+  { 155, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 33, 25, 0, 0, 0 }, 0x8, 126, },
   { 155, 3, 1, 0x0000002018000000ull, 0x000001eff8000000ull, { 35, 25, 0, 0, 0 }, 0x8, 127, },
   { 155, 3, 1, 0x0000002020000000ull, 0x000001eff8000000ull, { 36, 25, 0, 0, 0 }, 0x8, 128, },
   { 155, 3, 1, 0x0000002028000000ull, 0x000001eff8000000ull, { 37, 25, 0, 0, 0 }, 0x8, 129, },
   { 155, 3, 1, 0x0000002030000000ull, 0x000001eff8000000ull, { 34, 25, 0, 0, 0 }, 0x8, 130, },
   { 155, 3, 1, 0x0000002080000000ull, 0x000001eff8000000ull, { 24, 38, 0, 0, 0 }, 0x8, 131, },
-  { 155, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 24, 29, 0, 0, 0 }, 0x8, 132, },
-  { 155, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 24, 32, 0, 0, 0 }, 0x8, 133, },
+  { 155, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 24, 30, 0, 0, 0 }, 0x8, 132, },
+  { 155, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 24, 33, 0, 0, 0 }, 0x8, 133, },
   { 155, 3, 1, 0x0000002098000000ull, 0x000001eff8000000ull, { 24, 35, 0, 0, 0 }, 0x8, 134, },
   { 155, 3, 1, 0x00000020a0000000ull, 0x000001eff8000000ull, { 24, 36, 0, 0, 0 }, 0x8, 135, },
   { 155, 3, 1, 0x00000020a8000000ull, 0x000001eff8000000ull, { 24, 37, 0, 0, 0 }, 0x0, 136, },
   { 155, 3, 1, 0x00000020b0000000ull, 0x000001eff8000000ull, { 24, 34, 0, 0, 0 }, 0x8, 137, },
-  { 155, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 138, },
+  { 155, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 24, 29, 0, 0, 0 }, 0x0, 138, },
   { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 14, 0, 0, 0 }, 0x0, 139, },
   { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 55, 0, 0, 0 }, 0x0, 140, },
   { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 25, 0, 0, 0 }, 0x0, 141, },
@@ -5216,26 +5216,26 @@ main_table[] = {
   { 231, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 24, 25, 26, 44, 0 }, 0x0, 182, },
   { 236, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 832, },
   { 237, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x8, 183, },
-  { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 184, },
-  { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 185, },
-  { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 33, 25, 1, 0, 0 }, 0x0, 186, },
-  { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x40, 187, },
-  { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 188, },
-  { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 189, },
-  { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 190, },
-  { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 191, },
-  { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 192, },
-  { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 193, },
-  { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 2751, },
-  { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 2752, },
-  { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 194, },
-  { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 195, },
-  { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 196, },
-  { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 197, },
-  { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 198, },
-  { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 199, },
-  { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 200, },
-  { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 201, },
+  { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 184, },
+  { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 28, 25, 61, 0, 0 }, 0x400, 185, },
+  { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 1, 0, 0 }, 0x0, 186, },
+  { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x40, 187, },
+  { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 188, },
+  { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 28, 25, 61, 0, 0 }, 0x400, 189, },
+  { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 190, },
+  { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 28, 25, 61, 0, 0 }, 0x400, 191, },
+  { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 192, },
+  { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 28, 25, 61, 0, 0 }, 0x400, 193, },
+  { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 2751, },
+  { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 28, 19, 61, 0, 0 }, 0x400, 2752, },
+  { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 194, },
+  { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 28, 19, 61, 0, 0 }, 0x400, 195, },
+  { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 196, },
+  { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 28, 19, 61, 0, 0 }, 0x400, 197, },
+  { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 198, },
+  { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 28, 19, 61, 0, 0 }, 0x400, 199, },
+  { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 200, },
+  { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 28, 19, 61, 0, 0 }, 0x400, 201, },
   { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 202, },
   { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 203, },
   { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 204, },
@@ -5259,10 +5259,10 @@ main_table[] = {
   { 265, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1113, },
   { 266, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1114, },
   { 267, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1115, },
-  { 275, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 213, },
-  { 276, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 214, },
-  { 277, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 215, },
-  { 278, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 216, },
+  { 275, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 213, },
+  { 276, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 214, },
+  { 277, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 215, },
+  { 278, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 216, },
   { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 1161, },
   { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1243, },
   { 281, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 1162, },
diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c
index ca48ba2a579..289fdd6bfec 100644
--- a/opcodes/ip2k-desc.c
+++ b/opcodes/ip2k-desc.c
@@ -130,127 +130,127 @@ static const CGEN_MACH ip2k_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] =
 {
-  { "ADDRSEL", 2, {0, {0}}, 0, 0 },
-  { "ADDRX", 3, {0, {0}}, 0, 0 },
-  { "IPH", 4, {0, {0}}, 0, 0 },
-  { "IPL", 5, {0, {0}}, 0, 0 },
-  { "SPH", 6, {0, {0}}, 0, 0 },
-  { "SPL", 7, {0, {0}}, 0, 0 },
-  { "PCH", 8, {0, {0}}, 0, 0 },
-  { "PCL", 9, {0, {0}}, 0, 0 },
-  { "WREG", 10, {0, {0}}, 0, 0 },
-  { "STATUS", 11, {0, {0}}, 0, 0 },
-  { "DPH", 12, {0, {0}}, 0, 0 },
-  { "DPL", 13, {0, {0}}, 0, 0 },
-  { "SPDREG", 14, {0, {0}}, 0, 0 },
-  { "MULH", 15, {0, {0}}, 0, 0 },
-  { "ADDRH", 16, {0, {0}}, 0, 0 },
-  { "ADDRL", 17, {0, {0}}, 0, 0 },
-  { "DATAH", 18, {0, {0}}, 0, 0 },
-  { "DATAL", 19, {0, {0}}, 0, 0 },
-  { "INTVECH", 20, {0, {0}}, 0, 0 },
-  { "INTVECL", 21, {0, {0}}, 0, 0 },
-  { "INTSPD", 22, {0, {0}}, 0, 0 },
-  { "INTF", 23, {0, {0}}, 0, 0 },
-  { "INTE", 24, {0, {0}}, 0, 0 },
-  { "INTED", 25, {0, {0}}, 0, 0 },
-  { "FCFG", 26, {0, {0}}, 0, 0 },
-  { "TCTRL", 27, {0, {0}}, 0, 0 },
-  { "XCFG", 28, {0, {0}}, 0, 0 },
-  { "EMCFG", 29, {0, {0}}, 0, 0 },
-  { "IPCH", 30, {0, {0}}, 0, 0 },
-  { "IPCL", 31, {0, {0}}, 0, 0 },
-  { "RAIN", 32, {0, {0}}, 0, 0 },
-  { "RAOUT", 33, {0, {0}}, 0, 0 },
-  { "RADIR", 34, {0, {0}}, 0, 0 },
-  { "LFSRH", 35, {0, {0}}, 0, 0 },
-  { "RBIN", 36, {0, {0}}, 0, 0 },
-  { "RBOUT", 37, {0, {0}}, 0, 0 },
-  { "RBDIR", 38, {0, {0}}, 0, 0 },
-  { "LFSRL", 39, {0, {0}}, 0, 0 },
-  { "RCIN", 40, {0, {0}}, 0, 0 },
-  { "RCOUT", 41, {0, {0}}, 0, 0 },
-  { "RCDIR", 42, {0, {0}}, 0, 0 },
-  { "LFSRA", 43, {0, {0}}, 0, 0 },
-  { "RDIN", 44, {0, {0}}, 0, 0 },
-  { "RDOUT", 45, {0, {0}}, 0, 0 },
-  { "RDDIR", 46, {0, {0}}, 0, 0 },
-  { "REIN", 48, {0, {0}}, 0, 0 },
-  { "REOUT", 49, {0, {0}}, 0, 0 },
-  { "REDIR", 50, {0, {0}}, 0, 0 },
-  { "RFIN", 52, {0, {0}}, 0, 0 },
-  { "RFOUT", 53, {0, {0}}, 0, 0 },
-  { "RFDIR", 54, {0, {0}}, 0, 0 },
-  { "RGOUT", 57, {0, {0}}, 0, 0 },
-  { "RGDIR", 58, {0, {0}}, 0, 0 },
-  { "RTTMR", 64, {0, {0}}, 0, 0 },
-  { "RTCFG", 65, {0, {0}}, 0, 0 },
-  { "T0TMR", 66, {0, {0}}, 0, 0 },
-  { "T0CFG", 67, {0, {0}}, 0, 0 },
-  { "T1CNTH", 68, {0, {0}}, 0, 0 },
-  { "T1CNTL", 69, {0, {0}}, 0, 0 },
-  { "T1CAP1H", 70, {0, {0}}, 0, 0 },
-  { "T1CAP1L", 71, {0, {0}}, 0, 0 },
-  { "T1CAP2H", 72, {0, {0}}, 0, 0 },
-  { "T1CMP2H", 72, {0, {0}}, 0, 0 },
-  { "T1CAP2L", 73, {0, {0}}, 0, 0 },
-  { "T1CMP2L", 73, {0, {0}}, 0, 0 },
-  { "T1CMP1H", 74, {0, {0}}, 0, 0 },
-  { "T1CMP1L", 75, {0, {0}}, 0, 0 },
-  { "T1CFG1H", 76, {0, {0}}, 0, 0 },
-  { "T1CFG1L", 77, {0, {0}}, 0, 0 },
-  { "T1CFG2H", 78, {0, {0}}, 0, 0 },
-  { "T1CFG2L", 79, {0, {0}}, 0, 0 },
-  { "ADCH", 80, {0, {0}}, 0, 0 },
-  { "ADCL", 81, {0, {0}}, 0, 0 },
-  { "ADCCFG", 82, {0, {0}}, 0, 0 },
-  { "ADCTMR", 83, {0, {0}}, 0, 0 },
-  { "T2CNTH", 84, {0, {0}}, 0, 0 },
-  { "T2CNTL", 85, {0, {0}}, 0, 0 },
-  { "T2CAP1H", 86, {0, {0}}, 0, 0 },
-  { "T2CAP1L", 87, {0, {0}}, 0, 0 },
-  { "T2CAP2H", 88, {0, {0}}, 0, 0 },
-  { "T2CMP2H", 88, {0, {0}}, 0, 0 },
-  { "T2CAP2L", 89, {0, {0}}, 0, 0 },
-  { "T2CMP2L", 89, {0, {0}}, 0, 0 },
-  { "T2CMP1H", 90, {0, {0}}, 0, 0 },
-  { "T2CMP1L", 91, {0, {0}}, 0, 0 },
-  { "T2CFG1H", 92, {0, {0}}, 0, 0 },
-  { "T2CFG1L", 93, {0, {0}}, 0, 0 },
-  { "T2CFG2H", 94, {0, {0}}, 0, 0 },
-  { "T2CFG2L", 95, {0, {0}}, 0, 0 },
-  { "S1TMRH", 96, {0, {0}}, 0, 0 },
-  { "S1TMRL", 97, {0, {0}}, 0, 0 },
-  { "S1TBUFH", 98, {0, {0}}, 0, 0 },
-  { "S1TBUFL", 99, {0, {0}}, 0, 0 },
-  { "S1TCFG", 100, {0, {0}}, 0, 0 },
-  { "S1RCNT", 101, {0, {0}}, 0, 0 },
-  { "S1RBUFH", 102, {0, {0}}, 0, 0 },
-  { "S1RBUFL", 103, {0, {0}}, 0, 0 },
-  { "S1RCFG", 104, {0, {0}}, 0, 0 },
-  { "S1RSYNC", 105, {0, {0}}, 0, 0 },
-  { "S1INTF", 106, {0, {0}}, 0, 0 },
-  { "S1INTE", 107, {0, {0}}, 0, 0 },
-  { "S1MODE", 108, {0, {0}}, 0, 0 },
-  { "S1SMASK", 109, {0, {0}}, 0, 0 },
-  { "PSPCFG", 110, {0, {0}}, 0, 0 },
-  { "CMPCFG", 111, {0, {0}}, 0, 0 },
-  { "S2TMRH", 112, {0, {0}}, 0, 0 },
-  { "S2TMRL", 113, {0, {0}}, 0, 0 },
-  { "S2TBUFH", 114, {0, {0}}, 0, 0 },
-  { "S2TBUFL", 115, {0, {0}}, 0, 0 },
-  { "S2TCFG", 116, {0, {0}}, 0, 0 },
-  { "S2RCNT", 117, {0, {0}}, 0, 0 },
-  { "S2RBUFH", 118, {0, {0}}, 0, 0 },
-  { "S2RBUFL", 119, {0, {0}}, 0, 0 },
-  { "S2RCFG", 120, {0, {0}}, 0, 0 },
-  { "S2RSYNC", 121, {0, {0}}, 0, 0 },
-  { "S2INTF", 122, {0, {0}}, 0, 0 },
-  { "S2INTE", 123, {0, {0}}, 0, 0 },
-  { "S2MODE", 124, {0, {0}}, 0, 0 },
-  { "S2SMASK", 125, {0, {0}}, 0, 0 },
-  { "CALLH", 126, {0, {0}}, 0, 0 },
-  { "CALLL", 127, {0, {0}}, 0, 0 }
+  { "ADDRSEL", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADDRX", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "IPH", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "IPL", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "SPH", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "SPL", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "PCH", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "PCL", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "WREG", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "STATUS", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "DPH", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "DPL", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "SPDREG", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "MULH", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADDRH", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADDRL", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "DATAH", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "DATAL", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTVECH", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTVECL", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTSPD", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTF", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTE", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "INTED", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "FCFG", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "TCTRL", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "XCFG", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "EMCFG", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "IPCH", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "IPCL", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "RAIN", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "RAOUT", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "RADIR", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "LFSRH", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "RBIN", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "RBOUT", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "RBDIR", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "LFSRL", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "RCIN", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "RCOUT", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "RCDIR", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "LFSRA", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "RDIN", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "RDOUT", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "RDDIR", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "REIN", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "REOUT", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "REDIR", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "RFIN", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "RFOUT", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "RFDIR", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "RGOUT", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "RGDIR", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "RTTMR", 64, {0, {{{0, 0}}}}, 0, 0 },
+  { "RTCFG", 65, {0, {{{0, 0}}}}, 0, 0 },
+  { "T0TMR", 66, {0, {{{0, 0}}}}, 0, 0 },
+  { "T0CFG", 67, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CNTH", 68, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CNTL", 69, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CAP1H", 70, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CAP1L", 71, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CAP2H", 72, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CMP2H", 72, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CAP2L", 73, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CMP2L", 73, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CMP1H", 74, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CMP1L", 75, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CFG1H", 76, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CFG1L", 77, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CFG2H", 78, {0, {{{0, 0}}}}, 0, 0 },
+  { "T1CFG2L", 79, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADCH", 80, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADCL", 81, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADCCFG", 82, {0, {{{0, 0}}}}, 0, 0 },
+  { "ADCTMR", 83, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CNTH", 84, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CNTL", 85, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CAP1H", 86, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CAP1L", 87, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CAP2H", 88, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CMP2H", 88, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CAP2L", 89, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CMP2L", 89, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CMP1H", 90, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CMP1L", 91, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CFG1H", 92, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CFG1L", 93, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CFG2H", 94, {0, {{{0, 0}}}}, 0, 0 },
+  { "T2CFG2L", 95, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1TMRH", 96, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1TMRL", 97, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1TBUFH", 98, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1TBUFL", 99, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1TCFG", 100, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1RCNT", 101, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1RBUFH", 102, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1RBUFL", 103, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1RCFG", 104, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1RSYNC", 105, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1INTF", 106, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1INTE", 107, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1MODE", 108, {0, {{{0, 0}}}}, 0, 0 },
+  { "S1SMASK", 109, {0, {{{0, 0}}}}, 0, 0 },
+  { "PSPCFG", 110, {0, {{{0, 0}}}}, 0, 0 },
+  { "CMPCFG", 111, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2TMRH", 112, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2TMRL", 113, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2TBUFH", 114, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2TBUFL", 115, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2TCFG", 116, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2RCNT", 117, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2RBUFH", 118, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2RBUFL", 119, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2RCFG", 120, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2RSYNC", 121, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2INTF", 122, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2INTE", 123, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2MODE", 124, {0, {{{0, 0}}}}, 0, 0 },
+  { "S2SMASK", 125, {0, {{{0, 0}}}}, 0, 0 },
+  { "CALLH", 126, {0, {{{0, 0}}}}, 0, 0 },
+  { "CALLL", 127, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD ip2k_cgen_opval_register_names =
@@ -271,20 +271,20 @@ CGEN_KEYWORD ip2k_cgen_opval_register_names =
 
 const CGEN_HW_ENTRY ip2k_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -300,24 +300,24 @@ const CGEN_HW_ENTRY ip2k_cgen_hw_table[] =
 
 const CGEN_IFLD ip2k_cgen_ifld_table[] =
 {
-  { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } }  },
-  { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -349,59 +349,59 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* addr16cjp: 13-bit address */
   { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* fr: register */
   { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* lit8: 8-bit signed literal */
   { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* bitno: bit number */
   { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* addr16p: page number */
   { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* addr16h: high 8 bits of address */
   { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* addr16l: low 8 bits of address */
   { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* reti3: reti flags */
   { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
     { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* pabits: page bits */
   { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* zbit: zero bit */
   { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbit: carry bit */
   { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dcbit: digit carry bit */
   { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -421,436 +421,436 @@ static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 /* jmp $addr16cjp */
   {
     IP2K_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call $addr16cjp */
   {
     IP2K_INSN_CALL, "call", "call", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sb $fr,$bitno */
   {
     IP2K_INSN_SB, "sb", "sb", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* snb $fr,$bitno */
   {
     IP2K_INSN_SNB, "snb", "snb", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* setb $fr,$bitno */
   {
     IP2K_INSN_SETB, "setb", "setb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clrb $fr,$bitno */
   {
     IP2K_INSN_CLRB, "clrb", "clrb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor W,#$lit8 */
   {
     IP2K_INSN_XORW_L, "xorw_l", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and W,#$lit8 */
   {
     IP2K_INSN_ANDW_L, "andw_l", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or W,#$lit8 */
   {
     IP2K_INSN_ORW_L, "orw_l", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add W,#$lit8 */
   {
     IP2K_INSN_ADDW_L, "addw_l", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub W,#$lit8 */
   {
     IP2K_INSN_SUBW_L, "subw_l", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cmp W,#$lit8 */
   {
     IP2K_INSN_CMPW_L, "cmpw_l", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* retw #$lit8 */
   {
     IP2K_INSN_RETW_L, "retw_l", "retw", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cse W,#$lit8 */
   {
     IP2K_INSN_CSEW_L, "csew_l", "cse", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* csne W,#$lit8 */
   {
     IP2K_INSN_CSNEW_L, "csnew_l", "csne", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* push #$lit8 */
   {
     IP2K_INSN_PUSH_L, "push_l", "push", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* muls W,#$lit8 */
   {
     IP2K_INSN_MULSW_L, "mulsw_l", "muls", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mulu W,#$lit8 */
   {
     IP2K_INSN_MULUW_L, "muluw_l", "mulu", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* loadl #$lit8 */
   {
     IP2K_INSN_LOADL_L, "loadl_l", "loadl", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* loadh #$lit8 */
   {
     IP2K_INSN_LOADH_L, "loadh_l", "loadh", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* loadl $addr16l */
   {
     IP2K_INSN_LOADL_A, "loadl_a", "loadl", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* loadh $addr16h */
   {
     IP2K_INSN_LOADH_A, "loadh_a", "loadh", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addc $fr,W */
   {
     IP2K_INSN_ADDCFR_W, "addcfr_w", "addc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addc W,$fr */
   {
     IP2K_INSN_ADDCW_FR, "addcw_fr", "addc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* incsnz $fr */
   {
     IP2K_INSN_INCSNZ_FR, "incsnz_fr", "incsnz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* incsnz W,$fr */
   {
     IP2K_INSN_INCSNZW_FR, "incsnzw_fr", "incsnz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* muls W,$fr */
   {
     IP2K_INSN_MULSW_FR, "mulsw_fr", "muls", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mulu W,$fr */
   {
     IP2K_INSN_MULUW_FR, "muluw_fr", "mulu", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* decsnz $fr */
   {
     IP2K_INSN_DECSNZ_FR, "decsnz_fr", "decsnz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* decsnz W,$fr */
   {
     IP2K_INSN_DECSNZW_FR, "decsnzw_fr", "decsnz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subc W,$fr */
   {
     IP2K_INSN_SUBCW_FR, "subcw_fr", "subc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subc $fr,W */
   {
     IP2K_INSN_SUBCFR_W, "subcfr_w", "subc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* pop $fr */
   {
     IP2K_INSN_POP_FR, "pop_fr", "pop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* push $fr */
   {
     IP2K_INSN_PUSH_FR, "push_fr", "push", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cse W,$fr */
   {
     IP2K_INSN_CSEW_FR, "csew_fr", "cse", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* csne W,$fr */
   {
     IP2K_INSN_CSNEW_FR, "csnew_fr", "csne", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* incsz $fr */
   {
     IP2K_INSN_INCSZ_FR, "incsz_fr", "incsz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* incsz W,$fr */
   {
     IP2K_INSN_INCSZW_FR, "incszw_fr", "incsz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* swap $fr */
   {
     IP2K_INSN_SWAP_FR, "swap_fr", "swap", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* swap W,$fr */
   {
     IP2K_INSN_SWAPW_FR, "swapw_fr", "swap", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rl $fr */
   {
     IP2K_INSN_RL_FR, "rl_fr", "rl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rl W,$fr */
   {
     IP2K_INSN_RLW_FR, "rlw_fr", "rl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rr $fr */
   {
     IP2K_INSN_RR_FR, "rr_fr", "rr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rr W,$fr */
   {
     IP2K_INSN_RRW_FR, "rrw_fr", "rr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* decsz $fr */
   {
     IP2K_INSN_DECSZ_FR, "decsz_fr", "decsz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* decsz W,$fr */
   {
     IP2K_INSN_DECSZW_FR, "decszw_fr", "decsz", 16,
-    { 0|A(SKIP_CTI), { (1<<MACH_BASE) } }
+    { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* inc $fr */
   {
     IP2K_INSN_INC_FR, "inc_fr", "inc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* inc W,$fr */
   {
     IP2K_INSN_INCW_FR, "incw_fr", "inc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* not $fr */
   {
     IP2K_INSN_NOT_FR, "not_fr", "not", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* not W,$fr */
   {
     IP2K_INSN_NOTW_FR, "notw_fr", "not", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* test $fr */
   {
     IP2K_INSN_TEST_FR, "test_fr", "test", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov W,#$lit8 */
   {
     IP2K_INSN_MOVW_L, "movw_l", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $fr,W */
   {
     IP2K_INSN_MOVFR_W, "movfr_w", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov W,$fr */
   {
     IP2K_INSN_MOVW_FR, "movw_fr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $fr,W */
   {
     IP2K_INSN_ADDFR_W, "addfr_w", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add W,$fr */
   {
     IP2K_INSN_ADDW_FR, "addw_fr", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor $fr,W */
   {
     IP2K_INSN_XORFR_W, "xorfr_w", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor W,$fr */
   {
     IP2K_INSN_XORW_FR, "xorw_fr", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and $fr,W */
   {
     IP2K_INSN_ANDFR_W, "andfr_w", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and W,$fr */
   {
     IP2K_INSN_ANDW_FR, "andw_fr", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $fr,W */
   {
     IP2K_INSN_ORFR_W, "orfr_w", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or W,$fr */
   {
     IP2K_INSN_ORW_FR, "orw_fr", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dec $fr */
   {
     IP2K_INSN_DEC_FR, "dec_fr", "dec", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dec W,$fr */
   {
     IP2K_INSN_DECW_FR, "decw_fr", "dec", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $fr,W */
   {
     IP2K_INSN_SUBFR_W, "subfr_w", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub W,$fr */
   {
     IP2K_INSN_SUBW_FR, "subw_fr", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clr $fr */
   {
     IP2K_INSN_CLR_FR, "clr_fr", "clr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cmp W,$fr */
   {
     IP2K_INSN_CMPW_FR, "cmpw_fr", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* speed #$lit8 */
   {
     IP2K_INSN_SPEED, "speed", "speed", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ireadi */
   {
     IP2K_INSN_IREADI, "ireadi", "ireadi", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iwritei */
   {
     IP2K_INSN_IWRITEI, "iwritei", "iwritei", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fread */
   {
     IP2K_INSN_FREAD, "fread", "fread", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fwrite */
   {
     IP2K_INSN_FWRITE, "fwrite", "fwrite", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iread */
   {
     IP2K_INSN_IREAD, "iread", "iread", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iwrite */
   {
     IP2K_INSN_IWRITE, "iwrite", "iwrite", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* page $addr16p */
   {
     IP2K_INSN_PAGE, "page", "page", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* system */
   {
     IP2K_INSN_SYSTEM, "system", "system", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* reti #$reti3 */
   {
     IP2K_INSN_RETI, "reti", "reti", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ret */
   {
     IP2K_INSN_RET, "ret", "ret", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* int */
   {
     IP2K_INSN_INT, "int", "int", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* breakx */
   {
     IP2K_INSN_BREAKX, "breakx", "breakx", 16,
-    { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } }
+    { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cwdt */
   {
     IP2K_INSN_CWDT, "cwdt", "cwdt", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ferase */
   {
     IP2K_INSN_FERASE, "ferase", "ferase", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* retnp */
   {
     IP2K_INSN_RETNP, "retnp", "retnp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* break */
   {
     IP2K_INSN_BREAK, "break", "break", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nop */
   {
     IP2K_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
@@ -973,7 +973,7 @@ static void
 ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -985,7 +985,7 @@ ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & ip2k_cgen_isa_table[i];
 
@@ -1070,7 +1070,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -1089,7 +1089,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -1120,9 +1120,6 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -1130,7 +1127,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h
index fa85fbdf366..125849fbc8d 100644
--- a/opcodes/ip2k-desc.h
+++ b/opcodes/ip2k-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef IP2K_CPU_H
 #define IP2K_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH ip2k
 
 /* Given symbol S, return ip2k_cgen_<S>.  */
@@ -160,6 +162,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for ip2k ifield types.  */
 typedef enum ifield_type {
   IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
@@ -182,6 +193,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for ip2k hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -204,6 +222,17 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
 /* Enum declaration for ip2k operand types.  */
 typedef enum cgen_operand_type {
   IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
@@ -231,6 +260,21 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c
index 95cb9e49e97..b80e97fb6a1 100644
--- a/opcodes/ip2k-dis.c
+++ b/opcodes/ip2k-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -596,7 +596,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -608,11 +608,12 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -635,25 +636,34 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -669,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -682,7 +692,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c
index dd4648f8f11..30a734ec1ff 100644
--- a/opcodes/ip2k-opc.c
+++ b/opcodes/ip2k-opc.c
@@ -726,32 +726,32 @@ static const CGEN_IBASE ip2k_cgen_macro_insn_table[] =
 /* sc */
   {
     -1, "sc", "sc", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* snc */
   {
     -1, "snc", "snc", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sz */
   {
     -1, "sz", "sz", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* snz */
   {
     -1, "snz", "snz", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* skip */
   {
     -1, "skip", "skip", 16,
-    { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(SKIPA)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* skip */
   {
     -1, "skipb", "skip", 16,
-    { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(SKIPA)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index 1bfa926efdb..e2d8c490646 100644
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -192,6 +192,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
 }
 
 static const char *
+parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
+		int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_SIGNED;
+
+  if (value < -7 || value > 8)
+    return _("Immediate is out of range -7 to 8");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("Immediate is out of range -7 to 8");
+
+  *valuep = -value;
+  return 0;
+}
+
+static const char *
 parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
 	       int opindex, signed long *valuep)
 {
@@ -407,6 +432,26 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
   return 0;
 }
 
+/* This should only be used for #imm->reg.  */
+static const char *
+parse_signed24 (CGEN_CPU_DESC cd, const char **strp,
+		 int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  PARSE_SIGNED;
+
+  if (value <= 0xffffff && value > 0x7fffff)
+    value -= 0x1000000;
+
+  if (value > 0xffffff)
+    return _("dsp:24 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
 static const char *
 parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
 		int opindex, signed long *valuep)
@@ -749,14 +794,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
 			  const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
-  int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
   /* If attributes are absent, assume no restriction.  */
   if (machs == 0)
     machs = ~0;
 
   return ((machs & cd->machs)
-	  && (isas & cd->isas));
+          && cgen_bitset_intersect_p (& isas, cd->isas));
 }
 
 /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
@@ -1038,6 +1083,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_DSP_48_U8 :
       errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_48_U8, (unsigned long *) (& fields->f_dsp_48_u8));
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      errmsg = parse_signed24 (cd, strp, M32C_OPERAND_DSP_8_S24, (long *) (& fields->f_dsp_8_s24));
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_8_S8, (long *) (& fields->f_dsp_8_s8));
       break;
@@ -1149,6 +1197,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_12_S4 :
       errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4));
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_12_S4N, (long *) (& fields->f_imm_12_s4));
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3));
       break;
@@ -1218,6 +1269,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_8_S4 :
       errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_8_S4, (long *) (& fields->f_imm_8_s4));
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_8_S4N, (long *) (& fields->f_imm_8_s4));
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_12_s4);
       break;
diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index a86c086a773..12b9a1b385a 100644
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -134,10 +134,10 @@ static const CGEN_MACH m32c_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr =
@@ -149,10 +149,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
 {
-  { "r0l", 0, {0, {0}}, 0, 0 },
-  { "r0h", 1, {0, {0}}, 0, 0 },
-  { "r1l", 2, {0, {0}}, 0, 0 },
-  { "r1h", 3, {0, {0}}, 0, 0 }
+  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
@@ -164,10 +164,10 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
@@ -179,8 +179,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
 {
-  { "r2r0", 0, {0, {0}}, 0, 0 },
-  { "r3r1", 1, {0, {0}}, 0, 0 }
+  { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
@@ -192,8 +192,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
 {
-  { "r0l", 0, {0, {0}}, 0, 0 },
-  { "r1l", 1, {0, {0}}, 0, 0 }
+  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
@@ -205,8 +205,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
@@ -218,7 +218,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
 {
-  { "r0l", 0, {0, {0}}, 0, 0 }
+  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r0l =
@@ -230,7 +230,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
 {
-  { "r0h", 0, {0, {0}}, 0, 0 }
+  { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r0h =
@@ -242,7 +242,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0h =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
 {
-  { "r1l", 0, {0, {0}}, 0, 0 }
+  { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r1l =
@@ -254,7 +254,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1l =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
 {
-  { "r1h", 0, {0, {0}}, 0, 0 }
+  { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r1h =
@@ -266,7 +266,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1h =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r0 =
@@ -278,7 +278,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
 {
-  { "r1", 0, {0, {0}}, 0, 0 }
+  { "r1", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r1 =
@@ -290,7 +290,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
 {
-  { "r2", 0, {0, {0}}, 0, 0 }
+  { "r2", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r2 =
@@ -302,7 +302,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
 {
-  { "r3", 0, {0, {0}}, 0, 0 }
+  { "r3", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r3 =
@@ -314,8 +314,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
 {
-  { "r0l", 0, {0, {0}}, 0, 0 },
-  { "r0h", 1, {0, {0}}, 0, 0 }
+  { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
@@ -327,7 +327,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
 {
-  { "r2r0", 0, {0, {0}}, 0, 0 }
+  { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
@@ -339,7 +339,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
 {
-  { "r3r1", 0, {0, {0}}, 0, 0 }
+  { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
@@ -351,7 +351,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
 {
-  { "r1r2r0", 0, {0, {0}}, 0, 0 }
+  { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
@@ -363,8 +363,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
 {
-  { "a0", 0, {0, {0}}, 0, 0 },
-  { "a1", 1, {0, {0}}, 0, 0 }
+  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_ar =
@@ -376,8 +376,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
 {
-  { "a0", 0, {0, {0}}, 0, 0 },
-  { "a1", 1, {0, {0}}, 0, 0 }
+  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
@@ -389,8 +389,8 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
 {
-  { "a0", 0, {0, {0}}, 0, 0 },
-  { "a1", 1, {0, {0}}, 0, 0 }
+  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
@@ -402,7 +402,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
 {
-  { "a1a0", 0, {0, {0}}, 0, 0 }
+  { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
@@ -414,7 +414,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
 {
-  { "a0", 0, {0, {0}}, 0, 0 }
+  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_a0 =
@@ -426,7 +426,7 @@ CGEN_KEYWORD m32c_cgen_opval_h_a0 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
 {
-  { "a1", 1, {0, {0}}, 0, 0 }
+  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_a1 =
@@ -438,24 +438,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_a1 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
 {
-  { "geu", 0, {0, {0}}, 0, 0 },
-  { "c", 0, {0, {0}}, 0, 0 },
-  { "gtu", 1, {0, {0}}, 0, 0 },
-  { "eq", 2, {0, {0}}, 0, 0 },
-  { "z", 2, {0, {0}}, 0, 0 },
-  { "n", 3, {0, {0}}, 0, 0 },
-  { "le", 4, {0, {0}}, 0, 0 },
-  { "o", 5, {0, {0}}, 0, 0 },
-  { "ge", 6, {0, {0}}, 0, 0 },
-  { "ltu", 248, {0, {0}}, 0, 0 },
-  { "nc", 248, {0, {0}}, 0, 0 },
-  { "leu", 249, {0, {0}}, 0, 0 },
-  { "ne", 250, {0, {0}}, 0, 0 },
-  { "nz", 250, {0, {0}}, 0, 0 },
-  { "pz", 251, {0, {0}}, 0, 0 },
-  { "gt", 252, {0, {0}}, 0, 0 },
-  { "no", 253, {0, {0}}, 0, 0 },
-  { "lt", 254, {0, {0}}, 0, 0 }
+  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "leu", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "pz", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "no", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 254, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
@@ -467,24 +467,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
 {
-  { "geu", 0, {0, {0}}, 0, 0 },
-  { "c", 0, {0, {0}}, 0, 0 },
-  { "gtu", 1, {0, {0}}, 0, 0 },
-  { "eq", 2, {0, {0}}, 0, 0 },
-  { "z", 2, {0, {0}}, 0, 0 },
-  { "n", 3, {0, {0}}, 0, 0 },
-  { "ltu", 4, {0, {0}}, 0, 0 },
-  { "nc", 4, {0, {0}}, 0, 0 },
-  { "leu", 5, {0, {0}}, 0, 0 },
-  { "ne", 6, {0, {0}}, 0, 0 },
-  { "nz", 6, {0, {0}}, 0, 0 },
-  { "pz", 7, {0, {0}}, 0, 0 },
-  { "le", 8, {0, {0}}, 0, 0 },
-  { "o", 9, {0, {0}}, 0, 0 },
-  { "ge", 10, {0, {0}}, 0, 0 },
-  { "gt", 12, {0, {0}}, 0, 0 },
-  { "no", 13, {0, {0}}, 0, 0 },
-  { "lt", 14, {0, {0}}, 0, 0 }
+  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "pz", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
@@ -496,12 +496,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
 {
-  { "le", 8, {0, {0}}, 0, 0 },
-  { "o", 9, {0, {0}}, 0, 0 },
-  { "ge", 10, {0, {0}}, 0, 0 },
-  { "gt", 12, {0, {0}}, 0, 0 },
-  { "no", 13, {0, {0}}, 0, 0 },
-  { "lt", 14, {0, {0}}, 0, 0 }
+  { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
@@ -513,18 +513,18 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
 {
-  { "geu", 0, {0, {0}}, 0, 0 },
-  { "c", 0, {0, {0}}, 0, 0 },
-  { "gtu", 1, {0, {0}}, 0, 0 },
-  { "eq", 2, {0, {0}}, 0, 0 },
-  { "z", 2, {0, {0}}, 0, 0 },
-  { "n", 3, {0, {0}}, 0, 0 },
-  { "ltu", 4, {0, {0}}, 0, 0 },
-  { "nc", 4, {0, {0}}, 0, 0 },
-  { "leu", 5, {0, {0}}, 0, 0 },
-  { "ne", 6, {0, {0}}, 0, 0 },
-  { "nz", 6, {0, {0}}, 0, 0 },
-  { "pz", 7, {0, {0}}, 0, 0 }
+  { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
@@ -536,24 +536,24 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
 {
-  { "ltu", 0, {0, {0}}, 0, 0 },
-  { "nc", 0, {0, {0}}, 0, 0 },
-  { "leu", 1, {0, {0}}, 0, 0 },
-  { "ne", 2, {0, {0}}, 0, 0 },
-  { "nz", 2, {0, {0}}, 0, 0 },
-  { "pz", 3, {0, {0}}, 0, 0 },
-  { "no", 4, {0, {0}}, 0, 0 },
-  { "gt", 5, {0, {0}}, 0, 0 },
-  { "ge", 6, {0, {0}}, 0, 0 },
-  { "geu", 8, {0, {0}}, 0, 0 },
-  { "c", 8, {0, {0}}, 0, 0 },
-  { "gtu", 9, {0, {0}}, 0, 0 },
-  { "eq", 10, {0, {0}}, 0, 0 },
-  { "z", 10, {0, {0}}, 0, 0 },
-  { "n", 11, {0, {0}}, 0, 0 },
-  { "o", 12, {0, {0}}, 0, 0 },
-  { "le", 13, {0, {0}}, 0, 0 },
-  { "lt", 14, {0, {0}}, 0, 0 }
+  { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "leu", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "pz", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "no", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "geu", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "o", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
@@ -565,14 +565,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
 {
-  { "dct0", 0, {0, {0}}, 0, 0 },
-  { "dct1", 1, {0, {0}}, 0, 0 },
-  { "flg", 2, {0, {0}}, 0, 0 },
-  { "svf", 3, {0, {0}}, 0, 0 },
-  { "drc0", 4, {0, {0}}, 0, 0 },
-  { "drc1", 5, {0, {0}}, 0, 0 },
-  { "dmd0", 6, {0, {0}}, 0, 0 },
-  { "dmd1", 7, {0, {0}}, 0, 0 }
+  { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "flg", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "svf", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
@@ -584,13 +584,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
 {
-  { "intb", 0, {0, {0}}, 0, 0 },
-  { "sp", 1, {0, {0}}, 0, 0 },
-  { "sb", 2, {0, {0}}, 0, 0 },
-  { "fb", 3, {0, {0}}, 0, 0 },
-  { "svp", 4, {0, {0}}, 0, 0 },
-  { "vct", 5, {0, {0}}, 0, 0 },
-  { "isp", 7, {0, {0}}, 0, 0 }
+  { "intb", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "sb", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "fb", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "svp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "vct", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "isp", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
@@ -602,12 +602,12 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
 {
-  { "dma0", 2, {0, {0}}, 0, 0 },
-  { "dma1", 3, {0, {0}}, 0, 0 },
-  { "dra0", 4, {0, {0}}, 0, 0 },
-  { "dra1", 5, {0, {0}}, 0, 0 },
-  { "dsa0", 6, {0, {0}}, 0, 0 },
-  { "dsa1", 7, {0, {0}}, 0, 0 }
+  { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
@@ -619,13 +619,13 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
 {
-  { "intbl", 1, {0, {0}}, 0, 0 },
-  { "intbh", 2, {0, {0}}, 0, 0 },
-  { "flg", 3, {0, {0}}, 0, 0 },
-  { "isp", 4, {0, {0}}, 0, 0 },
-  { "sp", 5, {0, {0}}, 0, 0 },
-  { "sb", 6, {0, {0}}, 0, 0 },
-  { "fb", 7, {0, {0}}, 0, 0 }
+  { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "flg", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "isp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "sb", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "fb", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
@@ -637,14 +637,14 @@ CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
 {
-  { "c", 0, {0, {0}}, 0, 0 },
-  { "d", 1, {0, {0}}, 0, 0 },
-  { "z", 2, {0, {0}}, 0, 0 },
-  { "s", 3, {0, {0}}, 0, 0 },
-  { "b", 4, {0, {0}}, 0, 0 },
-  { "o", 5, {0, {0}}, 0, 0 },
-  { "i", 6, {0, {0}}, 0, 0 },
-  { "u", 7, {0, {0}}, 0, 0 }
+  { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "d", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "s", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "b", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "i", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "u", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_flags =
@@ -656,22 +656,22 @@ CGEN_KEYWORD m32c_cgen_opval_h_flags =
 
 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
 {
-  { "1", 0, {0, {0}}, 0, 0 },
-  { "2", 1, {0, {0}}, 0, 0 },
-  { "3", 2, {0, {0}}, 0, 0 },
-  { "4", 3, {0, {0}}, 0, 0 },
-  { "5", 4, {0, {0}}, 0, 0 },
-  { "6", 5, {0, {0}}, 0, 0 },
-  { "7", 6, {0, {0}}, 0, 0 },
-  { "8", 7, {0, {0}}, 0, 0 },
-  { "-1", -8, {0, {0}}, 0, 0 },
-  { "-2", -7, {0, {0}}, 0, 0 },
-  { "-3", -6, {0, {0}}, 0, 0 },
-  { "-4", -5, {0, {0}}, 0, 0 },
-  { "-5", -4, {0, {0}}, 0, 0 },
-  { "-6", -3, {0, {0}}, 0, 0 },
-  { "-7", -2, {0, {0}}, 0, 0 },
-  { "-8", -1, {0, {0}}, 0, 0 }
+  { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "4", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "5", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "6", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "7", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "8", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "-1", -8, {0, {{{0, 0}}}}, 0, 0 },
+  { "-2", -7, {0, {{{0, 0}}}}, 0, 0 },
+  { "-3", -6, {0, {{{0, 0}}}}, 0, 0 },
+  { "-4", -5, {0, {{{0, 0}}}}, 0, 0 },
+  { "-5", -4, {0, {{{0, 0}}}}, 0, 0 },
+  { "-6", -3, {0, {{{0, 0}}}}, 0, 0 },
+  { "-7", -2, {0, {{{0, 0}}}}, 0, 0 },
+  { "-8", -1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32c_cgen_opval_h_shimm =
@@ -692,82 +692,82 @@ CGEN_KEYWORD m32c_cgen_opval_h_shimm =
 
 const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
-  { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
-  { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
-  { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
-  { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
-  { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
-  { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
+  { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
+  { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
+  { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
+  { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } } },
+  { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
 #undef A
@@ -783,163 +783,164 @@ const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
 
 const CGEN_IFLD m32c_cgen_ifld_table[] =
 {
-  { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
-  { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
-  { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
-  { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
-  { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
+  { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
+  { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
 #undef A
@@ -1157,815 +1158,827 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* Src16RnQI: general register QI view */
   { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Src16RnHI: general register QH view */
   { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Src32RnUnprefixedQI: general register QI view */
   { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32RnUnprefixedHI: general register HI view */
   { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32RnUnprefixedSI: general register SI view */
   { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32RnPrefixedQI: general register QI view */
   { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32RnPrefixedHI: general register HI view */
   { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32RnPrefixedSI: general register SI view */
   { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src16An: address register */
   { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Src16AnQI: address register QI view */
   { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Src16AnHI: address register HI view */
   { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Src32AnUnprefixed: address register */
   { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnUnprefixedQI: address register QI view */
   { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnUnprefixedHI: address register HI view */
   { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnUnprefixedSI: address register SI view */
   { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnPrefixed: address register */
   { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnPrefixedQI: address register QI view */
   { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnPrefixedHI: address register HI view */
   { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Src32AnPrefixedSI: address register SI view */
   { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst16RnQI: general register QI view */
   { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16RnHI: general register HI view */
   { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16RnSI: general register SI view */
   { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
   { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst32R0QI-S: general register QI view */
   { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32R0HI-S: general register HI view */
   { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnUnprefixedQI: general register QI view */
   { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnUnprefixedHI: general register HI view */
   { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnUnprefixedSI: general register SI view */
   { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnExtUnprefixedQI: general register QI view */
   { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnExtUnprefixedHI: general register HI view */
   { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnPrefixedQI: general register QI view */
   { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnPrefixedHI: general register HI view */
   { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32RnPrefixedSI: general register SI view */
   { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst16RnQI-S: general register QI view */
   { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16AnQI-S: address register QI view */
   { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Bit16Rn: general register bit view */
   { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Bit32RnPrefixed: general register bit view */
   { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Bit32RnUnprefixed: general register bit view */
   { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* R0: r0 */
   { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R1: r1 */
   { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R2: r2 */
   { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R3: r3 */
   { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R0l: r0l */
   { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R0h: r0h */
   { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R2R0: r2r0 */
   { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R3R1: r3r1 */
   { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* R1R2R0: r1r2r0 */
   { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dst16An: address register */
   { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16AnQI: address register QI view */
   { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16AnHI: address register HI view */
   { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16AnSI: address register SI view */
   { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst16An-S: address register HI view */
   { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dst32AnUnprefixed: address register */
   { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnUnprefixedQI: address register QI view */
   { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnUnprefixedHI: address register HI view */
   { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnUnprefixedSI: address register SI view */
   { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnExtUnprefixed: address register */
   { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnPrefixed: address register */
   { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnPrefixedQI: address register QI view */
   { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnPrefixedHI: address register HI view */
   { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Dst32AnPrefixedSI: address register SI view */
   { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Bit16An: address register bit view */
   { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Bit32AnPrefixed: address register bit */
   { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Bit32AnUnprefixed: address register bit */
   { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* A0: a0 */
   { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* A1: a1 */
   { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* sb: SB register */
   { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* fb: FB register */
   { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* sp: SP register */
   { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
   { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Regsetpop: popm regset */
   { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Regsetpush: pushm regset */
   { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Rn16-push-S: r0[lh] */
   { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* An16-push-S: a[01] */
   { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } }, 
-    { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } } } }  },
 /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
   { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
   { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
   { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
   { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+/* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
+  { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
   { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
   { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
   { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
   { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
   { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
   { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
   { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
   { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
   { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
   { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
     { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
   { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
   { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
   { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
   { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
     { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
   { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
   { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
   { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
   { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
   { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
   { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
   { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
   { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
   { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
   { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
   { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
   { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
   { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
   { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
   { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
   { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
   { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+/* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
+  { "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
   { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
   { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
   { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
   { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+/* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
+  { "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
   { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
   { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
   { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
   { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
   { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
   { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
   { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
     { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
   { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
   { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
     { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
   { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
     { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
   { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
   { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
   { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
   { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
   { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
   { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
     { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
   { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
   { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
   { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
     { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
   { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
   { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
     { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
   { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Imm1-S: signed 1 bit immediate for short format binary insns */
   { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } }, 
-    { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* Imm3-S: signed 3 bit immediate for short format binary insns */
   { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
     { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* Bitno16R: bit number for indexing registers */
   { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* Bitno32Prefixed: bit number for indexing objects */
   { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* Bitno32Unprefixed: bit number for indexing objects */
   { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
   { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
   { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
   { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
   { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
     { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
   { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
     { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
   { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
     { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
   { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
     { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
   { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
     { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
   { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
     { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
   { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
     { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
   { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
     { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
   { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
     { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
   { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
     { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
   { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
     { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* Lab-5-3: 3 bit label */
   { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } }, 
-    { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab32-jmp-s: 3 bit label */
   { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
     { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } }, 
-    { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-8-8: 8 bit label */
   { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } }, 
-    { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-8-16: 16 bit label */
   { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } }, 
-    { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-8-24: 24 bit label */
   { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-16-8: 8 bit label */
   { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } }, 
-    { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-24-8: 8 bit label */
   { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-32-8: 8 bit label */
   { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Lab-40-8: 8 bit label */
   { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* sbit: negative    bit */
   { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* obit: overflow    bit */
   { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* zbit: zero        bit */
   { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* cbit: carry       bit */
   { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* ubit: stack ptr select bit */
   { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* ibit: interrupt enable bit */
   { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* bbit: reg bank select bit */
   { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* dbit: debug       bit */
   { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* cond16-16: condition */
   { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond16-24: condition */
   { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond16-32: condition */
   { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond32-16: condition */
   { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cond32-24: condition */
   { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cond32-32: condition */
   { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cond32-40: condition */
   { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cond16c: condition */
   { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond16j: condition */
   { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond16j5: condition */
   { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cond32: condition */
   { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
     { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cond32j: condition */
   { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
     { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } }, 
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* sccond32: scCND condition */
   { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* flags16: flags */
   { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* flags32: flags */
   { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cr16: control */
   { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
 /* cr1-Unprefixed-32: control */
   { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cr1-Prefixed-32: control */
   { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cr2-32: control */
   { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cr3-Unprefixed-32: control */
   { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* cr3-Prefixed-32: control */
   { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
 /* Z: Suffix for zero format insns */
   { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* S: Suffix for short format insns */
   { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* Q: Suffix for quick format insns */
   { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* G: Suffix for general format insns */
   { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* X: Empty suffix */
   { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* size: any size specifier */
   { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
 /* BitIndex: Bit Index for the next insn */
   { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* SrcIndex: Source Index for the next insn */
   { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* DstIndex: Destination Index for the next insn */
   { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* NoRemainder: Place holder for when the remainder is not kept */
   { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } } } }  },
 /* src16-Rn-direct-QI: m16c Rn direct source QI */
 /* src16-Rn-direct-HI: m16c Rn direct source HI */
 /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
@@ -2636,7 +2649,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
 #undef A
@@ -2656,59616 +2669,60001 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* extz [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w $Dst32RnExtUnprefixedHI */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w $Dst32AnUnprefixedSI */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w [$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u16} */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w ${Dsp-16-u24} */
   {
     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Dst32RnExtUnprefixedQI */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Dst32AnUnprefixedHI */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b [$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u16} */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b ${Dsp-16-u24} */
   {
     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.b $Dst16RnExtQI */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b [$Dst16An] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exts.b ${Dsp-16-u16} */
   {
     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r2,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a1,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w a0,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r1,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r0,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a1,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b a0,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u24} */
   {
     M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* xchg.w r3,$Dst16RnHI */
   {
     M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,$Dst16AnHI */
   {
     M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r3,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,$Dst16RnHI */
   {
     M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,$Dst16AnHI */
   {
     M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r2,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,$Dst16RnHI */
   {
     M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,$Dst16AnHI */
   {
     M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r1,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* xchg.w r0,$Dst16RnQI */
+/* xchg.w r0,$Dst16RnHI */
   {
-    M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, "xchg16w-r0-dst16-Rn-direct-QI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* xchg.w r0,$Dst16AnQI */
+/* xchg.w r0,$Dst16AnHI */
   {
-    M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, "xchg16w-r0-dst16-An-direct-QI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,[$Dst16An] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, "xchg16w-r0-dst16-An-indirect-QI", "xchg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-8-An-relative-QI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-16-An-relative-QI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-SB-relative-QI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-16-SB-relative-QI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-FB-relative-QI", "xchg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.w r0,${Dsp-16-u16} */
   {
-    M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, "xchg16w-r0-dst16-16-16-absolute-QI", "xchg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,$Dst16RnQI */
   {
     M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,$Dst16AnQI */
   {
     M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,$Dst16RnQI */
   {
     M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,$Dst16AnQI */
   {
     M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r1l,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,$Dst16RnQI */
   {
     M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,$Dst16AnQI */
   {
     M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0h,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,$Dst16RnQI */
   {
     M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,$Dst16AnQI */
   {
     M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* xchg.b r0l,${Dsp-16-u16} */
   {
     M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
+/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
+/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
+/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
+/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
+/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
+/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
+/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
+/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.w${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* tst.b${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
+/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
+/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24} */
+/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
+/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
+/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24} */
+/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst16RnHI */
+/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst16AnHI */
+/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-16-HI},[$Dst16An] */
+/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst16RnQI */
+/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst16AnQI */
+/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-16-QI},[$Dst16An] */
+/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
   {
     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
   {
     M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
   {
     M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stz${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stz${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stnz${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stnz${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w r1h,$Dst16RnHI */
   {
     M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,$Dst16AnHI */
   {
     M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,[$Dst16An] */
   {
     M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,$Dst16RnQI */
   {
     M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,$Dst16AnQI */
   {
     M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,[$Dst16An] */
   {
     M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b r1h,${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w r1h,$Dst16RnHI */
   {
     M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,$Dst16AnHI */
   {
     M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,[$Dst16An] */
   {
     M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,$Dst16RnQI */
   {
     M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,$Dst16AnQI */
   {
     M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,[$Dst16An] */
   {
     M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b r1h,${Dsp-16-u16} */
   {
     M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sc${sccond32} $Dst32RnUnprefixedHI */
   {
     M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} $Dst32AnUnprefixedHI */
   {
     M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} [$Dst32AnUnprefixed] */
   {
     M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u16} */
   {
     M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sc${sccond32} ${Dsp-16-u24} */
   {
     M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
   {
     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* rot.w r1h,$Dst32RnUnprefixedSI */
+/* rot.w r1h,$Dst32RnUnprefixedHI */
   {
-    M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-SI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* rot.w r1h,$Dst32AnUnprefixedSI */
+/* rot.w r1h,$Dst32AnUnprefixedHI */
   {
-    M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-direct-Unprefixed-SI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-indirect-Unprefixed-SI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-s16}[fb] */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16} */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,${Dsp-16-u24} */
   {
-    M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* rot.b r1h,$Dst32RnUnprefixedSI */
+/* rot.b r1h,$Dst32RnUnprefixedQI */
   {
-    M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-SI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* rot.b r1h,$Dst32AnUnprefixedSI */
+/* rot.b r1h,$Dst32AnUnprefixedQI */
   {
-    M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-direct-Unprefixed-SI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-indirect-Unprefixed-SI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-s16}[fb] */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16} */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b r1h,${Dsp-16-u24} */
   {
-    M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w r1h,$Dst16RnHI */
   {
     M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,$Dst16AnHI */
   {
     M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,[$Dst16An] */
   {
     M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w r1h,${Dsp-16-u16} */
   {
     M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* rot.b r1h,$Dst16RnHI */
+/* rot.b r1h,$Dst16RnQI */
   {
-    M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, "rot16.b-dst-dst16-Rn-direct-HI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* rot.b r1h,$Dst16AnHI */
+/* rot.b r1h,$Dst16AnQI */
   {
-    M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI, "rot16.b-dst-dst16-An-direct-HI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,[$Dst16An] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, "rot16.b-dst-dst16-An-indirect-HI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-8-An-relative-HI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-16-An-relative-HI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-SB-relative-HI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-16-SB-relative-HI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-FB-relative-HI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b r1h,${Dsp-16-u16} */
   {
-    M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, "rot16.b-dst-dst16-16-16-absolute-HI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u16} */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w ${Dsp-16-u24} */
   {
     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u16} */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.b ${Dsp-16-u24} */
   {
     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rorc.w $Dst16RnHI */
   {
     M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w $Dst16AnHI */
   {
     M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w [$Dst16An] */
   {
     M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.w ${Dsp-16-u16} */
   {
     M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b $Dst16RnQI */
   {
     M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b $Dst16AnQI */
   {
     M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b [$Dst16An] */
   {
     M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rorc.b ${Dsp-16-u16} */
   {
     M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u16} */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w ${Dsp-16-u24} */
   {
     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u16} */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.b ${Dsp-16-u24} */
   {
     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rolc.w $Dst16RnHI */
   {
     M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w $Dst16AnHI */
   {
     M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w [$Dst16An] */
   {
     M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.w ${Dsp-16-u16} */
   {
     M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b $Dst16RnQI */
   {
     M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b $Dst16AnQI */
   {
     M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b [$Dst16An] */
   {
     M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rolc.b ${Dsp-16-u16} */
   {
     M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha [$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u16} */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha ${Dsp-16-u24} */
   {
     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pusha [$Dst16An] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pusha ${Dsp-16-u16} */
   {
     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* push.l $Dst32RnUnprefixedSI */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l $Dst32AnUnprefixedSI */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l [$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u16} */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l ${Dsp-16-u24} */
   {
     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w${S} ${An16-push-S} */
   {
     M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* push.b${S} ${Rn16-push-S} */
   {
     M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* push.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u16} */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w ${Dsp-16-u24} */
   {
     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u16} */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b ${Dsp-16-u24} */
   {
     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* push.w $Dst16RnHI */
+/* push.w${G} $Dst16RnHI */
   {
     M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w $Dst16AnHI */
+/* push.w${G} $Dst16AnHI */
   {
     M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w [$Dst16An] */
+/* push.w${G} [$Dst16An] */
   {
     M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-u8}[$Dst16An] */
+/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-u16}[$Dst16An] */
+/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-u8}[sb] */
+/* push.w${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-u16}[sb] */
+/* push.w${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-s8}[fb] */
+/* push.w${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.w ${Dsp-16-u16} */
+/* push.w${G} ${Dsp-16-u16} */
   {
     M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b $Dst16RnQI */
+/* push.b${G} $Dst16RnQI */
   {
     M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b $Dst16AnQI */
+/* push.b${G} $Dst16AnQI */
   {
     M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b [$Dst16An] */
+/* push.b${G} [$Dst16An] */
   {
     M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-u8}[$Dst16An] */
+/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-u16}[$Dst16An] */
+/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-u8}[sb] */
+/* push.b${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-u16}[sb] */
+/* push.b${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-s8}[fb] */
+/* push.b${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* push.b ${Dsp-16-u16} */
+/* push.b${G} ${Dsp-16-u16} */
   {
     M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w${S} ${An16-push-S} */
   {
     M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b${S} ${Rn16-push-S} */
   {
     M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u16} */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w ${Dsp-16-u24} */
   {
     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u16} */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.b ${Dsp-16-u24} */
   {
     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pop.w $Dst16RnHI */
   {
     M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w $Dst16AnHI */
   {
     M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w [$Dst16An] */
   {
     M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.w ${Dsp-16-u16} */
   {
     M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b $Dst16RnQI */
   {
     M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b $Dst16AnQI */
   {
     M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b [$Dst16An] */
   {
     M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pop.b ${Dsp-16-u16} */
   {
     M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* or.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* not.b:s r0l */
+  {
+    M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
+    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+  },
+/* not.b:s r0h */
+  {
+    M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
   },
-/* not.w $Dst32RnUnprefixedHI */
+/* not.b:s ${Dsp-8-u8}[sb] */
+  {
+    M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
+    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+  },
+/* not.b:s ${Dsp-8-s8}[fb] */
+  {
+    M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
+    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+  },
+/* not.b:s ${Dsp-8-u16} */
+  {
+    M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
+    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+  },
+/* not.w${G} $Dst32RnUnprefixedHI */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w $Dst32AnUnprefixedHI */
+/* not.w${G} $Dst32AnUnprefixedHI */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w [$Dst32AnUnprefixed] */
+/* not.w${G} [$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u8}[sb] */
+/* not.w${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u16}[sb] */
+/* not.w${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-s8}[fb] */
+/* not.w${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-s16}[fb] */
+/* not.w${G} ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u16} */
+/* not.w${G} ${Dsp-16-u16} */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w ${Dsp-16-u24} */
+/* not.w${G} ${Dsp-16-u24} */
   {
     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b $Dst32RnUnprefixedQI */
+/* not.b${G} $Dst32RnUnprefixedQI */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b $Dst32AnUnprefixedQI */
+/* not.b${G} $Dst32AnUnprefixedQI */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b [$Dst32AnUnprefixed] */
+/* not.b${G} [$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u8}[sb] */
+/* not.b${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u16}[sb] */
+/* not.b${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-s8}[fb] */
+/* not.b${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-s16}[fb] */
+/* not.b${G} ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u16} */
+/* not.b${G} ${Dsp-16-u16} */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.b ${Dsp-16-u24} */
+/* not.b${G} ${Dsp-16-u24} */
   {
     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* not.w $Dst16RnHI */
+/* not.w${G} $Dst16RnHI */
   {
     M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w $Dst16AnHI */
+/* not.w${G} $Dst16AnHI */
   {
     M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w [$Dst16An] */
+/* not.w${G} [$Dst16An] */
   {
     M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-u8}[$Dst16An] */
+/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-u16}[$Dst16An] */
+/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-u8}[sb] */
+/* not.w${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-u16}[sb] */
+/* not.w${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-s8}[fb] */
+/* not.w${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.w ${Dsp-16-u16} */
+/* not.w${G} ${Dsp-16-u16} */
   {
     M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b $Dst16RnQI */
+/* not.b${G} $Dst16RnQI */
   {
     M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b $Dst16AnQI */
+/* not.b${G} $Dst16AnQI */
   {
     M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b [$Dst16An] */
+/* not.b${G} [$Dst16An] */
   {
     M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-u8}[$Dst16An] */
+/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-u16}[$Dst16An] */
+/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-u8}[sb] */
+/* not.b${G} ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-u16}[sb] */
+/* not.b${G} ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-s8}[fb] */
+/* not.b${G} ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* not.b ${Dsp-16-u16} */
+/* not.b${G} ${Dsp-16-u16} */
   {
     M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u16} */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w ${Dsp-16-u24} */
   {
     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u16} */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.b ${Dsp-16-u24} */
   {
     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* neg.w $Dst16RnHI */
   {
     M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w $Dst16AnHI */
   {
     M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w [$Dst16An] */
   {
     M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.w ${Dsp-16-u16} */
   {
     M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b $Dst16RnQI */
   {
     M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b $Dst16AnQI */
   {
     M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b [$Dst16An] */
   {
     M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* neg.b ${Dsp-16-u16} */
   {
     M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mulex $R3 */
   {
     M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex $Dst32AnUnprefixedHI */
   {
     M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex [$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u16} */
   {
     M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mulex ${Dsp-16-u24} */
   {
     M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh $Dst32RnPrefixedQI,r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh $Dst32AnPrefixedQI,r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh [$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u8}[sb],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u16}[sb],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-s8}[fb],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-s16}[fb],r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u16},r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh ${Dsp-24-u24},r0l */
   {
     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl $Dst32RnPrefixedQI,r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl $Dst32AnPrefixedQI,r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl [$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u8}[sb],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u16}[sb],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-s8}[fb],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-s16}[fb],r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u16},r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl ${Dsp-24-u24},r0l */
   {
     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh $Dst32RnPrefixedQI,r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh $Dst32AnPrefixedQI,r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh [$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u8}[sb],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u16}[sb],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-s8}[fb],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-s16}[fb],r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u16},r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh ${Dsp-24-u24},r0l */
   {
     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll $Dst32RnPrefixedQI,r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll $Dst32AnPrefixedQI,r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll [$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u8}[sb],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u16}[sb],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-s8}[fb],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-s16}[fb],r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u16},r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll ${Dsp-24-u24},r0l */
   {
     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u16} */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh r0l,${Dsp-24-u24} */
   {
     M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u16} */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhl r0l,${Dsp-24-u24} */
   {
     M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u16} */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movlh r0l,${Dsp-24-u24} */
   {
     M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u16} */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movll r0l,${Dsp-24-u24} */
   {
     M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* movhh $Dst16RnQI,r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh $Dst16AnQI,r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh [$Dst16An],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-u8}[$Dst16An],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-u16}[$Dst16An],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-u8}[sb],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-u16}[sb],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-s8}[fb],r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh ${Dsp-16-u16},r0l */
   {
     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl $Dst16RnQI,r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl $Dst16AnQI,r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl [$Dst16An],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-u8}[$Dst16An],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-u16}[$Dst16An],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-u8}[sb],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-u16}[sb],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-s8}[fb],r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl ${Dsp-16-u16},r0l */
   {
     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh $Dst16RnQI,r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh $Dst16AnQI,r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh [$Dst16An],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-u8}[$Dst16An],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-u16}[$Dst16An],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-u8}[sb],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-u16}[sb],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-s8}[fb],r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh ${Dsp-16-u16},r0l */
   {
     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll $Dst16RnQI,r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll $Dst16AnQI,r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll [$Dst16An],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-u8}[$Dst16An],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-u16}[$Dst16An],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-u8}[sb],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-u16}[sb],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-s8}[fb],r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll ${Dsp-16-u16},r0l */
   {
     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,$Dst16RnQI */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,$Dst16AnQI */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,[$Dst16An] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhh r0l,${Dsp-16-u16} */
   {
     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,$Dst16RnQI */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,$Dst16AnQI */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,[$Dst16An] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movhl r0l,${Dsp-16-u16} */
   {
     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,$Dst16RnQI */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,$Dst16AnQI */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,[$Dst16An] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movlh r0l,${Dsp-16-u16} */
   {
     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,$Dst16RnQI */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,$Dst16AnQI */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,[$Dst16An] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* movll r0l,${Dsp-16-u16} */
   {
     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst32AnUnprefixed],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s16}[fb],a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16},a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24},a1 */
   {
     M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova [$Dst32AnUnprefixed],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s16}[fb],a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16},a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24},a0 */
   {
     M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova [$Dst32AnUnprefixed],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s16}[fb],r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16},r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24},r3r1 */
   {
     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova [$Dst32AnUnprefixed],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-s16}[fb],r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u16},r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova ${Dsp-16-u24},r2r0 */
   {
     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mova [$Dst16An],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},a1 */
   {
     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst16An],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},a0 */
   {
     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst16An],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},r3 */
   {
     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst16An],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},r2 */
   {
     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst16An],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},r1 */
   {
     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova [$Dst16An],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[$Dst16An],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[$Dst16An],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u8}[sb],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16}[sb],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-s8}[fb],r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mova ${Dsp-16-u16},r0 */
   {
     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u24},${Dsp-40-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w $Dst32RnUnprefixedHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w $Dst32AnUnprefixedHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
+/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u24},${Dsp-40-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b $Dst32RnUnprefixedQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b $Dst32AnUnprefixedQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
+/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w $Dst16RnHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w $Dst16AnHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w [$Dst16An],${Dsp-16-u8}[sp] */
+/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b $Dst16RnQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b $Dst16AnQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b [$Dst16An],${Dsp-16-u8}[sp] */
+/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
   {
     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24} */
+/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst32RnUnprefixedHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst32AnUnprefixedHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24} */
+/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst32RnUnprefixedQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst32AnUnprefixedQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst16RnHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst16AnHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.w ${Dsp-16-u8}[sp],[$Dst16An] */
+/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst16RnQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst16AnQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* mov.b ${Dsp-16-u8}[sp],[$Dst16An] */
+/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${S} ${Dsp-8-s8}[fb],a1 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${S} ${Dsp-8-u8}[sb],a0 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${S} ${Dsp-8-s8}[fb],a0 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${S} ${Dsp-8-u16},a1 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${S} ${Dsp-8-u16},a0 */
   {
     M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} r0,${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} r0,${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} r0l,${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} r0l,${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} r0,${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} r0l,${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-u8}[sb],r1 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-s8}[fb],r1 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-u8}[sb],r1l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-s8}[fb],r1l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-u16},r1 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-u16},r1l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.w${S} r0,r1l */
+/* mov.w${S} r0,r1 */
   {
-    M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1l-dst32-2-S-R0-direct-HI", "mov.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} r0l,r1l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-u8}[sb],r0 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-s8}[fb],r0 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-u8}[sb],r0l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-s8}[fb],r0l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} ${Dsp-8-u16},r0 */
   {
     M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-u16},r0l */
   {
     M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
   {
     M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
   {
     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
   {
     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
   {
     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
   {
     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
   {
     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
   {
     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
   {
     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Z} #0,${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Z} #0,${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Z} #0,${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Z} #0,r0 */
   {
     M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Z} #0,r0l */
   {
     M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Z} #0,r0l */
   {
     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Z} #0,r0h */
   {
     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Z} #0,${Dsp-8-u16} */
   {
     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "ste.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "ste.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16},[a1a0] */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "ste.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "ste.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "ste.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "ste.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
+  {
+    M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
+  {
+    M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
+  {
+    M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w $Dst16RnHI,[a1a0] */
+  {
+    M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w $Dst16AnHI,[a1a0] */
+  {
+    M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w [$Dst16An],[a1a0] */
+  {
+    M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "ste.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-direct-HI", "ste.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.w [$Dst16An],${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-indirect-HI", "ste.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "ste.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "ste.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16},[a1a0] */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "ste.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "ste.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "ste.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "ste.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
+  {
+    M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
+  {
+    M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
+  {
+    M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
+  {
+    M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+  {
+    M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b $Dst16RnQI,[a1a0] */
+  {
+    M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b $Dst16AnQI,[a1a0] */
+  {
+    M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b [$Dst16An],[a1a0] */
+  {
+    M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
+  {
+    M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "ste.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-direct-QI", "ste.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ste.b [$Dst16An],${Dsp-16-u20} */
   {
-    M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-indirect-QI", "ste.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "lde.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+/* lde.w [a1a0],${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "lde.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+/* lde.w [a1a0],${Dsp-16-u16} */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "lde.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
+  {
+    M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
+  {
+    M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "lde.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "lde.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "lde.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],$Dst16RnHI */
+  {
+    M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],$Dst16AnHI */
+  {
+    M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w [a1a0],[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
+  {
+    M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
+  {
+    M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
+  {
+    M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "lde.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-direct-HI", "lde.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.w ${Dsp-16-u20},[$Dst16An] */
   {
-    M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-indirect-HI", "lde.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "lde.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+/* lde.b [a1a0],${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "lde.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+/* lde.b [a1a0],${Dsp-16-u16} */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "lde.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
+  {
+    M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
+  {
+    M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "lde.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "lde.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "lde.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+  {
+    M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+  {
+    M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],$Dst16RnQI */
+  {
+    M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],$Dst16AnQI */
+  {
+    M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b [a1a0],[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
+  {
+    M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
+  {
+    M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
+/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
+  {
+    M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "lde.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-direct-QI", "lde.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* lde.b ${Dsp-16-u20},[$Dst16An] */
   {
-    M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-indirect-QI", "lde.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
   {
     M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u16} */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr2-32},${Dsp-16-u24} */
   {
     M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
   {
     M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stc pc,$Dst16RnHI */
   {
     M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,$Dst16AnHI */
   {
     M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,[$Dst16An] */
   {
     M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc pc,${Dsp-16-u16} */
   {
     M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},$Dst16RnHI */
   {
     M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},$Dst16AnHI */
   {
     M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},[$Dst16An] */
   {
     M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stc ${cr16},${Dsp-16-u16} */
   {
     M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst32RnUnprefixedSI,${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst32AnUnprefixedSI,${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc [$Dst32AnUnprefixed],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u8}[sb],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u16}[sb],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-s8}[fb],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-s16}[fb],${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u16},${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-16-u24},${cr2-32} */
   {
     M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
   {
     M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc $Dst16RnHI,${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc $Dst16AnHI,${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc [$Dst16An],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-u8}[sb],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-u16}[sb],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-s8}[fb],${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc ${Dsp-16-u16},${cr16} */
   {
     M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u24} */
   {
     M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u16} */
   {
     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a ${Dsp-16-u16} */
   {
     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a $Dst32RnUnprefixedSI */
   {
     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a $Dst32AnUnprefixedSI */
   {
     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a [$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.a $Dst16RnSI */
   {
     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a $Dst16AnSI */
   {
     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.a [$Dst16An] */
   {
     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u24} */
   {
     M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u16} */
   {
     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u16} */
   {
     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsri.w $Dst16RnHI */
   {
     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w $Dst16AnHI */
   {
     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsri.w [$Dst16An] */
   {
     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a $Dst32RnUnprefixedSI */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a $Dst32AnUnprefixedSI */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a [$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u16} */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a ${Dsp-16-u24} */
   {
     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.a $Dst16RnSI */
   {
     M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a $Dst16AnSI */
   {
     M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a [$Dst16An] */
   {
     M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.a ${Dsp-16-u16} */
   {
     M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u16} */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w ${Dsp-16-u24} */
   {
     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmpi.w $Dst16RnHI */
   {
     M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w $Dst16AnHI */
   {
     M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w [$Dst16An] */
   {
     M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmpi.w ${Dsp-16-u16} */
   {
     M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* indexws.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexws.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexwd.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexw.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexls.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexld.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexl.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbs.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexbd.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.w ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u16} */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* indexb.b ${Dsp-16-u24} */
   {
     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u16} */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dsp-16-u24} */
   {
     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u16} */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b ${Dsp-16-u24} */
   {
     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.b r0l */
   {
     M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* inc.b r0h */
   {
     M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* inc.b ${Dsp-8-u8}[sb] */
   {
     M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* inc.b ${Dsp-8-s8}[fb] */
   {
     M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* inc.b ${Dsp-8-u16} */
   {
     M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
   {
     M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
   {
     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
   {
     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
   {
     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l $Dst32RnPrefixedSI */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l $Dst32AnPrefixedSI */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l [$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u16} */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.l ${Dsp-24-u24} */
   {
     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l $Dst32RnPrefixedSI */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l $Dst32AnPrefixedSI */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l [$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u16} */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.l ${Dsp-24-u24} */
   {
     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l $Dst32RnPrefixedSI */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l $Dst32AnPrefixedSI */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l [$Dst32AnPrefixed] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u16} */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.l ${Dsp-24-u24} */
   {
     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w ${Dsp-16-u24} */
   {
     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b ${Dsp-16-u24} */
   {
     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w $Dst16RnHI */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w $Dst16AnHI */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w [$Dst16An] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b $Dst16RnQI */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b $Dst16AnQI */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b [$Dst16An] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w ${Dsp-16-u24} */
   {
     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b ${Dsp-16-u24} */
   {
     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w $Dst16RnHI */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w $Dst16AnHI */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w [$Dst16An] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b $Dst16RnQI */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b $Dst16AnQI */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b [$Dst16An] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w ${Dsp-16-u24} */
   {
     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.b ${Dsp-16-u24} */
   {
     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w $Dst16RnHI */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w $Dst16AnHI */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w [$Dst16An] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w ${Dsp-16-u16} */
   {
     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b $Dst16RnQI */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b $Dst16AnQI */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b [$Dst16An] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b ${Dsp-16-u16} */
   {
     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dec.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u16} */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dsp-16-u24} */
   {
     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u16} */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b ${Dsp-16-u24} */
   {
     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.b r0l */
   {
     M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dec.b r0h */
   {
     M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dec.b ${Dsp-8-u8}[sb] */
   {
     M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dec.b ${Dsp-8-s8}[fb] */
   {
     M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dec.b ${Dsp-8-u16} */
   {
     M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
   {
     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
   {
     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
   {
     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
   {
     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
   {
     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
   {
     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
   {
     M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
   {
     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
   {
     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
   {
     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
   {
     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
   {
     M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
   {
     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
   {
     M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
   {
     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
   {
     M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bxor${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} [$Bit16An] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bxor${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btsts${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} [$Bit16An] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btsts${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btstc${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} [$Bit16An] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btstc${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* btst${G} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${S} ${BitBase16-8-u11-S}[sb] */
   {
     M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} ${BitBase16-16-u16} */
   {
     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* btst${G} [$Bit16An] */
   {
     M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bset${G} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${S} ${BitBase16-8-u11-S}[sb] */
   {
     M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} ${BitBase16-16-u16} */
   {
     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bset${G} [$Bit16An] */
   {
     M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bor${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} [$Bit16An] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bor${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnxor${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} [$Bit16An] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnxor${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bntst${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} [$Bit16An] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bntst${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnot${G} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${S} ${BitBase16-8-u11-S}[sb] */
   {
     M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} ${BitBase16-16-u16} */
   {
     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnot${G} [$Bit16An] */
   {
     M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnor${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} [$Bit16An] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnor${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bnand${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} [$Bit16An] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bnand${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bm${cond16-24} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-24} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-24} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-24} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-32} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-32} ${BitBase16-16-u16} */
   {
     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm${cond16-16} [$Bit16An] */
   {
     M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bitindex.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u16} */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.w ${Dsp-16-u24} */
   {
     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u16} */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bitindex.b ${Dsp-16-u24} */
   {
     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u19-Unprefixed} */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${X} ${BitBase32-16-u27-Unprefixed} */
   {
     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* bclr${G} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${S} ${BitBase16-8-u11-S}[sb] */
   {
     M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} ${BitBase16-16-u16} */
   {
     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bclr${G} [$Bit16An] */
   {
     M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u19-Prefixed} */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} ${BitBase32-24-u27-Prefixed} */
   {
     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* band${X} $Bitno16R,$Bit16Rn */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} $Bitno16R,$Bit16An */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} [$Bit16An] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${Dsp-16-u8}[$Bit16An] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${Dsp-16-u16}[$Bit16An] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${BitBase16-16-u8}[sb] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${BitBase16-16-u16}[sb] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${BitBase16-16-s8}[fb] */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* band${X} ${BitBase16-16-u16} */
   {
     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
   {
     M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
   {
     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
   {
     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
   {
     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* and.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
   {
     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
   {
     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
   {
     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
   {
     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
   {
     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
   {
     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
   {
     M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
   {
     M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${S} #${Imm-8-HI},r0 */
   {
     M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
   {
     M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
   {
     M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
   {
     M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${S} #${Imm1-S},a0 */
   {
     M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${S} #${Imm1-S},a1 */
   {
     M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
   {
     M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
   {
     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
   {
     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
   {
     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
   {
     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
   {
     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16RnHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} $Src16AnHI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
   {
     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
   {
     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16RnQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} $Src16AnQI,${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} [$Src16An],${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} #${Imm-8-QI},r0l */
   {
     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} #${Imm-8-QI},r0h */
   {
     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
   {
     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
   {
     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
   {
     M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u16} */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w ${Dsp-16-u24} */
   {
     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u16} */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.b ${Dsp-16-u24} */
   {
     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* adcf.w $Dst16RnHI */
   {
     M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w $Dst16AnHI */
   {
     M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w [$Dst16An] */
   {
     M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.w ${Dsp-16-u16} */
   {
     M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b $Dst16RnQI */
   {
     M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b $Dst16AnQI */
   {
     M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b [$Dst16An] */
   {
     M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* adcf.b ${Dsp-16-u16} */
   {
     M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w $Dst32AnUnprefixedHI */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u16} */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w ${Dsp-16-u24} */
   {
     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b $Dst32RnUnprefixedQI */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b $Dst32AnUnprefixedQI */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b [$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-s16}[fb] */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u16} */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.b ${Dsp-16-u24} */
   {
     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* abs.w $Dst16RnHI */
   {
     M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w $Dst16AnHI */
   {
     M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w [$Dst16An] */
   {
     M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.w ${Dsp-16-u16} */
   {
     M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b $Dst16RnQI */
   {
     M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b $Dst16AnQI */
   {
     M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b [$Dst16An] */
   {
     M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-u8}[$Dst16An] */
   {
     M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-u16}[$Dst16An] */
   {
     M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-u8}[sb] */
   {
     M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-u16}[sb] */
   {
     M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-s8}[fb] */
   {
     M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* abs.b ${Dsp-16-u16} */
   {
     M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* add${size}$Q #${Imm-12-s4},sp */
+/* add.w$Q #${Imm-12-s4},sp */
   {
-    M32C_INSN_ADD16_Q_SP, "add16-Q-sp", "add", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.b$G #${Imm-16-QI},sp */
   {
     M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.w$G #${Imm-16-HI},sp */
   {
     M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* add.l$Q #${Imm3-S},sp */
   {
     M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l$S #${Imm-16-QI},sp */
   {
     M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* add.l$G #${Imm-16-HI},sp */
   {
     M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dadc.b #${Imm-16-QI} */
   {
     M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadc.w #${Imm-16-HI} */
   {
     M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadc.b r0h,r0l */
   {
     M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadc.w r1,r0 */
   {
     M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadd.b #${Imm-16-QI} */
   {
     M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadd.w #${Imm-16-HI} */
   {
     M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadd.b r0h,r0l */
   {
     M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dadd.w r1,r0 */
   {
     M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm$cond16c c */
   {
     M32C_INSN_BM16_C, "bm16-c", "bm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* bm$cond32 c */
   {
     M32C_INSN_BM32_C, "bm32-c", "bm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* brk */
   {
     M32C_INSN_BRK16, "brk16", "brk", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* brk */
   {
     M32C_INSN_BRK32, "brk32", "brk", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* brk2 */
   {
     M32C_INSN_BRK232, "brk232", "brk2", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dec.w ${Dst16An-S} */
   {
     M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b #${Imm-16-QI} */
   {
     M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.w #${Imm-16-HI} */
   {
     M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* div.b #${Imm-16-QI} */
   {
     M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* div.w #${Imm-16-HI} */
   {
     M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.b #${Imm-16-QI} */
   {
     M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.w #${Imm-16-HI} */
   {
     M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divu.b #${Imm-16-QI} */
   {
     M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divu.w #${Imm-16-HI} */
   {
     M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.b #${Imm-16-QI} */
   {
     M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.w #${Imm-16-HI} */
   {
     M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* divx.b #${Imm-16-QI} */
   {
     M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* divx.w #${Imm-16-HI} */
   {
     M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dsbb.b #${Imm-16-QI} */
   {
     M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsbb.w #${Imm-16-HI} */
   {
     M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsbb.b r0h,r0l */
   {
     M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsbb.w r1,r0 */
   {
     M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsub.b #${Imm-16-QI} */
   {
     M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsub.w #${Imm-16-HI} */
   {
     M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsub.b r0h,r0l */
   {
     M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* dsub.w r1,r0 */
   {
     M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* enter #${Dsp-16-u8} */
   {
     M32C_INSN_ENTER16, "enter16", "enter", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* exitd */
   {
     M32C_INSN_EXITD16, "exitd16", "exitd", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* enter #${Dsp-8-u8} */
   {
     M32C_INSN_ENTER32, "enter32", "enter", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exitd */
   {
     M32C_INSN_EXITD32, "exitd32", "exitd", 8,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* fclr ${flags16} */
   {
     M32C_INSN_FCLR16, "fclr16", "fclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* fset ${flags16} */
   {
     M32C_INSN_FSET16, "fset16", "fset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* fclr ${flags32} */
   {
     M32C_INSN_FCLR, "fclr", "fclr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* fset ${flags32} */
   {
     M32C_INSN_FSET, "fset", "fset", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* inc.w ${Dst16An-S} */
   {
     M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* freit */
   {
     M32C_INSN_FREIT32, "freit32", "freit", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* int #${Dsp-10-u6} */
   {
     M32C_INSN_INT16, "int16", "int", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* into */
   {
     M32C_INSN_INTO16, "into16", "into", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* int #${Dsp-8-u6} */
   {
     M32C_INSN_INT32, "int32", "int", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* into */
   {
     M32C_INSN_INTO32, "into32", "into", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* j$cond16j5 ${Lab-8-8} */
   {
     M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* j$cond16j ${Lab-16-8} */
   {
     M32C_INSN_JCND16, "jcnd16", "j", 24,
-    { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* j$cond32j ${Lab-8-8} */
   {
     M32C_INSN_JCND32, "jcnd32", "j", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmp.s ${Lab-5-3} */
   {
     M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmp.b ${Lab-8-8} */
   {
     M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmp.w ${Lab-8-16} */
   {
     M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmp.a ${Lab-8-24} */
   {
     M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmps #${Imm-8-QI} */
   {
     M32C_INSN_JMPS16, "jmps16", "jmps", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jmp.s ${Lab32-jmp-s} */
   {
     M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmp.b ${Lab-8-8} */
   {
     M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmp.w ${Lab-8-16} */
   {
     M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmp.a ${Lab-8-24} */
   {
     M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jmps #${Imm-8-QI} */
   {
     M32C_INSN_JMPS32, "jmps32", "jmps", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsr.w ${Lab-8-16} */
   {
     M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsr.a ${Lab-8-24} */
   {
     M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsr.w ${Lab-8-16} */
   {
     M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
-    { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsr.a ${Lab-8-24} */
   {
     M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* jsrs #${Imm-8-QI} */
   {
     M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* jsrs #${Imm-8-QI} */
   {
     M32C_INSN_JSRS, "jsrs", "jsrs", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc #${Imm-16-HI},${cr16} */
   {
     M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
   {
     M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc #${Dsp-16-u24},${cr2-32} */
   {
     M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
   {
     M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_STCTX16, "stctx16", "stctx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
   {
     M32C_INSN_STCTX32, "stctx32", "stctx", 56,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* ldipl #${Imm-13-u3} */
   {
     M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* ldipl #${Imm-13-u3} */
   {
     M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b$S #${Imm-8-QI},a0 */
   {
     M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b$S #${Imm-8-QI},a1 */
   {
     M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w$S #${Imm-8-HI},a0 */
   {
     M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w$S #${Imm-8-HI},a1 */
   {
     M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.w$S #${Imm-8-HI},a0 */
   {
     M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.w$S #${Imm-8-HI},a1 */
   {
     M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.l$S #${Dsp-8-u24},a0 */
+/* mov.l$S #${Dsp-8-s24},a0 */
   {
     M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* mov.l$S #${Dsp-8-u24},a1 */
+/* mov.l$S #${Dsp-8-s24},a1 */
   {
     M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* mov.b$S r0l,a1 */
   {
     M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* mov.b$S r0h,a0 */
   {
     M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* nop */
   {
     M32C_INSN_NOP16, "nop16", "nop", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* nop */
   {
     M32C_INSN_NOP32, "nop32", "nop", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* popc ${cr16} */
   {
     M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* popc ${cr1-Unprefixed-32} */
   {
     M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* popc ${cr2-32} */
   {
     M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pushc ${cr16} */
   {
     M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pushc ${cr1-Unprefixed-32} */
   {
     M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pushc ${cr2-32} */
   {
     M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* popm ${Regsetpop} */
   {
     M32C_INSN_POPM16, "popm16", "popm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* pushm ${Regsetpush} */
   {
     M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* popm ${Regsetpop} */
   {
     M32C_INSN_POPM, "popm", "popm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* pushm ${Regsetpush} */
   {
     M32C_INSN_PUSHM, "pushm", "pushm", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.b$G #${Imm-16-QI} */
   {
     M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* push.w$G #${Imm-16-HI} */
   {
     M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* push.b #Imm-8-QI */
   {
     M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.w #${Imm-8-HI} */
   {
     M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* push.l #${Imm-16-SI} */
   {
     M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* reit */
   {
     M32C_INSN_REIT16, "reit16", "reit", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* reit */
   {
     M32C_INSN_REIT32, "reit32", "reit", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rmpa.b */
   {
     M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rmpa.w */
   {
     M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rmpa.b */
   {
     M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rmpa.w */
   {
     M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* rts */
   {
     M32C_INSN_RTS16, "rts16", "rts", 8,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* rts */
   {
     M32C_INSN_RTS32, "rts32", "rts", 8,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* scmpu.b */
   {
     M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* scmpu.w */
   {
     M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sha.l #${Imm-sh-12-s4},r2r0 */
   {
     M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.l #${Imm-sh-12-s4},r3r1 */
   {
     M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.l r1h,r2r0 */
   {
     M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sha.l r1h,r3r1 */
   {
     M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.l #${Imm-sh-12-s4},r2r0 */
   {
     M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.l #${Imm-sh-12-s4},r3r1 */
   {
     M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.l r1h,r2r0 */
   {
     M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* shl.l r1h,r3r1 */
   {
     M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sin.b */
   {
     M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sin.w */
   {
     M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovb.b */
   {
     M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* smovb.w */
   {
     M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* smovb.b */
   {
     M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovb.w */
   {
     M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovf.b */
   {
     M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* smovf.w */
   {
     M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* smovf.b */
   {
     M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovf.w */
   {
     M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovu.b */
   {
     M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* smovu.w */
   {
     M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sout.b */
   {
     M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sout.w */
   {
     M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sstr.b */
   {
     M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sstr.w */
   {
     M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* sstr.b */
   {
     M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* sstr.w */
   {
     M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
   {
     M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
   {
     M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
+/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
+/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
+/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
   {
     M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* und */
   {
     M32C_INSN_UND16, "und16", "und", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* und */
   {
     M32C_INSN_UND32, "und32", "und", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* wait */
   {
     M32C_INSN_WAIT16, "wait16", "wait", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* wait */
   {
     M32C_INSN_WAIT, "wait", "wait", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* exts.w r0 */
   {
     M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
 /* src-indirect */
   {
     M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* dest-indirect */
   {
     M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 /* src-dest-indirect */
   {
     M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
 };
 
@@ -62388,7 +62786,7 @@ static void
 m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -62400,7 +62798,7 @@ m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
 
@@ -62485,7 +62883,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -62504,7 +62902,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -62535,9 +62933,6 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -62545,7 +62940,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/m32c-desc.h b/opcodes/m32c-desc.h
index ef275415933..3fa1db9e435 100644
--- a/opcodes/m32c-desc.h
+++ b/opcodes/m32c-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef M32C_CPU_H
 #define M32C_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH m32c
 
 /* Given symbol S, return m32c_cgen_<S>.  */
@@ -50,7 +52,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_INT_INSN_P 0
 
 /* Maximum number of syntax elements in an instruction.  */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 26
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 21
 
 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
@@ -92,6 +94,16 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for m32c ifield types.  */
 typedef enum ifield_type {
   M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2
@@ -122,18 +134,18 @@ typedef enum ifield_type {
  , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16
  , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16
  , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16
- , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_U24
- , M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24, M32C_F_DSP_40_U24
- , M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32
- , M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16
- , M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED, M32C_F_BITNO32_UNPREFIXED
- , M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED, M32C_F_BITBASE32_16_U19_UNPREFIXED
- , M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED, M32C_F_BITBASE32_24_S11_PREFIXED
- , M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED, M32C_F_LAB_5_3
- , M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16, M32C_F_LAB_8_24
- , M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8, M32C_F_LAB_40_8
- , M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32, M32C_F_COND32J
- , M32C_F_MAX
+ , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_S24
+ , M32C_F_DSP_8_U24, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24
+ , M32C_F_DSP_40_U24, M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32
+ , M32C_F_DSP_24_S32, M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32
+ , M32C_F_DSP_56_S16, M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED
+ , M32C_F_BITNO32_UNPREFIXED, M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED
+ , M32C_F_BITBASE32_16_U19_UNPREFIXED, M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED
+ , M32C_F_BITBASE32_24_S11_PREFIXED, M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED
+ , M32C_F_LAB_5_3, M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16
+ , M32C_F_LAB_8_24, M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8
+ , M32C_F_LAB_40_8, M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32
+ , M32C_F_COND32J, M32C_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) M32C_F_MAX)
@@ -150,6 +162,14 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for m32c hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -188,6 +208,18 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
 /* Enum declaration for m32c operand types.  */
 typedef enum cgen_operand_type {
   M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI
@@ -209,209 +241,210 @@ typedef enum cgen_operand_type {
  , M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB
  , M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP
  , M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6
- , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_U24
- , M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20
- , M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8
- , M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8
- , M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24
- , M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8
- , M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24
- , M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16
- , M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI
- , M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3
- , M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI
- , M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI
- , M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI
- , M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI
- , M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI
- , M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED
- , M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16
- , M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED
- , M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED
- , M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3
- , M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24
- , M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8
- , M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT
- , M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT
- , M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16
- , M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C
- , M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J
- , M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16
- , M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32
- , M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q
- , M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX
- , M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI
- , M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI
- , M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI
- , M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI
- , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI
- , M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI
- , M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI
- , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI
- , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI
- , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI
- , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI
- , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI
- , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI
- , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI
- , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI
- , M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI
- , M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI
- , M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI
- , M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI
- , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI
- , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI
- , M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI
- , M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI
- , M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI
- , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI
- , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI
- , M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI
- , M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI
- , M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI
- , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI
- , M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI
- , M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI
- , M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI
- , M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI
- , M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI
- , M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED
- , M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED
- , M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE
- , M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE
- , M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED
- , M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED
- , M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED
- , M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED
- , M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED
- , M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI
- , M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI
- , M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI
- , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI
- , M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI
- , M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI
- , M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI
- , M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI
- , M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI
- , M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI
- , M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI
- , M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI
- , M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI
- , M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI
- , M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI
- , M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI
- , M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI
- , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI
- , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI
- , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI
- , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI
- , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI
- , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI
- , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI
- , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC
- , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED
- , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED
- , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8
- , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI
- , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI
- , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S
- , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
+ , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24
+ , M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16
+ , M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16
+ , M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24
+ , M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16
+ , M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16
+ , M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16
+ , M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16
+ , M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N
+ , M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4
+ , M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4
+ , M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI
+ , M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI
+ , M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI
+ , M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI
+ , M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S
+ , M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED
+ , M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S
+ , M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED
+ , M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED
+ , M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S
+ , M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8
+ , M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT
+ , M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT
+ , M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16
+ , M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24
+ , M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J
+ , M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32
+ , M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32
+ , M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32
+ , M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G
+ , M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX
+ , M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI
+ , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI
+ , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI
+ , M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI
+ , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI
+ , M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI
+ , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI
+ , M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI
+ , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI
+ , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI
+ , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI
+ , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI
+ , M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI
+ , M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI
+ , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI
+ , M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI
+ , M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI
+ , M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI
+ , M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI
+ , M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI
+ , M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI
+ , M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI
+ , M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI
+ , M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI
+ , M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI
+ , M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI
+ , M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI
+ , M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI
+ , M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI
+ , M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI
+ , M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI
+ , M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI
+ , M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI
+ , M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI
+ , M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED
+ , M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT
+ , M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE
+ , M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED
+ , M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED
+ , M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED
+ , M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED
+ , M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED
+ , M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED
+ , M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI
+ , M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI
+ , M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI
+ , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI
+ , M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI
+ , M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI
+ , M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI
+ , M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI
+ , M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI
+ , M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI
+ , M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI
+ , M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI
+ , M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI
+ , M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI
+ , M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI
+ , M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI
+ , M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI
+ , M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI
+ , M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8
+ , M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED
+ , M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S
+ , M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16
+ , M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI
+ , M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI
+ , M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF
+ , M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 870
+#define MAX_OPERANDS 873
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 8
@@ -429,6 +462,20 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index 70dc85f2dfd..43f93e2b2b8 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -262,6 +262,19 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
   print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
 }
 
+static void
+print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		void * dis_info,
+		signed long value,
+		unsigned int attrs ATTRIBUTE_UNUSED,
+		bfd_vma pc ATTRIBUTE_UNUSED,
+		int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", -value);
+}
+
 void m32c_cgen_print_operand
   (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 
@@ -458,6 +471,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_DSP_48_U8 :
       print_normal (cd, info, fields->f_dsp_48_u8, 0, pc, length);
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
@@ -569,6 +585,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_12_S4 :
       print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
@@ -638,6 +657,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_8_S4 :
       print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
       break;
@@ -1168,7 +1190,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -1180,11 +1202,12 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -1207,25 +1230,34 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -1241,7 +1273,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -1254,7 +1286,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c
index f5c2dc32946..16f0048e3b0 100644
--- a/opcodes/m32c-ibld.c
+++ b/opcodes/m32c-ibld.c
@@ -1027,6 +1027,13 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_DSP_48_U8 :
       errmsg = insert_normal (cd, fields->f_dsp_48_u8, 0, 32, 16, 8, 32, total_length, buffer);
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      {
+        long value = fields->f_dsp_8_s24;
+        value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16))));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 24, 32, total_length, buffer);
+      }
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       errmsg = insert_normal (cd, fields->f_dsp_8_s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
       break;
@@ -1167,6 +1174,9 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_12_S4 :
       errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       errmsg = insert_normal (cd, fields->f_imm_13_u3, 0, 0, 13, 3, 32, total_length, buffer);
       break;
@@ -1354,6 +1364,9 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_8_S4 :
       errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
       break;
@@ -2135,6 +2148,14 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_DSP_48_U8 :
       length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 8, 32, total_length, pc, & fields->f_dsp_48_u8);
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 24, 32, total_length, pc, & value);
+        value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16))));
+        fields->f_dsp_8_s24 = value;
+      }
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_s8);
       break;
@@ -2283,6 +2304,9 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_12_S4 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_imm_13_u3);
       break;
@@ -2465,6 +2489,9 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
     case M32C_OPERAND_IMM_8_S4 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
       break;
@@ -2977,6 +3004,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_DSP_48_U8 :
       value = fields->f_dsp_48_u8;
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      value = fields->f_dsp_8_s24;
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       value = fields->f_dsp_8_s8;
       break;
@@ -3088,6 +3118,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_12_S4 :
       value = fields->f_imm_12_s4;
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      value = fields->f_imm_12_s4;
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       value = fields->f_imm_13_u3;
       break;
@@ -3157,6 +3190,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_8_S4 :
       value = fields->f_imm_8_s4;
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      value = fields->f_imm_8_s4;
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       value = fields->f_imm_12_s4;
       break;
@@ -3558,6 +3594,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_DSP_48_U8 :
       value = fields->f_dsp_48_u8;
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      value = fields->f_dsp_8_s24;
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       value = fields->f_dsp_8_s8;
       break;
@@ -3669,6 +3708,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_12_S4 :
       value = fields->f_imm_12_s4;
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      value = fields->f_imm_12_s4;
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       value = fields->f_imm_13_u3;
       break;
@@ -3738,6 +3780,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_8_S4 :
       value = fields->f_imm_8_s4;
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      value = fields->f_imm_8_s4;
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       value = fields->f_imm_12_s4;
       break;
@@ -4144,6 +4189,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_DSP_48_U8 :
       fields->f_dsp_48_u8 = value;
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      fields->f_dsp_8_s24 = value;
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       fields->f_dsp_8_s8 = value;
       break;
@@ -4252,6 +4300,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_12_S4 :
       fields->f_imm_12_s4 = value;
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      fields->f_imm_12_s4 = value;
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       fields->f_imm_13_u3 = value;
       break;
@@ -4321,6 +4372,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_8_S4 :
       fields->f_imm_8_s4 = value;
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      fields->f_imm_8_s4 = value;
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       fields->f_imm_12_s4 = value;
       break;
@@ -4703,6 +4757,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_DSP_48_U8 :
       fields->f_dsp_48_u8 = value;
       break;
+    case M32C_OPERAND_DSP_8_S24 :
+      fields->f_dsp_8_s24 = value;
+      break;
     case M32C_OPERAND_DSP_8_S8 :
       fields->f_dsp_8_s8 = value;
       break;
@@ -4811,6 +4868,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_12_S4 :
       fields->f_imm_12_s4 = value;
       break;
+    case M32C_OPERAND_IMM_12_S4N :
+      fields->f_imm_12_s4 = value;
+      break;
     case M32C_OPERAND_IMM_13_U3 :
       fields->f_imm_13_u3 = value;
       break;
@@ -4880,6 +4940,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case M32C_OPERAND_IMM_8_S4 :
       fields->f_imm_8_s4 = value;
       break;
+    case M32C_OPERAND_IMM_8_S4N :
+      fields->f_imm_8_s4 = value;
+      break;
     case M32C_OPERAND_IMM_SH_12_S4 :
       fields->f_imm_12_s4 = value;
       break;
diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c
index eeb7321f7d1..0913c2cb22b 100644
--- a/opcodes/m32c-opc.c
+++ b/opcodes/m32c-opc.c
@@ -44,6 +44,10 @@ m32c_asm_hash (const char *mnem)
   if (mnem[0] == 's' && mnem[1] == 'c')
     return 's';
   
+  /* Don't hash bmCND  */
+  if (mnem[0] == 'b' && mnem[1] == 'm')
+    return 'b';
+  
   for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
     h += *mnem;
   return h % CGEN_ASM_HASH_SIZE;
@@ -2825,39 +2829,39 @@ static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED
   32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
   16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
   16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
   16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
   24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
   32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
   24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
   32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
   24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
   32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
 };
 
@@ -5621,6 +5625,26 @@ static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED =
   8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
+  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
+  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = {
+  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = {
+  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
   16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
@@ -5714,171 +5738,171 @@ static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_S
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
+  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
-  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
+  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = {
@@ -5917,7 +5941,7 @@ static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI AT
   24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
   8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
 };
 
@@ -6529,26 +6553,6 @@ static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUS
   24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
-  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
-  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = {
-  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = {
-  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = {
-  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } }
-};
-
 static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
   16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
 };
@@ -6729,75 +6733,75 @@ static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_
   32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
-  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
+  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
+  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
-  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
+  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
-  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
-  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
-  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
+  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
+  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
-  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
+  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
-  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
-  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
+static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
   32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
 };
 
@@ -7441,6 +7445,174 @@ static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTR
   24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
+  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
+  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = {
   8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
 };
@@ -7497,7 +7669,7 @@ static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Un
   32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_add16_Q_sp ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = {
   16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
 };
 
@@ -7638,7 +7810,7 @@ static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = {
 };
 
 static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = {
-  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U24) }, { 0 } }
+  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S24) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = {
@@ -7677,6 +7849,10 @@ static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = {
   32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8fb ATTRIBUTE_UNUSED = {
+  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
+};
+
 static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = {
   32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } }
 };
@@ -13458,275 +13634,275 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
     & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 }
   },
-/* xchg.w r0,$Dst16RnQI */
+/* xchg.w r0,$Dst16RnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '0', ',', OP (DST16RNQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7b00 }
+    { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } },
+    & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 }
   },
-/* xchg.w r0,$Dst16AnQI */
+/* xchg.w r0,$Dst16AnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '0', ',', OP (DST16ANQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7b04 }
+    { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } },
+    & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 }
   },
 /* xchg.w r0,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7b06 }
+    & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 }
   },
 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7b0800 }
+    & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 }
   },
 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7b0c0000 }
+    & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 }
   },
 /* xchg.w r0,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7b0a00 }
+    & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 }
   },
 /* xchg.w r0,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7b0e0000 }
+    & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 }
   },
 /* xchg.w r0,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7b0b00 }
+    & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 }
   },
 /* xchg.w r0,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7b0f0000 }
+    & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 }
   },
 /* xchg.b r1h,$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a30 }
+    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 }
   },
 /* xchg.b r1h,$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a34 }
+    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 }
   },
 /* xchg.b r1h,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a36 }
+    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 }
   },
 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a3800 }
+    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 }
   },
 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a3c0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 }
   },
 /* xchg.b r1h,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a3a00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 }
   },
 /* xchg.b r1h,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a3e0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 }
   },
 /* xchg.b r1h,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a3b00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 }
   },
 /* xchg.b r1h,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a3f0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 }
   },
 /* xchg.b r1l,$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a20 }
+    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 }
   },
 /* xchg.b r1l,$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a24 }
+    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 }
   },
 /* xchg.b r1l,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a26 }
+    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 }
   },
 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a2800 }
+    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 }
   },
 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a2c0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 }
   },
 /* xchg.b r1l,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a2a00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 }
   },
 /* xchg.b r1l,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a2e0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 }
   },
 /* xchg.b r1l,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a2b00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 }
   },
 /* xchg.b r1l,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a2f0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 }
   },
 /* xchg.b r0h,$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a10 }
+    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 }
   },
 /* xchg.b r0h,$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a14 }
+    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 }
   },
 /* xchg.b r0h,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a16 }
+    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 }
   },
 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a1800 }
+    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 }
   },
 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a1c0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 }
   },
 /* xchg.b r0h,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a1a00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 }
   },
 /* xchg.b r0h,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a1e0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 }
   },
 /* xchg.b r0h,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a1b00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 }
   },
 /* xchg.b r0h,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a1f0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 }
   },
 /* xchg.b r0l,$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a00 }
+    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 }
   },
 /* xchg.b r0l,$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
-    & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a04 }
+    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 }
   },
 /* xchg.b r0l,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a06 }
+    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 }
   },
 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a0800 }
+    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 }
   },
 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a0c0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 }
   },
 /* xchg.b r0l,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a0a00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 }
   },
 /* xchg.b r0l,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a0e0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 }
   },
 /* xchg.b r0l,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a0b00 }
+    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 }
   },
 /* xchg.b r0l,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a0f0000 }
+    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 }
   },
 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
   {
@@ -13776,1732 +13952,1732 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
     & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 }
   },
-/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 }
   },
-/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
+/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 }
   },
-/* tst.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 }
   },
-/* tst.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 }
   },
-/* tst.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 }
   },
-/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 }
   },
-/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 }
   },
-/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
+/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 }
   },
-/* tst.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 }
   },
-/* tst.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
+/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 }
   },
-/* tst.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 }
   },
-/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
+/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 }
   },
-/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
+/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
     & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
+/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
+/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 }
   },
-/* tst.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
+/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
+/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
+/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 }
   },
-/* tst.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
+/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 }
   },
-/* tst.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 }
   },
-/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
+/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 }
   },
-/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
+/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 }
   },
-/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
+/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 }
   },
-/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 }
   },
-/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
+/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
     & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 }
   },
-/* tst.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 }
   },
-/* tst.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 }
   },
-/* tst.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 }
   },
-/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 }
   },
-/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 }
   },
-/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
+/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
     & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 }
   },
-/* tst.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 }
   },
-/* tst.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
+/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 }
   },
-/* tst.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 }
   },
-/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
+/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 }
   },
-/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
+/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
     & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
+/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
+/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 }
   },
-/* tst.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
+/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
+/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
+/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 }
   },
-/* tst.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
+/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 }
   },
-/* tst.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 }
   },
-/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
+/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 }
   },
-/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
+/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 }
   },
-/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
+/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
     & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 }
   },
 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
@@ -16476,256 +16652,256 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
+/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
     & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
+/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
     & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 }
   },
-/* tst.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 }
   },
-/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 }
   },
-/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24} */
+/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
     & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
+/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
     & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
+/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
     & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 }
   },
-/* tst.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 }
   },
-/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 }
   },
-/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24} */
+/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
     & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst16RnHI */
+/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
     & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 }
   },
-/* tst.w${X} #${Imm-16-HI},$Dst16AnHI */
+/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
     & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 }
   },
-/* tst.w${X} #${Imm-16-HI},[$Dst16An] */
+/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 }
   },
-/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
+/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 }
   },
-/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
+/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst16RnQI */
+/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
     & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 }
   },
-/* tst.b${X} #${Imm-16-QI},$Dst16AnQI */
+/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
     & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 }
   },
-/* tst.b${X} #${Imm-16-QI},[$Dst16An] */
+/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 }
   },
-/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
+/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 }
   },
-/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
+/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 }
   },
 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
@@ -19668,256 +19844,256 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } },
     & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
   },
-/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
+/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
     & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
   },
-/* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
   },
-/* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
   },
-/* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
+/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
   },
-/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
+/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
     & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
   },
-/* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
   },
-/* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
   },
-/* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
+/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
   },
-/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
   },
-/* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
   },
-/* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
   },
-/* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
+/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
   },
-/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
+/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
     & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
   },
-/* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
   },
-/* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
   },
-/* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
+/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
     & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
   },
 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
@@ -22872,149 +23048,149 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 }
   },
-/* rot.w r1h,$Dst32RnUnprefixedSI */
+/* rot.w r1h,$Dst32RnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
-    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa93f }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f }
   },
-/* rot.w r1h,$Dst32AnUnprefixedSI */
+/* rot.w r1h,$Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
-    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa1bf }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf }
   },
 /* rot.w r1h,[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa13f }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f }
   },
 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa33f00 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 }
   },
 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa53f0000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 }
   },
 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa73f0000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 }
   },
 /* rot.w r1h,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa3bf00 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 }
   },
 /* rot.w r1h,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa5bf0000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 }
   },
 /* rot.w r1h,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa3ff00 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 }
   },
 /* rot.w r1h,${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa5ff0000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 }
   },
 /* rot.w r1h,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa7ff0000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 }
   },
 /* rot.w r1h,${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa7bf0000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 }
   },
-/* rot.b r1h,$Dst32RnUnprefixedSI */
+/* rot.b r1h,$Dst32RnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
-    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa83f }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
+    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f }
   },
-/* rot.b r1h,$Dst32AnUnprefixedSI */
+/* rot.b r1h,$Dst32AnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
-    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0bf }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
+    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf }
   },
 /* rot.b r1h,[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa03f }
+    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f }
   },
 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa23f00 }
+    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 }
   },
 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa43f0000 }
+    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 }
   },
 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa63f0000 }
+    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 }
   },
 /* rot.b r1h,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2bf00 }
+    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 }
   },
 /* rot.b r1h,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4bf0000 }
+    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 }
   },
 /* rot.b r1h,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2ff00 }
+    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 }
   },
 /* rot.b r1h,${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4ff0000 }
+    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 }
   },
 /* rot.b r1h,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6ff0000 }
+    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 }
   },
 /* rot.b r1h,${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6bf0000 }
+    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 }
   },
 /* rot.w r1h,$Dst16RnHI */
   {
@@ -23070,59 +23246,59 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
     & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 }
   },
-/* rot.b r1h,$Dst16RnHI */
+/* rot.b r1h,$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
-    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7460 }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
+    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 }
   },
-/* rot.b r1h,$Dst16AnHI */
+/* rot.b r1h,$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
-    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7464 }
+    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
+    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 }
   },
 /* rot.b r1h,[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7466 }
+    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 }
   },
 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x746800 }
+    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 }
   },
 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x746c0000 }
+    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 }
   },
 /* rot.b r1h,${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x746a00 }
+    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 }
   },
 /* rot.b r1h,${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x746e0000 }
+    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 }
   },
 /* rot.b r1h,${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x746b00 }
+    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 }
   },
 /* rot.b r1h,${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
-    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x746f0000 }
+    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 }
   },
 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
   {
@@ -24210,112 +24386,112 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
     & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 }
   },
-/* push.w $Dst16RnHI */
+/* push.w${G} $Dst16RnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
     & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 }
   },
-/* push.w $Dst16AnHI */
+/* push.w${G} $Dst16AnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
     & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 }
   },
-/* push.w [$Dst16An] */
+/* push.w${G} [$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 }
   },
-/* push.w ${Dsp-16-u8}[$Dst16An] */
+/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 }
   },
-/* push.w ${Dsp-16-u16}[$Dst16An] */
+/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 }
   },
-/* push.w ${Dsp-16-u8}[sb] */
+/* push.w${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 }
   },
-/* push.w ${Dsp-16-u16}[sb] */
+/* push.w${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 }
   },
-/* push.w ${Dsp-16-s8}[fb] */
+/* push.w${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 }
   },
-/* push.w ${Dsp-16-u16} */
+/* push.w${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 }
   },
-/* push.b $Dst16RnQI */
+/* push.b${G} $Dst16RnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
     & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 }
   },
-/* push.b $Dst16AnQI */
+/* push.b${G} $Dst16AnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
     & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 }
   },
-/* push.b [$Dst16An] */
+/* push.b${G} [$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 }
   },
-/* push.b ${Dsp-16-u8}[$Dst16An] */
+/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 }
   },
-/* push.b ${Dsp-16-u16}[$Dst16An] */
+/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 }
   },
-/* push.b ${Dsp-16-u8}[sb] */
+/* push.b${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 }
   },
-/* push.b ${Dsp-16-u16}[sb] */
+/* push.b${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 }
   },
-/* push.b ${Dsp-16-s8}[fb] */
+/* push.b${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 }
   },
-/* push.b ${Dsp-16-u16} */
+/* push.b${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 }
   },
 /* pop.w${S} ${An16-push-S} */
@@ -27612,256 +27788,286 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 }
   },
-/* not.w $Dst32RnUnprefixedHI */
+/* not.b:s r0l */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
+    { { MNEM, ' ', 'r', '0', 'l', 0 } },
+    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xbc }
+  },
+/* not.b:s r0h */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', 'r', '0', 'h', 0 } },
+    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xbb }
+  },
+/* not.b:s ${Dsp-8-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xbd00 }
+  },
+/* not.b:s ${Dsp-8-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xbe00 }
+  },
+/* not.b:s ${Dsp-8-u16} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_8_U16), 0 } },
+    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xbf0000 }
+  },
+/* not.w${G} $Dst32RnUnprefixedHI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
     & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e }
   },
-/* not.w $Dst32AnUnprefixedHI */
+/* not.w${G} $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
     & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e }
   },
-/* not.w [$Dst32AnUnprefixed] */
+/* not.w${G} [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e }
   },
-/* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 }
   },
-/* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 }
   },
-/* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 }
   },
-/* not.w ${Dsp-16-u8}[sb] */
+/* not.w${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 }
   },
-/* not.w ${Dsp-16-u16}[sb] */
+/* not.w${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 }
   },
-/* not.w ${Dsp-16-s8}[fb] */
+/* not.w${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 }
   },
-/* not.w ${Dsp-16-s16}[fb] */
+/* not.w${G} ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 }
   },
-/* not.w ${Dsp-16-u16} */
+/* not.w${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 }
   },
-/* not.w ${Dsp-16-u24} */
+/* not.w${G} ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
     & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 }
   },
-/* not.b $Dst32RnUnprefixedQI */
+/* not.b${G} $Dst32RnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
     & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e }
   },
-/* not.b $Dst32AnUnprefixedQI */
+/* not.b${G} $Dst32AnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
     & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e }
   },
-/* not.b [$Dst32AnUnprefixed] */
+/* not.b${G} [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e }
   },
-/* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 }
   },
-/* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 }
   },
-/* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 }
   },
-/* not.b ${Dsp-16-u8}[sb] */
+/* not.b${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 }
   },
-/* not.b ${Dsp-16-u16}[sb] */
+/* not.b${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 }
   },
-/* not.b ${Dsp-16-s8}[fb] */
+/* not.b${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 }
   },
-/* not.b ${Dsp-16-s16}[fb] */
+/* not.b${G} ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 }
   },
-/* not.b ${Dsp-16-u16} */
+/* not.b${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 }
   },
-/* not.b ${Dsp-16-u24} */
+/* not.b${G} ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
     & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 }
   },
-/* not.w $Dst16RnHI */
+/* not.w${G} $Dst16RnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
     & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 }
   },
-/* not.w $Dst16AnHI */
+/* not.w${G} $Dst16AnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
     & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 }
   },
-/* not.w [$Dst16An] */
+/* not.w${G} [$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 }
   },
-/* not.w ${Dsp-16-u8}[$Dst16An] */
+/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 }
   },
-/* not.w ${Dsp-16-u16}[$Dst16An] */
+/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 }
   },
-/* not.w ${Dsp-16-u8}[sb] */
+/* not.w${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 }
   },
-/* not.w ${Dsp-16-u16}[sb] */
+/* not.w${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 }
   },
-/* not.w ${Dsp-16-s8}[fb] */
+/* not.w${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 }
   },
-/* not.w ${Dsp-16-u16} */
+/* not.w${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 }
   },
-/* not.b $Dst16RnQI */
+/* not.b${G} $Dst16RnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
     & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 }
   },
-/* not.b $Dst16AnQI */
+/* not.b${G} $Dst16AnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
     & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 }
   },
-/* not.b [$Dst16An] */
+/* not.b${G} [$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 }
   },
-/* not.b ${Dsp-16-u8}[$Dst16An] */
+/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 }
   },
-/* not.b ${Dsp-16-u16}[$Dst16An] */
+/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 }
   },
-/* not.b ${Dsp-16-u8}[sb] */
+/* not.b${G} ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 }
   },
-/* not.b ${Dsp-16-u16}[sb] */
+/* not.b${G} ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 }
   },
-/* not.b ${Dsp-16-s8}[fb] */
+/* not.b${G} ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 }
   },
-/* not.b ${Dsp-16-u16} */
+/* not.b${G} ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 }
   },
 /* neg.w $Dst32RnUnprefixedHI */
@@ -35664,508 +35870,508 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } },
     & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 }
   },
-/* mov.w ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 }
   },
-/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 }
   },
-/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 }
   },
-/* mov.w ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 }
   },
-/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 }
   },
-/* mov.w ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 }
   },
-/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 }
   },
-/* mov.w ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 }
   },
-/* mov.w ${Dsp-16-u24},${Dsp-40-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 }
   },
-/* mov.w $Dst32RnUnprefixedHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 }
   },
-/* mov.w $Dst32AnUnprefixedHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 }
   },
-/* mov.w [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
+/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 }
   },
-/* mov.b ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 }
   },
-/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 }
   },
-/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 }
   },
-/* mov.b ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 }
   },
-/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 }
   },
-/* mov.b ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 }
   },
-/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 }
   },
-/* mov.b ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 }
   },
-/* mov.b ${Dsp-16-u24},${Dsp-40-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 }
   },
-/* mov.b $Dst32RnUnprefixedQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 }
   },
-/* mov.b $Dst32AnUnprefixedQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 }
   },
-/* mov.b [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
+/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 }
   },
-/* mov.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 }
   },
-/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 }
   },
-/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 }
   },
-/* mov.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 }
   },
-/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 }
   },
-/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 }
   },
-/* mov.w $Dst16RnHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 }
   },
-/* mov.w $Dst16AnHI,${Dsp-16-u8}[sp] */
+/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 }
   },
-/* mov.w [$Dst16An],${Dsp-16-u8}[sp] */
+/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 }
   },
-/* mov.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 }
   },
-/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 }
   },
-/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
+/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 }
   },
-/* mov.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 }
   },
-/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 }
   },
-/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
+/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 }
   },
-/* mov.b $Dst16RnQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16RNQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 }
   },
-/* mov.b $Dst16AnQI,${Dsp-16-u8}[sp] */
+/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DST16ANQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 }
   },
-/* mov.b [$Dst16An],${Dsp-16-u8}[sp] */
+/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } },
+    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
     & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 }
   },
-/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 }
   },
-/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24} */
+/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
     & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst32RnUnprefixedHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst32AnUnprefixedHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 }
   },
-/* mov.w ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
+/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
     & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 }
   },
-/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 }
   },
-/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24} */
+/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
     & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst32RnUnprefixedQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst32AnUnprefixedQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 }
   },
-/* mov.b ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
+/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
     & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 }
   },
-/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 }
   },
-/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
     & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst16RnHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 }
   },
-/* mov.w ${Dsp-16-u8}[sp],$Dst16AnHI */
+/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 }
   },
-/* mov.w ${Dsp-16-u8}[sp],[$Dst16An] */
+/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 }
   },
-/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
+/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 }
   },
-/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
+/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
     & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst16RnQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 }
   },
-/* mov.b ${Dsp-16-u8}[sp],$Dst16AnQI */
+/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 }
   },
-/* mov.b ${Dsp-16-u8}[sp],[$Dst16An] */
+/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
     & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 }
   },
 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
@@ -36276,11 +36482,11 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } },
     & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 }
   },
-/* mov.w${S} r0,r1l */
+/* mov.w${S} r0,r1 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 'l', 0 } },
-    & ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI, { 0x4f }
+    { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 0 } },
+    & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x4f }
   },
 /* mov.b${S} r0l,r1l */
   {
@@ -39970,7 +40176,7 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } },
-    & ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI, { 0x3 }
+    & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x3 }
   },
 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
   {
@@ -40000,31 +40206,31 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xb4 }
+    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xb4 }
   },
 /* mov.b${Z} #0,r0h */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xb3 }
+    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xb3 }
   },
 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xb500 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xb500 }
   },
 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xb600 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xb600 }
   },
 /* mov.b${Z} #0,${Dsp-8-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
+    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
   },
 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
   {
@@ -44424,221 +44630,653 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
     & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 }
   },
-/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75080000 }
+    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 }
   },
-/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x750a0000 }
+    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 }
   },
-/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+/* ste.w ${Dsp-16-u16},[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x750b0000 }
+    { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 }
+  },
+/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 }
+  },
+/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 }
+  },
+/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 }
   },
 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x750c0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 }
   },
 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x750e0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 }
   },
 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x750f0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 }
+  },
+/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 }
+  },
+/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 }
+  },
+/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 }
+  },
+/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 }
+  },
+/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 }
+  },
+/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 }
+  },
+/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 }
+  },
+/* ste.w $Dst16RnHI,[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 }
+  },
+/* ste.w $Dst16AnHI,[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 }
+  },
+/* ste.w [$Dst16An],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 }
+  },
+/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 }
+  },
+/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 }
+  },
+/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 }
   },
 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75000000 }
+    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 }
   },
 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75040000 }
+    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 }
   },
 /* ste.w [$Dst16An],${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75060000 }
+    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 }
   },
-/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74080000 }
+    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 }
   },
-/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x740a0000 }
+    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 }
   },
-/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+/* ste.b ${Dsp-16-u16},[a1a0] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x740b0000 }
+    { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 }
+  },
+/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 }
+  },
+/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 }
+  },
+/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 }
   },
 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x740c0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 }
   },
 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x740e0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 }
   },
 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x740f0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 }
+  },
+/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 }
+  },
+/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 }
+  },
+/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 }
+  },
+/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 }
+  },
+/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 }
+  },
+/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 }
+  },
+/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 }
+  },
+/* ste.b $Dst16RnQI,[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 }
+  },
+/* ste.b $Dst16AnQI,[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 }
+  },
+/* ste.b [$Dst16An],[a1a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 }
+  },
+/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 }
+  },
+/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 }
+  },
+/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 }
   },
 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74000000 }
+    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 }
   },
 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74040000 }
+    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 }
   },
 /* ste.b [$Dst16An],${Dsp-16-u20} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74060000 }
+    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75880000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+/* lde.w [a1a0],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x758a0000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 }
   },
-/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+/* lde.w [a1a0],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x758b0000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
+    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 }
+  },
+/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x758c0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x758e0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 }
   },
 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
-    & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x758f0000 }
+    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 }
+  },
+/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 }
+  },
+/* lde.w [a1a0],${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 }
+  },
+/* lde.w [a1a0],${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 }
+  },
+/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 }
+  },
+/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 }
+  },
+/* lde.w [a1a0],$Dst16RnHI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
+    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 }
+  },
+/* lde.w [a1a0],$Dst16AnHI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
+    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 }
+  },
+/* lde.w [a1a0],[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 }
+  },
+/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 }
+  },
+/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 }
+  },
+/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 }
   },
 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75800000 }
+    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 }
   },
 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75840000 }
+    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 }
   },
 /* lde.w ${Dsp-16-u20},[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75860000 }
+    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74880000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+/* lde.b [a1a0],${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x748a0000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 }
   },
-/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+/* lde.b [a1a0],${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x748b0000 }
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
+    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 }
+  },
+/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x748c0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x748e0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 }
   },
 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
-    & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x748f0000 }
+    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 }
+  },
+/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 }
+  },
+/* lde.b [a1a0],${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 }
+  },
+/* lde.b [a1a0],${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 }
+  },
+/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 }
+  },
+/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 }
+  },
+/* lde.b [a1a0],$Dst16RnQI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
+    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 }
+  },
+/* lde.b [a1a0],$Dst16AnQI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
+    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 }
+  },
+/* lde.b [a1a0],[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 }
+  },
+/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 }
+  },
+/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 }
+  },
+/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
+    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 }
   },
 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74800000 }
+    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 }
   },
 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74840000 }
+    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 }
   },
 /* lde.b ${Dsp-16-u20},[$Dst16An] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
-    & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74860000 }
+    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 }
   },
 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
   {
@@ -45742,73 +46380,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc933 }
   },
 /* indexws.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1b3 }
   },
 /* indexws.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc133 }
   },
 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33300 }
   },
 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5330000 }
   },
 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7330000 }
   },
 /* indexws.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3b300 }
   },
 /* indexws.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5b30000 }
   },
 /* indexws.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3f300 }
   },
 /* indexws.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5f30000 }
   },
 /* indexws.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7f30000 }
   },
 /* indexws.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7b30000 }
   },
 /* indexws.b $Dst32RnUnprefixedQI */
   {
@@ -45886,73 +46524,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa933 }
   },
 /* indexwd.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1b3 }
   },
 /* indexwd.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa133 }
   },
 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33300 }
   },
 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5330000 }
   },
 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7330000 }
   },
 /* indexwd.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3b300 }
   },
 /* indexwd.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5b30000 }
   },
 /* indexwd.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3f300 }
   },
 /* indexwd.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5f30000 }
   },
 /* indexwd.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7f30000 }
   },
 /* indexwd.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7b30000 }
   },
 /* indexwd.b $Dst32RnUnprefixedQI */
   {
@@ -46030,73 +46668,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8933 }
   },
 /* indexw.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x81b3 }
   },
 /* indexw.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8133 }
   },
 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x833300 }
   },
 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85330000 }
   },
 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87330000 }
   },
 /* indexw.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83b300 }
   },
 /* indexw.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85b30000 }
   },
 /* indexw.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83f300 }
   },
 /* indexw.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85f30000 }
   },
 /* indexw.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87f30000 }
   },
 /* indexw.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87b30000 }
   },
 /* indexw.b $Dst32RnUnprefixedQI */
   {
@@ -46174,73 +46812,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9913 }
   },
 /* indexls.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9193 }
   },
 /* indexls.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9113 }
   },
 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931300 }
   },
 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95130000 }
   },
 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97130000 }
   },
 /* indexls.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939300 }
   },
 /* indexls.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95930000 }
   },
 /* indexls.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93d300 }
   },
 /* indexls.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95d30000 }
   },
 /* indexls.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97d30000 }
   },
 /* indexls.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97930000 }
   },
 /* indexls.b $Dst32RnUnprefixedQI */
   {
@@ -46318,73 +46956,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb933 }
   },
 /* indexld.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1b3 }
   },
 /* indexld.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb133 }
   },
 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33300 }
   },
 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb5330000 }
   },
 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb7330000 }
   },
 /* indexld.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3b300 }
   },
 /* indexld.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5b30000 }
   },
 /* indexld.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3f300 }
   },
 /* indexld.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5f30000 }
   },
 /* indexld.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7f30000 }
   },
 /* indexld.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7b30000 }
   },
 /* indexld.b $Dst32RnUnprefixedQI */
   {
@@ -46462,73 +47100,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9933 }
   },
 /* indexl.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x91b3 }
   },
 /* indexl.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9133 }
   },
 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x933300 }
   },
 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x95330000 }
   },
 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x97330000 }
   },
 /* indexl.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93b300 }
   },
 /* indexl.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95b30000 }
   },
 /* indexl.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93f300 }
   },
 /* indexl.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95f30000 }
   },
 /* indexl.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97f30000 }
   },
 /* indexl.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x97b30000 }
   },
 /* indexl.b $Dst32RnUnprefixedQI */
   {
@@ -46606,73 +47244,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc913 }
   },
 /* indexbs.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc193 }
   },
 /* indexbs.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc113 }
   },
 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31300 }
   },
 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5130000 }
   },
 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7130000 }
   },
 /* indexbs.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39300 }
   },
 /* indexbs.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5930000 }
   },
 /* indexbs.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3d300 }
   },
 /* indexbs.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5d30000 }
   },
 /* indexbs.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7d30000 }
   },
 /* indexbs.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7930000 }
   },
 /* indexbs.b $Dst32RnUnprefixedQI */
   {
@@ -46750,73 +47388,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa913 }
   },
 /* indexbd.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa193 }
   },
 /* indexbd.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa113 }
   },
 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31300 }
   },
 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa5130000 }
   },
 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa7130000 }
   },
 /* indexbd.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39300 }
   },
 /* indexbd.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5930000 }
   },
 /* indexbd.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3d300 }
   },
 /* indexbd.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5d30000 }
   },
 /* indexbd.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7d30000 }
   },
 /* indexbd.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7930000 }
   },
 /* indexbd.b $Dst32RnUnprefixedQI */
   {
@@ -46894,73 +47532,73 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
-    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 }
+    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8913 }
   },
 /* indexb.w $Dst32AnUnprefixedHI */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
-    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 }
+    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8193 }
   },
 /* indexb.w [$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 }
+    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8113 }
   },
 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 }
+    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831300 }
   },
 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 }
+    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x85130000 }
   },
 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 }
+    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x87130000 }
   },
 /* indexb.w ${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 }
+    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839300 }
   },
 /* indexb.w ${Dsp-16-u16}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 }
+    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85930000 }
   },
 /* indexb.w ${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 }
+    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83d300 }
   },
 /* indexb.w ${Dsp-16-s16}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85d30000 }
   },
 /* indexb.w ${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 }
+    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87d30000 }
   },
 /* indexb.w ${Dsp-16-u24} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_16_U24), 0 } },
-    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 }
+    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x87930000 }
   },
 /* indexb.b $Dst32RnUnprefixedQI */
   {
@@ -47182,31 +47820,31 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xa4 }
+    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xa4 }
   },
 /* inc.b r0h */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xa3 }
+    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xa3 }
   },
 /* inc.b ${Dsp-8-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xa500 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xa500 }
   },
 /* inc.b ${Dsp-8-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xa600 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xa600 }
   },
 /* inc.b ${Dsp-8-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_U16), 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xa70000 }
+    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xa70000 }
   },
 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
@@ -56062,31 +56700,31 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'l', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xac }
+    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xac }
   },
 /* dec.b r0h */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', 'r', '0', 'h', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xab }
+    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xab }
   },
 /* dec.b ${Dsp-8-u8}[sb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xad00 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xad00 }
   },
 /* dec.b ${Dsp-8-s8}[fb] */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xae00 }
+    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xae00 }
   },
 /* dec.b ${Dsp-8-u16} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (DSP_8_U16), 0 } },
-    & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xaf0000 }
+    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xaf0000 }
   },
 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
   {
@@ -65572,253 +66210,253 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
+    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
+    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
+    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
+    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
+    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
+    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
+    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
+    & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
   },
 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
+    & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
   },
 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
+    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
   },
 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
+    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
   },
 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
+    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
+    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
+    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
+    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
+    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
+    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
+    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
+    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
+    & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
   },
 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
+    & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
   },
 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
+    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
   },
 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
+    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
   },
 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
+    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
+    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
+    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
+    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
+    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
+    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
   },
 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
+    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
   },
 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
+    & ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
   },
 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
+    & ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
   },
 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
+    & ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
+    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
+    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
+    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
+    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
+    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
   },
 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
+    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
   },
 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
+    & ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
   },
 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
+    & ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
   },
 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
-    & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
+    & ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
   },
 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
   {
@@ -78282,11 +78920,11 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSP_16_U16), 0 } },
     & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 }
   },
-/* add${size}$Q #${Imm-12-s4},sp */
+/* add.w$Q #${Imm-12-s4},sp */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (SIZE), OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
-    & ifmt_add16_Q_sp, { 0x7db0 }
+    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
+    & ifmt_add16_wQ_sp, { 0x7db0 }
   },
 /* add.b$G #${Imm-16-QI},sp */
   {
@@ -78816,16 +79454,16 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
     & ifmt_mov16_w_S_imm_a0, { 0x9d0000 }
   },
-/* mov.l$S #${Dsp-8-u24},a0 */
+/* mov.l$S #${Dsp-8-s24},a0 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '0', 0 } },
+    { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '0', 0 } },
     & ifmt_mov32_l_a0, { 0xbc000000 }
   },
-/* mov.l$S #${Dsp-8-u24},a1 */
+/* mov.l$S #${Dsp-8-s24},a1 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '1', 0 } },
+    { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '1', 0 } },
     & ifmt_mov32_l_a0, { 0xbd000000 }
   },
 /* mov.b$S r0l,a1 */
@@ -79170,22 +79808,22 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
     & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
+/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 's', 'b', ']', 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
     & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
+/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 'f', 'b', ']', 0 } },
-    & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xde000000 }
+    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+    & ifmt_stzx16_imm8_imm8_dsp8fb, { 0xde000000 }
   },
-/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
+/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '1', '6', 0 } },
+    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
     & ifmt_stzx16_imm8_imm8_abs16, { 0xde000000 }
   },
 /* und */
@@ -79250,6 +79888,10 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
 #else
 #define F(f) & m32c_cgen_ifld_table[M32C_/**/f]
 #endif
+static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = {
+  16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
+};
+
 #undef F
 
 /* Each non-simple macro entry points to an array of expansion possibilities.  */
@@ -79271,12 +79913,23 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
 
 static const CGEN_IBASE m32c_cgen_macro_insn_table[] =
 {
+/* add.b:q #${Imm-12-s4},sp */
+  {
+    -1, "add16-bQ-sp", "add.b:q", 16,
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+  },
 };
 
 /* The macro instruction opcode table.  */
 
 static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] =
 {
+/* add.b:q #${Imm-12-s4},sp */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
+    & ifmt_add16_bQ_sp, { 0x7db0 }
+  },
 };
 
 #undef A
diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h
index 4e49ff454d6..b0448fb471c 100644
--- a/opcodes/m32c-opc.h
+++ b/opcodes/m32c-opc.h
@@ -286,9 +286,9 @@ typedef enum cgen_insn_type {
  , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI
  , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI
  , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
+ , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
  , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI
  , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI
  , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI
@@ -678,17 +678,17 @@ typedef enum cgen_insn_type {
  , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
  , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
  , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
+ , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
  , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI
- , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI
+ , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
  , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
@@ -875,2158 +875,2177 @@ typedef enum cgen_insn_type {
  , M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
  , M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
  , M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI
- , M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI
- , M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI
- , M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
- , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
- , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI
- , M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI
- , M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI
- , M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI
- , M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI
- , M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI
- , M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI
- , M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
- , M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI
- , M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI
- , M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED
- , M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
- , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
- , M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
- , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI
- , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
- , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI
- , M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI
- , M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI
- , M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI
- , M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI
- , M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI
- , M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI
- , M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI
- , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI
- , M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI
- , M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI
- , M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI
- , M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI
- , M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI
- , M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI
- , M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
- , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
- , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
- , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI
- , M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI
- , M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI
- , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI
- , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI
- , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI
- , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI
- , M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI
- , M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
- , M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED
- , M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
- , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI
- , M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI
- , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI
- , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI
- , M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED
- , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED
- , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED
- , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT
- , M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE
- , M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED
- , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED
- , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED
- , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT
- , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE
- , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED
- , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED
- , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED
- , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE
- , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE
- , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED
- , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED
- , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED
- , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE
- , M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED
- , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED
- , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED
- , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT
- , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE
- , M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE
- , M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED
- , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED
- , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED
- , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT
- , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE
- , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED
- , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED
- , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED
- , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT
- , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE
- , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
- , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
- , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
- , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT
- , M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE
- , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED
- , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED
- , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED
- , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE
- , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE
- , M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED
- , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED
- , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED
- , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT
- , M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE
- , M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
- , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
- , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
- , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT
- , M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE
- , M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED
- , M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED
- , M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED
- , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE
- , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE
- , M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED
- , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED
- , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED
- , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE
- , M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
- , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
- , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
- , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT
- , M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
- , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE
- , M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI
- , M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI
- , M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
- , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
- , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI
- , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI
- , M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI
- , M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
- , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
- , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
- , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI
- , M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI
- , M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI
- , M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
- , M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
- , M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
- , M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI
- , M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI
- , M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI
- , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
- , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
- , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
- , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI
- , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
- , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI
- , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI
- , M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI
- , M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
- , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI
- , M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI
- , M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI
- , M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
- , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI
- , M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI
- , M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI
- , M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI
- , M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI
- , M32C_INSN_ADD16_Q_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP, M32C_INSN_ADD32_L_IMM3_Q
- , M32C_INSN_ADD32_L_IMM8_S, M32C_INSN_ADD32_L_IMM16_G, M32C_INSN_DADC16_B_IMM8, M32C_INSN_DADC16_W_IMM16
- , M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8, M32C_INSN_DADD16_W_IMM16
- , M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C, M32C_INSN_BM32_C
- , M32C_INSN_BRK16, M32C_INSN_BRK32, M32C_INSN_BRK232, M32C_INSN_DEC16_W
- , M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI, M32C_INSN_DIV32_B_IMM_16_QI, M32C_INSN_DIV32_W_IMM_16_HI
- , M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI, M32C_INSN_DIVU32_B_IMM_16_QI, M32C_INSN_DIVU32_W_IMM_16_HI
- , M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI, M32C_INSN_DIVX32_B_IMM_16_QI, M32C_INSN_DIVX32_W_IMM_16_HI
- , M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16, M32C_INSN_DSBB16_B_R0H_R0L, M32C_INSN_DSBB16_W_R1_R0
- , M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16, M32C_INSN_DSUB16_B_R0H_R0L, M32C_INSN_DSUB16_W_R1_R0
- , M32C_INSN_ENTER16, M32C_INSN_EXITD16, M32C_INSN_ENTER32, M32C_INSN_EXITD32
- , M32C_INSN_FCLR16, M32C_INSN_FSET16, M32C_INSN_FCLR, M32C_INSN_FSET
- , M32C_INSN_INC16_W, M32C_INSN_FREIT32, M32C_INSN_INT16, M32C_INSN_INTO16
- , M32C_INSN_INT32, M32C_INSN_INTO32, M32C_INSN_JCND16_5, M32C_INSN_JCND16
- , M32C_INSN_JCND32, M32C_INSN_JMP16_S, M32C_INSN_JMP16_B, M32C_INSN_JMP16_W
- , M32C_INSN_JMP16_A, M32C_INSN_JMPS16, M32C_INSN_JMP32_S, M32C_INSN_JMP32_B
- , M32C_INSN_JMP32_W, M32C_INSN_JMP32_A, M32C_INSN_JMPS32, M32C_INSN_JSR16_W
- , M32C_INSN_JSR16_A, M32C_INSN_JSR32_W, M32C_INSN_JSR32_A, M32C_INSN_JSRS16
- , M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16, M32C_INSN_LDC32_IMM16_CR1, M32C_INSN_LDC32_IMM16_CR2
- , M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16, M32C_INSN_LDCTX32, M32C_INSN_STCTX16
- , M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM, M32C_INSN_LDIPL32_IMM, M32C_INSN_MOV16_B_S_IMM_A0
- , M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0, M32C_INSN_MOV16_W_S_IMM_A1, M32C_INSN_MOV32_W_A0
- , M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0, M32C_INSN_MOV32_L_A1, M32C_INSN_MOV16_B_S_R0L_A1
- , M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16, M32C_INSN_NOP32, M32C_INSN_POPC16_IMM16
- , M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2, M32C_INSN_PUSHC16_IMM16, M32C_INSN_PUSHC32_IMM16_CR1
- , M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16, M32C_INSN_PUSHM16, M32C_INSN_POPM
- , M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM, M32C_INSN_PUSH16_W_G_IMM, M32C_INSN_PUSH32_B_IMM
- , M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM, M32C_INSN_REIT16, M32C_INSN_REIT32
- , M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W, M32C_INSN_RMPA32_B, M32C_INSN_RMPA32_W
- , M32C_INSN_RTS16, M32C_INSN_RTS32, M32C_INSN_SCMPU_B, M32C_INSN_SCMPU_W
- , M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1, M32C_INSN_SHA16_L_R1H_R2R0, M32C_INSN_SHA16_L_R1H_R3R1
- , M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1, M32C_INSN_SHL16_L_R1H_R2R0, M32C_INSN_SHL16_L_R1H_R3R1
- , M32C_INSN_SIN32_B, M32C_INSN_SIN32_W, M32C_INSN_SMOVB16_B, M32C_INSN_SMOVB16_W
- , M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W, M32C_INSN_SMOVF16_B, M32C_INSN_SMOVF16_W
- , M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W, M32C_INSN_SMOVU_B, M32C_INSN_SMOVU_W
- , M32C_INSN_SOUT_B, M32C_INSN_SOUT_W, M32C_INSN_SSTR16_B, M32C_INSN_SSTR16_W
- , M32C_INSN_SSTR_B, M32C_INSN_SSTR_W, M32C_INSN_STZX16_IMM8_IMM8_R0H, M32C_INSN_STZX16_IMM8_IMM8_R0L
- , M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, M32C_INSN_STZX16_IMM8_IMM8_ABS16, M32C_INSN_UND16
- , M32C_INSN_UND32, M32C_INSN_WAIT16, M32C_INSN_WAIT, M32C_INSN_EXTS16_W_R0
- , M32C_INSN_SRCIND, M32C_INSN_DESTIND, M32C_INSN_SRCDESTIND
+ , M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI
+ , M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI
+ , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI
+ , M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI
+ , M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI
+ , M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI
+ , M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI
+ , M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI
+ , M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI
+ , M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI
+ , M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI
+ , M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI
+ , M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI
+ , M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI
+ , M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI
+ , M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI
+ , M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI
+ , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI
+ , M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
+ , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
+ , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI
+ , M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI
+ , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI
+ , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
+ , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI
+ , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI
+ , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI
+ , M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI
+ , M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI
+ , M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI
+ , M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI
+ , M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI
+ , M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI
+ , M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI
+ , M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI
+ , M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI
+ , M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI
+ , M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI
+ , M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI
+ , M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI
+ , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI
+ , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI
+ , M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI
+ , M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI
+ , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI
+ , M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI
+ , M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI
+ , M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
+ , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
+ , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI
+ , M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
+ , M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI
+ , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI
+ , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI
+ , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI
+ , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI
+ , M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI
+ , M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI
+ , M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI
+ , M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI
+ , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI
+ , M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI
+ , M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
+ , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
+ , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT
+ , M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
+ , M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE
+ , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED
+ , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE
+ , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED
+ , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED
+ , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT
+ , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE
+ , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED
+ , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT
+ , M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S
+ , M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT
+ , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED
+ , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE
+ , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE
+ , M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED
+ , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED
+ , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT
+ , M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE
+ , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
+ , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
+ , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT
+ , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
+ , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE
+ , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED
+ , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED
+ , M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE
+ , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED
+ , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED
+ , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE
+ , M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED
+ , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED
+ , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT
+ , M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE
+ , M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE
+ , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED
+ , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED
+ , M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE
+ , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED
+ , M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE
+ , M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED
+ , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED
+ , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED
+ , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT
+ , M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S
+ , M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT
+ , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED
+ , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED
+ , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED
+ , M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE
+ , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE
+ , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI
+ , M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI
+ , M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI
+ , M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI
+ , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
+ , M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI
+ , M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI
+ , M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI
+ , M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI
+ , M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI
+ , M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI
+ , M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI
+ , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI
+ , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI
+ , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI
+ , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI
+ , M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI
+ , M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
+ , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
+ , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI
+ , M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI
+ , M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI
+ , M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI
+ , M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
+ , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI
+ , M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI
+ , M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI
+ , M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_WQ_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP
+ , M32C_INSN_ADD32_L_IMM3_Q, M32C_INSN_ADD32_L_IMM8_S, M32C_INSN_ADD32_L_IMM16_G, M32C_INSN_DADC16_B_IMM8
+ , M32C_INSN_DADC16_W_IMM16, M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8
+ , M32C_INSN_DADD16_W_IMM16, M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C
+ , M32C_INSN_BM32_C, M32C_INSN_BRK16, M32C_INSN_BRK32, M32C_INSN_BRK232
+ , M32C_INSN_DEC16_W, M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI, M32C_INSN_DIV32_B_IMM_16_QI
+ , M32C_INSN_DIV32_W_IMM_16_HI, M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI, M32C_INSN_DIVU32_B_IMM_16_QI
+ , M32C_INSN_DIVU32_W_IMM_16_HI, M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI, M32C_INSN_DIVX32_B_IMM_16_QI
+ , M32C_INSN_DIVX32_W_IMM_16_HI, M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16, M32C_INSN_DSBB16_B_R0H_R0L
+ , M32C_INSN_DSBB16_W_R1_R0, M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16, M32C_INSN_DSUB16_B_R0H_R0L
+ , M32C_INSN_DSUB16_W_R1_R0, M32C_INSN_ENTER16, M32C_INSN_EXITD16, M32C_INSN_ENTER32
+ , M32C_INSN_EXITD32, M32C_INSN_FCLR16, M32C_INSN_FSET16, M32C_INSN_FCLR
+ , M32C_INSN_FSET, M32C_INSN_INC16_W, M32C_INSN_FREIT32, M32C_INSN_INT16
+ , M32C_INSN_INTO16, M32C_INSN_INT32, M32C_INSN_INTO32, M32C_INSN_JCND16_5
+ , M32C_INSN_JCND16, M32C_INSN_JCND32, M32C_INSN_JMP16_S, M32C_INSN_JMP16_B
+ , M32C_INSN_JMP16_W, M32C_INSN_JMP16_A, M32C_INSN_JMPS16, M32C_INSN_JMP32_S
+ , M32C_INSN_JMP32_B, M32C_INSN_JMP32_W, M32C_INSN_JMP32_A, M32C_INSN_JMPS32
+ , M32C_INSN_JSR16_W, M32C_INSN_JSR16_A, M32C_INSN_JSR32_W, M32C_INSN_JSR32_A
+ , M32C_INSN_JSRS16, M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16, M32C_INSN_LDC32_IMM16_CR1
+ , M32C_INSN_LDC32_IMM16_CR2, M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16, M32C_INSN_LDCTX32
+ , M32C_INSN_STCTX16, M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM, M32C_INSN_LDIPL32_IMM
+ , M32C_INSN_MOV16_B_S_IMM_A0, M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0, M32C_INSN_MOV16_W_S_IMM_A1
+ , M32C_INSN_MOV32_W_A0, M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0, M32C_INSN_MOV32_L_A1
+ , M32C_INSN_MOV16_B_S_R0L_A1, M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16, M32C_INSN_NOP32
+ , M32C_INSN_POPC16_IMM16, M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2, M32C_INSN_PUSHC16_IMM16
+ , M32C_INSN_PUSHC32_IMM16_CR1, M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16, M32C_INSN_PUSHM16
+ , M32C_INSN_POPM, M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM, M32C_INSN_PUSH16_W_G_IMM
+ , M32C_INSN_PUSH32_B_IMM, M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM, M32C_INSN_REIT16
+ , M32C_INSN_REIT32, M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W, M32C_INSN_RMPA32_B
+ , M32C_INSN_RMPA32_W, M32C_INSN_RTS16, M32C_INSN_RTS32, M32C_INSN_SCMPU_B
+ , M32C_INSN_SCMPU_W, M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1, M32C_INSN_SHA16_L_R1H_R2R0
+ , M32C_INSN_SHA16_L_R1H_R3R1, M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1, M32C_INSN_SHL16_L_R1H_R2R0
+ , M32C_INSN_SHL16_L_R1H_R3R1, M32C_INSN_SIN32_B, M32C_INSN_SIN32_W, M32C_INSN_SMOVB16_B
+ , M32C_INSN_SMOVB16_W, M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W, M32C_INSN_SMOVF16_B
+ , M32C_INSN_SMOVF16_W, M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W, M32C_INSN_SMOVU_B
+ , M32C_INSN_SMOVU_W, M32C_INSN_SOUT_B, M32C_INSN_SOUT_W, M32C_INSN_SSTR16_B
+ , M32C_INSN_SSTR16_W, M32C_INSN_SSTR_B, M32C_INSN_SSTR_W, M32C_INSN_STZX16_IMM8_IMM8_R0H
+ , M32C_INSN_STZX16_IMM8_IMM8_R0L, M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, M32C_INSN_STZX16_IMM8_IMM8_ABS16
+ , M32C_INSN_UND16, M32C_INSN_UND32, M32C_INSN_WAIT16, M32C_INSN_WAIT
+ , M32C_INSN_EXTS16_W_R0, M32C_INSN_SRCIND, M32C_INSN_DESTIND, M32C_INSN_SRCDESTIND
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
@@ -3154,6 +3173,7 @@ struct cgen_fields
   long f_dsp_48_u16;
   long f_dsp_48_s16;
   long f_dsp_64_u16;
+  long f_dsp_8_s24;
   long f_dsp_8_u24;
   long f_dsp_16_u24;
   long f_dsp_24_u24;
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 50f1363e777..a5bd3633168 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -89,7 +89,10 @@ parse_hi16 (CGEN_CPU_DESC cd,
       ++*strp;
       if (errmsg == NULL
   	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	value >>= 16;
+	{
+	  value >>= 16;
+	  value &= 0xffff;
+	}
       *valuep = value;
       return errmsg;
     }
@@ -104,8 +107,9 @@ parse_hi16 (CGEN_CPU_DESC cd,
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
         {
-          value = value + (value & 0x8000 ? 0x10000 : 0);
+          value += 0x8000;
           value >>= 16;
+	  value &= 0xffff;
         }
       *valuep = value;
       return errmsg;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 3b8cb56c7c9..c9cd3bb5163 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -148,25 +148,25 @@ static const CGEN_MACH m32r_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 {
-  { "fp", 13, {0, {0}}, 0, 0 },
-  { "lr", 14, {0, {0}}, 0, 0 },
-  { "sp", 15, {0, {0}}, 0, 0 },
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 }
+  { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32r_cgen_opval_gr_names =
@@ -178,30 +178,30 @@ CGEN_KEYWORD m32r_cgen_opval_gr_names =
 
 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 {
-  { "psw", 0, {0, {0}}, 0, 0 },
-  { "cbr", 1, {0, {0}}, 0, 0 },
-  { "spi", 2, {0, {0}}, 0, 0 },
-  { "spu", 3, {0, {0}}, 0, 0 },
-  { "bpc", 6, {0, {0}}, 0, 0 },
-  { "bbpsw", 8, {0, {0}}, 0, 0 },
-  { "bbpc", 14, {0, {0}}, 0, 0 },
-  { "evb", 5, {0, {0}}, 0, 0 },
-  { "cr0", 0, {0, {0}}, 0, 0 },
-  { "cr1", 1, {0, {0}}, 0, 0 },
-  { "cr2", 2, {0, {0}}, 0, 0 },
-  { "cr3", 3, {0, {0}}, 0, 0 },
-  { "cr4", 4, {0, {0}}, 0, 0 },
-  { "cr5", 5, {0, {0}}, 0, 0 },
-  { "cr6", 6, {0, {0}}, 0, 0 },
-  { "cr7", 7, {0, {0}}, 0, 0 },
-  { "cr8", 8, {0, {0}}, 0, 0 },
-  { "cr9", 9, {0, {0}}, 0, 0 },
-  { "cr10", 10, {0, {0}}, 0, 0 },
-  { "cr11", 11, {0, {0}}, 0, 0 },
-  { "cr12", 12, {0, {0}}, 0, 0 },
-  { "cr13", 13, {0, {0}}, 0, 0 },
-  { "cr14", 14, {0, {0}}, 0, 0 },
-  { "cr15", 15, {0, {0}}, 0, 0 }
+  { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32r_cgen_opval_cr_names =
@@ -213,8 +213,8 @@ CGEN_KEYWORD m32r_cgen_opval_cr_names =
 
 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 {
-  { "a0", 0, {0, {0}}, 0, 0 },
-  { "a1", 1, {0, {0}}, 0, 0 }
+  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32r_cgen_opval_h_accums =
@@ -235,25 +235,25 @@ CGEN_KEYWORD m32r_cgen_opval_h_accums =
 
 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
-  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
-  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -269,36 +269,36 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 
 const CGEN_IFLD m32r_cgen_ifld_table[] =
 {
-  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
-  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
-  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -330,119 +330,119 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sr: source register */
   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dr: destination register */
   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* src1: source register 1 */
   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* src2: source register 2 */
   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* scr: source control register */
   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dcr: destination control register */
   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* simm8: 8 bit signed immediate */
   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* simm16: 16 bit signed immediate */
   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm3: 3 bit unsigned number */
   { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm4: 4 bit trap number */
   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm5: 5 bit shift count */
   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm8: 8 bit unsigned immediate */
   { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm1: 1 bit immediate */
   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 /* accd: accumulator destination register */
   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 /* accs: accumulator source register */
   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 /* acc: accumulator reg (d) */
   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 /* hash: # prefix */
   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* hi16: high 16 bit immediate, sign optional */
   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, 
-    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
+    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 /* slo16: 16 bit signed immediate, for low() */
   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ulo16: 16 bit unsigned immediate, for low() */
   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm24: 24 bit address */
   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, 
-    { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp8: 8 bit displacement */
   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, 
-    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp16: 16 bit displacement */
   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, 
-    { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp24: 24 bit displacement */
   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, 
-    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* condbit: condition bit */
   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* accum: accumulator */
   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -462,746 +462,746 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
 /* add $dr,$sr */
   {
     M32R_INSN_ADD, "add", "add", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* add3 $dr,$sr,$hash$slo16 */
   {
     M32R_INSN_ADD3, "add3", "add3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* and $dr,$sr */
   {
     M32R_INSN_AND, "and", "and", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_AND3, "and3", "and3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* or $dr,$sr */
   {
     M32R_INSN_OR, "or", "or", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* or3 $dr,$sr,$hash$ulo16 */
   {
     M32R_INSN_OR3, "or3", "or3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* xor $dr,$sr */
   {
     M32R_INSN_XOR, "xor", "xor", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_XOR3, "xor3", "xor3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* addi $dr,$simm8 */
   {
     M32R_INSN_ADDI, "addi", "addi", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* addv $dr,$sr */
   {
     M32R_INSN_ADDV, "addv", "addv", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     M32R_INSN_ADDV3, "addv3", "addv3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* addx $dr,$sr */
   {
     M32R_INSN_ADDX, "addx", "addx", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* bc.s $disp8 */
   {
     M32R_INSN_BC8, "bc8", "bc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bc.l $disp24 */
   {
     M32R_INSN_BC24, "bc24", "bc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     M32R_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* beqz $src2,$disp16 */
   {
     M32R_INSN_BEQZ, "beqz", "beqz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bgez $src2,$disp16 */
   {
     M32R_INSN_BGEZ, "bgez", "bgez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bgtz $src2,$disp16 */
   {
     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* blez $src2,$disp16 */
   {
     M32R_INSN_BLEZ, "blez", "blez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bltz $src2,$disp16 */
   {
     M32R_INSN_BLTZ, "bltz", "bltz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bnez $src2,$disp16 */
   {
     M32R_INSN_BNEZ, "bnez", "bnez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bl.s $disp8 */
   {
     M32R_INSN_BL8, "bl8", "bl.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bl.l $disp24 */
   {
     M32R_INSN_BL24, "bl24", "bl.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bcl.s $disp8 */
   {
     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bcl.l $disp24 */
   {
     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bnc.s $disp8 */
   {
     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bnc.l $disp24 */
   {
     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     M32R_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bra.s $disp8 */
   {
     M32R_INSN_BRA8, "bra8", "bra.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bra.l $disp24 */
   {
     M32R_INSN_BRA24, "bra24", "bra.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bncl.s $disp8 */
   {
     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bncl.l $disp24 */
   {
     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* cmp $src1,$src2 */
   {
     M32R_INSN_CMP, "cmp", "cmp", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* cmpi $src2,$simm16 */
   {
     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* cmpu $src1,$src2 */
   {
     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* cmpui $src2,$simm16 */
   {
     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* cmpeq $src1,$src2 */
   {
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* cmpz $src2 */
   {
     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* div $dr,$sr */
   {
     M32R_INSN_DIV, "div", "div", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* divu $dr,$sr */
   {
     M32R_INSN_DIVU, "divu", "divu", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* rem $dr,$sr */
   {
     M32R_INSN_REM, "rem", "rem", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* remu $dr,$sr */
   {
     M32R_INSN_REMU, "remu", "remu", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* remh $dr,$sr */
   {
     M32R_INSN_REMH, "remh", "remh", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* remuh $dr,$sr */
   {
     M32R_INSN_REMUH, "remuh", "remuh", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* remb $dr,$sr */
   {
     M32R_INSN_REMB, "remb", "remb", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* remub $dr,$sr */
   {
     M32R_INSN_REMUB, "remub", "remub", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* divuh $dr,$sr */
   {
     M32R_INSN_DIVUH, "divuh", "divuh", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* divb $dr,$sr */
   {
     M32R_INSN_DIVB, "divb", "divb", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* divub $dr,$sr */
   {
     M32R_INSN_DIVUB, "divub", "divub", 32,
-    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* divh $dr,$sr */
   {
     M32R_INSN_DIVH, "divh", "divh", 32,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* jc $sr */
   {
     M32R_INSN_JC, "jc", "jc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* jnc $sr */
   {
     M32R_INSN_JNC, "jnc", "jnc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* jl $sr */
   {
     M32R_INSN_JL, "jl", "jl", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* jmp $sr */
   {
     M32R_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ld $dr,@$sr */
   {
     M32R_INSN_LD, "ld", "ld", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     M32R_INSN_LD_D, "ld-d", "ld", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldb $dr,@$sr */
   {
     M32R_INSN_LDB, "ldb", "ldb", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldh $dr,@$sr */
   {
     M32R_INSN_LDH, "ldh", "ldh", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldub $dr,@$sr */
   {
     M32R_INSN_LDUB, "ldub", "ldub", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* lduh $dr,@$sr */
   {
     M32R_INSN_LDUH, "lduh", "lduh", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ld $dr,@$sr+ */
   {
     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ld24 $dr,$uimm24 */
   {
     M32R_INSN_LD24, "ld24", "ld24", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldi8 $dr,$simm8 */
   {
     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* ldi16 $dr,$hash$slo16 */
   {
     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* lock $dr,@$sr */
   {
     M32R_INSN_LOCK, "lock", "lock", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* machi $src1,$src2 */
   {
     M32R_INSN_MACHI, "machi", "machi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* machi $src1,$src2,$acc */
   {
     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* maclo $src1,$src2 */
   {
     M32R_INSN_MACLO, "maclo", "maclo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* maclo $src1,$src2,$acc */
   {
     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* macwhi $src1,$src2 */
   {
     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* macwhi $src1,$src2,$acc */
   {
     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* macwlo $src1,$src2 */
   {
     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* macwlo $src1,$src2,$acc */
   {
     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mul $dr,$sr */
   {
     M32R_INSN_MUL, "mul", "mul", 16,
-    { 0, { (1<<MACH_BASE), PIPE_S } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulhi $src1,$src2 */
   {
     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulhi $src1,$src2,$acc */
   {
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mullo $src1,$src2 */
   {
     M32R_INSN_MULLO, "mullo", "mullo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mullo $src1,$src2,$acc */
   {
     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulwhi $src1,$src2 */
   {
     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulwhi $src1,$src2,$acc */
   {
     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulwlo $src1,$src2 */
   {
     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulwlo $src1,$src2,$acc */
   {
     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mv $dr,$sr */
   {
     M32R_INSN_MV, "mv", "mv", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* mvfachi $dr */
   {
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfachi $dr,$accs */
   {
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfaclo $dr */
   {
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfaclo $dr,$accs */
   {
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfacmi $dr */
   {
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfacmi $dr,$accs */
   {
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvfc $dr,$scr */
   {
     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* mvtachi $src1 */
   {
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvtachi $src1,$accs */
   {
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvtaclo $src1 */
   {
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvtaclo $src1,$accs */
   {
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mvtc $sr,$dcr */
   {
     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* neg $dr,$sr */
   {
     M32R_INSN_NEG, "neg", "neg", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* nop */
   {
     M32R_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* not $dr,$sr */
   {
     M32R_INSN_NOT, "not", "not", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* rac */
   {
     M32R_INSN_RAC, "rac", "rac", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rac $accd,$accs,$imm1 */
   {
     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rach */
   {
     M32R_INSN_RACH, "rach", "rach", 16,
-    { 0, { (1<<MACH_M32R), PIPE_S } }
+    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rach $accd,$accs,$imm1 */
   {
     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rte */
   {
     M32R_INSN_RTE, "rte", "rte", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* seth $dr,$hash$hi16 */
   {
     M32R_INSN_SETH, "seth", "seth", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* sll $dr,$sr */
   {
     M32R_INSN_SLL, "sll", "sll", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SLL3, "sll3", "sll3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* slli $dr,$uimm5 */
   {
     M32R_INSN_SLLI, "slli", "slli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* sra $dr,$sr */
   {
     M32R_INSN_SRA, "sra", "sra", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRA3, "sra3", "sra3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* srai $dr,$uimm5 */
   {
     M32R_INSN_SRAI, "srai", "srai", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* srl $dr,$sr */
   {
     M32R_INSN_SRL, "srl", "srl", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRL3, "srl3", "srl3", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* srli $dr,$uimm5 */
   {
     M32R_INSN_SRLI, "srli", "srli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
   },
 /* st $src1,@$src2 */
   {
     M32R_INSN_ST, "st", "st", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     M32R_INSN_ST_D, "st-d", "st", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* stb $src1,@$src2 */
   {
     M32R_INSN_STB, "stb", "stb", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     M32R_INSN_STB_D, "stb-d", "stb", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* sth $src1,@$src2 */
   {
     M32R_INSN_STH, "sth", "sth", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     M32R_INSN_STH_D, "sth-d", "sth", 32,
-    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* st $src1,@+$src2 */
   {
     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* sth $src1,@$src2+ */
   {
     M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* stb $src1,@$src2+ */
   {
     M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* st $src1,@-$src2 */
   {
     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* sub $dr,$sr */
   {
     M32R_INSN_SUB, "sub", "sub", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* subv $dr,$sr */
   {
     M32R_INSN_SUBV, "subv", "subv", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* subx $dr,$sr */
   {
     M32R_INSN_SUBX, "subx", "subx", 16,
-    { 0, { (1<<MACH_BASE), PIPE_OS } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* trap $uimm4 */
   {
     M32R_INSN_TRAP, "trap", "trap", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* unlock $src1,@$src2 */
   {
     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* satb $dr,$sr */
   {
     M32R_INSN_SATB, "satb", "satb", 32,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* sath $dr,$sr */
   {
     M32R_INSN_SATH, "sath", "sath", 32,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* sat $dr,$sr */
   {
     M32R_INSN_SAT, "sat", "sat", 32,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* pcmpbz $src2 */
   {
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* sadd */
   {
     M32R_INSN_SADD, "sadd", "sadd", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* macwu1 $src1,$src2 */
   {
     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* msblo $src1,$src2 */
   {
     M32R_INSN_MSBLO, "msblo", "msblo", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* mulwu1 $src1,$src2 */
   {
     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* maclh1 $src1,$src2 */
   {
     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
-    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* sc */
   {
     M32R_INSN_SC, "sc", "sc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* snc */
   {
     M32R_INSN_SNC, "snc", "snc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* clrpsw $uimm8 */
   {
     M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
-    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* setpsw $uimm8 */
   {
     M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
-    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bset $uimm3,@($slo16,$sr) */
   {
     M32R_INSN_BSET, "bset", "bset", 32,
-    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bclr $uimm3,@($slo16,$sr) */
   {
     M32R_INSN_BCLR, "bclr", "bclr", 32,
-    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* btst $uimm3,$sr */
   {
     M32R_INSN_BTST, "btst", "btst", 16,
-    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 };
 
@@ -1324,7 +1324,7 @@ static void
 m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1336,7 +1336,7 @@ m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
 
@@ -1421,7 +1421,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -1440,7 +1440,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -1471,9 +1471,6 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -1481,7 +1478,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 2080b5cdc0f..9624852bea9 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef M32R_CPU_H
 #define M32R_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH m32r
 
 /* Given symbol S, return m32r_cgen_<S>.  */
@@ -135,6 +137,16 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
+
 /* Enum declaration for m32r ifield types.  */
 typedef enum ifield_type {
   M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
@@ -160,6 +172,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for m32r hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -184,6 +203,19 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
+
 /* Enum declaration for m32r operand types.  */
 typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
@@ -216,6 +248,24 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index fb65bfee728..e381c919d75 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -564,7 +564,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -576,11 +576,12 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -603,25 +604,34 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -637,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -650,7 +660,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 29b7a21c290..7669eb6187c 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -1301,182 +1301,182 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bc $disp8 */
   {
     -1, "bc8r", "bc", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bc $disp24 */
   {
     -1, "bc24r", "bc", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bl $disp8 */
   {
     -1, "bl8r", "bl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bl $disp24 */
   {
     -1, "bl24r", "bl", 32,
-    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bcl $disp8 */
   {
     -1, "bcl8r", "bcl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bcl $disp24 */
   {
     -1, "bcl24r", "bcl", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bnc $disp8 */
   {
     -1, "bnc8r", "bnc", 16,
-    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bnc $disp24 */
   {
     -1, "bnc24r", "bnc", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bra $disp8 */
   {
     -1, "bra8r", "bra", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bra $disp24 */
   {
     -1, "bra24r", "bra", 32,
-    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* bncl $disp8 */
   {
     -1, "bncl8r", "bncl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* bncl $disp24 */
   {
     -1, "bncl24r", "bncl", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ld $dr,@($sr) */
   {
     -1, "ld-2", "ld", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ld $dr,@($sr,$slo16) */
   {
     -1, "ld-d2", "ld", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldb $dr,@($sr) */
   {
     -1, "ldb-2", "ldb", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldb $dr,@($sr,$slo16) */
   {
     -1, "ldb-d2", "ldb", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldh $dr,@($sr) */
   {
     -1, "ldh-2", "ldh", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldh $dr,@($sr,$slo16) */
   {
     -1, "ldh-d2", "ldh", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* ldub $dr,@($sr) */
   {
     -1, "ldub-2", "ldub", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldub $dr,@($sr,$slo16) */
   {
     -1, "ldub-d2", "ldub", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* lduh $dr,@($sr) */
   {
     -1, "lduh-2", "lduh", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* lduh $dr,@($sr,$slo16) */
   {
     -1, "lduh-d2", "lduh", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* pop $dr */
   {
     -1, "pop", "pop", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* ldi $dr,$simm8 */
   {
     -1, "ldi8a", "ldi", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
   },
 /* ldi $dr,$hash$slo16 */
   {
     -1, "ldi16a", "ldi", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* rac $accd */
   {
     -1, "rac-d", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rac $accd,$accs */
   {
     -1, "rac-ds", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rach $accd */
   {
     -1, "rach-d", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* rach $accd,$accs */
   {
     -1, "rach-ds", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
   },
 /* st $src1,@($src2) */
   {
     -1, "st-2", "st", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* st $src1,@($src2,$slo16) */
   {
     -1, "st-d2", "st", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* stb $src1,@($src2) */
   {
     -1, "stb-2", "stb", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* stb $src1,@($src2,$slo16) */
   {
     -1, "stb-d2", "stb", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* sth $src1,@($src2) */
   {
     -1, "sth-2", "sth", 16,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 /* sth $src1,@($src2,$slo16) */
   {
     -1, "sth-d2", "sth", 32,
-    { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
   },
 /* push $src1 */
   {
     -1, "push", "push", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
   },
 };
 
diff --git a/opcodes/ms1-desc.c b/opcodes/ms1-desc.c
index 8428c6c0125..c48a8a89c85 100644
--- a/opcodes/ms1-desc.c
+++ b/opcodes/ms1-desc.c
@@ -138,8 +138,8 @@ static const CGEN_MACH ms1_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] =
 {
-  { "DUP", 1, {0, {0}}, 0, 0 },
-  { "XX", 0, {0, {0}}, 0, 0 }
+  { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD ms1_cgen_opval_msys_syms =
@@ -151,26 +151,26 @@ CGEN_KEYWORD ms1_cgen_opval_msys_syms =
 
 static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] =
 {
-  { "R0", 0, {0, {0}}, 0, 0 },
-  { "R1", 1, {0, {0}}, 0, 0 },
-  { "R2", 2, {0, {0}}, 0, 0 },
-  { "R3", 3, {0, {0}}, 0, 0 },
-  { "R4", 4, {0, {0}}, 0, 0 },
-  { "R5", 5, {0, {0}}, 0, 0 },
-  { "R6", 6, {0, {0}}, 0, 0 },
-  { "R7", 7, {0, {0}}, 0, 0 },
-  { "R8", 8, {0, {0}}, 0, 0 },
-  { "R9", 9, {0, {0}}, 0, 0 },
-  { "R10", 10, {0, {0}}, 0, 0 },
-  { "R11", 11, {0, {0}}, 0, 0 },
-  { "R12", 12, {0, {0}}, 0, 0 },
-  { "fp", 12, {0, {0}}, 0, 0 },
-  { "R13", 13, {0, {0}}, 0, 0 },
-  { "sp", 13, {0, {0}}, 0, 0 },
-  { "R14", 14, {0, {0}}, 0, 0 },
-  { "ra", 14, {0, {0}}, 0, 0 },
-  { "R15", 15, {0, {0}}, 0, 0 },
-  { "ira", 15, {0, {0}}, 0, 0 }
+  { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "R14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "ra", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "R15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD ms1_cgen_opval_h_spr =
@@ -191,14 +191,14 @@ CGEN_KEYWORD ms1_cgen_opval_h_spr =
 
 const CGEN_HW_ENTRY ms1_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -214,76 +214,76 @@ const CGEN_HW_ENTRY ms1_cgen_hw_table[] =
 
 const CGEN_IFLD ms1_cgen_ifld_table[] =
 {
-  { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
-  { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -315,199 +315,199 @@ const CGEN_OPERAND ms1_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", MS1_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frsr1: register */
   { "frsr1", MS1_OPERAND_FRSR1, HW_H_SPR, 23, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR1] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frsr2: register */
   { "frsr2", MS1_OPERAND_FRSR2, HW_H_SPR, 19, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR2] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frdr: register */
   { "frdr", MS1_OPERAND_FRDR, HW_H_SPR, 19, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DR] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frdrrr: register */
   { "frdrrr", MS1_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DRRR] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16: immediate value - sign extd */
   { "imm16", MS1_OPERAND_IMM16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16z: immediate value - zero extd */
   { "imm16z", MS1_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16U] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16o: immediate value */
   { "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc: rc */
   { "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rcnum: rcnum */
   { "rcnum", MS1_OPERAND_RCNUM, HW_H_UINT, 14, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RCNUM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* contnum: context number */
   { "contnum", MS1_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CONTNUM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rbbc: omega network configuration */
   { "rbbc", MS1_OPERAND_RBBC, HW_H_UINT, 25, 2,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RBBC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* colnum: column number */
   { "colnum", MS1_OPERAND_COLNUM, HW_H_UINT, 18, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_COLNUM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum: row number */
   { "rownum", MS1_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum1: row number */
   { "rownum1", MS1_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum2: row number */
   { "rownum2", MS1_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc1: rc1 */
   { "rc1", MS1_OPERAND_RC1, HW_H_UINT, 11, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc2: rc2 */
   { "rc2", MS1_OPERAND_RC2, HW_H_UINT, 6, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbrb: data-bus orientation */
   { "cbrb", MS1_OPERAND_CBRB, HW_H_UINT, 10, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBRB] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cell: cell */
   { "cell", MS1_OPERAND_CELL, HW_H_UINT, 9, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CELL] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dup: dup */
   { "dup", MS1_OPERAND_DUP, HW_H_UINT, 6, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DUP] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ctxdisp: context displacement */
   { "ctxdisp", MS1_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CTXDISP] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* fbdisp: frame buffer displacement */
   { "fbdisp", MS1_OPERAND_FBDISP, HW_H_UINT, 15, 6,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBDISP] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* type: type */
   { "type", MS1_OPERAND_TYPE, HW_H_UINT, 21, 2,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_TYPE] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mask: mask */
   { "mask", MS1_OPERAND_MASK, HW_H_UINT, 25, 16,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* bankaddr: bank address */
   { "bankaddr", MS1_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BANKADDR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* incamt: increment amount */
   { "incamt", MS1_OPERAND_INCAMT, HW_H_UINT, 19, 8,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCAMT] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* xmode: xmode */
   { "xmode", MS1_OPERAND_XMODE, HW_H_UINT, 23, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_XMODE] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mask1: mask1 */
   { "mask1", MS1_OPERAND_MASK1, HW_H_UINT, 22, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ball: b_all */
   { "ball", MS1_OPERAND_BALL, HW_H_UINT, 19, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* brc: b_r_c */
   { "brc", MS1_OPERAND_BRC, HW_H_UINT, 18, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rda: rd */
   { "rda", MS1_OPERAND_RDA, HW_H_UINT, 25, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RDA] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* wr: wr */
   { "wr", MS1_OPERAND_WR, HW_H_UINT, 24, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_WR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ball2: b_all2 */
   { "ball2", MS1_OPERAND_BALL2, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* brc2: b_r_c2 */
   { "brc2", MS1_OPERAND_BRC2, HW_H_UINT, 14, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* perm: perm */
   { "perm", MS1_OPERAND_PERM, HW_H_UINT, 25, 2,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_PERM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* a23: a23 */
   { "a23", MS1_OPERAND_A23, HW_H_UINT, 23, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_A23] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cr: c-r */
   { "cr", MS1_OPERAND_CR, HW_H_UINT, 22, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbs: cbs */
   { "cbs", MS1_OPERAND_CBS, HW_H_UINT, 19, 2,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBS] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* incr: incr */
   { "incr", MS1_OPERAND_INCR, HW_H_UINT, 17, 6,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* length: length */
   { "length", MS1_OPERAND_LENGTH, HW_H_UINT, 15, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LENGTH] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbx: cbx */
   { "cbx", MS1_OPERAND_CBX, HW_H_UINT, 14, 3,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBX] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ccb: ccb */
   { "ccb", MS1_OPERAND_CCB, HW_H_UINT, 11, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CCB] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cdb: cdb */
   { "cdb", MS1_OPERAND_CDB, HW_H_UINT, 10, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CDB] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mode: mode */
   { "mode", MS1_OPERAND_MODE, HW_H_UINT, 25, 2,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MODE] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* id: i/d */
   { "id", MS1_OPERAND_ID, HW_H_UINT, 14, 1,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ID] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* size: size */
   { "size", MS1_OPERAND_SIZE, HW_H_UINT, 13, 14,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SIZE] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* fbincr: fb incr */
   { "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4,
     { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -527,391 +527,391 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 /* add $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_ADD, "add", "add", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addu $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_ADDU, "addu", "addu", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addi $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_ADDI, "addi", "addi", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* addui $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_ADDUI, "addui", "addui", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_SUB, "sub", "sub", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subu $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_SUBU, "subu", "subu", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subi $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_SUBI, "subi", "subi", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* subui $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_SUBUI, "subui", "subui", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mul $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_MUL, "mul", "mul", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_MS1_003) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* muli $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_MULI, "muli", "muli", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_MS1_003) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* and $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_AND, "and", "and", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* andi $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_ANDI, "andi", "andi", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_OR, "or", "or", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nop */
   {
     MS1_INSN_NOP, "nop", "nop", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ori $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_ORI, "ori", "ori", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_XOR, "xor", "xor", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xori $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_XORI, "xori", "xori", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nand $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_NAND, "nand", "nand", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nandi $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_NANDI, "nandi", "nandi", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nor $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_NOR, "nor", "nor", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nori $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_NORI, "nori", "nori", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xnor $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_XNOR, "xnor", "xnor", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xnori $frdr,$frsr1,#$imm16z */
   {
     MS1_INSN_XNORI, "xnori", "xnori", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldui $frdr,#$imm16z */
   {
     MS1_INSN_LDUI, "ldui", "ldui", 32,
-    { 0|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsl $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_LSL, "lsl", "lsl", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsli $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_LSLI, "lsli", "lsli", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsr $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_LSR, "lsr", "lsr", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* lsri $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_LSRI, "lsri", "lsri", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr $frdrrr,$frsr1,$frsr2 */
   {
     MS1_INSN_ASR, "asr", "asr", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asri $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_ASRI, "asri", "asri", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* brlt $frsr1,$frsr2,$imm16o */
   {
     MS1_INSN_BRLT, "brlt", "brlt", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* brle $frsr1,$frsr2,$imm16o */
   {
     MS1_INSN_BRLE, "brle", "brle", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* breq $frsr1,$frsr2,$imm16o */
   {
     MS1_INSN_BREQ, "breq", "breq", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* brne $frsr1,$frsr2,$imm16o */
   {
     MS1_INSN_BRNE, "brne", "brne", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jmp $imm16o */
   {
     MS1_INSN_JMP, "jmp", "jmp", 32,
-    { 0|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jal $frdrrr,$frsr1 */
   {
     MS1_INSN_JAL, "jal", "jal", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dbnz $frsr1,$imm16o */
   {
     MS1_INSN_DBNZ, "dbnz", "dbnz", 32,
-    { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_MS1_003) } }
+    { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* ei */
   {
     MS1_INSN_EI, "ei", "ei", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* di */
   {
     MS1_INSN_DI, "di", "di", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* si $frdrrr */
   {
     MS1_INSN_SI, "si", "si", 32,
-    { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* reti $frsr1 */
   {
     MS1_INSN_RETI, "reti", "reti", 32,
-    { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldw $frdr,$frsr1,#$imm16 */
   {
     MS1_INSN_LDW, "ldw", "ldw", 32,
-    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stw $frsr2,$frsr1,#$imm16 */
   {
     MS1_INSN_STW, "stw", "stw", 32,
-    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { (1<<MACH_BASE) } }
+    { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* break */
   {
     MS1_INSN_BREAK, "break", "break", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iflush */
   {
     MS1_INSN_IFLUSH, "iflush", "iflush", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
   {
     MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ldfb $frsr1,$frsr2,#$imm16z */
   {
     MS1_INSN_LDFB, "ldfb", "ldfb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* stfb $frsr1,$frsr2,#$imm16z */
   {
     MS1_INSN_STFB, "stfb", "stfb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCB, "fbcb", "fbcb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCB, "mfbcb", "mfbcb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCCI, "fbcci", "fbcci", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBRCI, "fbrci", "fbrci", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCRI, "fbcri", "fbcri", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBRRI, "fbrri", "fbrri", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cbcast #$mask,#$rc2,#$ctxdisp */
   {
     MS1_INSN_CBCAST, "cbcast", "cbcast", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
   {
     MS1_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_WFBI, "wfbi", "wfbi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
   {
     MS1_INSN_WFB, "wfb", "wfb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_RCRISC, "rcrisc", "rcrisc", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
   {
     MS1_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
   {
     MS1_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
   {
     MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
-    { 0, { (1<<MACH_MS1_003) } }
+    { 0, { { { (1<<MACH_MS1_003), 0 } } } }
   },
 };
 
@@ -1034,7 +1034,7 @@ static void
 ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1046,7 +1046,7 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & ms1_cgen_isa_table[i];
 
@@ -1131,7 +1131,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -1150,7 +1150,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -1181,9 +1181,6 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -1191,7 +1188,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/ms1-desc.h b/opcodes/ms1-desc.h
index 9dfd4da44d2..4a3dd2f5e21 100644
--- a/opcodes/ms1-desc.h
+++ b/opcodes/ms1-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef MS1_CPU_H
 #define MS1_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH ms1
 
 /* Given symbol S, return ms1_cgen_<S>.  */
@@ -131,6 +133,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for ms1 ifield types.  */
 typedef enum ifield_type {
   MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC
@@ -166,6 +177,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for ms1 hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -186,6 +204,17 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
 /* Enum declaration for ms1 operand types.  */
 typedef enum cgen_operand_type {
   MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR
@@ -224,6 +253,29 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
+#define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/ms1-dis.c b/opcodes/ms1-dis.c
index 980e8e09632..0026124f7db 100644
--- a/opcodes/ms1-dis.c
+++ b/opcodes/ms1-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -566,7 +566,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -578,11 +578,12 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -605,25 +606,34 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -639,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -652,7 +662,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index c469694cf59..5bdbeca536b 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -136,41 +136,41 @@ static const CGEN_MACH openrisc_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 },
-  { "r16", 16, {0, {0}}, 0, 0 },
-  { "r17", 17, {0, {0}}, 0, 0 },
-  { "r18", 18, {0, {0}}, 0, 0 },
-  { "r19", 19, {0, {0}}, 0, 0 },
-  { "r20", 20, {0, {0}}, 0, 0 },
-  { "r21", 21, {0, {0}}, 0, 0 },
-  { "r22", 22, {0, {0}}, 0, 0 },
-  { "r23", 23, {0, {0}}, 0, 0 },
-  { "r24", 24, {0, {0}}, 0, 0 },
-  { "r25", 25, {0, {0}}, 0, 0 },
-  { "r26", 26, {0, {0}}, 0, 0 },
-  { "r27", 27, {0, {0}}, 0, 0 },
-  { "r28", 28, {0, {0}}, 0, 0 },
-  { "r29", 29, {0, {0}}, 0, 0 },
-  { "r30", 30, {0, {0}}, 0, 0 },
-  { "r31", 31, {0, {0}}, 0, 0 },
-  { "lr", 11, {0, {0}}, 0, 0 },
-  { "sp", 1, {0, {0}}, 0, 0 },
-  { "fp", 2, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "lr", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD openrisc_cgen_opval_h_gr =
@@ -191,19 +191,19 @@ CGEN_KEYWORD openrisc_cgen_opval_h_gr =
 
 const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
-  { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -219,37 +219,37 @@ const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
 
 const CGEN_IFLD openrisc_cgen_ifld_table[] =
 {
-  { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -288,71 +288,71 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sr: special register */
   { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbit: condition bit */
   { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* simm-16: 16 bit signed immediate */
   { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm-16: 16 bit unsigned immediate */
   { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* disp-26: pc-rel 26 bit */
   { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* abs-26: abs 26 bit */
   { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm-5: imm5 */
   { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rD: destination register */
   { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rA: source register A */
   { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rB: source register B */
   { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* op-f-23: f-op23 */
   { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* op-f-3: f-op3 */
   { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* hi16: high 16 bit immediate, sign optional */
   { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
-    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
+    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 /* lo16: low 16 bit immediate, sign optional */
   { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, 
-    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
+    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 /* ui16nc: 16 bit immediate, sign optional */
   { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
     { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } }, 
-    { 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -372,326 +372,326 @@ static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 /* l.j ${abs-26} */
   {
     OPENRISC_INSN_L_J, "l-j", "l.j", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.jal ${abs-26} */
   {
     OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.jr $rA */
   {
     OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.jalr $rA */
   {
     OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.bal ${disp-26} */
   {
     OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.bnf ${disp-26} */
   {
     OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.bf ${disp-26} */
   {
     OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.brk ${uimm-16} */
   {
     OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32,
-    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.rfe $rA */
   {
     OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sys ${uimm-16} */
   {
     OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32,
-    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.nop */
   {
     OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.movhi $rD,$hi16 */
   {
     OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.mfsr $rD,$rA */
   {
     OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.mtsr $rA,$rB */
   {
     OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.lw $rD,${simm-16}($rA) */
   {
     OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.lbz $rD,${simm-16}($rA) */
   {
     OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.lbs $rD,${simm-16}($rA) */
   {
     OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.lhz $rD,${simm-16}($rA) */
   {
     OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.lhs $rD,${simm-16}($rA) */
   {
     OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sw ${ui16nc}($rA),$rB */
   {
     OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sb ${ui16nc}($rA),$rB */
   {
     OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sh ${ui16nc}($rA),$rB */
   {
     OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sll $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.slli $rD,$rA,${uimm-5} */
   {
     OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.srl $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.srli $rD,$rA,${uimm-5} */
   {
     OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sra $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.srai $rD,$rA,${uimm-5} */
   {
     OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.ror $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.rori $rD,$rA,${uimm-5} */
   {
     OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.add $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_ADD, "l-add", "l.add", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.addi $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sub $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.subi $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.and $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_AND, "l-and", "l.and", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.andi $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.or $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_OR, "l-or", "l.or", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.ori $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.xor $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.xori $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.mul $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.muli $rD,$rA,$lo16 */
   {
     OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.div $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_DIV, "l-div", "l.div", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.divu $rD,$rA,$rB */
   {
     OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgts $rA,$rB */
   {
     OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgtu $rA,$rB */
   {
     OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfges $rA,$rB */
   {
     OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgeu $rA,$rB */
   {
     OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sflts $rA,$rB */
   {
     OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfltu $rA,$rB */
   {
     OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfles $rA,$rB */
   {
     OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfleu $rA,$rB */
   {
     OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgtsi $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgtui $rA,${uimm-16} */
   {
     OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgesi $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfgeui $rA,${uimm-16} */
   {
     OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfltsi $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfltui $rA,${uimm-16} */
   {
     OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sflesi $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfleui $rA,${uimm-16} */
   {
     OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfeq $rA,$rB */
   {
     OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfeqi $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfne $rA,$rB */
   {
     OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* l.sfnei $rA,${simm-16} */
   {
     OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
-    { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
@@ -814,7 +814,7 @@ static void
 openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -826,7 +826,7 @@ openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
 
@@ -911,7 +911,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -930,7 +930,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -961,9 +961,6 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -971,7 +968,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h
index b47da960eae..dd0ccf8b2a7 100644
--- a/opcodes/openrisc-desc.h
+++ b/opcodes/openrisc-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef OPENRISC_CPU_H
 #define OPENRISC_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH openrisc
 
 /* Given symbol S, return openrisc_cgen_<S>.  */
@@ -154,6 +156,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for openrisc ifield types.  */
 typedef enum ifield_type {
   OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB
@@ -179,6 +190,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for openrisc hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -201,6 +219,17 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
 /* Enum declaration for openrisc operand types.  */
 typedef enum cgen_operand_type {
   OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16
@@ -229,6 +258,20 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
index cb3f99b82e0..d3c4f681d95 100644
--- a/opcodes/openrisc-dis.c
+++ b/opcodes/openrisc-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -443,7 +443,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -455,11 +455,12 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -482,25 +483,34 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -516,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -529,7 +539,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c
index 58aed98c667..ff9d52c37d8 100644
--- a/opcodes/openrisc-opc.c
+++ b/opcodes/openrisc-opc.c
@@ -560,7 +560,7 @@ static const CGEN_IBASE openrisc_cgen_macro_insn_table[] =
 /* l.ret */
   {
     -1, "l-ret", "l.ret", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index 278ae95f6cd..a2112677efc 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -5,6 +5,7 @@ arc-ext.c
 arc-opc.c
 arm-dis.c
 avr-dis.c
+bfin-dis.c
 cgen-asm.c
 cgen-dis.c
 cgen-opc.c
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index 12fdd5c2ef3..e387290cd4a 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2005-07-11 09:24-0500\n"
+"POT-Creation-Date: 2005-10-25 10:50+0930\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -110,23 +110,23 @@ msgstr ""
 msgid "must specify .jd or no nullify suffix"
 msgstr ""
 
-#: arm-dis.c:1505
+#: arm-dis.c:1302
 msgid "<illegal precision>"
 msgstr ""
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:2551
+#: arm-dis.c:2746
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
 #. XXX - should break 'option' at following delimiter.
-#: arm-dis.c:2559
+#: arm-dis.c:2754
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:2721
+#: arm-dis.c:2916
 #, c-format
 msgid ""
 "\n"
@@ -150,7 +150,7 @@ msgid "unknown constraint `%c'"
 msgstr ""
 
 #: cgen-asm.c:336 fr30-ibld.c:192 frv-ibld.c:192 ip2k-ibld.c:192
-#: iq2000-ibld.c:192 m32c-ibld.c:197 m32r-ibld.c:192 ms1-ibld.c:192
+#: iq2000-ibld.c:192 m32c-ibld.c:192 m32r-ibld.c:192 ms1-ibld.c:192
 #: openrisc-ibld.c:192 xstormy16-ibld.c:192
 #, c-format
 msgid "operand out of range (%ld not between %ld and %ld)"
@@ -177,7 +177,7 @@ msgstr ""
 msgid "Address 0x%s is out of bounds.\n"
 msgstr ""
 
-#: fr30-asm.c:92 m32c-asm.c:872 m32c-asm.c:879
+#: fr30-asm.c:92 m32c-asm.c:782 m32c-asm.c:789
 msgid "Register number is not valid"
 msgstr ""
 
@@ -189,19 +189,19 @@ msgstr ""
 msgid "Register must be between r8 and r15"
 msgstr ""
 
-#: fr30-asm.c:115 m32c-asm.c:910
+#: fr30-asm.c:115 m32c-asm.c:820
 msgid "Register list is not valid"
 msgstr ""
 
 #: fr30-asm.c:309 frv-asm.c:1262 ip2k-asm.c:510 iq2000-asm.c:456
-#: m32c-asm.c:1564 m32r-asm.c:327 ms1-asm.c:546 openrisc-asm.c:240
+#: m32c-asm.c:1476 m32r-asm.c:323 ms1-asm.c:546 openrisc-asm.c:240
 #: xstormy16-asm.c:275
 #, c-format
 msgid "Unrecognized field %d while parsing.\n"
 msgstr ""
 
 #: fr30-asm.c:357 frv-asm.c:1310 ip2k-asm.c:558 iq2000-asm.c:504
-#: m32c-asm.c:1613 m32r-asm.c:375 ms1-asm.c:594 openrisc-asm.c:288
+#: m32c-asm.c:1524 m32r-asm.c:371 ms1-asm.c:594 openrisc-asm.c:288
 #: xstormy16-asm.c:323
 msgid "missing mnemonic in syntax string"
 msgstr ""
@@ -210,9 +210,9 @@ msgstr ""
 #: fr30-asm.c:492 fr30-asm.c:496 fr30-asm.c:583 fr30-asm.c:684 frv-asm.c:1445
 #: frv-asm.c:1449 frv-asm.c:1536 frv-asm.c:1637 ip2k-asm.c:693 ip2k-asm.c:697
 #: ip2k-asm.c:784 ip2k-asm.c:885 iq2000-asm.c:639 iq2000-asm.c:643
-#: iq2000-asm.c:730 iq2000-asm.c:831 m32c-asm.c:1748 m32c-asm.c:1752
-#: m32c-asm.c:1839 m32c-asm.c:1940 m32r-asm.c:510 m32r-asm.c:514
-#: m32r-asm.c:601 m32r-asm.c:702 ms1-asm.c:729 ms1-asm.c:733 ms1-asm.c:820
+#: iq2000-asm.c:730 iq2000-asm.c:831 m32c-asm.c:1659 m32c-asm.c:1663
+#: m32c-asm.c:1750 m32c-asm.c:1851 m32r-asm.c:506 m32r-asm.c:510
+#: m32r-asm.c:597 m32r-asm.c:698 ms1-asm.c:729 ms1-asm.c:733 ms1-asm.c:820
 #: ms1-asm.c:921 openrisc-asm.c:423 openrisc-asm.c:427 openrisc-asm.c:514
 #: openrisc-asm.c:615 xstormy16-asm.c:458 xstormy16-asm.c:462
 #: xstormy16-asm.c:549 xstormy16-asm.c:650
@@ -220,40 +220,40 @@ msgid "unrecognized instruction"
 msgstr ""
 
 #: fr30-asm.c:539 frv-asm.c:1492 ip2k-asm.c:740 iq2000-asm.c:686
-#: m32c-asm.c:1795 m32r-asm.c:557 ms1-asm.c:776 openrisc-asm.c:470
+#: m32c-asm.c:1706 m32r-asm.c:553 ms1-asm.c:776 openrisc-asm.c:470
 #: xstormy16-asm.c:505
 #, c-format
 msgid "syntax error (expected char `%c', found `%c')"
 msgstr ""
 
 #: fr30-asm.c:549 frv-asm.c:1502 ip2k-asm.c:750 iq2000-asm.c:696
-#: m32c-asm.c:1805 m32r-asm.c:567 ms1-asm.c:786 openrisc-asm.c:480
+#: m32c-asm.c:1716 m32r-asm.c:563 ms1-asm.c:786 openrisc-asm.c:480
 #: xstormy16-asm.c:515
 #, c-format
 msgid "syntax error (expected char `%c', found end of instruction)"
 msgstr ""
 
 #: fr30-asm.c:577 frv-asm.c:1530 ip2k-asm.c:778 iq2000-asm.c:724
-#: m32c-asm.c:1833 m32r-asm.c:595 ms1-asm.c:814 openrisc-asm.c:508
+#: m32c-asm.c:1744 m32r-asm.c:591 ms1-asm.c:814 openrisc-asm.c:508
 #: xstormy16-asm.c:543
 msgid "junk at end of line"
 msgstr ""
 
 #: fr30-asm.c:683 frv-asm.c:1636 ip2k-asm.c:884 iq2000-asm.c:830
-#: m32c-asm.c:1939 m32r-asm.c:701 ms1-asm.c:920 openrisc-asm.c:614
+#: m32c-asm.c:1850 m32r-asm.c:697 ms1-asm.c:920 openrisc-asm.c:614
 #: xstormy16-asm.c:649
 msgid "unrecognized form of instruction"
 msgstr ""
 
 #: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:842
-#: m32c-asm.c:1951 m32r-asm.c:713 ms1-asm.c:932 openrisc-asm.c:626
+#: m32c-asm.c:1862 m32r-asm.c:709 ms1-asm.c:932 openrisc-asm.c:626
 #: xstormy16-asm.c:661
 #, c-format
 msgid "bad instruction `%.50s...'"
 msgstr ""
 
 #: fr30-asm.c:698 frv-asm.c:1651 ip2k-asm.c:899 iq2000-asm.c:845
-#: m32c-asm.c:1954 m32r-asm.c:716 ms1-asm.c:935 openrisc-asm.c:629
+#: m32c-asm.c:1865 m32r-asm.c:712 ms1-asm.c:935 openrisc-asm.c:629
 #: xstormy16-asm.c:664
 #, c-format
 msgid "bad instruction `%.50s'"
@@ -266,63 +266,63 @@ msgstr ""
 msgid "*unknown*"
 msgstr ""
 
-#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:868
+#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:860
 #: m32r-dis.c:256 ms1-dis.c:258 openrisc-dis.c:135 xstormy16-dis.c:168
 #, c-format
 msgid "Unrecognized field %d while printing insn.\n"
 msgstr ""
 
 #: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163
-#: m32c-ibld.c:168 m32r-ibld.c:163 ms1-ibld.c:163 openrisc-ibld.c:163
+#: m32c-ibld.c:163 m32r-ibld.c:163 ms1-ibld.c:163 openrisc-ibld.c:163
 #: xstormy16-ibld.c:163
 #, c-format
 msgid "operand out of range (%ld not between %ld and %lu)"
 msgstr ""
 
 #: fr30-ibld.c:176 frv-ibld.c:176 ip2k-ibld.c:176 iq2000-ibld.c:176
-#: m32c-ibld.c:181 m32r-ibld.c:176 ms1-ibld.c:176 openrisc-ibld.c:176
+#: m32c-ibld.c:176 m32r-ibld.c:176 ms1-ibld.c:176 openrisc-ibld.c:176
 #: xstormy16-ibld.c:176
 #, c-format
 msgid "operand out of range (%lu not between 0 and %lu)"
 msgstr ""
 
 #: fr30-ibld.c:719 frv-ibld.c:845 ip2k-ibld.c:596 iq2000-ibld.c:702
-#: m32c-ibld.c:1672 m32r-ibld.c:654 ms1-ibld.c:713 openrisc-ibld.c:622
+#: m32c-ibld.c:1668 m32r-ibld.c:654 ms1-ibld.c:713 openrisc-ibld.c:622
 #: xstormy16-ibld.c:667
 #, c-format
 msgid "Unrecognized field %d while building insn.\n"
 msgstr ""
 
 #: fr30-ibld.c:924 frv-ibld.c:1162 ip2k-ibld.c:671 iq2000-ibld.c:877
-#: m32c-ibld.c:2778 m32r-ibld.c:791 ms1-ibld.c:907 openrisc-ibld.c:722
+#: m32c-ibld.c:2780 m32r-ibld.c:791 ms1-ibld.c:907 openrisc-ibld.c:722
 #: xstormy16-ibld.c:813
 #, c-format
 msgid "Unrecognized field %d while decoding insn.\n"
 msgstr ""
 
 #: fr30-ibld.c:1070 frv-ibld.c:1440 ip2k-ibld.c:745 iq2000-ibld.c:1008
-#: m32c-ibld.c:3377 m32r-ibld.c:904 ms1-ibld.c:1086 openrisc-ibld.c:799
+#: m32c-ibld.c:3379 m32r-ibld.c:904 ms1-ibld.c:1086 openrisc-ibld.c:799
 #: xstormy16-ibld.c:923
 #, c-format
 msgid "Unrecognized field %d while getting int operand.\n"
 msgstr ""
 
 #: fr30-ibld.c:1198 frv-ibld.c:1700 ip2k-ibld.c:801 iq2000-ibld.c:1121
-#: m32c-ibld.c:3956 m32r-ibld.c:999 ms1-ibld.c:1247 openrisc-ibld.c:858
+#: m32c-ibld.c:3960 m32r-ibld.c:999 ms1-ibld.c:1247 openrisc-ibld.c:858
 #: xstormy16-ibld.c:1015
 #, c-format
 msgid "Unrecognized field %d while getting vma operand.\n"
 msgstr ""
 
 #: fr30-ibld.c:1329 frv-ibld.c:1967 ip2k-ibld.c:860 iq2000-ibld.c:1241
-#: m32c-ibld.c:4525 m32r-ibld.c:1100 ms1-ibld.c:1415 openrisc-ibld.c:924
+#: m32c-ibld.c:4529 m32r-ibld.c:1100 ms1-ibld.c:1415 openrisc-ibld.c:924
 #: xstormy16-ibld.c:1114
 #, c-format
 msgid "Unrecognized field %d while setting int operand.\n"
 msgstr ""
 
 #: fr30-ibld.c:1450 frv-ibld.c:2224 ip2k-ibld.c:909 iq2000-ibld.c:1351
-#: m32c-ibld.c:5082 m32r-ibld.c:1191 ms1-ibld.c:1573 openrisc-ibld.c:980
+#: m32c-ibld.c:5088 m32r-ibld.c:1191 ms1-ibld.c:1573 openrisc-ibld.c:980
 #: xstormy16-ibld.c:1203
 #, c-format
 msgid "Unrecognized field %d while setting vma operand.\n"
@@ -346,7 +346,8 @@ msgstr ""
 
 #. -- assembler routines inserted here.
 #. -- asm.c
-#: frv-asm.c:971 iq2000-asm.c:55 m32r-asm.c:52 openrisc-asm.c:53
+#: frv-asm.c:971 iq2000-asm.c:55 m32c-asm.c:140 m32c-asm.c:211 m32c-asm.c:253
+#: m32c-asm.c:312 m32c-asm.c:334 m32r-asm.c:52 openrisc-asm.c:53
 msgid "missing `)'"
 msgstr ""
 
@@ -371,7 +372,7 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:1737
+#: i386-dis.c:1742
 msgid "<internal disassembler error>"
 msgstr ""
 
@@ -555,46 +556,68 @@ msgstr ""
 msgid "unknown\t0x%02lx"
 msgstr ""
 
-#: m32c-asm.c:100
+#: m32c-asm.c:116
 msgid "imm:6 immediate is out of range"
 msgstr ""
 
-#: m32c-asm.c:127 m32c-asm.c:131 m32c-asm.c:187
+#: m32c-asm.c:146
+#, c-format
+msgid "%dsp8() takes a symbolic address, not a number"
+msgstr ""
+
+#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:229
 msgid "dsp:8 immediate is out of range"
 msgstr ""
 
-#: m32c-asm.c:158 m32c-asm.c:162
+#: m32c-asm.c:184 m32c-asm.c:188
 msgid "Immediate is out of range -8 to 7"
 msgstr ""
 
-#: m32c-asm.c:218 m32c-asm.c:225 m32c-asm.c:250
+#: m32c-asm.c:259
+#, c-format
+msgid "%dsp16() takes a symbolic address, not a number"
+msgstr ""
+
+#: m32c-asm.c:282 m32c-asm.c:289 m32c-asm.c:352
 msgid "dsp:16 immediate is out of range"
 msgstr ""
 
-#: m32c-asm.c:276
+#: m32c-asm.c:378
 msgid "dsp:20 immediate is out of range"
 msgstr ""
 
-#: m32c-asm.c:302
+#: m32c-asm.c:404
 msgid "dsp:24 immediate is out of range"
 msgstr ""
 
-#: m32c-asm.c:355
+#: m32c-asm.c:437
 msgid "immediate is out of range 1-2"
 msgstr ""
 
-#: m32c-asm.c:383
+#: m32c-asm.c:455
 msgid "immediate is out of range 1-8"
 msgstr ""
 
-#: m32c-asm.c:407
+#: m32c-asm.c:491
+msgid "immediate is out of range 2-9"
+msgstr ""
+
+#: m32c-asm.c:509
 msgid "Bit number for indexing general register is out of range 0-15"
 msgstr ""
 
-#: m32c-asm.c:445 m32c-asm.c:486
+#: m32c-asm.c:541 m32c-asm.c:576
 msgid "bit,base is out of range"
 msgstr ""
 
+#: m32c-asm.c:712
+msgid "not a valid r0l/r0h pair"
+msgstr ""
+
+#: m32c-asm.c:742
+msgid "Invalid size specifier"
+msgstr ""
+
 #: m68k-dis.c:1162
 #, c-format
 msgid "<function code %d>"
@@ -614,22 +637,22 @@ msgstr ""
 msgid "# internal error, incomplete extension sequence (+)"
 msgstr ""
 
-#: mips-dis.c:777
+#: mips-dis.c:805
 #, c-format
 msgid "# internal error, undefined extension sequence (+%c)"
 msgstr ""
 
-#: mips-dis.c:1038
+#: mips-dis.c:1153
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
 msgstr ""
 
-#: mips-dis.c:1548
+#: mips-dis.c:1663
 #, c-format
 msgid "# internal disassembler error, unrecognised modifier (%c)"
 msgstr ""
 
-#: mips-dis.c:1779
+#: mips-dis.c:1894
 #, c-format
 msgid ""
 "\n"
@@ -637,7 +660,7 @@ msgid ""
 "with the -M switch (multiple options should be separated by commas):\n"
 msgstr ""
 
-#: mips-dis.c:1783
+#: mips-dis.c:1898
 #, c-format
 msgid ""
 "\n"
@@ -645,7 +668,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1787
+#: mips-dis.c:1902
 #, c-format
 msgid ""
 "\n"
@@ -653,7 +676,7 @@ msgid ""
 "                           Default: numeric.\n"
 msgstr ""
 
-#: mips-dis.c:1791
+#: mips-dis.c:1906
 #, c-format
 msgid ""
 "\n"
@@ -662,7 +685,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1796
+#: mips-dis.c:1911
 #, c-format
 msgid ""
 "\n"
@@ -671,7 +694,7 @@ msgid ""
 "                           Default: based on binary being disassembled.\n"
 msgstr ""
 
-#: mips-dis.c:1801
+#: mips-dis.c:1916
 #, c-format
 msgid ""
 "\n"
@@ -679,7 +702,7 @@ msgid ""
 "                           specified ABI.\n"
 msgstr ""
 
-#: mips-dis.c:1805
+#: mips-dis.c:1920
 #, c-format
 msgid ""
 "\n"
@@ -687,7 +710,7 @@ msgid ""
 "                           specified architecture.\n"
 msgstr ""
 
-#: mips-dis.c:1809
+#: mips-dis.c:1924
 #, c-format
 msgid ""
 "\n"
@@ -695,12 +718,12 @@ msgid ""
 "   "
 msgstr ""
 
-#: mips-dis.c:1814 mips-dis.c:1822 mips-dis.c:1824
+#: mips-dis.c:1929 mips-dis.c:1937 mips-dis.c:1939
 #, c-format
 msgid "\n"
 msgstr ""
 
-#: mips-dis.c:1816
+#: mips-dis.c:1931
 #, c-format
 msgid ""
 "\n"
diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
index a63a4518499..80c7bf92984 100644
--- a/opcodes/xstormy16-desc.c
+++ b/opcodes/xstormy16-desc.c
@@ -126,24 +126,24 @@ static const CGEN_MACH xstormy16_cgen_mach_table[] = {
 
 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
 {
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 },
-  { "psw", 14, {0, {0}}, 0, 0 },
-  { "sp", 15, {0, {0}}, 0, 0 }
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
@@ -155,16 +155,16 @@ CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
 
 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
 {
-  { "r8", 0, {0, {0}}, 0, 0 },
-  { "r9", 1, {0, {0}}, 0, 0 },
-  { "r10", 2, {0, {0}}, 0, 0 },
-  { "r11", 3, {0, {0}}, 0, 0 },
-  { "r12", 4, {0, {0}}, 0, 0 },
-  { "r13", 5, {0, {0}}, 0, 0 },
-  { "r14", 6, {0, {0}}, 0, 0 },
-  { "r15", 7, {0, {0}}, 0, 0 },
-  { "psw", 6, {0, {0}}, 0, 0 },
-  { "sp", 7, {0, {0}}, 0, 0 }
+  { "r8", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 7, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
@@ -176,22 +176,22 @@ CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
 
 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
 {
-  { "ge", 0, {0, {0}}, 0, 0 },
-  { "nc", 1, {0, {0}}, 0, 0 },
-  { "lt", 2, {0, {0}}, 0, 0 },
-  { "c", 3, {0, {0}}, 0, 0 },
-  { "gt", 4, {0, {0}}, 0, 0 },
-  { "hi", 5, {0, {0}}, 0, 0 },
-  { "le", 6, {0, {0}}, 0, 0 },
-  { "ls", 7, {0, {0}}, 0, 0 },
-  { "pl", 8, {0, {0}}, 0, 0 },
-  { "nv", 9, {0, {0}}, 0, 0 },
-  { "mi", 10, {0, {0}}, 0, 0 },
-  { "v", 11, {0, {0}}, 0, 0 },
-  { "nz.b", 12, {0, {0}}, 0, 0 },
-  { "nz", 13, {0, {0}}, 0, 0 },
-  { "z.b", 14, {0, {0}}, 0, 0 },
-  { "z", 15, {0, {0}}, 0, 0 }
+  { "ge", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "hi", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "ls", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "pl", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "nv", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "mi", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "v", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 15, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
@@ -203,9 +203,9 @@ CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
 
 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
 {
-  { ".b", 0, {0, {0}}, 0, 0 },
-  { ".w", 1, {0, {0}}, 0, 0 },
-  { "", 1, {0, {0}}, 0, 0 }
+  { ".b", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".w", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
@@ -226,26 +226,26 @@ CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
 
 const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
-  { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
-  { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -261,44 +261,44 @@ const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
 
 const CGEN_IFLD xstormy16_cgen_ifld_table[] =
 {
-  { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
-  { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+  { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -337,163 +337,163 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-z8:  */
   { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-z16:  */
   { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-cy:  */
   { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-hc:  */
   { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-ov:  */
   { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-pt:  */
   { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw-s:  */
   { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rd: general register destination */
   { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rdm: general register destination */
   { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rm: general register for memory */
   { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rs: general register source */
   { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rb: base register */
   { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rbj: base register for jump */
   { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* bcond2: branch condition opcode */
   { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ws2: word size opcode */
   { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* bcond5: branch condition opcode */
   { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm2: 2 bit unsigned immediate */
   { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm3: 3 bit unsigned immediate */
   { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm3b: 3 bit unsigned immediate for bit tests */
   { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm4: 4 bit unsigned immediate */
   { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm8: 8 bit unsigned immediate */
   { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm8small: 8 bit unsigned immediate */
   { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm12: 12 bit signed immediate */
   { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } }, 
-    { 0, { (1<<MACH_BASE) } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16: 16 bit immediate */
   { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } }, 
-    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
+    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 /* lmem8: 8 bit unsigned immediate low memory */
   { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* hmem8: 8 bit unsigned immediate high memory */
   { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } }, 
-    { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rel8-2: 8 bit relative address */
   { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rel8-4: 8 bit relative address */
   { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rel12: 12 bit relative address */
   { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rel12a: 12 bit relative address */
   { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } }, 
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* abs24: 24 bit absolute address */
   { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
     { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } }, 
-    { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+    { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
 /* psw: program status word */
   { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* Rpsw: N0-N3 of the program status word */
   { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sp: stack pointer */
   { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* R0: R0 */
   { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* R1: R1 */
   { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* R2: R2 */
   { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* R8: R8 */
   { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
     { 0, { (const PTR) 0 } }, 
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
-    { 0, { 0 } } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
 };
 
 #undef A
@@ -513,646 +513,646 @@ static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 /* mov$ws2 $lmem8,#$imm16 */
   {
     XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $hmem8,#$imm16 */
   {
     XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rm,$lmem8 */
   {
     XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rm,$hmem8 */
   {
     XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $lmem8,$Rm */
   {
     XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $hmem8,$Rm */
   {
     XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,($Rs) */
   {
     XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,($Rs++) */
   {
     XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,(--$Rs) */
   {
     XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 ($Rs),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 ($Rs++),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 (--$Rs),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,($Rs,$imm12) */
   {
     XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,($Rs++,$imm12) */
   {
     XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 $Rdm,(--$Rs,$imm12) */
   {
     XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 ($Rs,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 ($Rs++,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov$ws2 (--$Rs,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Rd,$Rs */
   {
     XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.w Rx,#$imm8 */
   {
     XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.w $Rm,#$imm8small */
   {
     XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.w $Rd,#$imm16 */
   {
     XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.b $Rd,RxL */
   {
     XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov.b $Rd,RxH */
   {
     XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,($Rs) */
   {
     XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,($Rs++) */
   {
     XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,(--$Rs) */
   {
     XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 ($Rs),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 ($Rs++),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 (--$Rs),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
   {
     XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
   {
     XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
   {
     XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
   {
     XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mask $Rd,$Rs */
   {
     XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mask $Rd,#$imm16 */
   {
     XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* push $Rd */
   {
     XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* pop $Rd */
   {
     XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* swpn $Rd */
   {
     XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* swpb $Rd */
   {
     XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* swpw $Rd,$Rs */
   {
     XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and $Rd,$Rs */
   {
     XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and Rx,#$imm8 */
   {
     XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* and $Rd,#$imm16 */
   {
     XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $Rd,$Rs */
   {
     XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or Rx,#$imm8 */
   {
     XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* or $Rd,#$imm16 */
   {
     XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor $Rd,$Rs */
   {
     XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor Rx,#$imm8 */
   {
     XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* xor $Rd,#$imm16 */
   {
     XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* not $Rd */
   {
     XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $Rd,$Rs */
   {
     XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $Rd,#$imm4 */
   {
     XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add Rx,#$imm8 */
   {
     XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* add $Rd,#$imm16 */
   {
     XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* adc $Rd,$Rs */
   {
     XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* adc $Rd,#$imm4 */
   {
     XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* adc Rx,#$imm8 */
   {
     XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* adc $Rd,#$imm16 */
   {
     XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $Rd,$Rs */
   {
     XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $Rd,#$imm4 */
   {
     XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub Rx,#$imm8 */
   {
     XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sub $Rd,#$imm16 */
   {
     XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sbc $Rd,$Rs */
   {
     XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sbc $Rd,#$imm4 */
   {
     XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sbc Rx,#$imm8 */
   {
     XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sbc $Rd,#$imm16 */
   {
     XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* inc $Rd,#$imm2 */
   {
     XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dec $Rd,#$imm2 */
   {
     XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rrc $Rd,$Rs */
   {
     XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rrc $Rd,#$imm4 */
   {
     XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rlc $Rd,$Rs */
   {
     XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rlc $Rd,#$imm4 */
   {
     XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* shr $Rd,$Rs */
   {
     XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* shr $Rd,#$imm4 */
   {
     XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* shl $Rd,$Rs */
   {
     XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* shl $Rd,#$imm4 */
   {
     XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr $Rd,$Rs */
   {
     XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* asr $Rd,#$imm4 */
   {
     XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* set1 $Rd,#$imm4 */
   {
     XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* set1 $Rd,$Rs */
   {
     XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* set1 $lmem8,#$imm3 */
   {
     XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* set1 $hmem8,#$imm3 */
   {
     XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clr1 $Rd,#$imm4 */
   {
     XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clr1 $Rd,$Rs */
   {
     XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clr1 $lmem8,#$imm3 */
   {
     XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* clr1 $hmem8,#$imm3 */
   {
     XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* cbw $Rd */
   {
     XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* rev $Rd */
   {
     XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* b$bcond5 $Rd,$Rs,$rel12 */
   {
     XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* b$bcond5 $Rm,#$imm8,$rel12 */
   {
     XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* b$bcond2 Rx,#$imm16,${rel8-4} */
   {
     XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn $Rd,#$imm4,$rel12 */
   {
     XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn $Rd,$Rs,$rel12 */
   {
     XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn $lmem8,#$imm3b,$rel12 */
   {
     XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bn $hmem8,#$imm3b,$rel12 */
   {
     XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp $Rd,#$imm4,$rel12 */
   {
     XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp $Rd,$Rs,$rel12 */
   {
     XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp $lmem8,#$imm3b,$rel12 */
   {
     XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* bp $hmem8,#$imm3b,$rel12 */
   {
     XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* b$bcond2 ${rel8-2} */
   {
     XSTORMY16_INSN_BCC, "bcc", "b", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* br $Rd */
   {
     XSTORMY16_INSN_BGR, "bgr", "br", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* br $rel12a */
   {
     XSTORMY16_INSN_BR, "br", "br", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jmp $Rbj,$Rd */
   {
     XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* jmpf $abs24 */
   {
     XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* callr $Rd */
   {
     XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* callr $rel12a */
   {
     XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* call $Rbj,$Rd */
   {
     XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* callf $abs24 */
   {
     XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* icallr $Rd */
   {
     XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* icall $Rbj,$Rd */
   {
     XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* icallf $abs24 */
   {
     XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* iret */
   {
     XSTORMY16_INSN_IRET, "iret", "iret", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* ret */
   {
     XSTORMY16_INSN_RET, "ret", "ret", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mul */
   {
     XSTORMY16_INSN_MUL, "mul", "mul", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* div */
   {
     XSTORMY16_INSN_DIV, "div", "div", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sdiv */
   {
     XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* sdivlh */
   {
     XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* divlh */
   {
     XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* reset */
   {
     XSTORMY16_INSN_RESET, "reset", "reset", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* nop */
   {
     XSTORMY16_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* halt */
   {
     XSTORMY16_INSN_HALT, "halt", "halt", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* hold */
   {
     XSTORMY16_INSN_HOLD, "hold", "hold", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* holdx */
   {
     XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* brk */
   {
     XSTORMY16_INSN_BRK, "brk", "brk", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 /* --unused-- */
   {
     XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
@@ -1275,7 +1275,7 @@ static void
 xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 {
   int i;
-  unsigned int isas = cd->isas;
+  CGEN_BITSET *isas = cd->isas;
   unsigned int machs = cd->machs;
 
   cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1287,7 +1287,7 @@ xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   cd->max_insn_bitsize = 0;
   for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
+    if (cgen_bitset_contains (isas, i))
       {
 	const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
 
@@ -1372,7 +1372,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 {
   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   unsigned int machs = 0; /* 0 = "unspecified" */
   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   va_list ap;
@@ -1391,7 +1391,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       switch (arg_type)
 	{
 	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
+	  isas = va_arg (ap, CGEN_BITSET *);
 	  break;
 	case CGEN_CPU_OPEN_MACHS :
 	  machs = va_arg (ap, unsigned int);
@@ -1422,9 +1422,6 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
     machs = (1 << MAX_MACHS) - 1;
   /* Base mach is always selected.  */
   machs |= 1;
-  /* ISA unspecified means "all".  */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
@@ -1432,7 +1429,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
       abort ();
     }
 
-  cd->isas = isas;
+  cd->isas = cgen_bitset_copy (isas);
   cd->machs = machs;
   cd->endian = endian;
   /* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h
index 823a03ba3c1..4614fa5eb52 100644
--- a/opcodes/xstormy16-desc.h
+++ b/opcodes/xstormy16-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifndef XSTORMY16_CPU_H
 #define XSTORMY16_CPU_H
 
+#include "opcode/cgen-bitset.h"
+
 #define CGEN_ARCH xstormy16
 
 /* Given symbol S, return xstormy16_cgen_<S>.  */
@@ -184,6 +186,15 @@ typedef enum cgen_ifld_attr {
 /* Number of non-boolean elements in cgen_ifld_attr.  */
 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
 /* Enum declaration for xstormy16 ifield types.  */
 typedef enum ifield_type {
   XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM
@@ -211,6 +222,13 @@ typedef enum cgen_hw_attr {
 /* Number of non-boolean elements in cgen_hw_attr.  */
 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
 /* Enum declaration for xstormy16 hardware types.  */
 typedef enum cgen_hw_type {
   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -234,6 +252,17 @@ typedef enum cgen_operand_attr {
 /* Number of non-boolean elements in cgen_operand_attr.  */
 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
 /* Enum declaration for xstormy16 operand types.  */
 typedef enum cgen_operand_type {
   XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY
@@ -267,6 +296,19 @@ typedef enum cgen_insn_attr {
 /* Number of non-boolean elements in cgen_insn_attr.  */
 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+
 /* cgen.h uses things we just defined.  */
 #include "opcode/cgen.h"
 
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index 91cde6be6a9..aaff53f863d 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -4,7 +4,7 @@
    THIS FILE IS MACHINE GENERATED WITH CGEN.
    - the resultant file is machine generated, cgen-dis.in isn't
 
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -476,7 +476,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 typedef struct cpu_desc_list
 {
   struct cpu_desc_list *next;
-  int isa;
+  CGEN_BITSET *isa;
   int mach;
   int endian;
   CGEN_CPU_DESC cd;
@@ -488,11 +488,12 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
   static cpu_desc_list *cd_list = 0;
   cpu_desc_list *cl = 0;
   static CGEN_CPU_DESC cd = 0;
-  static int prev_isa;
+  static CGEN_BITSET *prev_isa;
   static int prev_mach;
   static int prev_endian;
   int length;
-  int isa,mach;
+  CGEN_BITSET *isa;
+  int mach;
   int endian = (info->endian == BFD_ENDIAN_BIG
 		? CGEN_ENDIAN_BIG
 		: CGEN_ENDIAN_LITTLE);
@@ -515,25 +516,34 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
 #endif
 
 #ifdef CGEN_COMPUTE_ISA
-  isa = CGEN_COMPUTE_ISA (info);
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
 #else
   isa = info->insn_sets;
 #endif
 
   /* If we've switched cpu's, try to find a handle we've used before */
   if (cd
-      && (isa != prev_isa
+      && (cgen_bitset_compare (isa, prev_isa) != 0
 	  || mach != prev_mach
 	  || endian != prev_endian))
     {
       cd = 0;
       for (cl = cd_list; cl; cl = cl->next)
 	{
-	  if (cl->isa == isa &&
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 	      cl->mach == mach &&
 	      cl->endian == endian)
 	    {
 	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
 	      break;
 	    }
 	}
@@ -549,7 +559,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
 	abort ();
       mach_name = arch_type->printable_name;
 
-      prev_isa = isa;
+      prev_isa = cgen_bitset_copy (isa);
       prev_mach = mach;
       prev_endian = endian;
       cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -562,7 +572,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
       /* Save this away for future reference.  */
       cl = xmalloc (sizeof (struct cpu_desc_list));
       cl->cd = cd;
-      cl->isa = isa;
+      cl->isa = prev_isa;
       cl->mach = mach;
       cl->endian = endian;
       cl->next = cd_list;
diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c
index 8237472f3aa..14823ee7ca1 100644
--- a/opcodes/xstormy16-opc.c
+++ b/opcodes/xstormy16-opc.c
@@ -1010,27 +1010,27 @@ static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] =
 /* mov Rx,#$imm8 */
   {
     -1, "movimm8", "mov", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Rm,#$imm8small */
   {
     -1, "movgrimm8", "mov", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* mov $Rd,#$imm16 */
   {
     -1, "movgrimm16", "mov", 32,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* inc $Rd */
   {
     -1, "incgr", "inc", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 /* dec $Rd */
   {
     -1, "decgr", "dec", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE) } }
+    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   },
 };
 
diff --git a/opcodes/z80-dis.c b/opcodes/z80-dis.c
new file mode 100644
index 00000000000..38ce4d11809
--- /dev/null
+++ b/opcodes/z80-dis.c
@@ -0,0 +1,620 @@
+/* Print Z80 and R800 instructions
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "sysdep.h"
+#include "dis-asm.h"
+#include <stdio.h>
+
+struct buffer
+{
+  bfd_vma base;
+  int n_fetch;
+  int n_used;
+  char data[4];
+} ;
+
+typedef int (*func)(struct buffer *, disassemble_info *, char *);
+
+struct tab_elt
+{
+  unsigned char val;
+  unsigned char mask;
+  func          fp;
+  char *        text;
+} ;
+
+#define TXTSIZ 16
+/* Names of 16-bit registers.  */
+static char * rr_str[] = { "bc", "de", "hl", "sp" };
+/* Names of 8-bit registers.  */
+static char * r_str[]  = { "b", "c", "d", "e", "h", "l", "(hl)", "a" };
+/* Texts for condition codes.  */
+static char * cc_str[] = { "nz", "z", "nc", "c", "po", "pe", "p", "m" };
+/* Instruction names for 8-bit arithmetic, operand "a" is often implicit */
+static char * arit_str[] =
+{
+  "add a,", "adc a,", "sub ", "sbc a,", "and ", "xor ", "or ", "cp "
+} ;
+
+static int
+fetch_data (struct buffer *buf, disassemble_info * info, int n)
+{
+  int r;
+
+  if (buf->n_fetch + n > 4)
+    abort ();
+
+  r = info->read_memory_func (buf->base + buf->n_fetch,
+			      buf->data + buf->n_fetch,
+			      n, info);
+  if (r == 0)
+    buf->n_fetch += n;
+  return !r;
+}
+
+static int
+prt (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, "%s", txt);
+  buf->n_used = buf->n_fetch;
+  return 1;
+}
+
+static int
+prt_e (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char e;
+  int target_addr;
+
+  if (fetch_data (buf, info, 1))
+    {
+      e = buf->data[1];
+      target_addr = (buf->base + 2 + e) & 0xffff;
+      buf->n_used = buf->n_fetch;
+      info->fprintf_func (info->stream, "%s0x%04x", txt, target_addr);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+static int
+jr_cc (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt, TXTSIZ, txt, cc_str[(buf->data[0] >> 3) & 3]);
+  return prt_e (buf, info, mytxt);
+}
+
+static int
+prt_nn (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  int nn;
+  unsigned char *p;
+
+  p = (unsigned char*) buf->data + buf->n_fetch;
+  if (fetch_data (buf, info, 2))
+    {
+      nn = p[0] + (p[1] << 8);
+      info->fprintf_func (info->stream, txt, nn);
+      buf->n_used = buf->n_fetch;
+    }
+  else
+    buf->n_used = -1;
+  return buf->n_used;
+}
+
+static int
+prt_rr_nn (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt, TXTSIZ, txt, rr_str[(buf->data[0] >> 4) & 3]);
+  return prt_nn (buf, info, mytxt);
+}
+
+static int
+prt_rr (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, "%s%s", txt,
+		      rr_str[(buf->data[buf->n_fetch - 1] >> 4) & 3]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+static int
+prt_n (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  int n;
+  unsigned char *p;
+
+  p = (unsigned char*) buf->data + buf->n_fetch;
+
+  if (fetch_data (buf, info, 1))
+    {
+      n = p[0];
+      info->fprintf_func (info->stream, txt, n);
+      buf->n_used = buf->n_fetch;
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+static int
+ld_r_n (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt, TXTSIZ, txt, r_str[(buf->data[0] >> 3) & 7]);
+  return prt_n (buf, info, mytxt);
+}
+
+static int
+prt_r (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, txt,
+		      r_str[(buf->data[buf->n_fetch - 1] >> 3) & 7]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+static int
+ld_r_r (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, txt,
+		      r_str[(buf->data[buf->n_fetch - 1] >> 3) & 7],
+		      r_str[buf->data[buf->n_fetch - 1] & 7]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+static int
+arit_r (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, txt,
+		      arit_str[(buf->data[buf->n_fetch - 1] >> 3) & 7],
+		      r_str[buf->data[buf->n_fetch - 1] & 7]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+static int
+prt_cc (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, "%s%s", txt,
+		      cc_str[(buf->data[0] >> 3) & 7]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+static int
+pop_rr (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  static char *rr_stack[] = { "bc","de","hl","af"};
+
+  info->fprintf_func (info->stream, "%s %s", txt,
+		      rr_stack[(buf->data[0] >> 4) & 3]);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+
+static int
+jp_cc_nn (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt,TXTSIZ,
+	    "%s%s,0x%%04x", txt, cc_str[(buf->data[0] >> 3) & 7]);
+  return prt_nn (buf, info, mytxt);
+}
+
+static int
+arit_n (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt,TXTSIZ, txt, arit_str[(buf->data[0] >> 3) & 7]);
+  return prt_n (buf, info, mytxt);
+}
+
+static int
+rst (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  info->fprintf_func (info->stream, txt, buf->data[0] & 0x38);
+  buf->n_used = buf->n_fetch;
+  return buf->n_used;
+}
+
+
+static int
+cis (struct buffer *buf, disassemble_info * info, char *txt ATTRIBUTE_UNUSED)
+{
+  static char * opar[] = { "ld", "cp", "in", "out" };
+  char * op;
+  char c;
+
+  c = buf->data[1];
+  op = ((0x13 & c) == 0x13) ? "ot" : (opar[c & 3]);
+  info->fprintf_func (info->stream,
+		      "%s%c%s", op,
+		      (c & 0x08) ? 'd' : 'i',
+		      (c & 0x10) ? "r" : "");
+  buf->n_used = 2;
+  return buf->n_used;
+}
+
+static int
+dump (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  int i;
+
+  info->fprintf_func (info->stream, "defb ");
+  for (i = 0; txt[i]; ++i)
+    info->fprintf_func (info->stream, i ? ", 0x%02x" : "0x%02x",
+			(unsigned char) buf->data[i]);
+  buf->n_used = i;
+  return buf->n_used;
+}
+
+/* Table to disassemble machine codes with prefix 0xED.  */
+struct tab_elt opc_ed[] =
+{
+  { 0x70, 0xFF, prt, "in f,(c)" },
+  { 0x70, 0xFF, dump, "xx" },
+  { 0x40, 0xC7, prt_r, "in %s,(c)" },
+  { 0x71, 0xFF, prt, "out (c),0" },
+  { 0x70, 0xFF, dump, "xx" },
+  { 0x41, 0xC7, prt_r, "out (c),%s" },
+  { 0x42, 0xCF, prt_rr, "sbc hl," },
+  { 0x43, 0xCF, prt_rr_nn, "ld (0x%%04x),%s" },
+  { 0x44, 0xFF, prt, "neg" },
+  { 0x45, 0xFF, prt, "retn" },
+  { 0x46, 0xFF, prt, "im 0" },
+  { 0x47, 0xFF, prt, "ld i,a" },
+  { 0x4A, 0xCF, prt_rr, "adc hl," },
+  { 0x4B, 0xCF, prt_rr_nn, "ld %s,(0x%%04x)" },
+  { 0x4D, 0xFF, prt, "reti" },
+  { 0x56, 0xFF, prt, "im 1" },
+  { 0x57, 0xFF, prt, "ld a,i" },
+  { 0x5E, 0xFF, prt, "im 2" },
+  { 0x67, 0xFF, prt, "rrd" },
+  { 0x6F, 0xFF, prt, "rld" },
+  { 0xA0, 0xE4, cis, "" },
+  { 0xC3, 0xFF, prt, "muluw hl,bc" },
+  { 0xC5, 0xE7, prt_r, "mulub a,%s" },
+  { 0xF3, 0xFF, prt, "muluw hl,sp" },
+  { 0x00, 0x00, dump, "xx" }
+};
+
+static int
+pref_ed (struct buffer * buf, disassemble_info * info, 
+	 char* txt ATTRIBUTE_UNUSED)
+{
+  struct tab_elt *p;
+
+  if (fetch_data(buf, info, 1))
+    {
+      for (p = opc_ed; p->val != (buf->data[1] & p->mask); ++p)
+	;
+      p->fp (buf, info, p->text);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+/* Instruction names for the instructions addressing single bits.  */
+static char *cb1_str[] = { "", "bit", "res", "set"};
+/* Instruction names for shifts and rotates.  */
+static char *cb2_str[] =
+{
+  "rlc", "rrc", "rl", "rr", "sla", "sra", "sli", "srl"
+};
+
+static int
+pref_cb (struct buffer * buf, disassemble_info * info,
+	 char* txt ATTRIBUTE_UNUSED)
+{
+  if (fetch_data (buf, info, 1))
+    {
+      buf->n_used = 2;
+      if ((buf->data[1] & 0xc0) == 0)
+	info->fprintf_func (info->stream, "%s %s",
+			    cb2_str[(buf->data[1] >> 3) & 7],
+			    r_str[buf->data[1] & 7]);
+      else
+	info->fprintf_func (info->stream, "%s %d,%s",
+			    cb1_str[(buf->data[1] >> 6) & 3],
+			    (buf->data[1] >> 3) & 7,
+			    r_str[buf->data[1] & 7]);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+static int
+addvv (struct buffer * buf, disassemble_info * info, char* txt)
+{
+  info->fprintf_func (info->stream, "add %s,%s", txt, txt);
+
+  return buf->n_used = buf->n_fetch;
+}
+
+static int
+ld_v_v (struct buffer * buf, disassemble_info * info, char* txt)
+{
+  char mytxt[TXTSIZ];
+
+  snprintf (mytxt, TXTSIZ, "ld %s%%s,%s%%s", txt, txt);
+  return ld_r_r (buf, info, mytxt);
+}
+
+static int
+prt_d (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  int d;
+  signed char *p;
+
+  p = (unsigned char*) buf->data + buf->n_fetch;
+
+  if (fetch_data (buf, info, 1))
+    {
+      d = p[0];
+      info->fprintf_func (info->stream, txt, d);
+      buf->n_used = buf->n_fetch;
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+static int
+prt_d_n (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+  int d;
+  signed char *p;
+
+  p = (unsigned char*) buf->data + buf->n_fetch;
+
+  if (fetch_data (buf, info, 1))
+    {
+      d = p[0];
+      snprintf (mytxt, TXTSIZ, txt, d);
+      return prt_n (buf, info, mytxt);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+static int
+arit_d (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+  unsigned char c;
+
+  c = buf->data[buf->n_fetch - 1];
+  snprintf (mytxt, TXTSIZ, txt, arit_str[(c >> 3) & 7]);
+  return prt_d (buf, info, mytxt);
+}
+
+static int
+ld_r_d (struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+  unsigned char c;
+
+  c = buf->data[buf->n_fetch - 1];
+  snprintf (mytxt, TXTSIZ, txt, r_str[(c >> 3) & 7]);
+  return prt_d (buf, info, mytxt);
+}
+
+static int
+ld_d_r(struct buffer *buf, disassemble_info * info, char *txt)
+{
+  char mytxt[TXTSIZ];
+  unsigned char c;
+
+  c = buf->data[buf->n_fetch - 1];
+  snprintf (mytxt, TXTSIZ, txt, r_str[c & 7]);
+  return prt_d (buf, info, mytxt);
+}
+
+static int
+pref_xd_cb (struct buffer * buf, disassemble_info * info, char* txt)
+{
+  if (fetch_data (buf, info, 2))
+    {
+      int d;
+      char arg[TXTSIZ];
+      signed char *p;
+
+      buf->n_used = 4;
+      p = buf->data;
+      d = p[2];
+
+      if (((p[3] & 0xC0) == 0x40) || ((p[3] & 7) == 0x06))
+	snprintf (arg, TXTSIZ, "(%s+%d)", txt, d);
+      else
+	snprintf (arg, TXTSIZ, "(%s+%d),%s", txt, d, r_str[p[3] & 7]);
+
+      if ((p[3] & 0xc0) == 0)
+	info->fprintf_func (info->stream, "%s %s",
+			    cb2_str[(buf->data[3] >> 3) & 7],
+			    arg);
+      else
+	info->fprintf_func (info->stream, "%s %d,%s",
+			    cb1_str[(buf->data[3] >> 6) & 3],
+			    (buf->data[3] >> 3) & 7,
+			    arg);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+/* Table to disassemble machine codes with prefix 0xDD or 0xFD.  */
+static struct tab_elt opc_ind[] =
+{
+  { 0x24, 0xF7, prt_r, "inc %s%%s" },
+  { 0x25, 0xF7, prt_r, "dec %s%%s" },
+  { 0x26, 0xF7, ld_r_n, "ld %s%%s,0x%%%%02x" },
+  { 0x21, 0xFF, prt_nn, "ld %s,0x%%04x" },
+  { 0x22, 0xFF, prt_nn, "ld (0x%%04x),%s" },
+  { 0x2A, 0xFF, prt_nn, "ld %s,(0x%%04x)" },
+  { 0x23, 0xFF, prt, "inc %s" },
+  { 0x2B, 0xFF, prt, "dec %s" },
+  { 0x29, 0xFF, addvv, "%s" },
+  { 0x09, 0xCF, prt_rr, "add %s," },
+  { 0x34, 0xFF, prt_d, "inc (%s+%%d)" },
+  { 0x35, 0xFF, prt_d, "dec (%s+%%d)" },
+  { 0x36, 0xFF, prt_d_n, "ld (%s+%%d),0x%%02x" },
+
+  { 0x76, 0xFF, dump, "h" },
+  { 0x46, 0xC7, ld_r_d, "ld %%s,(%s+%%%%d)" },
+  { 0x70, 0xF8, ld_d_r, "ld (%s+%%%%d),%%s" },
+  { 0x64, 0xF6, ld_v_v, "%s" },
+  { 0x60, 0xF0, ld_r_r, "ld %s%%s,%%s" },
+  { 0x44, 0xC6, ld_r_r, "ld %%s,%s%%s" },
+
+  { 0x86, 0xC7, arit_d, "%%s(%s+%%%%d)" },
+  { 0x84, 0xC6, arit_r, "%%s%s%%s" },
+
+  { 0xE1, 0xFF, prt, "pop %s" },
+  { 0xE5, 0xFF, prt, "push %s" },
+  { 0xCB, 0xFF, pref_xd_cb, "%s" },
+  { 0xE3, 0xFF, prt, "ex (sp),%s" },
+  { 0xE9, 0xFF, prt, "jp (%s)" },
+  { 0xF9, 0xFF, prt, "ld sp,%s" },
+  { 0x00, 0x00, dump, "?" },
+} ;
+
+static int
+pref_ind (struct buffer * buf, disassemble_info * info, char* txt)
+{
+  if (fetch_data (buf, info, 1))
+    {
+      char mytxt[TXTSIZ];
+      struct tab_elt *p;
+
+      for (p = opc_ind; p->val != (buf->data[1] & p->mask); ++p)
+	;
+      snprintf (mytxt, TXTSIZ, p->text, txt);
+      p->fp (buf, info, mytxt);
+    }
+  else
+    buf->n_used = -1;
+
+  return buf->n_used;
+}
+
+/* Table to disassemble machine codes without prefix.  */
+static struct tab_elt opc_main[] =
+{
+  { 0x00, 0xFF, prt, "nop" },
+  { 0x01, 0xCF, prt_rr_nn, "ld %s,0x%%04x" },
+  { 0x02, 0xFF, prt, "ld (bc),a" },
+  { 0x03, 0xCF, prt_rr, "inc " },
+  { 0x04, 0xC7, prt_r, "inc %s" },
+  { 0x05, 0xC7, prt_r, "dec %s" },
+  { 0x06, 0xC7, ld_r_n, "ld %s,0x%%02x" },
+  { 0x07, 0xFF, prt, "rlca" },
+  { 0x08, 0xFF, prt, "ex af,af'" },
+  { 0x09, 0xCF, prt_rr, "add hl," },
+  { 0x0A, 0xFF, prt, "ld a,(bc)" },
+  { 0x0B, 0xCF, prt_rr, "dec " },
+  { 0x0F, 0xFF, prt, "rrca" },
+  { 0x10, 0xFF, prt_e, "djnz " },
+  { 0x12, 0xFF, prt, "ld (de),a" },
+  { 0x17, 0xFF, prt, "rla" },
+  { 0x18, 0xFF, prt_e, "jr "},
+  { 0x1A, 0xFF, prt, "ld a,(de)" },
+  { 0x1F, 0xFF, prt, "rra" },
+  { 0x20, 0xE7, jr_cc, "jr %s,"},
+  { 0x22, 0xFF, prt_nn, "ld (0x%04x),hl" },
+  { 0x27, 0xFF, prt, "daa"},
+  { 0x2A, 0xFF, prt_nn, "ld hl,(0x%04x)" },
+  { 0x2F, 0xFF, prt, "cpl" },
+  { 0x32, 0xFF, prt_nn, "ld (0x%04x),a" },
+  { 0x37, 0xFF, prt, "scf" },
+  { 0x3A, 0xFF, prt_nn, "ld a,(0x%04x)" },
+  { 0x3F, 0xFF, prt, "ccf" },
+
+  { 0x76, 0xFF, prt, "halt" },
+  { 0x40, 0xC0, ld_r_r, "ld %s,%s"},
+
+  { 0x80, 0xC0, arit_r, "%s%s" },
+
+  { 0xC0, 0xC7, prt_cc, "ret " },
+  { 0xC1, 0xCF, pop_rr, "pop" },
+  { 0xC2, 0xC7, jp_cc_nn, "jp " },
+  { 0xC3, 0xFF, prt_nn, "jp 0x%04x" },
+  { 0xC4, 0xC7, jp_cc_nn, "call " },
+  { 0xC5, 0xCF, pop_rr, "push" },
+  { 0xC6, 0xC7, arit_n, "%s0x%%02x" },
+  { 0xC7, 0xC7, rst, "rst 0x%02x" },
+  { 0xC9, 0xFF, prt, "ret" },
+  { 0xCB, 0xFF, pref_cb, "" },
+  { 0xCD, 0xFF, prt_nn, "call 0x%04x" },
+  { 0xD3, 0xFF, prt_n, "out (0x%02x),a" },
+  { 0xD9, 0xFF, prt, "exx" },
+  { 0xDB, 0xFF, prt_n, "in a,(0x%02x)" },
+  { 0xDD, 0xFF, pref_ind, "ix" },
+  { 0xE3, 0xFF, prt, "ex (sp),hl" },
+  { 0xE9, 0xFF, prt, "jp (hl)" },
+  { 0xEB, 0xFF, prt, "ex de,hl" },
+  { 0xED, 0xFF, pref_ed, ""},
+  { 0xF3, 0xFF, prt, "di" },
+  { 0xF9, 0xFF, prt, "ld sp,hl" },
+  { 0xFB, 0xFF, prt, "ei" },
+  { 0xFD, 0xFF, pref_ind, "iy" },
+  { 0x00, 0x00, prt, "????" },
+} ;
+
+int
+print_insn_z80 (bfd_vma addr, disassemble_info * info)
+{
+  struct buffer buf;
+  struct tab_elt *p;
+
+  buf.base = addr;
+  buf.n_fetch = 0;
+  buf.n_used = 0;
+
+  if (! fetch_data (& buf, info, 1))
+    return -1;
+
+  for (p = opc_main; p->val != (buf.data[0] & p->mask); ++p)
+    ;
+  p->fp (& buf, info, p->text);
+
+  return buf.n_used;
+}
diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog
index bcf909d77b4..c9e74e903a2 100644
--- a/sim/frv/ChangeLog
+++ b/sim/frv/ChangeLog
@@ -1,3 +1,16 @@
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
+	
+	Contribute the following changes:
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* frv-sim.h: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
+	CGEN_ATTR_VALUE_TYPE.
+	* mloop.in: Ditto.
+	* pipeline.c: Ditto.
+	* traps.c: Ditto.
+
 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 
 	* configure: Regenerate.
diff --git a/sim/frv/arch.c b/sim/frv/arch.c
index a8fc4e9b4db..e8c73146a58 100644
--- a/sim/frv/arch.c
+++ b/sim/frv/arch.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/frv/arch.h b/sim/frv/arch.h
index 685496ba37e..afb484ab225 100644
--- a/sim/frv/arch.h
+++ b/sim/frv/arch.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/frv/cpu.c b/sim/frv/cpu.c
index 111ec333b60..b0de504af65 100644
--- a/sim/frv/cpu.c
+++ b/sim/frv/cpu.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -28,6 +28,22 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "sim-main.h"
 #include "cgen-ops.h"
 
+/* Get the value of h-reloc-ann.  */
+
+BI
+frvbf_h_reloc_ann_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_reloc_ann);
+}
+
+/* Set a value for h-reloc-ann.  */
+
+void
+frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_reloc_ann) = newval;
+}
+
 /* Get the value of h-pc.  */
 
 USI
diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h
index 006bb135789..310726685a8 100644
--- a/sim/frv/cpu.h
+++ b/sim/frv/cpu.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -36,6 +36,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 typedef struct {
   /* Hardware elements.  */
   struct {
+  /* relocation annotation */
+  BI h_reloc_ann;
+#define GET_H_RELOC_ANN() CPU (h_reloc_ann)
+#define SET_H_RELOC_ANN(x) (CPU (h_reloc_ann) = (x))
   /* program counter */
   USI h_pc;
 #define GET_H_PC() CPU (h_pc)
@@ -267,6 +271,8 @@ SET_H_SPR (((UINT) 281), TRUNCDISI ((x)));\
 ;} while (0)
 
 /* Cover fns for register access.  */
+BI frvbf_h_reloc_ann_get (SIM_CPU *);
+void frvbf_h_reloc_ann_set (SIM_CPU *, BI);
 USI frvbf_h_pc_get (SIM_CPU *);
 void frvbf_h_pc_set (SIM_CPU *, USI);
 UQI frvbf_h_psr_imple_get (SIM_CPU *);
diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h
index 7923b4a2e05..c49965271fa 100644
--- a/sim/frv/cpuall.h
+++ b/sim/frv/cpuall.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index 60c27eb836e..7dcf928bf7d 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -873,22 +873,70 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_ADD; goto extract_sfmt_add;
-          case 1 : itype = FRVBF_INSN_ADDCC; goto extract_sfmt_addcc;
-          case 2 : itype = FRVBF_INSN_ADDX; goto extract_sfmt_addx;
-          case 3 : itype = FRVBF_INSN_ADDXCC; goto extract_sfmt_addcc;
-          case 4 : itype = FRVBF_INSN_SUB; goto extract_sfmt_add;
-          case 5 : itype = FRVBF_INSN_SUBCC; goto extract_sfmt_addcc;
-          case 6 : itype = FRVBF_INSN_SUBX; goto extract_sfmt_addx;
-          case 7 : itype = FRVBF_INSN_SUBXCC; goto extract_sfmt_addcc;
-          case 8 : itype = FRVBF_INSN_SMUL; goto extract_sfmt_smul;
-          case 9 : itype = FRVBF_INSN_SMULCC; goto extract_sfmt_smulcc;
-          case 10 : itype = FRVBF_INSN_UMUL; goto extract_sfmt_smul;
-          case 11 : itype = FRVBF_INSN_UMULCC; goto extract_sfmt_smulcc;
-          case 12 : itype = FRVBF_INSN_CMPB; goto extract_sfmt_cmpb;
-          case 13 : itype = FRVBF_INSN_CMPBA; goto extract_sfmt_cmpb;
-          case 14 : itype = FRVBF_INSN_SDIV; goto extract_sfmt_sdiv;
-          case 15 : itype = FRVBF_INSN_UDIV; goto extract_sfmt_sdiv;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x0)
+              { itype = FRVBF_INSN_ADD; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc03c0) == 0x40)
+              { itype = FRVBF_INSN_ADDCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc03c0) == 0x80)
+              { itype = FRVBF_INSN_ADDX; goto extract_sfmt_addx; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc03c0) == 0xc0)
+              { itype = FRVBF_INSN_ADDXCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fc0) == 0x100)
+              { itype = FRVBF_INSN_SUB; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc03c0) == 0x140)
+              { itype = FRVBF_INSN_SUBCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc03c0) == 0x180)
+              { itype = FRVBF_INSN_SUBX; goto extract_sfmt_addx; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x1fc03c0) == 0x1c0)
+              { itype = FRVBF_INSN_SUBXCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0x200)
+              { itype = FRVBF_INSN_SMUL; goto extract_sfmt_smul; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc03c0) == 0x240)
+              { itype = FRVBF_INSN_SMULCC; goto extract_sfmt_smulcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1fc0fc0) == 0x280)
+              { itype = FRVBF_INSN_UMUL; goto extract_sfmt_smul; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc03c0) == 0x2c0)
+              { itype = FRVBF_INSN_UMULCC; goto extract_sfmt_smulcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x7ffc03c0) == 0x300)
+              { itype = FRVBF_INSN_CMPB; goto extract_sfmt_cmpb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x7ffc03c0) == 0x340)
+              { itype = FRVBF_INSN_CMPBA; goto extract_sfmt_cmpb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1fc0fc0) == 0x380)
+              { itype = FRVBF_INSN_SDIV; goto extract_sfmt_sdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1fc0fc0) == 0x3c0)
+              { itype = FRVBF_INSN_UDIV; goto extract_sfmt_sdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -897,21 +945,66 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_AND; goto extract_sfmt_add;
-          case 1 : itype = FRVBF_INSN_ANDCC; goto extract_sfmt_andcc;
-          case 2 : itype = FRVBF_INSN_OR; goto extract_sfmt_add;
-          case 3 : itype = FRVBF_INSN_ORCC; goto extract_sfmt_andcc;
-          case 4 : itype = FRVBF_INSN_XOR; goto extract_sfmt_add;
-          case 5 : itype = FRVBF_INSN_XORCC; goto extract_sfmt_andcc;
-          case 6 : itype = FRVBF_INSN_NOT; goto extract_sfmt_not;
-          case 8 : itype = FRVBF_INSN_SLL; goto extract_sfmt_add;
-          case 9 : itype = FRVBF_INSN_SLLCC; goto extract_sfmt_addcc;
-          case 10 : itype = FRVBF_INSN_SRL; goto extract_sfmt_add;
-          case 11 : itype = FRVBF_INSN_SRLCC; goto extract_sfmt_addcc;
-          case 12 : itype = FRVBF_INSN_SRA; goto extract_sfmt_add;
-          case 13 : itype = FRVBF_INSN_SRACC; goto extract_sfmt_addcc;
-          case 14 : itype = FRVBF_INSN_NSDIV; goto extract_sfmt_sdiv;
-          case 15 : itype = FRVBF_INSN_NUDIV; goto extract_sfmt_sdiv;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40000)
+              { itype = FRVBF_INSN_AND; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc03c0) == 0x40040)
+              { itype = FRVBF_INSN_ANDCC; goto extract_sfmt_andcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40080)
+              { itype = FRVBF_INSN_OR; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc03c0) == 0x400c0)
+              { itype = FRVBF_INSN_ORCC; goto extract_sfmt_andcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40100)
+              { itype = FRVBF_INSN_XOR; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc03c0) == 0x40140)
+              { itype = FRVBF_INSN_XORCC; goto extract_sfmt_andcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1ffffc0) == 0x40180)
+              { itype = FRVBF_INSN_NOT; goto extract_sfmt_not; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40200)
+              { itype = FRVBF_INSN_SLL; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc03c0) == 0x40240)
+              { itype = FRVBF_INSN_SLLCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40280)
+              { itype = FRVBF_INSN_SRL; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc03c0) == 0x402c0)
+              { itype = FRVBF_INSN_SRLCC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40300)
+              { itype = FRVBF_INSN_SRA; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x1fc03c0) == 0x40340)
+              { itype = FRVBF_INSN_SRACC; goto extract_sfmt_addcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1fc0fc0) == 0x40380)
+              { itype = FRVBF_INSN_NSDIV; goto extract_sfmt_sdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1fc0fc0) == 0x403c0)
+              { itype = FRVBF_INSN_NUDIV; goto extract_sfmt_sdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -920,60 +1013,222 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (63 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_LDSB; goto extract_sfmt_ldsb;
-          case 1 : itype = FRVBF_INSN_LDUB; goto extract_sfmt_ldsb;
-          case 2 : itype = FRVBF_INSN_LDSH; goto extract_sfmt_ldsb;
-          case 3 : itype = FRVBF_INSN_LDUH; goto extract_sfmt_ldsb;
-          case 4 : itype = FRVBF_INSN_LD; goto extract_sfmt_ldsb;
-          case 5 : itype = FRVBF_INSN_LDD; goto extract_sfmt_ldd;
-          case 6 : itype = FRVBF_INSN_LDQ; goto extract_sfmt_ldq;
-          case 8 : itype = FRVBF_INSN_LDBF; goto extract_sfmt_ldbf;
-          case 9 : itype = FRVBF_INSN_LDHF; goto extract_sfmt_ldbf;
-          case 10 : itype = FRVBF_INSN_LDF; goto extract_sfmt_ldbf;
-          case 11 : itype = FRVBF_INSN_LDDF; goto extract_sfmt_lddf;
-          case 12 : itype = FRVBF_INSN_LDQF; goto extract_sfmt_ldqf;
-          case 13 : itype = FRVBF_INSN_LDC; goto extract_sfmt_ldc;
-          case 14 : itype = FRVBF_INSN_LDDC; goto extract_sfmt_lddc;
-          case 15 : itype = FRVBF_INSN_LDQC; goto extract_sfmt_ldqc;
-          case 16 : itype = FRVBF_INSN_LDSBU; goto extract_sfmt_ldsbu;
-          case 17 : itype = FRVBF_INSN_LDUBU; goto extract_sfmt_ldsbu;
-          case 18 : itype = FRVBF_INSN_LDSHU; goto extract_sfmt_ldsbu;
-          case 19 : itype = FRVBF_INSN_LDUHU; goto extract_sfmt_ldsbu;
-          case 20 : itype = FRVBF_INSN_LDU; goto extract_sfmt_ldsbu;
-          case 21 : itype = FRVBF_INSN_LDDU; goto extract_sfmt_lddu;
-          case 22 : itype = FRVBF_INSN_LDQU; goto extract_sfmt_ldqu;
-          case 24 : itype = FRVBF_INSN_LDBFU; goto extract_sfmt_ldbfu;
-          case 25 : itype = FRVBF_INSN_LDHFU; goto extract_sfmt_ldbfu;
-          case 26 : itype = FRVBF_INSN_LDFU; goto extract_sfmt_ldbfu;
-          case 27 : itype = FRVBF_INSN_LDDFU; goto extract_sfmt_lddfu;
-          case 28 : itype = FRVBF_INSN_LDQFU; goto extract_sfmt_ldqfu;
-          case 29 : itype = FRVBF_INSN_LDCU; goto extract_sfmt_ldcu;
-          case 30 : itype = FRVBF_INSN_LDDCU; goto extract_sfmt_lddcu;
-          case 31 : itype = FRVBF_INSN_LDQCU; goto extract_sfmt_ldqcu;
-          case 32 : itype = FRVBF_INSN_NLDSB; goto extract_sfmt_nldsb;
-          case 33 : itype = FRVBF_INSN_NLDUB; goto extract_sfmt_nldsb;
-          case 34 : itype = FRVBF_INSN_NLDSH; goto extract_sfmt_nldsb;
-          case 35 : itype = FRVBF_INSN_NLDUH; goto extract_sfmt_nldsb;
-          case 36 : itype = FRVBF_INSN_NLD; goto extract_sfmt_nldsb;
-          case 37 : itype = FRVBF_INSN_NLDD; goto extract_sfmt_nldd;
-          case 38 : itype = FRVBF_INSN_NLDQ; goto extract_sfmt_nldq;
-          case 40 : itype = FRVBF_INSN_NLDBF; goto extract_sfmt_nldbf;
-          case 41 : itype = FRVBF_INSN_NLDHF; goto extract_sfmt_nldbf;
-          case 42 : itype = FRVBF_INSN_NLDF; goto extract_sfmt_nldbf;
-          case 43 : itype = FRVBF_INSN_NLDDF; goto extract_sfmt_nlddf;
-          case 44 : itype = FRVBF_INSN_NLDQF; goto extract_sfmt_nldqf;
-          case 48 : itype = FRVBF_INSN_NLDSBU; goto extract_sfmt_nldsbu;
-          case 49 : itype = FRVBF_INSN_NLDUBU; goto extract_sfmt_nldsbu;
-          case 50 : itype = FRVBF_INSN_NLDSHU; goto extract_sfmt_nldsbu;
-          case 51 : itype = FRVBF_INSN_NLDUHU; goto extract_sfmt_nldsbu;
-          case 52 : itype = FRVBF_INSN_NLDU; goto extract_sfmt_nldsbu;
-          case 53 : itype = FRVBF_INSN_NLDDU; goto extract_sfmt_nlddu;
-          case 54 : itype = FRVBF_INSN_NLDQU; goto extract_sfmt_nldqu;
-          case 56 : itype = FRVBF_INSN_NLDBFU; goto extract_sfmt_nldbfu;
-          case 57 : itype = FRVBF_INSN_NLDHFU; goto extract_sfmt_nldbfu;
-          case 58 : itype = FRVBF_INSN_NLDFU; goto extract_sfmt_nldbfu;
-          case 59 : itype = FRVBF_INSN_NLDDFU; goto extract_sfmt_nlddfu;
-          case 60 : itype = FRVBF_INSN_NLDQFU; goto extract_sfmt_nldqfu;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80000)
+              { itype = FRVBF_INSN_LDSB; goto extract_sfmt_ldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80040)
+              { itype = FRVBF_INSN_LDUB; goto extract_sfmt_ldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80080)
+              { itype = FRVBF_INSN_LDSH; goto extract_sfmt_ldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc0fc0) == 0x800c0)
+              { itype = FRVBF_INSN_LDUH; goto extract_sfmt_ldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80100)
+              { itype = FRVBF_INSN_LD; goto extract_sfmt_ldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80140)
+              { itype = FRVBF_INSN_LDD; goto extract_sfmt_ldd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80180)
+              { itype = FRVBF_INSN_LDQ; goto extract_sfmt_ldq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80200)
+              { itype = FRVBF_INSN_LDBF; goto extract_sfmt_ldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80240)
+              { itype = FRVBF_INSN_LDHF; goto extract_sfmt_ldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80280)
+              { itype = FRVBF_INSN_LDF; goto extract_sfmt_ldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc0fc0) == 0x802c0)
+              { itype = FRVBF_INSN_LDDF; goto extract_sfmt_lddf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80300)
+              { itype = FRVBF_INSN_LDQF; goto extract_sfmt_ldqf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80340)
+              { itype = FRVBF_INSN_LDC; goto extract_sfmt_ldc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80380)
+              { itype = FRVBF_INSN_LDDC; goto extract_sfmt_lddc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1fc0fc0) == 0x803c0)
+              { itype = FRVBF_INSN_LDQC; goto extract_sfmt_ldqc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80400)
+              { itype = FRVBF_INSN_LDSBU; goto extract_sfmt_ldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80440)
+              { itype = FRVBF_INSN_LDUBU; goto extract_sfmt_ldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 18 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80480)
+              { itype = FRVBF_INSN_LDSHU; goto extract_sfmt_ldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x1fc0fc0) == 0x804c0)
+              { itype = FRVBF_INSN_LDUHU; goto extract_sfmt_ldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80500)
+              { itype = FRVBF_INSN_LDU; goto extract_sfmt_ldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80540)
+              { itype = FRVBF_INSN_LDDU; goto extract_sfmt_lddu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 22 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80580)
+              { itype = FRVBF_INSN_LDQU; goto extract_sfmt_ldqu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80600)
+              { itype = FRVBF_INSN_LDBFU; goto extract_sfmt_ldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80640)
+              { itype = FRVBF_INSN_LDHFU; goto extract_sfmt_ldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 26 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80680)
+              { itype = FRVBF_INSN_LDFU; goto extract_sfmt_ldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 27 :
+            if ((entire_insn & 0x1fc0fc0) == 0x806c0)
+              { itype = FRVBF_INSN_LDDFU; goto extract_sfmt_lddfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80700)
+              { itype = FRVBF_INSN_LDQFU; goto extract_sfmt_ldqfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 29 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80740)
+              { itype = FRVBF_INSN_LDCU; goto extract_sfmt_ldcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 30 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80780)
+              { itype = FRVBF_INSN_LDDCU; goto extract_sfmt_lddcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 31 :
+            if ((entire_insn & 0x1fc0fc0) == 0x807c0)
+              { itype = FRVBF_INSN_LDQCU; goto extract_sfmt_ldqcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80800)
+              { itype = FRVBF_INSN_NLDSB; goto extract_sfmt_nldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80840)
+              { itype = FRVBF_INSN_NLDUB; goto extract_sfmt_nldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 34 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80880)
+              { itype = FRVBF_INSN_NLDSH; goto extract_sfmt_nldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 35 :
+            if ((entire_insn & 0x1fc0fc0) == 0x808c0)
+              { itype = FRVBF_INSN_NLDUH; goto extract_sfmt_nldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80900)
+              { itype = FRVBF_INSN_NLD; goto extract_sfmt_nldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80940)
+              { itype = FRVBF_INSN_NLDD; goto extract_sfmt_nldd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 38 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80980)
+              { itype = FRVBF_INSN_NLDQ; goto extract_sfmt_nldq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 40 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80a00)
+              { itype = FRVBF_INSN_NLDBF; goto extract_sfmt_nldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 41 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80a40)
+              { itype = FRVBF_INSN_NLDHF; goto extract_sfmt_nldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 42 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80a80)
+              { itype = FRVBF_INSN_NLDF; goto extract_sfmt_nldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 43 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80ac0)
+              { itype = FRVBF_INSN_NLDDF; goto extract_sfmt_nlddf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 44 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80b00)
+              { itype = FRVBF_INSN_NLDQF; goto extract_sfmt_nldqf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 48 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80c00)
+              { itype = FRVBF_INSN_NLDSBU; goto extract_sfmt_nldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 49 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80c40)
+              { itype = FRVBF_INSN_NLDUBU; goto extract_sfmt_nldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 50 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80c80)
+              { itype = FRVBF_INSN_NLDSHU; goto extract_sfmt_nldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 51 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80cc0)
+              { itype = FRVBF_INSN_NLDUHU; goto extract_sfmt_nldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 52 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80d00)
+              { itype = FRVBF_INSN_NLDU; goto extract_sfmt_nldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 53 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80d40)
+              { itype = FRVBF_INSN_NLDDU; goto extract_sfmt_nlddu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 54 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80d80)
+              { itype = FRVBF_INSN_NLDQU; goto extract_sfmt_nldqu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 56 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80e00)
+              { itype = FRVBF_INSN_NLDBFU; goto extract_sfmt_nldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 57 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80e40)
+              { itype = FRVBF_INSN_NLDHFU; goto extract_sfmt_nldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 58 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80e80)
+              { itype = FRVBF_INSN_NLDFU; goto extract_sfmt_nldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 59 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80ec0)
+              { itype = FRVBF_INSN_NLDDFU; goto extract_sfmt_nlddfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 60 :
+            if ((entire_insn & 0x1fc0fc0) == 0x80f00)
+              { itype = FRVBF_INSN_NLDQFU; goto extract_sfmt_nldqfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -982,60 +1237,222 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (63 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_STB; goto extract_sfmt_stb;
-          case 1 : itype = FRVBF_INSN_STH; goto extract_sfmt_stb;
-          case 2 : itype = FRVBF_INSN_ST; goto extract_sfmt_stb;
-          case 3 : itype = FRVBF_INSN_STD; goto extract_sfmt_std;
-          case 4 : itype = FRVBF_INSN_STQ; goto extract_sfmt_ldq;
-          case 5 : itype = FRVBF_INSN_SWAP; goto extract_sfmt_swap;
-          case 6 : itype = FRVBF_INSN_MOVGS; goto extract_sfmt_movgs;
-          case 7 : itype = FRVBF_INSN_MOVSG; goto extract_sfmt_movsg;
-          case 8 : itype = FRVBF_INSN_STBF; goto extract_sfmt_stbf;
-          case 9 : itype = FRVBF_INSN_STHF; goto extract_sfmt_stbf;
-          case 10 : itype = FRVBF_INSN_STF; goto extract_sfmt_stbf;
-          case 11 : itype = FRVBF_INSN_STDF; goto extract_sfmt_stdf;
-          case 12 : itype = FRVBF_INSN_STQF; goto extract_sfmt_ldqf;
-          case 13 : itype = FRVBF_INSN_MOVFG; goto extract_sfmt_movfg;
-          case 14 : itype = FRVBF_INSN_MOVFGD; goto extract_sfmt_movfgd;
-          case 15 : itype = FRVBF_INSN_MOVFGQ; goto extract_sfmt_movfgq;
-          case 16 : itype = FRVBF_INSN_STBU; goto extract_sfmt_stbu;
-          case 17 : itype = FRVBF_INSN_STHU; goto extract_sfmt_stbu;
-          case 18 : itype = FRVBF_INSN_STU; goto extract_sfmt_stbu;
-          case 19 : itype = FRVBF_INSN_STDU; goto extract_sfmt_stdu;
-          case 20 : itype = FRVBF_INSN_STQU; goto extract_sfmt_stqu;
-          case 21 : itype = FRVBF_INSN_MOVGF; goto extract_sfmt_movgf;
-          case 22 : itype = FRVBF_INSN_MOVGFD; goto extract_sfmt_movgfd;
-          case 23 : itype = FRVBF_INSN_MOVGFQ; goto extract_sfmt_movgfq;
-          case 24 : itype = FRVBF_INSN_STBFU; goto extract_sfmt_stbfu;
-          case 25 : itype = FRVBF_INSN_STHFU; goto extract_sfmt_stbfu;
-          case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
-          case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
-          case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
-          case 32 : itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei;
-          case 33 : itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei;
-          case 36 : itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei;
-          case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
-          case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
-          case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
-          case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu;
-          case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu;
-          case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu;
-          case 48 : itype = FRVBF_INSN_ICPL; goto extract_sfmt_icpl;
-          case 49 : itype = FRVBF_INSN_ICUL; goto extract_sfmt_icul;
-          case 50 : itype = FRVBF_INSN_WITLB; goto extract_sfmt_rei;
-          case 51 : itype = FRVBF_INSN_ITLBI; goto extract_sfmt_rei;
-          case 52 : itype = FRVBF_INSN_DCPL; goto extract_sfmt_icpl;
-          case 53 : itype = FRVBF_INSN_DCUL; goto extract_sfmt_icul;
-          case 54 : itype = FRVBF_INSN_WDTLB; goto extract_sfmt_rei;
-          case 55 : itype = FRVBF_INSN_DTLBI; goto extract_sfmt_rei;
-          case 56 : itype = FRVBF_INSN_ICI; goto extract_sfmt_ici;
-          case 57 : itype = FRVBF_INSN_ICEI; goto extract_sfmt_icei;
-          case 58 : itype = FRVBF_INSN_DCEI; goto extract_sfmt_icei;
-          case 59 : itype = FRVBF_INSN_DCEF; goto extract_sfmt_icei;
-          case 60 : itype = FRVBF_INSN_DCI; goto extract_sfmt_ici;
-          case 61 : itype = FRVBF_INSN_DCF; goto extract_sfmt_ici;
-          case 62 : itype = FRVBF_INSN_BAR; goto extract_sfmt_rei;
-          case 63 : itype = FRVBF_INSN_MEMBAR; goto extract_sfmt_rei;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0000)
+              { itype = FRVBF_INSN_STB; goto extract_sfmt_stb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0040)
+              { itype = FRVBF_INSN_STH; goto extract_sfmt_stb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0080)
+              { itype = FRVBF_INSN_ST; goto extract_sfmt_stb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc00c0)
+              { itype = FRVBF_INSN_STD; goto extract_sfmt_std; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0100)
+              { itype = FRVBF_INSN_STQ; goto extract_sfmt_ldq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0140)
+              { itype = FRVBF_INSN_SWAP; goto extract_sfmt_swap; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0180)
+              { itype = FRVBF_INSN_MOVGS; goto extract_sfmt_movgs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc01c0)
+              { itype = FRVBF_INSN_MOVSG; goto extract_sfmt_movsg; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0200)
+              { itype = FRVBF_INSN_STBF; goto extract_sfmt_stbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0240)
+              { itype = FRVBF_INSN_STHF; goto extract_sfmt_stbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0280)
+              { itype = FRVBF_INSN_STF; goto extract_sfmt_stbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc02c0)
+              { itype = FRVBF_INSN_STDF; goto extract_sfmt_stdf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0300)
+              { itype = FRVBF_INSN_STQF; goto extract_sfmt_ldqf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x1ffffc0) == 0xc0340)
+              { itype = FRVBF_INSN_MOVFG; goto extract_sfmt_movfg; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1ffffc0) == 0xc0380)
+              { itype = FRVBF_INSN_MOVFGD; goto extract_sfmt_movfgd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1ffffc0) == 0xc03c0)
+              { itype = FRVBF_INSN_MOVFGQ; goto extract_sfmt_movfgq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0400)
+              { itype = FRVBF_INSN_STBU; goto extract_sfmt_stbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0440)
+              { itype = FRVBF_INSN_STHU; goto extract_sfmt_stbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 18 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0480)
+              { itype = FRVBF_INSN_STU; goto extract_sfmt_stbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc04c0)
+              { itype = FRVBF_INSN_STDU; goto extract_sfmt_stdu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0500)
+              { itype = FRVBF_INSN_STQU; goto extract_sfmt_stqu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x1ffffc0) == 0xc0540)
+              { itype = FRVBF_INSN_MOVGF; goto extract_sfmt_movgf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 22 :
+            if ((entire_insn & 0x1ffffc0) == 0xc0580)
+              { itype = FRVBF_INSN_MOVGFD; goto extract_sfmt_movgfd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 23 :
+            if ((entire_insn & 0x1ffffc0) == 0xc05c0)
+              { itype = FRVBF_INSN_MOVGFQ; goto extract_sfmt_movgfq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0600)
+              { itype = FRVBF_INSN_STBFU; goto extract_sfmt_stbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0640)
+              { itype = FRVBF_INSN_STHFU; goto extract_sfmt_stbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 26 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0680)
+              { itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 27 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc06c0)
+              { itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0700)
+              { itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x1fc0fc7) == 0xc0800)
+              { itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x1fc0fc7) == 0xc0840)
+              { itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x61fc0fc0) == 0xc0900)
+              { itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0940)
+              { itype = FRVBF_INSN_STC; goto extract_sfmt_stc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 38 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0980)
+              { itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 39 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc09c0)
+              { itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 45 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0b40)
+              { itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 46 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0b80)
+              { itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 47 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0bc0)
+              { itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 48 :
+            if ((entire_insn & 0x7dfc0fc0) == 0xc0c00)
+              { itype = FRVBF_INSN_ICPL; goto extract_sfmt_icpl; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 49 :
+            if ((entire_insn & 0x7ffc0fff) == 0xc0c40)
+              { itype = FRVBF_INSN_ICUL; goto extract_sfmt_icul; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 50 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0c80)
+              { itype = FRVBF_INSN_WITLB; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 51 :
+            if ((entire_insn & 0x7ffc0fc0) == 0xc0cc0)
+              { itype = FRVBF_INSN_ITLBI; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 52 :
+            if ((entire_insn & 0x7dfc0fc0) == 0xc0d00)
+              { itype = FRVBF_INSN_DCPL; goto extract_sfmt_icpl; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 53 :
+            if ((entire_insn & 0x7ffc0fff) == 0xc0d40)
+              { itype = FRVBF_INSN_DCUL; goto extract_sfmt_icul; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 54 :
+            if ((entire_insn & 0x1fc0fc0) == 0xc0d80)
+              { itype = FRVBF_INSN_WDTLB; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 55 :
+            if ((entire_insn & 0x7ffc0fc0) == 0xc0dc0)
+              { itype = FRVBF_INSN_DTLBI; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 56 :
+            if ((entire_insn & 0x7ffc0fc0) == 0xc0e00)
+              { itype = FRVBF_INSN_ICI; goto extract_sfmt_ici; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 57 :
+            if ((entire_insn & 0x7dfc0fc0) == 0xc0e40)
+              { itype = FRVBF_INSN_ICEI; goto extract_sfmt_icei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 58 :
+            if ((entire_insn & 0x7dfc0fc0) == 0xc0e80)
+              { itype = FRVBF_INSN_DCEI; goto extract_sfmt_icei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 59 :
+            if ((entire_insn & 0x7dfc0fc0) == 0xc0ec0)
+              { itype = FRVBF_INSN_DCEF; goto extract_sfmt_icei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 60 :
+            if ((entire_insn & 0x7ffc0fc0) == 0xc0f00)
+              { itype = FRVBF_INSN_DCI; goto extract_sfmt_ici; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 61 :
+            if ((entire_insn & 0x7ffc0fc0) == 0xc0f40)
+              { itype = FRVBF_INSN_DCF; goto extract_sfmt_ici; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 62 :
+            if ((entire_insn & 0x7fffffff) == 0xc0f80)
+              { itype = FRVBF_INSN_BAR; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 63 :
+            if ((entire_insn & 0x7fffffff) == 0xc0fc0)
+              { itype = FRVBF_INSN_MEMBAR; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1044,65 +1461,218 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_TNO; goto extract_sfmt_rei;
-          case 1 : itype = FRVBF_INSN_FTNO; goto extract_sfmt_rei;
-          case 2 : itype = FRVBF_INSN_MTRAP; goto extract_sfmt_rei;
-          case 3 : itype = FRVBF_INSN_BREAK; goto extract_sfmt_break;
-          case 4 : itype = FRVBF_INSN_TC; goto extract_sfmt_teq;
-          case 5 : itype = FRVBF_INSN_FTU; goto extract_sfmt_ftne;
-          case 8 : itype = FRVBF_INSN_TV; goto extract_sfmt_teq;
-          case 9 : itype = FRVBF_INSN_FTGT; goto extract_sfmt_ftne;
-          case 12 : itype = FRVBF_INSN_TLT; goto extract_sfmt_teq;
-          case 13 : itype = FRVBF_INSN_FTUG; goto extract_sfmt_ftne;
-          case 16 : itype = FRVBF_INSN_TEQ; goto extract_sfmt_teq;
-          case 17 : itype = FRVBF_INSN_FTLT; goto extract_sfmt_ftne;
-          case 20 : itype = FRVBF_INSN_TLS; goto extract_sfmt_teq;
-          case 21 : itype = FRVBF_INSN_FTUL; goto extract_sfmt_ftne;
-          case 24 : itype = FRVBF_INSN_TN; goto extract_sfmt_teq;
-          case 25 : itype = FRVBF_INSN_FTLG; goto extract_sfmt_ftne;
-          case 28 : itype = FRVBF_INSN_TLE; goto extract_sfmt_teq;
-          case 29 : itype = FRVBF_INSN_FTNE; goto extract_sfmt_ftne;
-          case 32 : itype = FRVBF_INSN_TRA; goto extract_sfmt_tra;
-          case 33 : itype = FRVBF_INSN_FTEQ; goto extract_sfmt_ftne;
-          case 36 : itype = FRVBF_INSN_TNC; goto extract_sfmt_teq;
-          case 37 : itype = FRVBF_INSN_FTUE; goto extract_sfmt_ftne;
-          case 40 : itype = FRVBF_INSN_TNV; goto extract_sfmt_teq;
-          case 41 : itype = FRVBF_INSN_FTGE; goto extract_sfmt_ftne;
-          case 44 : itype = FRVBF_INSN_TGE; goto extract_sfmt_teq;
-          case 45 : itype = FRVBF_INSN_FTUGE; goto extract_sfmt_ftne;
-          case 48 : itype = FRVBF_INSN_TNE; goto extract_sfmt_teq;
-          case 49 : itype = FRVBF_INSN_FTLE; goto extract_sfmt_ftne;
-          case 52 : itype = FRVBF_INSN_THI; goto extract_sfmt_teq;
-          case 53 : itype = FRVBF_INSN_FTULE; goto extract_sfmt_ftne;
-          case 56 : itype = FRVBF_INSN_TP; goto extract_sfmt_teq;
-          case 57 : itype = FRVBF_INSN_FTO; goto extract_sfmt_ftne;
-          case 60 : itype = FRVBF_INSN_TGT; goto extract_sfmt_teq;
-          case 61 : itype = FRVBF_INSN_FTRA; goto extract_sfmt_tra;
+          case 0 :
+            if ((entire_insn & 0x7fffffff) == 0x100000)
+              { itype = FRVBF_INSN_TNO; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x7fffffff) == 0x100040)
+              { itype = FRVBF_INSN_FTNO; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x7fffffff) == 0x100080)
+              { itype = FRVBF_INSN_MTRAP; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x7fffffff) == 0x1000c0)
+              { itype = FRVBF_INSN_BREAK; goto extract_sfmt_break; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fc0fc0) == 0x8100000)
+              { itype = FRVBF_INSN_TC; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fc0fc0) == 0x8100040)
+              { itype = FRVBF_INSN_FTU; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fc0fc0) == 0x10100000)
+              { itype = FRVBF_INSN_TV; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fc0fc0) == 0x10100040)
+              { itype = FRVBF_INSN_FTGT; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fc0fc0) == 0x18100000)
+              { itype = FRVBF_INSN_TLT; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fc0fc0) == 0x18100040)
+              { itype = FRVBF_INSN_FTUG; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x79fc0fc0) == 0x20100000)
+              { itype = FRVBF_INSN_TEQ; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x79fc0fc0) == 0x20100040)
+              { itype = FRVBF_INSN_FTLT; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x79fc0fc0) == 0x28100000)
+              { itype = FRVBF_INSN_TLS; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x79fc0fc0) == 0x28100040)
+              { itype = FRVBF_INSN_FTUL; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x79fc0fc0) == 0x30100000)
+              { itype = FRVBF_INSN_TN; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x79fc0fc0) == 0x30100040)
+              { itype = FRVBF_INSN_FTLG; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x79fc0fc0) == 0x38100000)
+              { itype = FRVBF_INSN_TLE; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 29 :
+            if ((entire_insn & 0x79fc0fc0) == 0x38100040)
+              { itype = FRVBF_INSN_FTNE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x40100000)
+              { itype = FRVBF_INSN_TRA; goto extract_sfmt_tra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x79fc0fc0) == 0x40100040)
+              { itype = FRVBF_INSN_FTEQ; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x79fc0fc0) == 0x48100000)
+              { itype = FRVBF_INSN_TNC; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x79fc0fc0) == 0x48100040)
+              { itype = FRVBF_INSN_FTUE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 40 :
+            if ((entire_insn & 0x79fc0fc0) == 0x50100000)
+              { itype = FRVBF_INSN_TNV; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 41 :
+            if ((entire_insn & 0x79fc0fc0) == 0x50100040)
+              { itype = FRVBF_INSN_FTGE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 44 :
+            if ((entire_insn & 0x79fc0fc0) == 0x58100000)
+              { itype = FRVBF_INSN_TGE; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 45 :
+            if ((entire_insn & 0x79fc0fc0) == 0x58100040)
+              { itype = FRVBF_INSN_FTUGE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 48 :
+            if ((entire_insn & 0x79fc0fc0) == 0x60100000)
+              { itype = FRVBF_INSN_TNE; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 49 :
+            if ((entire_insn & 0x79fc0fc0) == 0x60100040)
+              { itype = FRVBF_INSN_FTLE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 52 :
+            if ((entire_insn & 0x79fc0fc0) == 0x68100000)
+              { itype = FRVBF_INSN_THI; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 53 :
+            if ((entire_insn & 0x79fc0fc0) == 0x68100040)
+              { itype = FRVBF_INSN_FTULE; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 56 :
+            if ((entire_insn & 0x79fc0fc0) == 0x70100000)
+              { itype = FRVBF_INSN_TP; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 57 :
+            if ((entire_insn & 0x79fc0fc0) == 0x70100040)
+              { itype = FRVBF_INSN_FTO; goto extract_sfmt_ftne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 60 :
+            if ((entire_insn & 0x79fc0fc0) == 0x78100000)
+              { itype = FRVBF_INSN_TGT; goto extract_sfmt_teq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 61 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x78100040)
+              { itype = FRVBF_INSN_FTRA; goto extract_sfmt_tra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 5 : itype = FRVBF_INSN_RETT; goto extract_sfmt_rett;
+      case 5 :
+        if ((entire_insn & 0x7dffffff) == 0x140000)
+          { itype = FRVBF_INSN_RETT; goto extract_sfmt_rett; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 6 :
         {
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_BNO; goto extract_sfmt_bno;
-          case 1 : itype = FRVBF_INSN_BC; goto extract_sfmt_beq;
-          case 2 : itype = FRVBF_INSN_BV; goto extract_sfmt_beq;
-          case 3 : itype = FRVBF_INSN_BLT; goto extract_sfmt_beq;
-          case 4 : itype = FRVBF_INSN_BEQ; goto extract_sfmt_beq;
-          case 5 : itype = FRVBF_INSN_BLS; goto extract_sfmt_beq;
-          case 6 : itype = FRVBF_INSN_BN; goto extract_sfmt_beq;
-          case 7 : itype = FRVBF_INSN_BLE; goto extract_sfmt_beq;
-          case 8 : itype = FRVBF_INSN_BRA; goto extract_sfmt_bra;
-          case 9 : itype = FRVBF_INSN_BNC; goto extract_sfmt_beq;
-          case 10 : itype = FRVBF_INSN_BNV; goto extract_sfmt_beq;
-          case 11 : itype = FRVBF_INSN_BGE; goto extract_sfmt_beq;
-          case 12 : itype = FRVBF_INSN_BNE; goto extract_sfmt_beq;
-          case 13 : itype = FRVBF_INSN_BHI; goto extract_sfmt_beq;
-          case 14 : itype = FRVBF_INSN_BP; goto extract_sfmt_beq;
-          case 15 : itype = FRVBF_INSN_BGT; goto extract_sfmt_beq;
+          case 0 :
+            if ((entire_insn & 0x7ffcffff) == 0x180000)
+              { itype = FRVBF_INSN_BNO; goto extract_sfmt_bno; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fc0000) == 0x8180000)
+              { itype = FRVBF_INSN_BC; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fc0000) == 0x10180000)
+              { itype = FRVBF_INSN_BV; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fc0000) == 0x18180000)
+              { itype = FRVBF_INSN_BLT; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fc0000) == 0x20180000)
+              { itype = FRVBF_INSN_BEQ; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fc0000) == 0x28180000)
+              { itype = FRVBF_INSN_BLS; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fc0000) == 0x30180000)
+              { itype = FRVBF_INSN_BN; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fc0000) == 0x38180000)
+              { itype = FRVBF_INSN_BLE; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x7ffc0000) == 0x40180000)
+              { itype = FRVBF_INSN_BRA; goto extract_sfmt_bra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fc0000) == 0x48180000)
+              { itype = FRVBF_INSN_BNC; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fc0000) == 0x50180000)
+              { itype = FRVBF_INSN_BNV; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fc0000) == 0x58180000)
+              { itype = FRVBF_INSN_BGE; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fc0000) == 0x60180000)
+              { itype = FRVBF_INSN_BNE; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fc0000) == 0x68180000)
+              { itype = FRVBF_INSN_BHI; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fc0000) == 0x70180000)
+              { itype = FRVBF_INSN_BP; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fc0000) == 0x78180000)
+              { itype = FRVBF_INSN_BGT; goto extract_sfmt_beq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1111,22 +1681,70 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_FBNO; goto extract_sfmt_bno;
-          case 1 : itype = FRVBF_INSN_FBU; goto extract_sfmt_fbne;
-          case 2 : itype = FRVBF_INSN_FBGT; goto extract_sfmt_fbne;
-          case 3 : itype = FRVBF_INSN_FBUG; goto extract_sfmt_fbne;
-          case 4 : itype = FRVBF_INSN_FBLT; goto extract_sfmt_fbne;
-          case 5 : itype = FRVBF_INSN_FBUL; goto extract_sfmt_fbne;
-          case 6 : itype = FRVBF_INSN_FBLG; goto extract_sfmt_fbne;
-          case 7 : itype = FRVBF_INSN_FBNE; goto extract_sfmt_fbne;
-          case 8 : itype = FRVBF_INSN_FBEQ; goto extract_sfmt_fbne;
-          case 9 : itype = FRVBF_INSN_FBUE; goto extract_sfmt_fbne;
-          case 10 : itype = FRVBF_INSN_FBGE; goto extract_sfmt_fbne;
-          case 11 : itype = FRVBF_INSN_FBUGE; goto extract_sfmt_fbne;
-          case 12 : itype = FRVBF_INSN_FBLE; goto extract_sfmt_fbne;
-          case 13 : itype = FRVBF_INSN_FBULE; goto extract_sfmt_fbne;
-          case 14 : itype = FRVBF_INSN_FBO; goto extract_sfmt_fbne;
-          case 15 : itype = FRVBF_INSN_FBRA; goto extract_sfmt_bra;
+          case 0 :
+            if ((entire_insn & 0x7ffcffff) == 0x1c0000)
+              { itype = FRVBF_INSN_FBNO; goto extract_sfmt_bno; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fc0000) == 0x81c0000)
+              { itype = FRVBF_INSN_FBU; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fc0000) == 0x101c0000)
+              { itype = FRVBF_INSN_FBGT; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fc0000) == 0x181c0000)
+              { itype = FRVBF_INSN_FBUG; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fc0000) == 0x201c0000)
+              { itype = FRVBF_INSN_FBLT; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fc0000) == 0x281c0000)
+              { itype = FRVBF_INSN_FBUL; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fc0000) == 0x301c0000)
+              { itype = FRVBF_INSN_FBLG; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fc0000) == 0x381c0000)
+              { itype = FRVBF_INSN_FBNE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fc0000) == 0x401c0000)
+              { itype = FRVBF_INSN_FBEQ; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fc0000) == 0x481c0000)
+              { itype = FRVBF_INSN_FBUE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fc0000) == 0x501c0000)
+              { itype = FRVBF_INSN_FBGE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fc0000) == 0x581c0000)
+              { itype = FRVBF_INSN_FBUGE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fc0000) == 0x601c0000)
+              { itype = FRVBF_INSN_FBLE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fc0000) == 0x681c0000)
+              { itype = FRVBF_INSN_FBULE; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fc0000) == 0x701c0000)
+              { itype = FRVBF_INSN_FBO; goto extract_sfmt_fbne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x7ffc0000) == 0x781c0000)
+              { itype = FRVBF_INSN_FBRA; goto extract_sfmt_bra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1135,22 +1753,70 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CKNO; goto extract_sfmt_ckra;
-          case 1 : itype = FRVBF_INSN_CKC; goto extract_sfmt_ckeq;
-          case 2 : itype = FRVBF_INSN_CKV; goto extract_sfmt_ckeq;
-          case 3 : itype = FRVBF_INSN_CKLT; goto extract_sfmt_ckeq;
-          case 4 : itype = FRVBF_INSN_CKEQ; goto extract_sfmt_ckeq;
-          case 5 : itype = FRVBF_INSN_CKLS; goto extract_sfmt_ckeq;
-          case 6 : itype = FRVBF_INSN_CKN; goto extract_sfmt_ckeq;
-          case 7 : itype = FRVBF_INSN_CKLE; goto extract_sfmt_ckeq;
-          case 8 : itype = FRVBF_INSN_CKRA; goto extract_sfmt_ckra;
-          case 9 : itype = FRVBF_INSN_CKNC; goto extract_sfmt_ckeq;
-          case 10 : itype = FRVBF_INSN_CKNV; goto extract_sfmt_ckeq;
-          case 11 : itype = FRVBF_INSN_CKGE; goto extract_sfmt_ckeq;
-          case 12 : itype = FRVBF_INSN_CKNE; goto extract_sfmt_ckeq;
-          case 13 : itype = FRVBF_INSN_CKHI; goto extract_sfmt_ckeq;
-          case 14 : itype = FRVBF_INSN_CKP; goto extract_sfmt_ckeq;
-          case 15 : itype = FRVBF_INSN_CKGT; goto extract_sfmt_ckeq;
+          case 0 :
+            if ((entire_insn & 0x79ffffff) == 0x200000)
+              { itype = FRVBF_INSN_CKNO; goto extract_sfmt_ckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fffffc) == 0x8200000)
+              { itype = FRVBF_INSN_CKC; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fffffc) == 0x10200000)
+              { itype = FRVBF_INSN_CKV; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fffffc) == 0x18200000)
+              { itype = FRVBF_INSN_CKLT; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fffffc) == 0x20200000)
+              { itype = FRVBF_INSN_CKEQ; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fffffc) == 0x28200000)
+              { itype = FRVBF_INSN_CKLS; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fffffc) == 0x30200000)
+              { itype = FRVBF_INSN_CKN; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fffffc) == 0x38200000)
+              { itype = FRVBF_INSN_CKLE; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79ffffff) == 0x40200000)
+              { itype = FRVBF_INSN_CKRA; goto extract_sfmt_ckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fffffc) == 0x48200000)
+              { itype = FRVBF_INSN_CKNC; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fffffc) == 0x50200000)
+              { itype = FRVBF_INSN_CKNV; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fffffc) == 0x58200000)
+              { itype = FRVBF_INSN_CKGE; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fffffc) == 0x60200000)
+              { itype = FRVBF_INSN_CKNE; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fffffc) == 0x68200000)
+              { itype = FRVBF_INSN_CKHI; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fffffc) == 0x70200000)
+              { itype = FRVBF_INSN_CKP; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fffffc) == 0x78200000)
+              { itype = FRVBF_INSN_CKGT; goto extract_sfmt_ckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1159,22 +1825,70 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_FCKNO; goto extract_sfmt_fckra;
-          case 1 : itype = FRVBF_INSN_FCKU; goto extract_sfmt_fckne;
-          case 2 : itype = FRVBF_INSN_FCKGT; goto extract_sfmt_fckne;
-          case 3 : itype = FRVBF_INSN_FCKUG; goto extract_sfmt_fckne;
-          case 4 : itype = FRVBF_INSN_FCKLT; goto extract_sfmt_fckne;
-          case 5 : itype = FRVBF_INSN_FCKUL; goto extract_sfmt_fckne;
-          case 6 : itype = FRVBF_INSN_FCKLG; goto extract_sfmt_fckne;
-          case 7 : itype = FRVBF_INSN_FCKNE; goto extract_sfmt_fckne;
-          case 8 : itype = FRVBF_INSN_FCKEQ; goto extract_sfmt_fckne;
-          case 9 : itype = FRVBF_INSN_FCKUE; goto extract_sfmt_fckne;
-          case 10 : itype = FRVBF_INSN_FCKGE; goto extract_sfmt_fckne;
-          case 11 : itype = FRVBF_INSN_FCKUGE; goto extract_sfmt_fckne;
-          case 12 : itype = FRVBF_INSN_FCKLE; goto extract_sfmt_fckne;
-          case 13 : itype = FRVBF_INSN_FCKULE; goto extract_sfmt_fckne;
-          case 14 : itype = FRVBF_INSN_FCKO; goto extract_sfmt_fckne;
-          case 15 : itype = FRVBF_INSN_FCKRA; goto extract_sfmt_fckra;
+          case 0 :
+            if ((entire_insn & 0x79fffffc) == 0x240000)
+              { itype = FRVBF_INSN_FCKNO; goto extract_sfmt_fckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fffffc) == 0x8240000)
+              { itype = FRVBF_INSN_FCKU; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fffffc) == 0x10240000)
+              { itype = FRVBF_INSN_FCKGT; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fffffc) == 0x18240000)
+              { itype = FRVBF_INSN_FCKUG; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fffffc) == 0x20240000)
+              { itype = FRVBF_INSN_FCKLT; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fffffc) == 0x28240000)
+              { itype = FRVBF_INSN_FCKUL; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fffffc) == 0x30240000)
+              { itype = FRVBF_INSN_FCKLG; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fffffc) == 0x38240000)
+              { itype = FRVBF_INSN_FCKNE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fffffc) == 0x40240000)
+              { itype = FRVBF_INSN_FCKEQ; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fffffc) == 0x48240000)
+              { itype = FRVBF_INSN_FCKUE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fffffc) == 0x50240000)
+              { itype = FRVBF_INSN_FCKGE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fffffc) == 0x58240000)
+              { itype = FRVBF_INSN_FCKUGE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fffffc) == 0x60240000)
+              { itype = FRVBF_INSN_FCKLE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fffffc) == 0x68240000)
+              { itype = FRVBF_INSN_FCKULE; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fffffc) == 0x70240000)
+              { itype = FRVBF_INSN_FCKO; goto extract_sfmt_fckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fffffc) == 0x78240000)
+              { itype = FRVBF_INSN_FCKRA; goto extract_sfmt_fckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1183,35 +1897,98 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (31 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLRGR; goto extract_sfmt_clrgr;
-          case 1 : itype = FRVBF_INSN_CLRGA; goto extract_sfmt_rei;
-          case 2 : itype = FRVBF_INSN_CLRFR; goto extract_sfmt_clrfr;
-          case 3 : itype = FRVBF_INSN_CLRFA; goto extract_sfmt_rei;
-          case 4 : itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_commitgr;
-          case 5 : itype = FRVBF_INSN_COMMITGA; goto extract_sfmt_rei;
-          case 6 : itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_commitfr;
-          case 7 : itype = FRVBF_INSN_COMMITFA; goto extract_sfmt_rei;
-          case 8 : itype = FRVBF_INSN_ANDCR; goto extract_sfmt_andcr;
-          case 9 : itype = FRVBF_INSN_ORCR; goto extract_sfmt_andcr;
-          case 10 : itype = FRVBF_INSN_XORCR; goto extract_sfmt_andcr;
-          case 11 : itype = FRVBF_INSN_NOTCR; goto extract_sfmt_notcr;
-          case 12 : itype = FRVBF_INSN_NANDCR; goto extract_sfmt_andcr;
-          case 13 : itype = FRVBF_INSN_NORCR; goto extract_sfmt_andcr;
-          case 16 : itype = FRVBF_INSN_ANDNCR; goto extract_sfmt_andcr;
-          case 17 : itype = FRVBF_INSN_ORNCR; goto extract_sfmt_andcr;
-          case 20 : itype = FRVBF_INSN_NANDNCR; goto extract_sfmt_andcr;
-          case 21 : itype = FRVBF_INSN_NORNCR; goto extract_sfmt_andcr;
+          case 0 :
+            if ((entire_insn & 0x1ffffff) == 0x280000)
+              { itype = FRVBF_INSN_CLRGR; goto extract_sfmt_clrgr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x7fffffff) == 0x280040)
+              { itype = FRVBF_INSN_CLRGA; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1ffffff) == 0x280080)
+              { itype = FRVBF_INSN_CLRFR; goto extract_sfmt_clrfr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x7fffffff) == 0x2800c0)
+              { itype = FRVBF_INSN_CLRFA; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1ffffff) == 0x280100)
+              { itype = FRVBF_INSN_COMMITGR; goto extract_sfmt_commitgr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x7fffffff) == 0x280140)
+              { itype = FRVBF_INSN_COMMITGA; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1ffffff) == 0x280180)
+              { itype = FRVBF_INSN_COMMITFR; goto extract_sfmt_commitfr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x7fffffff) == 0x2801c0)
+              { itype = FRVBF_INSN_COMMITFA; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280200)
+              { itype = FRVBF_INSN_ANDCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280240)
+              { itype = FRVBF_INSN_ORCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280280)
+              { itype = FRVBF_INSN_XORCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x71fffff8) == 0x2802c0)
+              { itype = FRVBF_INSN_NOTCR; goto extract_sfmt_notcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280300)
+              { itype = FRVBF_INSN_NANDCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280340)
+              { itype = FRVBF_INSN_NORCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280400)
+              { itype = FRVBF_INSN_ANDNCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280440)
+              { itype = FRVBF_INSN_ORNCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280500)
+              { itype = FRVBF_INSN_NANDNCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x71ff8ff8) == 0x280540)
+              { itype = FRVBF_INSN_NORNCR; goto extract_sfmt_andcr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 11 : itype = FRVBF_INSN_SCAN; goto extract_sfmt_add;
+      case 11 :
+        if ((entire_insn & 0x1fc0fc0) == 0x2c0000)
+          { itype = FRVBF_INSN_SCAN; goto extract_sfmt_add; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 12 :
         {
           unsigned int val = (((insn >> 25) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_JMPL; goto extract_sfmt_jmpl;
-          case 1 : itype = FRVBF_INSN_CALLL; goto extract_sfmt_jmpl;
+          case 0 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x300000)
+              { itype = FRVBF_INSN_JMPL; goto extract_sfmt_jmpl; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x2300000)
+              { itype = FRVBF_INSN_CALLL; goto extract_sfmt_jmpl; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1220,8 +1997,14 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 25) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_JMPIL; goto extract_sfmt_jmpil;
-          case 1 : itype = FRVBF_INSN_CALLIL; goto extract_sfmt_jmpil;
+          case 0 :
+            if ((entire_insn & 0x7ffc0000) == 0x340000)
+              { itype = FRVBF_INSN_JMPIL; goto extract_sfmt_jmpil; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x7ffc0000) == 0x2340000)
+              { itype = FRVBF_INSN_CALLIL; goto extract_sfmt_jmpil; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1230,116 +2013,398 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 14) & (1 << 1)) | ((insn >> 13) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_BNOLR; goto extract_sfmt_bnolr;
+          case 0 :
+            if ((entire_insn & 0x7ffcffff) == 0x384000)
+              { itype = FRVBF_INSN_BNOLR; goto extract_sfmt_bnolr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 1 :
             {
               unsigned int val = (((insn >> 14) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_BCTRLR; goto extract_sfmt_bctrlr;
-              case 1 : itype = FRVBF_INSN_BCNOLR; goto extract_sfmt_bcnolr;
+              case 0 :
+                if ((entire_insn & 0x7ffcefff) == 0x382000)
+                  { itype = FRVBF_INSN_BCTRLR; goto extract_sfmt_bctrlr; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x7ffcffff) == 0x386000)
+                  { itype = FRVBF_INSN_BCNOLR; goto extract_sfmt_bcnolr; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
-          case 2 : itype = FRVBF_INSN_FBNOLR; goto extract_sfmt_bnolr;
-          case 3 : itype = FRVBF_INSN_FCBNOLR; goto extract_sfmt_bcnolr;
-          case 4 : itype = FRVBF_INSN_BCLR; goto extract_sfmt_beqlr;
-          case 5 : itype = FRVBF_INSN_BCCLR; goto extract_sfmt_bceqlr;
-          case 6 : itype = FRVBF_INSN_FBULR; goto extract_sfmt_fbeqlr;
-          case 7 : itype = FRVBF_INSN_FCBULR; goto extract_sfmt_fcbeqlr;
-          case 8 : itype = FRVBF_INSN_BVLR; goto extract_sfmt_beqlr;
-          case 9 : itype = FRVBF_INSN_BCVLR; goto extract_sfmt_bceqlr;
-          case 10 : itype = FRVBF_INSN_FBGTLR; goto extract_sfmt_fbeqlr;
-          case 11 : itype = FRVBF_INSN_FCBGTLR; goto extract_sfmt_fcbeqlr;
-          case 12 : itype = FRVBF_INSN_BLTLR; goto extract_sfmt_beqlr;
-          case 13 : itype = FRVBF_INSN_BCLTLR; goto extract_sfmt_bceqlr;
-          case 14 : itype = FRVBF_INSN_FBUGLR; goto extract_sfmt_fbeqlr;
-          case 15 : itype = FRVBF_INSN_FCBUGLR; goto extract_sfmt_fcbeqlr;
-          case 16 : itype = FRVBF_INSN_BEQLR; goto extract_sfmt_beqlr;
-          case 17 : itype = FRVBF_INSN_BCEQLR; goto extract_sfmt_bceqlr;
-          case 18 : itype = FRVBF_INSN_FBLTLR; goto extract_sfmt_fbeqlr;
-          case 19 : itype = FRVBF_INSN_FCBLTLR; goto extract_sfmt_fcbeqlr;
-          case 20 : itype = FRVBF_INSN_BLSLR; goto extract_sfmt_beqlr;
-          case 21 : itype = FRVBF_INSN_BCLSLR; goto extract_sfmt_bceqlr;
-          case 22 : itype = FRVBF_INSN_FBULLR; goto extract_sfmt_fbeqlr;
-          case 23 : itype = FRVBF_INSN_FCBULLR; goto extract_sfmt_fcbeqlr;
-          case 24 : itype = FRVBF_INSN_BNLR; goto extract_sfmt_beqlr;
-          case 25 : itype = FRVBF_INSN_BCNLR; goto extract_sfmt_bceqlr;
-          case 26 : itype = FRVBF_INSN_FBLGLR; goto extract_sfmt_fbeqlr;
-          case 27 : itype = FRVBF_INSN_FCBLGLR; goto extract_sfmt_fcbeqlr;
-          case 28 : itype = FRVBF_INSN_BLELR; goto extract_sfmt_beqlr;
-          case 29 : itype = FRVBF_INSN_BCLELR; goto extract_sfmt_bceqlr;
-          case 30 : itype = FRVBF_INSN_FBNELR; goto extract_sfmt_fbeqlr;
-          case 31 : itype = FRVBF_INSN_FCBNELR; goto extract_sfmt_fcbeqlr;
-          case 32 : itype = FRVBF_INSN_BRALR; goto extract_sfmt_bralr;
-          case 33 : itype = FRVBF_INSN_BCRALR; goto extract_sfmt_bcralr;
-          case 34 : itype = FRVBF_INSN_FBEQLR; goto extract_sfmt_fbeqlr;
-          case 35 : itype = FRVBF_INSN_FCBEQLR; goto extract_sfmt_fcbeqlr;
-          case 36 : itype = FRVBF_INSN_BNCLR; goto extract_sfmt_beqlr;
-          case 37 : itype = FRVBF_INSN_BCNCLR; goto extract_sfmt_bceqlr;
-          case 38 : itype = FRVBF_INSN_FBUELR; goto extract_sfmt_fbeqlr;
-          case 39 : itype = FRVBF_INSN_FCBUELR; goto extract_sfmt_fcbeqlr;
-          case 40 : itype = FRVBF_INSN_BNVLR; goto extract_sfmt_beqlr;
-          case 41 : itype = FRVBF_INSN_BCNVLR; goto extract_sfmt_bceqlr;
-          case 42 : itype = FRVBF_INSN_FBGELR; goto extract_sfmt_fbeqlr;
-          case 43 : itype = FRVBF_INSN_FCBGELR; goto extract_sfmt_fcbeqlr;
-          case 44 : itype = FRVBF_INSN_BGELR; goto extract_sfmt_beqlr;
-          case 45 : itype = FRVBF_INSN_BCGELR; goto extract_sfmt_bceqlr;
-          case 46 : itype = FRVBF_INSN_FBUGELR; goto extract_sfmt_fbeqlr;
-          case 47 : itype = FRVBF_INSN_FCBUGELR; goto extract_sfmt_fcbeqlr;
-          case 48 : itype = FRVBF_INSN_BNELR; goto extract_sfmt_beqlr;
-          case 49 : itype = FRVBF_INSN_BCNELR; goto extract_sfmt_bceqlr;
-          case 50 : itype = FRVBF_INSN_FBLELR; goto extract_sfmt_fbeqlr;
-          case 51 : itype = FRVBF_INSN_FCBLELR; goto extract_sfmt_fcbeqlr;
-          case 52 : itype = FRVBF_INSN_BHILR; goto extract_sfmt_beqlr;
-          case 53 : itype = FRVBF_INSN_BCHILR; goto extract_sfmt_bceqlr;
-          case 54 : itype = FRVBF_INSN_FBULELR; goto extract_sfmt_fbeqlr;
-          case 55 : itype = FRVBF_INSN_FCBULELR; goto extract_sfmt_fcbeqlr;
-          case 56 : itype = FRVBF_INSN_BPLR; goto extract_sfmt_beqlr;
-          case 57 : itype = FRVBF_INSN_BCPLR; goto extract_sfmt_bceqlr;
-          case 58 : itype = FRVBF_INSN_FBOLR; goto extract_sfmt_fbeqlr;
-          case 59 : itype = FRVBF_INSN_FCBOLR; goto extract_sfmt_fcbeqlr;
-          case 60 : itype = FRVBF_INSN_BGTLR; goto extract_sfmt_beqlr;
-          case 61 : itype = FRVBF_INSN_BCGTLR; goto extract_sfmt_bceqlr;
-          case 62 : itype = FRVBF_INSN_FBRALR; goto extract_sfmt_bralr;
-          case 63 : itype = FRVBF_INSN_FCBRALR; goto extract_sfmt_bcralr;
+          case 2 :
+            if ((entire_insn & 0x7ffcffff) == 0x38c000)
+              { itype = FRVBF_INSN_FBNOLR; goto extract_sfmt_bnolr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x7ffcffff) == 0x38e000)
+              { itype = FRVBF_INSN_FCBNOLR; goto extract_sfmt_bcnolr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fcffff) == 0x8384000)
+              { itype = FRVBF_INSN_BCLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fcefff) == 0x8386000)
+              { itype = FRVBF_INSN_BCCLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fcffff) == 0x838c000)
+              { itype = FRVBF_INSN_FBULR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fcefff) == 0x838e000)
+              { itype = FRVBF_INSN_FCBULR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fcffff) == 0x10384000)
+              { itype = FRVBF_INSN_BVLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fcefff) == 0x10386000)
+              { itype = FRVBF_INSN_BCVLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fcffff) == 0x1038c000)
+              { itype = FRVBF_INSN_FBGTLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fcefff) == 0x1038e000)
+              { itype = FRVBF_INSN_FCBGTLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fcffff) == 0x18384000)
+              { itype = FRVBF_INSN_BLTLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fcefff) == 0x18386000)
+              { itype = FRVBF_INSN_BCLTLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fcffff) == 0x1838c000)
+              { itype = FRVBF_INSN_FBUGLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fcefff) == 0x1838e000)
+              { itype = FRVBF_INSN_FCBUGLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x79fcffff) == 0x20384000)
+              { itype = FRVBF_INSN_BEQLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x79fcefff) == 0x20386000)
+              { itype = FRVBF_INSN_BCEQLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 18 :
+            if ((entire_insn & 0x79fcffff) == 0x2038c000)
+              { itype = FRVBF_INSN_FBLTLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x79fcefff) == 0x2038e000)
+              { itype = FRVBF_INSN_FCBLTLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x79fcffff) == 0x28384000)
+              { itype = FRVBF_INSN_BLSLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x79fcefff) == 0x28386000)
+              { itype = FRVBF_INSN_BCLSLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 22 :
+            if ((entire_insn & 0x79fcffff) == 0x2838c000)
+              { itype = FRVBF_INSN_FBULLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 23 :
+            if ((entire_insn & 0x79fcefff) == 0x2838e000)
+              { itype = FRVBF_INSN_FCBULLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x79fcffff) == 0x30384000)
+              { itype = FRVBF_INSN_BNLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x79fcefff) == 0x30386000)
+              { itype = FRVBF_INSN_BCNLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 26 :
+            if ((entire_insn & 0x79fcffff) == 0x3038c000)
+              { itype = FRVBF_INSN_FBLGLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 27 :
+            if ((entire_insn & 0x79fcefff) == 0x3038e000)
+              { itype = FRVBF_INSN_FCBLGLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x79fcffff) == 0x38384000)
+              { itype = FRVBF_INSN_BLELR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 29 :
+            if ((entire_insn & 0x79fcefff) == 0x38386000)
+              { itype = FRVBF_INSN_BCLELR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 30 :
+            if ((entire_insn & 0x79fcffff) == 0x3838c000)
+              { itype = FRVBF_INSN_FBNELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 31 :
+            if ((entire_insn & 0x79fcefff) == 0x3838e000)
+              { itype = FRVBF_INSN_FCBNELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x7ffcffff) == 0x40384000)
+              { itype = FRVBF_INSN_BRALR; goto extract_sfmt_bralr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x7ffcefff) == 0x40386000)
+              { itype = FRVBF_INSN_BCRALR; goto extract_sfmt_bcralr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 34 :
+            if ((entire_insn & 0x79fcffff) == 0x4038c000)
+              { itype = FRVBF_INSN_FBEQLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 35 :
+            if ((entire_insn & 0x79fcefff) == 0x4038e000)
+              { itype = FRVBF_INSN_FCBEQLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x79fcffff) == 0x48384000)
+              { itype = FRVBF_INSN_BNCLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x79fcefff) == 0x48386000)
+              { itype = FRVBF_INSN_BCNCLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 38 :
+            if ((entire_insn & 0x79fcffff) == 0x4838c000)
+              { itype = FRVBF_INSN_FBUELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 39 :
+            if ((entire_insn & 0x79fcefff) == 0x4838e000)
+              { itype = FRVBF_INSN_FCBUELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 40 :
+            if ((entire_insn & 0x79fcffff) == 0x50384000)
+              { itype = FRVBF_INSN_BNVLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 41 :
+            if ((entire_insn & 0x79fcefff) == 0x50386000)
+              { itype = FRVBF_INSN_BCNVLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 42 :
+            if ((entire_insn & 0x79fcffff) == 0x5038c000)
+              { itype = FRVBF_INSN_FBGELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 43 :
+            if ((entire_insn & 0x79fcefff) == 0x5038e000)
+              { itype = FRVBF_INSN_FCBGELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 44 :
+            if ((entire_insn & 0x79fcffff) == 0x58384000)
+              { itype = FRVBF_INSN_BGELR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 45 :
+            if ((entire_insn & 0x79fcefff) == 0x58386000)
+              { itype = FRVBF_INSN_BCGELR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 46 :
+            if ((entire_insn & 0x79fcffff) == 0x5838c000)
+              { itype = FRVBF_INSN_FBUGELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 47 :
+            if ((entire_insn & 0x79fcefff) == 0x5838e000)
+              { itype = FRVBF_INSN_FCBUGELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 48 :
+            if ((entire_insn & 0x79fcffff) == 0x60384000)
+              { itype = FRVBF_INSN_BNELR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 49 :
+            if ((entire_insn & 0x79fcefff) == 0x60386000)
+              { itype = FRVBF_INSN_BCNELR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 50 :
+            if ((entire_insn & 0x79fcffff) == 0x6038c000)
+              { itype = FRVBF_INSN_FBLELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 51 :
+            if ((entire_insn & 0x79fcefff) == 0x6038e000)
+              { itype = FRVBF_INSN_FCBLELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 52 :
+            if ((entire_insn & 0x79fcffff) == 0x68384000)
+              { itype = FRVBF_INSN_BHILR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 53 :
+            if ((entire_insn & 0x79fcefff) == 0x68386000)
+              { itype = FRVBF_INSN_BCHILR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 54 :
+            if ((entire_insn & 0x79fcffff) == 0x6838c000)
+              { itype = FRVBF_INSN_FBULELR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 55 :
+            if ((entire_insn & 0x79fcefff) == 0x6838e000)
+              { itype = FRVBF_INSN_FCBULELR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 56 :
+            if ((entire_insn & 0x79fcffff) == 0x70384000)
+              { itype = FRVBF_INSN_BPLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 57 :
+            if ((entire_insn & 0x79fcefff) == 0x70386000)
+              { itype = FRVBF_INSN_BCPLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 58 :
+            if ((entire_insn & 0x79fcffff) == 0x7038c000)
+              { itype = FRVBF_INSN_FBOLR; goto extract_sfmt_fbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 59 :
+            if ((entire_insn & 0x79fcefff) == 0x7038e000)
+              { itype = FRVBF_INSN_FCBOLR; goto extract_sfmt_fcbeqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 60 :
+            if ((entire_insn & 0x79fcffff) == 0x78384000)
+              { itype = FRVBF_INSN_BGTLR; goto extract_sfmt_beqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 61 :
+            if ((entire_insn & 0x79fcefff) == 0x78386000)
+              { itype = FRVBF_INSN_BCGTLR; goto extract_sfmt_bceqlr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 62 :
+            if ((entire_insn & 0x7ffcffff) == 0x7838c000)
+              { itype = FRVBF_INSN_FBRALR; goto extract_sfmt_bralr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 63 :
+            if ((entire_insn & 0x7ffcefff) == 0x7838e000)
+              { itype = FRVBF_INSN_FCBRALR; goto extract_sfmt_bcralr; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 15 : itype = FRVBF_INSN_CALL; goto extract_sfmt_call;
-      case 16 : itype = FRVBF_INSN_ADDI; goto extract_sfmt_addi;
-      case 17 : itype = FRVBF_INSN_ADDICC; goto extract_sfmt_addicc;
-      case 18 : itype = FRVBF_INSN_ADDXI; goto extract_sfmt_addxi;
-      case 19 : itype = FRVBF_INSN_ADDXICC; goto extract_sfmt_addicc;
-      case 20 : itype = FRVBF_INSN_SUBI; goto extract_sfmt_addi;
-      case 21 : itype = FRVBF_INSN_SUBICC; goto extract_sfmt_addicc;
-      case 22 : itype = FRVBF_INSN_SUBXI; goto extract_sfmt_addxi;
-      case 23 : itype = FRVBF_INSN_SUBXICC; goto extract_sfmt_addicc;
-      case 24 : itype = FRVBF_INSN_SMULI; goto extract_sfmt_smuli;
-      case 25 : itype = FRVBF_INSN_SMULICC; goto extract_sfmt_smulicc;
-      case 26 : itype = FRVBF_INSN_UMULI; goto extract_sfmt_smuli;
-      case 27 : itype = FRVBF_INSN_UMULICC; goto extract_sfmt_smulicc;
+      case 15 :
+        if ((entire_insn & 0x1fc0000) == 0x3c0000)
+          { itype = FRVBF_INSN_CALL; goto extract_sfmt_call; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 16 :
+        if ((entire_insn & 0x1fc0000) == 0x400000)
+          { itype = FRVBF_INSN_ADDI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 17 :
+        if ((entire_insn & 0x1fc0000) == 0x440000)
+          { itype = FRVBF_INSN_ADDICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 18 :
+        if ((entire_insn & 0x1fc0000) == 0x480000)
+          { itype = FRVBF_INSN_ADDXI; goto extract_sfmt_addxi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 19 :
+        if ((entire_insn & 0x1fc0000) == 0x4c0000)
+          { itype = FRVBF_INSN_ADDXICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 20 :
+        if ((entire_insn & 0x1fc0000) == 0x500000)
+          { itype = FRVBF_INSN_SUBI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 21 :
+        if ((entire_insn & 0x1fc0000) == 0x540000)
+          { itype = FRVBF_INSN_SUBICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 22 :
+        if ((entire_insn & 0x1fc0000) == 0x580000)
+          { itype = FRVBF_INSN_SUBXI; goto extract_sfmt_addxi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 23 :
+        if ((entire_insn & 0x1fc0000) == 0x5c0000)
+          { itype = FRVBF_INSN_SUBXICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 24 :
+        if ((entire_insn & 0x1fc0000) == 0x600000)
+          { itype = FRVBF_INSN_SMULI; goto extract_sfmt_smuli; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 25 :
+        if ((entire_insn & 0x1fc0000) == 0x640000)
+          { itype = FRVBF_INSN_SMULICC; goto extract_sfmt_smulicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 26 :
+        if ((entire_insn & 0x1fc0000) == 0x680000)
+          { itype = FRVBF_INSN_UMULI; goto extract_sfmt_smuli; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 27 :
+        if ((entire_insn & 0x1fc0000) == 0x6c0000)
+          { itype = FRVBF_INSN_UMULICC; goto extract_sfmt_smulicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 28 :
         {
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_TINO; goto extract_sfmt_rei;
-          case 1 : itype = FRVBF_INSN_TIC; goto extract_sfmt_tieq;
-          case 2 : itype = FRVBF_INSN_TIV; goto extract_sfmt_tieq;
-          case 3 : itype = FRVBF_INSN_TILT; goto extract_sfmt_tieq;
-          case 4 : itype = FRVBF_INSN_TIEQ; goto extract_sfmt_tieq;
-          case 5 : itype = FRVBF_INSN_TILS; goto extract_sfmt_tieq;
-          case 6 : itype = FRVBF_INSN_TIN; goto extract_sfmt_tieq;
-          case 7 : itype = FRVBF_INSN_TILE; goto extract_sfmt_tieq;
-          case 8 : itype = FRVBF_INSN_TIRA; goto extract_sfmt_tira;
-          case 9 : itype = FRVBF_INSN_TINC; goto extract_sfmt_tieq;
-          case 10 : itype = FRVBF_INSN_TINV; goto extract_sfmt_tieq;
-          case 11 : itype = FRVBF_INSN_TIGE; goto extract_sfmt_tieq;
-          case 12 : itype = FRVBF_INSN_TINE; goto extract_sfmt_tieq;
-          case 13 : itype = FRVBF_INSN_TIHI; goto extract_sfmt_tieq;
-          case 14 : itype = FRVBF_INSN_TIP; goto extract_sfmt_tieq;
-          case 15 : itype = FRVBF_INSN_TIGT; goto extract_sfmt_tieq;
+          case 0 :
+            if ((entire_insn & 0x7fffffff) == 0x700000)
+              { itype = FRVBF_INSN_TINO; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fc0000) == 0x8700000)
+              { itype = FRVBF_INSN_TIC; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fc0000) == 0x10700000)
+              { itype = FRVBF_INSN_TIV; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fc0000) == 0x18700000)
+              { itype = FRVBF_INSN_TILT; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fc0000) == 0x20700000)
+              { itype = FRVBF_INSN_TIEQ; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fc0000) == 0x28700000)
+              { itype = FRVBF_INSN_TILS; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fc0000) == 0x30700000)
+              { itype = FRVBF_INSN_TIN; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fc0000) == 0x38700000)
+              { itype = FRVBF_INSN_TILE; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x7ffc0000) == 0x40700000)
+              { itype = FRVBF_INSN_TIRA; goto extract_sfmt_tira; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fc0000) == 0x48700000)
+              { itype = FRVBF_INSN_TINC; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fc0000) == 0x50700000)
+              { itype = FRVBF_INSN_TINV; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fc0000) == 0x58700000)
+              { itype = FRVBF_INSN_TIGE; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fc0000) == 0x60700000)
+              { itype = FRVBF_INSN_TINE; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fc0000) == 0x68700000)
+              { itype = FRVBF_INSN_TIHI; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fc0000) == 0x70700000)
+              { itype = FRVBF_INSN_TIP; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fc0000) == 0x78700000)
+              { itype = FRVBF_INSN_TIGT; goto extract_sfmt_tieq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1348,104 +2413,350 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 27) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_FTINO; goto extract_sfmt_rei;
-          case 1 : itype = FRVBF_INSN_FTIU; goto extract_sfmt_ftine;
-          case 2 : itype = FRVBF_INSN_FTIGT; goto extract_sfmt_ftine;
-          case 3 : itype = FRVBF_INSN_FTIUG; goto extract_sfmt_ftine;
-          case 4 : itype = FRVBF_INSN_FTILT; goto extract_sfmt_ftine;
-          case 5 : itype = FRVBF_INSN_FTIUL; goto extract_sfmt_ftine;
-          case 6 : itype = FRVBF_INSN_FTILG; goto extract_sfmt_ftine;
-          case 7 : itype = FRVBF_INSN_FTINE; goto extract_sfmt_ftine;
-          case 8 : itype = FRVBF_INSN_FTIEQ; goto extract_sfmt_ftine;
-          case 9 : itype = FRVBF_INSN_FTIUE; goto extract_sfmt_ftine;
-          case 10 : itype = FRVBF_INSN_FTIGE; goto extract_sfmt_ftine;
-          case 11 : itype = FRVBF_INSN_FTIUGE; goto extract_sfmt_ftine;
-          case 12 : itype = FRVBF_INSN_FTILE; goto extract_sfmt_ftine;
-          case 13 : itype = FRVBF_INSN_FTIULE; goto extract_sfmt_ftine;
-          case 14 : itype = FRVBF_INSN_FTIO; goto extract_sfmt_ftine;
-          case 15 : itype = FRVBF_INSN_FTIRA; goto extract_sfmt_tira;
+          case 0 :
+            if ((entire_insn & 0x7fffffff) == 0x740000)
+              { itype = FRVBF_INSN_FTINO; goto extract_sfmt_rei; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x79fc0000) == 0x8740000)
+              { itype = FRVBF_INSN_FTIU; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fc0000) == 0x10740000)
+              { itype = FRVBF_INSN_FTIGT; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fc0000) == 0x18740000)
+              { itype = FRVBF_INSN_FTIUG; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fc0000) == 0x20740000)
+              { itype = FRVBF_INSN_FTILT; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fc0000) == 0x28740000)
+              { itype = FRVBF_INSN_FTIUL; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fc0000) == 0x30740000)
+              { itype = FRVBF_INSN_FTILG; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fc0000) == 0x38740000)
+              { itype = FRVBF_INSN_FTINE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fc0000) == 0x40740000)
+              { itype = FRVBF_INSN_FTIEQ; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fc0000) == 0x48740000)
+              { itype = FRVBF_INSN_FTIUE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fc0000) == 0x50740000)
+              { itype = FRVBF_INSN_FTIGE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fc0000) == 0x58740000)
+              { itype = FRVBF_INSN_FTIUGE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fc0000) == 0x60740000)
+              { itype = FRVBF_INSN_FTILE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fc0000) == 0x68740000)
+              { itype = FRVBF_INSN_FTIULE; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fc0000) == 0x70740000)
+              { itype = FRVBF_INSN_FTIO; goto extract_sfmt_ftine; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x7ffc0000) == 0x78740000)
+              { itype = FRVBF_INSN_FTIRA; goto extract_sfmt_tira; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 30 : itype = FRVBF_INSN_SDIVI; goto extract_sfmt_sdivi;
-      case 31 : itype = FRVBF_INSN_UDIVI; goto extract_sfmt_sdivi;
-      case 32 : itype = FRVBF_INSN_ANDI; goto extract_sfmt_addi;
-      case 33 : itype = FRVBF_INSN_ANDICC; goto extract_sfmt_andicc;
-      case 34 : itype = FRVBF_INSN_ORI; goto extract_sfmt_addi;
-      case 35 : itype = FRVBF_INSN_ORICC; goto extract_sfmt_andicc;
-      case 36 : itype = FRVBF_INSN_XORI; goto extract_sfmt_addi;
-      case 37 : itype = FRVBF_INSN_XORICC; goto extract_sfmt_andicc;
-      case 40 : itype = FRVBF_INSN_SLLI; goto extract_sfmt_addi;
-      case 41 : itype = FRVBF_INSN_SLLICC; goto extract_sfmt_addicc;
-      case 42 : itype = FRVBF_INSN_SRLI; goto extract_sfmt_addi;
-      case 43 : itype = FRVBF_INSN_SRLICC; goto extract_sfmt_addicc;
-      case 44 : itype = FRVBF_INSN_SRAI; goto extract_sfmt_addi;
-      case 45 : itype = FRVBF_INSN_SRAICC; goto extract_sfmt_addicc;
-      case 46 : itype = FRVBF_INSN_NSDIVI; goto extract_sfmt_sdivi;
-      case 47 : itype = FRVBF_INSN_NUDIVI; goto extract_sfmt_sdivi;
-      case 48 : itype = FRVBF_INSN_LDSBI; goto extract_sfmt_ldsbi;
-      case 49 : itype = FRVBF_INSN_LDSHI; goto extract_sfmt_ldsbi;
-      case 50 : itype = FRVBF_INSN_LDI; goto extract_sfmt_ldsbi;
-      case 51 : itype = FRVBF_INSN_LDDI; goto extract_sfmt_lddi;
-      case 52 : itype = FRVBF_INSN_LDQI; goto extract_sfmt_ldqi;
-      case 53 : itype = FRVBF_INSN_LDUBI; goto extract_sfmt_ldsbi;
-      case 54 : itype = FRVBF_INSN_LDUHI; goto extract_sfmt_ldsbi;
-      case 55 : itype = FRVBF_INSN_REI; goto extract_sfmt_rei;
-      case 56 : itype = FRVBF_INSN_LDBFI; goto extract_sfmt_ldbfi;
-      case 57 : itype = FRVBF_INSN_LDHFI; goto extract_sfmt_ldbfi;
-      case 58 : itype = FRVBF_INSN_LDFI; goto extract_sfmt_ldbfi;
-      case 59 : itype = FRVBF_INSN_LDDFI; goto extract_sfmt_lddfi;
-      case 60 : itype = FRVBF_INSN_LDQFI; goto extract_sfmt_ldqfi;
-      case 61 : itype = FRVBF_INSN_SETLO; goto extract_sfmt_setlo;
-      case 62 : itype = FRVBF_INSN_SETHI; goto extract_sfmt_sethi;
-      case 63 : itype = FRVBF_INSN_SETLOS; goto extract_sfmt_setlos;
-      case 64 : itype = FRVBF_INSN_NLDSBI; goto extract_sfmt_nldsbi;
-      case 65 : itype = FRVBF_INSN_NLDUBI; goto extract_sfmt_nldsbi;
-      case 66 : itype = FRVBF_INSN_NLDSHI; goto extract_sfmt_nldsbi;
-      case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi;
-      case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi;
-      case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi;
+      case 30 :
+        if ((entire_insn & 0x1fc0000) == 0x780000)
+          { itype = FRVBF_INSN_SDIVI; goto extract_sfmt_sdivi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 31 :
+        if ((entire_insn & 0x1fc0000) == 0x7c0000)
+          { itype = FRVBF_INSN_UDIVI; goto extract_sfmt_sdivi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 32 :
+        if ((entire_insn & 0x1fc0000) == 0x800000)
+          { itype = FRVBF_INSN_ANDI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 33 :
+        if ((entire_insn & 0x1fc0000) == 0x840000)
+          { itype = FRVBF_INSN_ANDICC; goto extract_sfmt_andicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 34 :
+        if ((entire_insn & 0x1fc0000) == 0x880000)
+          { itype = FRVBF_INSN_ORI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 35 :
+        if ((entire_insn & 0x1fc0000) == 0x8c0000)
+          { itype = FRVBF_INSN_ORICC; goto extract_sfmt_andicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 36 :
+        if ((entire_insn & 0x1fc0000) == 0x900000)
+          { itype = FRVBF_INSN_XORI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 37 :
+        if ((entire_insn & 0x1fc0000) == 0x940000)
+          { itype = FRVBF_INSN_XORICC; goto extract_sfmt_andicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 40 :
+        if ((entire_insn & 0x1fc0000) == 0xa00000)
+          { itype = FRVBF_INSN_SLLI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 41 :
+        if ((entire_insn & 0x1fc0000) == 0xa40000)
+          { itype = FRVBF_INSN_SLLICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 42 :
+        if ((entire_insn & 0x1fc0000) == 0xa80000)
+          { itype = FRVBF_INSN_SRLI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 43 :
+        if ((entire_insn & 0x1fc0000) == 0xac0000)
+          { itype = FRVBF_INSN_SRLICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 44 :
+        if ((entire_insn & 0x1fc0000) == 0xb00000)
+          { itype = FRVBF_INSN_SRAI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 45 :
+        if ((entire_insn & 0x1fc0000) == 0xb40000)
+          { itype = FRVBF_INSN_SRAICC; goto extract_sfmt_addicc; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 46 :
+        if ((entire_insn & 0x1fc0000) == 0xb80000)
+          { itype = FRVBF_INSN_NSDIVI; goto extract_sfmt_sdivi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 47 :
+        if ((entire_insn & 0x1fc0000) == 0xbc0000)
+          { itype = FRVBF_INSN_NUDIVI; goto extract_sfmt_sdivi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 48 :
+        if ((entire_insn & 0x1fc0000) == 0xc00000)
+          { itype = FRVBF_INSN_LDSBI; goto extract_sfmt_ldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 49 :
+        if ((entire_insn & 0x1fc0000) == 0xc40000)
+          { itype = FRVBF_INSN_LDSHI; goto extract_sfmt_ldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 50 :
+        if ((entire_insn & 0x1fc0000) == 0xc80000)
+          { itype = FRVBF_INSN_LDI; goto extract_sfmt_ldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 51 :
+        if ((entire_insn & 0x1fc0000) == 0xcc0000)
+          { itype = FRVBF_INSN_LDDI; goto extract_sfmt_lddi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 52 :
+        if ((entire_insn & 0x1fc0000) == 0xd00000)
+          { itype = FRVBF_INSN_LDQI; goto extract_sfmt_ldqi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 53 :
+        if ((entire_insn & 0x1fc0000) == 0xd40000)
+          { itype = FRVBF_INSN_LDUBI; goto extract_sfmt_ldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 54 :
+        if ((entire_insn & 0x1fc0000) == 0xd80000)
+          { itype = FRVBF_INSN_LDUHI; goto extract_sfmt_ldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 55 :
+        if ((entire_insn & 0x7ffc0fff) == 0xdc0000)
+          { itype = FRVBF_INSN_REI; goto extract_sfmt_rei; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 56 :
+        if ((entire_insn & 0x1fc0000) == 0xe00000)
+          { itype = FRVBF_INSN_LDBFI; goto extract_sfmt_ldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 57 :
+        if ((entire_insn & 0x1fc0000) == 0xe40000)
+          { itype = FRVBF_INSN_LDHFI; goto extract_sfmt_ldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 58 :
+        if ((entire_insn & 0x1fc0000) == 0xe80000)
+          { itype = FRVBF_INSN_LDFI; goto extract_sfmt_ldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 59 :
+        if ((entire_insn & 0x1fc0000) == 0xec0000)
+          { itype = FRVBF_INSN_LDDFI; goto extract_sfmt_lddfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 60 :
+        if ((entire_insn & 0x1fc0000) == 0xf00000)
+          { itype = FRVBF_INSN_LDQFI; goto extract_sfmt_ldqfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 61 :
+        if ((entire_insn & 0x1ff0000) == 0xf40000)
+          { itype = FRVBF_INSN_SETLO; goto extract_sfmt_setlo; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 62 :
+        if ((entire_insn & 0x1ff0000) == 0xf80000)
+          { itype = FRVBF_INSN_SETHI; goto extract_sfmt_sethi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 63 :
+        if ((entire_insn & 0x1ff0000) == 0xfc0000)
+          { itype = FRVBF_INSN_SETLOS; goto extract_sfmt_setlos; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 64 :
+        if ((entire_insn & 0x1fc0000) == 0x1000000)
+          { itype = FRVBF_INSN_NLDSBI; goto extract_sfmt_nldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 65 :
+        if ((entire_insn & 0x1fc0000) == 0x1040000)
+          { itype = FRVBF_INSN_NLDUBI; goto extract_sfmt_nldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 66 :
+        if ((entire_insn & 0x1fc0000) == 0x1080000)
+          { itype = FRVBF_INSN_NLDSHI; goto extract_sfmt_nldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 67 :
+        if ((entire_insn & 0x1fc0000) == 0x10c0000)
+          { itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 68 :
+        if ((entire_insn & 0x1fc0000) == 0x1100000)
+          { itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 69 :
+        if ((entire_insn & 0x1fc0000) == 0x1140000)
+          { itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 70 :
         {
           unsigned int val = (((insn >> 6) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_ADDSS; goto extract_sfmt_add;
-          case 1 : itype = FRVBF_INSN_SUBSS; goto extract_sfmt_add;
-          case 2 : itype = FRVBF_INSN_SLASS; goto extract_sfmt_add;
-          case 4 : itype = FRVBF_INSN_SCUTSS; goto extract_sfmt_scutss;
-          case 5 : itype = FRVBF_INSN_SMU; goto extract_sfmt_smu;
-          case 6 : itype = FRVBF_INSN_SMASS; goto extract_sfmt_smass;
-          case 7 : itype = FRVBF_INSN_SMSSS; goto extract_sfmt_smass;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1180000)
+              { itype = FRVBF_INSN_ADDSS; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1180040)
+              { itype = FRVBF_INSN_SUBSS; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1180080)
+              { itype = FRVBF_INSN_SLASS; goto extract_sfmt_add; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1ffffc0) == 0x1180100)
+              { itype = FRVBF_INSN_SCUTSS; goto extract_sfmt_scutss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x1180140)
+              { itype = FRVBF_INSN_SMU; goto extract_sfmt_smu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x1180180)
+              { itype = FRVBF_INSN_SMASS; goto extract_sfmt_smass; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x7ffc0fc0) == 0x11801c0)
+              { itype = FRVBF_INSN_SMSSS; goto extract_sfmt_smass; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi;
-      case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi;
-      case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi;
-      case 74 : itype = FRVBF_INSN_NLDFI; goto extract_sfmt_nldbfi;
-      case 75 : itype = FRVBF_INSN_NLDDFI; goto extract_sfmt_nlddfi;
-      case 76 : itype = FRVBF_INSN_NLDQFI; goto extract_sfmt_nldqfi;
-      case 77 : itype = FRVBF_INSN_SWAPI; goto extract_sfmt_swapi;
-      case 78 : itype = FRVBF_INSN_STBFI; goto extract_sfmt_stbfi;
-      case 79 : itype = FRVBF_INSN_STHFI; goto extract_sfmt_stbfi;
-      case 80 : itype = FRVBF_INSN_STBI; goto extract_sfmt_stbi;
-      case 81 : itype = FRVBF_INSN_STHI; goto extract_sfmt_stbi;
-      case 82 : itype = FRVBF_INSN_STI; goto extract_sfmt_stbi;
-      case 83 : itype = FRVBF_INSN_STDI; goto extract_sfmt_stdi;
-      case 84 : itype = FRVBF_INSN_STQI; goto extract_sfmt_ldqi;
-      case 85 : itype = FRVBF_INSN_STFI; goto extract_sfmt_stbfi;
-      case 86 : itype = FRVBF_INSN_STDFI; goto extract_sfmt_stdfi;
-      case 87 : itype = FRVBF_INSN_STQFI; goto extract_sfmt_ldqfi;
+      case 71 :
+        if ((entire_insn & 0x1fc0000) == 0x11c0000)
+          { itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 72 :
+        if ((entire_insn & 0x1fc0000) == 0x1200000)
+          { itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 73 :
+        if ((entire_insn & 0x1fc0000) == 0x1240000)
+          { itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 74 :
+        if ((entire_insn & 0x1fc0000) == 0x1280000)
+          { itype = FRVBF_INSN_NLDFI; goto extract_sfmt_nldbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 75 :
+        if ((entire_insn & 0x1fc0000) == 0x12c0000)
+          { itype = FRVBF_INSN_NLDDFI; goto extract_sfmt_nlddfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 76 :
+        if ((entire_insn & 0x1fc0000) == 0x1300000)
+          { itype = FRVBF_INSN_NLDQFI; goto extract_sfmt_nldqfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 77 :
+        if ((entire_insn & 0x1fc0000) == 0x1340000)
+          { itype = FRVBF_INSN_SWAPI; goto extract_sfmt_swapi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 78 :
+        if ((entire_insn & 0x1fc0000) == 0x1380000)
+          { itype = FRVBF_INSN_STBFI; goto extract_sfmt_stbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 79 :
+        if ((entire_insn & 0x1fc0000) == 0x13c0000)
+          { itype = FRVBF_INSN_STHFI; goto extract_sfmt_stbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 80 :
+        if ((entire_insn & 0x1fc0000) == 0x1400000)
+          { itype = FRVBF_INSN_STBI; goto extract_sfmt_stbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 81 :
+        if ((entire_insn & 0x1fc0000) == 0x1440000)
+          { itype = FRVBF_INSN_STHI; goto extract_sfmt_stbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 82 :
+        if ((entire_insn & 0x1fc0000) == 0x1480000)
+          { itype = FRVBF_INSN_STI; goto extract_sfmt_stbi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 83 :
+        if ((entire_insn & 0x1fc0000) == 0x14c0000)
+          { itype = FRVBF_INSN_STDI; goto extract_sfmt_stdi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 84 :
+        if ((entire_insn & 0x1fc0000) == 0x1500000)
+          { itype = FRVBF_INSN_STQI; goto extract_sfmt_ldqi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 85 :
+        if ((entire_insn & 0x1fc0000) == 0x1540000)
+          { itype = FRVBF_INSN_STFI; goto extract_sfmt_stbfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 86 :
+        if ((entire_insn & 0x1fc0000) == 0x1580000)
+          { itype = FRVBF_INSN_STDFI; goto extract_sfmt_stdfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 87 :
+        if ((entire_insn & 0x1fc0000) == 0x15c0000)
+          { itype = FRVBF_INSN_STQFI; goto extract_sfmt_ldqfi; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 88 :
         {
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CADD; goto extract_sfmt_cadd;
-          case 1 : itype = FRVBF_INSN_CSUB; goto extract_sfmt_cadd;
-          case 2 : itype = FRVBF_INSN_CSMUL; goto extract_sfmt_csmul;
-          case 3 : itype = FRVBF_INSN_CSDIV; goto extract_sfmt_csdiv;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1600000)
+              { itype = FRVBF_INSN_CADD; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1600040)
+              { itype = FRVBF_INSN_CSUB; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1600080)
+              { itype = FRVBF_INSN_CSMUL; goto extract_sfmt_csmul; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x16000c0)
+              { itype = FRVBF_INSN_CSDIV; goto extract_sfmt_csdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1454,10 +2765,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CADDCC; goto extract_sfmt_caddcc;
-          case 1 : itype = FRVBF_INSN_CSUBCC; goto extract_sfmt_caddcc;
-          case 2 : itype = FRVBF_INSN_CSMULCC; goto extract_sfmt_csmulcc;
-          case 3 : itype = FRVBF_INSN_CUDIV; goto extract_sfmt_csdiv;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1640000)
+              { itype = FRVBF_INSN_CADDCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1640040)
+              { itype = FRVBF_INSN_CSUBCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1640080)
+              { itype = FRVBF_INSN_CSMULCC; goto extract_sfmt_csmulcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x16400c0)
+              { itype = FRVBF_INSN_CUDIV; goto extract_sfmt_csdiv; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1466,10 +2789,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CAND; goto extract_sfmt_cadd;
-          case 1 : itype = FRVBF_INSN_COR; goto extract_sfmt_cadd;
-          case 2 : itype = FRVBF_INSN_CXOR; goto extract_sfmt_cadd;
-          case 3 : itype = FRVBF_INSN_CNOT; goto extract_sfmt_cnot;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1680000)
+              { itype = FRVBF_INSN_CAND; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1680040)
+              { itype = FRVBF_INSN_COR; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1680080)
+              { itype = FRVBF_INSN_CXOR; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fff0c0) == 0x16800c0)
+              { itype = FRVBF_INSN_CNOT; goto extract_sfmt_cnot; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1478,9 +2813,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CANDCC; goto extract_sfmt_caddcc;
-          case 1 : itype = FRVBF_INSN_CORCC; goto extract_sfmt_caddcc;
-          case 2 : itype = FRVBF_INSN_CXORCC; goto extract_sfmt_caddcc;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x16c0000)
+              { itype = FRVBF_INSN_CANDCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x16c0040)
+              { itype = FRVBF_INSN_CORCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x16c0080)
+              { itype = FRVBF_INSN_CXORCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1489,9 +2833,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSLL; goto extract_sfmt_cadd;
-          case 1 : itype = FRVBF_INSN_CSRL; goto extract_sfmt_cadd;
-          case 2 : itype = FRVBF_INSN_CSRA; goto extract_sfmt_cadd;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1700000)
+              { itype = FRVBF_INSN_CSLL; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1700040)
+              { itype = FRVBF_INSN_CSRL; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1700080)
+              { itype = FRVBF_INSN_CSRA; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1500,9 +2853,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSLLCC; goto extract_sfmt_caddcc;
-          case 1 : itype = FRVBF_INSN_CSRLCC; goto extract_sfmt_caddcc;
-          case 2 : itype = FRVBF_INSN_CSRACC; goto extract_sfmt_caddcc;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1740000)
+              { itype = FRVBF_INSN_CSLLCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1740040)
+              { itype = FRVBF_INSN_CSRLCC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1740080)
+              { itype = FRVBF_INSN_CSRACC; goto extract_sfmt_caddcc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1511,10 +2873,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLDSB; goto extract_sfmt_cldsb;
-          case 1 : itype = FRVBF_INSN_CLDUB; goto extract_sfmt_cldsb;
-          case 2 : itype = FRVBF_INSN_CLDSH; goto extract_sfmt_cldsb;
-          case 3 : itype = FRVBF_INSN_CLDUH; goto extract_sfmt_cldsb;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1780000)
+              { itype = FRVBF_INSN_CLDSB; goto extract_sfmt_cldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1780040)
+              { itype = FRVBF_INSN_CLDUB; goto extract_sfmt_cldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1780080)
+              { itype = FRVBF_INSN_CLDSH; goto extract_sfmt_cldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x17800c0)
+              { itype = FRVBF_INSN_CLDUH; goto extract_sfmt_cldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1523,9 +2897,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLD; goto extract_sfmt_cldsb;
-          case 1 : itype = FRVBF_INSN_CLDD; goto extract_sfmt_cldd;
-          case 2 : itype = FRVBF_INSN_CLDQ; goto extract_sfmt_cldq;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x17c0000)
+              { itype = FRVBF_INSN_CLD; goto extract_sfmt_cldsb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x17c0040)
+              { itype = FRVBF_INSN_CLDD; goto extract_sfmt_cldd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x17c0080)
+              { itype = FRVBF_INSN_CLDQ; goto extract_sfmt_cldq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1534,10 +2917,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLDBF; goto extract_sfmt_cldbf;
-          case 1 : itype = FRVBF_INSN_CLDHF; goto extract_sfmt_cldbf;
-          case 2 : itype = FRVBF_INSN_CLDF; goto extract_sfmt_cldbf;
-          case 3 : itype = FRVBF_INSN_CLDDF; goto extract_sfmt_clddf;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1800000)
+              { itype = FRVBF_INSN_CLDBF; goto extract_sfmt_cldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1800040)
+              { itype = FRVBF_INSN_CLDHF; goto extract_sfmt_cldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1800080)
+              { itype = FRVBF_INSN_CLDF; goto extract_sfmt_cldbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x18000c0)
+              { itype = FRVBF_INSN_CLDDF; goto extract_sfmt_clddf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1546,10 +2941,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLDSBU; goto extract_sfmt_cldsbu;
-          case 1 : itype = FRVBF_INSN_CLDUBU; goto extract_sfmt_cldsbu;
-          case 2 : itype = FRVBF_INSN_CLDSHU; goto extract_sfmt_cldsbu;
-          case 3 : itype = FRVBF_INSN_CLDUHU; goto extract_sfmt_cldsbu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1840000)
+              { itype = FRVBF_INSN_CLDSBU; goto extract_sfmt_cldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1840040)
+              { itype = FRVBF_INSN_CLDUBU; goto extract_sfmt_cldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1840080)
+              { itype = FRVBF_INSN_CLDSHU; goto extract_sfmt_cldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x18400c0)
+              { itype = FRVBF_INSN_CLDUHU; goto extract_sfmt_cldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1558,9 +2965,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLDU; goto extract_sfmt_cldsbu;
-          case 1 : itype = FRVBF_INSN_CLDDU; goto extract_sfmt_clddu;
-          case 2 : itype = FRVBF_INSN_CLDQU; goto extract_sfmt_cldqu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1880000)
+              { itype = FRVBF_INSN_CLDU; goto extract_sfmt_cldsbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1880040)
+              { itype = FRVBF_INSN_CLDDU; goto extract_sfmt_clddu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1880080)
+              { itype = FRVBF_INSN_CLDQU; goto extract_sfmt_cldqu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1569,10 +2985,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CLDBFU; goto extract_sfmt_cldbfu;
-          case 1 : itype = FRVBF_INSN_CLDHFU; goto extract_sfmt_cldbfu;
-          case 2 : itype = FRVBF_INSN_CLDFU; goto extract_sfmt_cldbfu;
-          case 3 : itype = FRVBF_INSN_CLDDFU; goto extract_sfmt_clddfu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x18c0000)
+              { itype = FRVBF_INSN_CLDBFU; goto extract_sfmt_cldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x18c0040)
+              { itype = FRVBF_INSN_CLDHFU; goto extract_sfmt_cldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x18c0080)
+              { itype = FRVBF_INSN_CLDFU; goto extract_sfmt_cldbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x18c00c0)
+              { itype = FRVBF_INSN_CLDDFU; goto extract_sfmt_clddfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1581,10 +3009,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSTB; goto extract_sfmt_cstb;
-          case 1 : itype = FRVBF_INSN_CSTH; goto extract_sfmt_cstb;
-          case 2 : itype = FRVBF_INSN_CST; goto extract_sfmt_cstb;
-          case 3 : itype = FRVBF_INSN_CSTD; goto extract_sfmt_cstd;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1900000)
+              { itype = FRVBF_INSN_CSTB; goto extract_sfmt_cstb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1900040)
+              { itype = FRVBF_INSN_CSTH; goto extract_sfmt_cstb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1900080)
+              { itype = FRVBF_INSN_CST; goto extract_sfmt_cstb; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x19000c0)
+              { itype = FRVBF_INSN_CSTD; goto extract_sfmt_cstd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1593,9 +3033,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSTQ; goto extract_sfmt_cldq;
-          case 2 : itype = FRVBF_INSN_CSWAP; goto extract_sfmt_cswap;
-          case 3 : itype = FRVBF_INSN_CSCAN; goto extract_sfmt_cadd;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1940000)
+              { itype = FRVBF_INSN_CSTQ; goto extract_sfmt_cldq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1940080)
+              { itype = FRVBF_INSN_CSWAP; goto extract_sfmt_cswap; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x19400c0)
+              { itype = FRVBF_INSN_CSCAN; goto extract_sfmt_cadd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1604,10 +3053,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSTBF; goto extract_sfmt_cstbf;
-          case 1 : itype = FRVBF_INSN_CSTHF; goto extract_sfmt_cstbf;
-          case 2 : itype = FRVBF_INSN_CSTF; goto extract_sfmt_cstbf;
-          case 3 : itype = FRVBF_INSN_CSTDF; goto extract_sfmt_cstdf;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1980000)
+              { itype = FRVBF_INSN_CSTBF; goto extract_sfmt_cstbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1980040)
+              { itype = FRVBF_INSN_CSTHF; goto extract_sfmt_cstbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1980080)
+              { itype = FRVBF_INSN_CSTF; goto extract_sfmt_cstbf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x19800c0)
+              { itype = FRVBF_INSN_CSTDF; goto extract_sfmt_cstdf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1616,10 +3077,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSTBU; goto extract_sfmt_cstbu;
-          case 1 : itype = FRVBF_INSN_CSTHU; goto extract_sfmt_cstbu;
-          case 2 : itype = FRVBF_INSN_CSTU; goto extract_sfmt_cstbu;
-          case 3 : itype = FRVBF_INSN_CSTDU; goto extract_sfmt_cstdu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x19c0000)
+              { itype = FRVBF_INSN_CSTBU; goto extract_sfmt_cstbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x19c0040)
+              { itype = FRVBF_INSN_CSTHU; goto extract_sfmt_cstbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x19c0080)
+              { itype = FRVBF_INSN_CSTU; goto extract_sfmt_cstbu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x19c00c0)
+              { itype = FRVBF_INSN_CSTDU; goto extract_sfmt_cstdu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1628,10 +3101,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CSTBFU; goto extract_sfmt_cstbfu;
-          case 1 : itype = FRVBF_INSN_CSTHFU; goto extract_sfmt_cstbfu;
-          case 2 : itype = FRVBF_INSN_CSTFU; goto extract_sfmt_cstbfu;
-          case 3 : itype = FRVBF_INSN_CSTDFU; goto extract_sfmt_cstdfu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1a00000)
+              { itype = FRVBF_INSN_CSTBFU; goto extract_sfmt_cstbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1a00040)
+              { itype = FRVBF_INSN_CSTHFU; goto extract_sfmt_cstbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1a00080)
+              { itype = FRVBF_INSN_CSTFU; goto extract_sfmt_cstbfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1a000c0)
+              { itype = FRVBF_INSN_CSTDFU; goto extract_sfmt_cstdfu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1640,10 +3125,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMOVGF; goto extract_sfmt_cmovgf;
-          case 1 : itype = FRVBF_INSN_CMOVGFD; goto extract_sfmt_cmovgfd;
-          case 2 : itype = FRVBF_INSN_CMOVFG; goto extract_sfmt_cmovfg;
-          case 3 : itype = FRVBF_INSN_CMOVFGD; goto extract_sfmt_cmovfgd;
+          case 0 :
+            if ((entire_insn & 0x1fff0c0) == 0x1a40000)
+              { itype = FRVBF_INSN_CMOVGF; goto extract_sfmt_cmovgf; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fff0c0) == 0x1a40040)
+              { itype = FRVBF_INSN_CMOVGFD; goto extract_sfmt_cmovgfd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fff0c0) == 0x1a40080)
+              { itype = FRVBF_INSN_CMOVFG; goto extract_sfmt_cmovfg; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fff0c0) == 0x1a400c0)
+              { itype = FRVBF_INSN_CMOVFGD; goto extract_sfmt_cmovfgd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1658,43 +3155,145 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               switch (val)
               {
               case 0 : /* fall through */
-              case 2 : itype = FRVBF_INSN_CCKNO; goto extract_sfmt_cckra;
-              case 1 : itype = FRVBF_INSN_CJMPL; goto extract_sfmt_cjmpl;
-              case 3 : itype = FRVBF_INSN_CCALLL; goto extract_sfmt_cjmpl;
+              case 2 :
+                if ((entire_insn & 0x79fff0ff) == 0x1a80000)
+                  { itype = FRVBF_INSN_CCKNO; goto extract_sfmt_cckra; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x7ffc00c0) == 0x1a80080)
+                  { itype = FRVBF_INSN_CJMPL; goto extract_sfmt_cjmpl; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x7ffc00c0) == 0x3a80080)
+                  { itype = FRVBF_INSN_CCALLL; goto extract_sfmt_cjmpl; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
-          case 1 : itype = FRVBF_INSN_CFCKNO; goto extract_sfmt_cfckra;
-          case 2 : itype = FRVBF_INSN_CCKC; goto extract_sfmt_cckeq;
-          case 3 : itype = FRVBF_INSN_CFCKU; goto extract_sfmt_cfckne;
-          case 4 : itype = FRVBF_INSN_CCKV; goto extract_sfmt_cckeq;
-          case 5 : itype = FRVBF_INSN_CFCKGT; goto extract_sfmt_cfckne;
-          case 6 : itype = FRVBF_INSN_CCKLT; goto extract_sfmt_cckeq;
-          case 7 : itype = FRVBF_INSN_CFCKUG; goto extract_sfmt_cfckne;
-          case 8 : itype = FRVBF_INSN_CCKEQ; goto extract_sfmt_cckeq;
-          case 9 : itype = FRVBF_INSN_CFCKLT; goto extract_sfmt_cfckne;
-          case 10 : itype = FRVBF_INSN_CCKLS; goto extract_sfmt_cckeq;
-          case 11 : itype = FRVBF_INSN_CFCKUL; goto extract_sfmt_cfckne;
-          case 12 : itype = FRVBF_INSN_CCKN; goto extract_sfmt_cckeq;
-          case 13 : itype = FRVBF_INSN_CFCKLG; goto extract_sfmt_cfckne;
-          case 14 : itype = FRVBF_INSN_CCKLE; goto extract_sfmt_cckeq;
-          case 15 : itype = FRVBF_INSN_CFCKNE; goto extract_sfmt_cfckne;
-          case 16 : itype = FRVBF_INSN_CCKRA; goto extract_sfmt_cckra;
-          case 17 : itype = FRVBF_INSN_CFCKEQ; goto extract_sfmt_cfckne;
-          case 18 : itype = FRVBF_INSN_CCKNC; goto extract_sfmt_cckeq;
-          case 19 : itype = FRVBF_INSN_CFCKUE; goto extract_sfmt_cfckne;
-          case 20 : itype = FRVBF_INSN_CCKNV; goto extract_sfmt_cckeq;
-          case 21 : itype = FRVBF_INSN_CFCKGE; goto extract_sfmt_cfckne;
-          case 22 : itype = FRVBF_INSN_CCKGE; goto extract_sfmt_cckeq;
-          case 23 : itype = FRVBF_INSN_CFCKUGE; goto extract_sfmt_cfckne;
-          case 24 : itype = FRVBF_INSN_CCKNE; goto extract_sfmt_cckeq;
-          case 25 : itype = FRVBF_INSN_CFCKLE; goto extract_sfmt_cfckne;
-          case 26 : itype = FRVBF_INSN_CCKHI; goto extract_sfmt_cckeq;
-          case 27 : itype = FRVBF_INSN_CFCKULE; goto extract_sfmt_cfckne;
-          case 28 : itype = FRVBF_INSN_CCKP; goto extract_sfmt_cckeq;
-          case 29 : itype = FRVBF_INSN_CFCKO; goto extract_sfmt_cfckne;
-          case 30 : itype = FRVBF_INSN_CCKGT; goto extract_sfmt_cckeq;
-          case 31 : itype = FRVBF_INSN_CFCKRA; goto extract_sfmt_cfckra;
+          case 1 :
+            if ((entire_insn & 0x79fff0ff) == 0x1a80040)
+              { itype = FRVBF_INSN_CFCKNO; goto extract_sfmt_cfckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fff0fc) == 0x9a80000)
+              { itype = FRVBF_INSN_CCKC; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x79fff0fc) == 0x9a80040)
+              { itype = FRVBF_INSN_CFCKU; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x79fff0fc) == 0x11a80000)
+              { itype = FRVBF_INSN_CCKV; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x79fff0fc) == 0x11a80040)
+              { itype = FRVBF_INSN_CFCKGT; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x79fff0fc) == 0x19a80000)
+              { itype = FRVBF_INSN_CCKLT; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x79fff0fc) == 0x19a80040)
+              { itype = FRVBF_INSN_CFCKUG; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x79fff0fc) == 0x21a80000)
+              { itype = FRVBF_INSN_CCKEQ; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x79fff0fc) == 0x21a80040)
+              { itype = FRVBF_INSN_CFCKLT; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fff0fc) == 0x29a80000)
+              { itype = FRVBF_INSN_CCKLS; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x79fff0fc) == 0x29a80040)
+              { itype = FRVBF_INSN_CFCKUL; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x79fff0fc) == 0x31a80000)
+              { itype = FRVBF_INSN_CCKN; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x79fff0fc) == 0x31a80040)
+              { itype = FRVBF_INSN_CFCKLG; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fff0fc) == 0x39a80000)
+              { itype = FRVBF_INSN_CCKLE; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fff0fc) == 0x39a80040)
+              { itype = FRVBF_INSN_CFCKNE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x79fff0ff) == 0x41a80000)
+              { itype = FRVBF_INSN_CCKRA; goto extract_sfmt_cckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x79fff0fc) == 0x41a80040)
+              { itype = FRVBF_INSN_CFCKEQ; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 18 :
+            if ((entire_insn & 0x79fff0fc) == 0x49a80000)
+              { itype = FRVBF_INSN_CCKNC; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x79fff0fc) == 0x49a80040)
+              { itype = FRVBF_INSN_CFCKUE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x79fff0fc) == 0x51a80000)
+              { itype = FRVBF_INSN_CCKNV; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x79fff0fc) == 0x51a80040)
+              { itype = FRVBF_INSN_CFCKGE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 22 :
+            if ((entire_insn & 0x79fff0fc) == 0x59a80000)
+              { itype = FRVBF_INSN_CCKGE; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 23 :
+            if ((entire_insn & 0x79fff0fc) == 0x59a80040)
+              { itype = FRVBF_INSN_CFCKUGE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x79fff0fc) == 0x61a80000)
+              { itype = FRVBF_INSN_CCKNE; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x79fff0fc) == 0x61a80040)
+              { itype = FRVBF_INSN_CFCKLE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 26 :
+            if ((entire_insn & 0x79fff0fc) == 0x69a80000)
+              { itype = FRVBF_INSN_CCKHI; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 27 :
+            if ((entire_insn & 0x79fff0fc) == 0x69a80040)
+              { itype = FRVBF_INSN_CFCKULE; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x79fff0fc) == 0x71a80000)
+              { itype = FRVBF_INSN_CCKP; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 29 :
+            if ((entire_insn & 0x79fff0fc) == 0x71a80040)
+              { itype = FRVBF_INSN_CFCKO; goto extract_sfmt_cfckne; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 30 :
+            if ((entire_insn & 0x79fff0fc) == 0x79a80000)
+              { itype = FRVBF_INSN_CCKGT; goto extract_sfmt_cckeq; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 31 :
+            if ((entire_insn & 0x79fff0ff) == 0x79a80040)
+              { itype = FRVBF_INSN_CFCKRA; goto extract_sfmt_cfckra; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1703,8 +3302,14 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CFITOS; goto extract_sfmt_cfitos;
-          case 1 : itype = FRVBF_INSN_CFSTOI; goto extract_sfmt_cfstoi;
+          case 0 :
+            if ((entire_insn & 0x1fff0c0) == 0x1ac0000)
+              { itype = FRVBF_INSN_CFITOS; goto extract_sfmt_cfitos; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fff0c0) == 0x1ac0040)
+              { itype = FRVBF_INSN_CFSTOI; goto extract_sfmt_cfstoi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1713,9 +3318,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CFMOVS; goto extract_sfmt_cfmovs;
-          case 1 : itype = FRVBF_INSN_CFNEGS; goto extract_sfmt_cfmovs;
-          case 2 : itype = FRVBF_INSN_CFABSS; goto extract_sfmt_cfmovs;
+          case 0 :
+            if ((entire_insn & 0x1fff0c0) == 0x1b00000)
+              { itype = FRVBF_INSN_CFMOVS; goto extract_sfmt_cfmovs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fff0c0) == 0x1b00040)
+              { itype = FRVBF_INSN_CFNEGS; goto extract_sfmt_cfmovs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fff0c0) == 0x1b00080)
+              { itype = FRVBF_INSN_CFABSS; goto extract_sfmt_cfmovs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1724,9 +3338,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CFADDS; goto extract_sfmt_cfadds;
-          case 1 : itype = FRVBF_INSN_CFSUBS; goto extract_sfmt_cfadds;
-          case 2 : itype = FRVBF_INSN_CFCMPS; goto extract_sfmt_cfcmps;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1b40000)
+              { itype = FRVBF_INSN_CFADDS; goto extract_sfmt_cfadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1b40040)
+              { itype = FRVBF_INSN_CFSUBS; goto extract_sfmt_cfadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x79fc00c0) == 0x1b40080)
+              { itype = FRVBF_INSN_CFCMPS; goto extract_sfmt_cfcmps; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1735,9 +3358,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CFMULS; goto extract_sfmt_cfadds;
-          case 1 : itype = FRVBF_INSN_CFDIVS; goto extract_sfmt_cfadds;
-          case 2 : itype = FRVBF_INSN_CFSQRTS; goto extract_sfmt_cfmovs;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1b80000)
+              { itype = FRVBF_INSN_CFMULS; goto extract_sfmt_cfadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1b80040)
+              { itype = FRVBF_INSN_CFDIVS; goto extract_sfmt_cfadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fff0c0) == 0x1b80080)
+              { itype = FRVBF_INSN_CFSQRTS; goto extract_sfmt_cfmovs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1746,10 +3378,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CFMADDS; goto extract_sfmt_cfmadds;
-          case 1 : itype = FRVBF_INSN_CFMSUBS; goto extract_sfmt_cfmadds;
-          case 2 : itype = FRVBF_INSN_CFMAS; goto extract_sfmt_cfmas;
-          case 3 : itype = FRVBF_INSN_CFMSS; goto extract_sfmt_cfmas;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1bc0000)
+              { itype = FRVBF_INSN_CFMADDS; goto extract_sfmt_cfmadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1bc0040)
+              { itype = FRVBF_INSN_CFMSUBS; goto extract_sfmt_cfmadds; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1bc0080)
+              { itype = FRVBF_INSN_CFMAS; goto extract_sfmt_cfmas; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1bc00c0)
+              { itype = FRVBF_INSN_CFMSS; goto extract_sfmt_cfmas; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1758,10 +3402,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMAND; goto extract_sfmt_cmand;
-          case 1 : itype = FRVBF_INSN_CMOR; goto extract_sfmt_cmand;
-          case 2 : itype = FRVBF_INSN_CMXOR; goto extract_sfmt_cmand;
-          case 3 : itype = FRVBF_INSN_CMNOT; goto extract_sfmt_cmnot;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c00000)
+              { itype = FRVBF_INSN_CMAND; goto extract_sfmt_cmand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c00040)
+              { itype = FRVBF_INSN_CMOR; goto extract_sfmt_cmand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c00080)
+              { itype = FRVBF_INSN_CMXOR; goto extract_sfmt_cmand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fff0c0) == 0x1c000c0)
+              { itype = FRVBF_INSN_CMNOT; goto extract_sfmt_cmnot; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1770,10 +3426,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMADDHSS; goto extract_sfmt_cmaddhss;
-          case 1 : itype = FRVBF_INSN_CMADDHUS; goto extract_sfmt_cmaddhss;
-          case 2 : itype = FRVBF_INSN_CMSUBHSS; goto extract_sfmt_cmaddhss;
-          case 3 : itype = FRVBF_INSN_CMSUBHUS; goto extract_sfmt_cmaddhss;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c40000)
+              { itype = FRVBF_INSN_CMADDHSS; goto extract_sfmt_cmaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c40040)
+              { itype = FRVBF_INSN_CMADDHUS; goto extract_sfmt_cmaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c40080)
+              { itype = FRVBF_INSN_CMSUBHSS; goto extract_sfmt_cmaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c400c0)
+              { itype = FRVBF_INSN_CMSUBHUS; goto extract_sfmt_cmaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1782,10 +3450,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMMULHS; goto extract_sfmt_cmmulhs;
-          case 1 : itype = FRVBF_INSN_CMMULHU; goto extract_sfmt_cmmulhs;
-          case 2 : itype = FRVBF_INSN_CMMACHS; goto extract_sfmt_cmmachs;
-          case 3 : itype = FRVBF_INSN_CMMACHU; goto extract_sfmt_cmmachu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c80000)
+              { itype = FRVBF_INSN_CMMULHS; goto extract_sfmt_cmmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c80040)
+              { itype = FRVBF_INSN_CMMULHU; goto extract_sfmt_cmmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c80080)
+              { itype = FRVBF_INSN_CMMACHS; goto extract_sfmt_cmmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1c800c0)
+              { itype = FRVBF_INSN_CMMACHU; goto extract_sfmt_cmmachu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1794,10 +3474,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMQADDHSS; goto extract_sfmt_cmqaddhss;
-          case 1 : itype = FRVBF_INSN_CMQADDHUS; goto extract_sfmt_cmqaddhss;
-          case 2 : itype = FRVBF_INSN_CMQSUBHSS; goto extract_sfmt_cmqaddhss;
-          case 3 : itype = FRVBF_INSN_CMQSUBHUS; goto extract_sfmt_cmqaddhss;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1cc0000)
+              { itype = FRVBF_INSN_CMQADDHSS; goto extract_sfmt_cmqaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1cc0040)
+              { itype = FRVBF_INSN_CMQADDHUS; goto extract_sfmt_cmqaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1cc0080)
+              { itype = FRVBF_INSN_CMQSUBHSS; goto extract_sfmt_cmqaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1cc00c0)
+              { itype = FRVBF_INSN_CMQSUBHUS; goto extract_sfmt_cmqaddhss; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1806,10 +3498,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMQMULHS; goto extract_sfmt_cmqmulhs;
-          case 1 : itype = FRVBF_INSN_CMQMULHU; goto extract_sfmt_cmqmulhs;
-          case 2 : itype = FRVBF_INSN_CMQMACHS; goto extract_sfmt_cmqmachs;
-          case 3 : itype = FRVBF_INSN_CMQMACHU; goto extract_sfmt_cmqmachu;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d00000)
+              { itype = FRVBF_INSN_CMQMULHS; goto extract_sfmt_cmqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d00040)
+              { itype = FRVBF_INSN_CMQMULHU; goto extract_sfmt_cmqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d00080)
+              { itype = FRVBF_INSN_CMQMACHS; goto extract_sfmt_cmqmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d000c0)
+              { itype = FRVBF_INSN_CMQMACHU; goto extract_sfmt_cmqmachu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1818,10 +3522,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMCPXRS; goto extract_sfmt_cmcpxrs;
-          case 1 : itype = FRVBF_INSN_CMCPXRU; goto extract_sfmt_cmcpxrs;
-          case 2 : itype = FRVBF_INSN_CMCPXIS; goto extract_sfmt_cmcpxrs;
-          case 3 : itype = FRVBF_INSN_CMCPXIU; goto extract_sfmt_cmcpxrs;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d40000)
+              { itype = FRVBF_INSN_CMCPXRS; goto extract_sfmt_cmcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d40040)
+              { itype = FRVBF_INSN_CMCPXRU; goto extract_sfmt_cmcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d40080)
+              { itype = FRVBF_INSN_CMCPXIS; goto extract_sfmt_cmcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d400c0)
+              { itype = FRVBF_INSN_CMCPXIU; goto extract_sfmt_cmcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1830,8 +3546,14 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMEXPDHW; goto extract_sfmt_cmexpdhw;
-          case 1 : itype = FRVBF_INSN_CMEXPDHD; goto extract_sfmt_cmexpdhd;
+          case 0 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d80080)
+              { itype = FRVBF_INSN_CMEXPDHW; goto extract_sfmt_cmexpdhw; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc00c0) == 0x1d800c0)
+              { itype = FRVBF_INSN_CMEXPDHD; goto extract_sfmt_cmexpdhd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1840,9 +3562,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_CMBTOH; goto extract_sfmt_cmbtoh;
-          case 1 : itype = FRVBF_INSN_CMHTOB; goto extract_sfmt_cmhtob;
-          case 2 : itype = FRVBF_INSN_CMBTOHE; goto extract_sfmt_cmbtohe;
+          case 0 :
+            if ((entire_insn & 0x1fff0c0) == 0x1dc0000)
+              { itype = FRVBF_INSN_CMBTOH; goto extract_sfmt_cmbtoh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fff0c0) == 0x1dc0040)
+              { itype = FRVBF_INSN_CMHTOB; goto extract_sfmt_cmhtob; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fff0c0) == 0x1dc0080)
+              { itype = FRVBF_INSN_CMBTOHE; goto extract_sfmt_cmbtohe; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1851,31 +3582,106 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (63 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs;
-          case 1 : itype = FRVBF_INSN_MQXMACXHS; goto extract_sfmt_mqmachs;
-          case 2 : itype = FRVBF_INSN_MQMACXHS; goto extract_sfmt_mqmachs;
-          case 4 : itype = FRVBF_INSN_MADDACCS; goto extract_sfmt_maddaccs;
-          case 5 : itype = FRVBF_INSN_MSUBACCS; goto extract_sfmt_maddaccs;
-          case 6 : itype = FRVBF_INSN_MDADDACCS; goto extract_sfmt_mdaddaccs;
-          case 7 : itype = FRVBF_INSN_MDSUBACCS; goto extract_sfmt_mdaddaccs;
-          case 8 : itype = FRVBF_INSN_MASACCS; goto extract_sfmt_masaccs;
-          case 9 : itype = FRVBF_INSN_MDASACCS; goto extract_sfmt_mdasaccs;
-          case 10 : itype = FRVBF_INSN_MABSHS; goto extract_sfmt_mabshs;
-          case 11 : itype = FRVBF_INSN_MDROTLI; goto extract_sfmt_mdrotli;
-          case 12 : itype = FRVBF_INSN_MCPLHI; goto extract_sfmt_mcplhi;
-          case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli;
-          case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi;
-          case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths;
-          case 16 : itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths;
-          case 17 : itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi;
-          case 19 : itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi;
-          case 20 : itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths;
-          case 32 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
-          case 33 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
-          case 34 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
-          case 35 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
-          case 36 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
-          case 37 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00000)
+              { itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00040)
+              { itype = FRVBF_INSN_MQXMACXHS; goto extract_sfmt_mqmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00080)
+              { itype = FRVBF_INSN_MQMACXHS; goto extract_sfmt_mqmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e00100)
+              { itype = FRVBF_INSN_MADDACCS; goto extract_sfmt_maddaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e00140)
+              { itype = FRVBF_INSN_MSUBACCS; goto extract_sfmt_maddaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e00180)
+              { itype = FRVBF_INSN_MDADDACCS; goto extract_sfmt_mdaddaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e001c0)
+              { itype = FRVBF_INSN_MDSUBACCS; goto extract_sfmt_mdaddaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e00200)
+              { itype = FRVBF_INSN_MASACCS; goto extract_sfmt_masaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc0fff) == 0x1e00240)
+              { itype = FRVBF_INSN_MDASACCS; goto extract_sfmt_mdasaccs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e00280)
+              { itype = FRVBF_INSN_MABSHS; goto extract_sfmt_mabshs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e002c0)
+              { itype = FRVBF_INSN_MDROTLI; goto extract_sfmt_mdrotli; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00300)
+              { itype = FRVBF_INSN_MCPLHI; goto extract_sfmt_mcplhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00340)
+              { itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00380)
+              { itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e003c0)
+              { itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00400)
+              { itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00440)
+              { itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e004c0)
+              { itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00500)
+              { itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00800)
+              { itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x1ffffe0) == 0x1e00840)
+              { itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 34 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00880)
+              { itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 35 :
+            if ((entire_insn & 0x1ffffe0) == 0x1e008c0)
+              { itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e00900)
+              { itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x1ffffe0) == 0x1e00940)
+              { itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -1889,10 +3695,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FITOS; goto extract_sfmt_fitos;
-              case 1 : itype = FRVBF_INSN_FMULS; goto extract_sfmt_fadds;
-              case 2 : itype = FRVBF_INSN_NFITOS; goto extract_sfmt_nfitos;
-              case 3 : itype = FRVBF_INSN_NFMULS; goto extract_sfmt_nfadds;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40000)
+                  { itype = FRVBF_INSN_FITOS; goto extract_sfmt_fitos; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40200)
+                  { itype = FRVBF_INSN_FMULS; goto extract_sfmt_fadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40800)
+                  { itype = FRVBF_INSN_NFITOS; goto extract_sfmt_nfitos; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40a00)
+                  { itype = FRVBF_INSN_NFMULS; goto extract_sfmt_nfadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1901,10 +3719,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FSTOI; goto extract_sfmt_fstoi;
-              case 1 : itype = FRVBF_INSN_FDIVS; goto extract_sfmt_fadds;
-              case 2 : itype = FRVBF_INSN_NFSTOI; goto extract_sfmt_nfstoi;
-              case 3 : itype = FRVBF_INSN_NFDIVS; goto extract_sfmt_nfadds;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40040)
+                  { itype = FRVBF_INSN_FSTOI; goto extract_sfmt_fstoi; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40240)
+                  { itype = FRVBF_INSN_FDIVS; goto extract_sfmt_fadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40840)
+                  { itype = FRVBF_INSN_NFSTOI; goto extract_sfmt_nfstoi; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40a40)
+                  { itype = FRVBF_INSN_NFDIVS; goto extract_sfmt_nfadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1913,8 +3743,14 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FMOVS; goto extract_sfmt_fmovs;
-              case 1 : itype = FRVBF_INSN_FCMPS; goto extract_sfmt_fcmps;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40080)
+                  { itype = FRVBF_INSN_FMOVS; goto extract_sfmt_fmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x79fc0fc0) == 0x1e40280)
+                  { itype = FRVBF_INSN_FCMPS; goto extract_sfmt_fcmps; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1923,9 +3759,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FNEGS; goto extract_sfmt_fmovs;
-              case 1 : itype = FRVBF_INSN_FMADDS; goto extract_sfmt_fmadds;
-              case 3 : itype = FRVBF_INSN_NFMADDS; goto extract_sfmt_nfmadds;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e400c0)
+                  { itype = FRVBF_INSN_FNEGS; goto extract_sfmt_fmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e402c0)
+                  { itype = FRVBF_INSN_FMADDS; goto extract_sfmt_fmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40ac0)
+                  { itype = FRVBF_INSN_NFMADDS; goto extract_sfmt_nfmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1934,9 +3779,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FABSS; goto extract_sfmt_fmovs;
-              case 1 : itype = FRVBF_INSN_FMSUBS; goto extract_sfmt_fmadds;
-              case 3 : itype = FRVBF_INSN_NFMSUBS; goto extract_sfmt_nfmadds;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40100)
+                  { itype = FRVBF_INSN_FABSS; goto extract_sfmt_fmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40300)
+                  { itype = FRVBF_INSN_FMSUBS; goto extract_sfmt_fmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40b00)
+                  { itype = FRVBF_INSN_NFMSUBS; goto extract_sfmt_nfmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1945,9 +3799,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FSQRTS; goto extract_sfmt_fmovs;
-              case 1 : itype = FRVBF_INSN_FNOP; goto extract_sfmt_rei;
-              case 2 : itype = FRVBF_INSN_NFSQRTS; goto extract_sfmt_nfsqrts;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40140)
+                  { itype = FRVBF_INSN_FSQRTS; goto extract_sfmt_fmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x7fffffff) == 0x1e40340)
+                  { itype = FRVBF_INSN_FNOP; goto extract_sfmt_rei; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40940)
+                  { itype = FRVBF_INSN_NFSQRTS; goto extract_sfmt_nfsqrts; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1956,10 +3819,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FADDS; goto extract_sfmt_fadds;
-              case 1 : itype = FRVBF_INSN_FMAS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFADDS; goto extract_sfmt_nfadds;
-              case 3 : itype = FRVBF_INSN_NFMAS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40180)
+                  { itype = FRVBF_INSN_FADDS; goto extract_sfmt_fadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40380)
+                  { itype = FRVBF_INSN_FMAS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40980)
+                  { itype = FRVBF_INSN_NFADDS; goto extract_sfmt_nfadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40b80)
+                  { itype = FRVBF_INSN_NFMAS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1968,10 +3843,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FSUBS; goto extract_sfmt_fadds;
-              case 1 : itype = FRVBF_INSN_FMSS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFSUBS; goto extract_sfmt_nfadds;
-              case 3 : itype = FRVBF_INSN_NFMSS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e401c0)
+                  { itype = FRVBF_INSN_FSUBS; goto extract_sfmt_fadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e403c0)
+                  { itype = FRVBF_INSN_FMSS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e409c0)
+                  { itype = FRVBF_INSN_NFSUBS; goto extract_sfmt_nfadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40bc0)
+                  { itype = FRVBF_INSN_NFMSS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1980,10 +3867,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDITOS; goto extract_sfmt_fditos;
-              case 1 : itype = FRVBF_INSN_FDMULS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFDITOS; goto extract_sfmt_fditos;
-              case 3 : itype = FRVBF_INSN_NFDMULS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40400)
+                  { itype = FRVBF_INSN_FDITOS; goto extract_sfmt_fditos; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40600)
+                  { itype = FRVBF_INSN_FDMULS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40c00)
+                  { itype = FRVBF_INSN_NFDITOS; goto extract_sfmt_fditos; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40e00)
+                  { itype = FRVBF_INSN_NFDMULS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -1992,10 +3891,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDSTOI; goto extract_sfmt_fdstoi;
-              case 1 : itype = FRVBF_INSN_FDDIVS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFDSTOI; goto extract_sfmt_fdstoi;
-              case 3 : itype = FRVBF_INSN_NFDDIVS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40440)
+                  { itype = FRVBF_INSN_FDSTOI; goto extract_sfmt_fdstoi; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40640)
+                  { itype = FRVBF_INSN_FDDIVS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40c40)
+                  { itype = FRVBF_INSN_NFDSTOI; goto extract_sfmt_fdstoi; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40e40)
+                  { itype = FRVBF_INSN_NFDDIVS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2004,9 +3915,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDMOVS; goto extract_sfmt_fdmovs;
-              case 1 : itype = FRVBF_INSN_FDCMPS; goto extract_sfmt_fdcmps;
-              case 3 : itype = FRVBF_INSN_NFDCMPS; goto extract_sfmt_nfdcmps;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40480)
+                  { itype = FRVBF_INSN_FDMOVS; goto extract_sfmt_fdmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x79fc0fc0) == 0x1e40680)
+                  { itype = FRVBF_INSN_FDCMPS; goto extract_sfmt_fdcmps; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x79fc0fc0) == 0x1e40e80)
+                  { itype = FRVBF_INSN_NFDCMPS; goto extract_sfmt_nfdcmps; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2015,9 +3935,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDNEGS; goto extract_sfmt_fdmovs;
-              case 1 : itype = FRVBF_INSN_FDMADDS; goto extract_sfmt_fdmadds;
-              case 3 : itype = FRVBF_INSN_NFDMADDS; goto extract_sfmt_fdmadds;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e404c0)
+                  { itype = FRVBF_INSN_FDNEGS; goto extract_sfmt_fdmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e406c0)
+                  { itype = FRVBF_INSN_FDMADDS; goto extract_sfmt_fdmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40ec0)
+                  { itype = FRVBF_INSN_NFDMADDS; goto extract_sfmt_fdmadds; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2026,9 +3955,18 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDABSS; goto extract_sfmt_fdmovs;
-              case 1 : itype = FRVBF_INSN_FDMAS; goto extract_sfmt_fdmas;
-              case 3 : itype = FRVBF_INSN_NFDMAS; goto extract_sfmt_fdmas;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40500)
+                  { itype = FRVBF_INSN_FDABSS; goto extract_sfmt_fdmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40700)
+                  { itype = FRVBF_INSN_FDMAS; goto extract_sfmt_fdmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40f00)
+                  { itype = FRVBF_INSN_NFDMAS; goto extract_sfmt_fdmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2037,10 +3975,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDSQRTS; goto extract_sfmt_fdmovs;
-              case 1 : itype = FRVBF_INSN_FDMSS; goto extract_sfmt_fdmas;
-              case 2 : itype = FRVBF_INSN_NFDSQRTS; goto extract_sfmt_fdmovs;
-              case 3 : itype = FRVBF_INSN_NFDMSS; goto extract_sfmt_fdmas;
+              case 0 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40540)
+                  { itype = FRVBF_INSN_FDSQRTS; goto extract_sfmt_fdmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40740)
+                  { itype = FRVBF_INSN_FDMSS; goto extract_sfmt_fdmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1ffffc0) == 0x1e40d40)
+                  { itype = FRVBF_INSN_NFDSQRTS; goto extract_sfmt_fdmovs; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40f40)
+                  { itype = FRVBF_INSN_NFDMSS; goto extract_sfmt_fdmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2049,10 +3999,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDADDS; goto extract_sfmt_fmas;
-              case 1 : itype = FRVBF_INSN_FDSADS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFDADDS; goto extract_sfmt_fmas;
-              case 3 : itype = FRVBF_INSN_NFDSADS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40580)
+                  { itype = FRVBF_INSN_FDADDS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40780)
+                  { itype = FRVBF_INSN_FDSADS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40d80)
+                  { itype = FRVBF_INSN_NFDADDS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40f80)
+                  { itype = FRVBF_INSN_NFDSADS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2061,10 +4023,22 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
               unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_FDSUBS; goto extract_sfmt_fmas;
-              case 1 : itype = FRVBF_INSN_FDMULCS; goto extract_sfmt_fmas;
-              case 2 : itype = FRVBF_INSN_NFDSUBS; goto extract_sfmt_fmas;
-              case 3 : itype = FRVBF_INSN_NFDMULCS; goto extract_sfmt_fmas;
+              case 0 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e405c0)
+                  { itype = FRVBF_INSN_FDSUBS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 1 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e407c0)
+                  { itype = FRVBF_INSN_FDMULCS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 2 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40dc0)
+                  { itype = FRVBF_INSN_NFDSUBS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+              case 3 :
+                if ((entire_insn & 0x1fc0fc0) == 0x1e40fc0)
+                  { itype = FRVBF_INSN_NFDMULCS; goto extract_sfmt_fmas; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
@@ -2076,21 +4050,66 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_FITOD; goto extract_sfmt_fitod;
-          case 1 : itype = FRVBF_INSN_FDTOI; goto extract_sfmt_fdtoi;
-          case 2 : itype = FRVBF_INSN_FMOVD; goto extract_sfmt_fmovd;
-          case 3 : itype = FRVBF_INSN_FNEGD; goto extract_sfmt_fmovd;
-          case 4 : itype = FRVBF_INSN_FABSD; goto extract_sfmt_fmovd;
-          case 5 : itype = FRVBF_INSN_FSQRTD; goto extract_sfmt_fmovd;
-          case 6 : itype = FRVBF_INSN_FADDD; goto extract_sfmt_faddd;
-          case 7 : itype = FRVBF_INSN_FSUBD; goto extract_sfmt_faddd;
-          case 8 : itype = FRVBF_INSN_FMULD; goto extract_sfmt_faddd;
-          case 9 : itype = FRVBF_INSN_FDIVD; goto extract_sfmt_faddd;
-          case 10 : itype = FRVBF_INSN_FCMPD; goto extract_sfmt_fcmpd;
-          case 11 : itype = FRVBF_INSN_FMADDD; goto extract_sfmt_fmaddd;
-          case 12 : itype = FRVBF_INSN_FMSUBD; goto extract_sfmt_fmaddd;
-          case 14 : itype = FRVBF_INSN_FMAD; goto extract_sfmt_fmas;
-          case 15 : itype = FRVBF_INSN_FMSD; goto extract_sfmt_fmas;
+          case 0 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e80000)
+              { itype = FRVBF_INSN_FITOD; goto extract_sfmt_fitod; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e80040)
+              { itype = FRVBF_INSN_FDTOI; goto extract_sfmt_fdtoi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e80080)
+              { itype = FRVBF_INSN_FMOVD; goto extract_sfmt_fmovd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e800c0)
+              { itype = FRVBF_INSN_FNEGD; goto extract_sfmt_fmovd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e80100)
+              { itype = FRVBF_INSN_FABSD; goto extract_sfmt_fmovd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1ffffc0) == 0x1e80140)
+              { itype = FRVBF_INSN_FSQRTD; goto extract_sfmt_fmovd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e80180)
+              { itype = FRVBF_INSN_FADDD; goto extract_sfmt_faddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e801c0)
+              { itype = FRVBF_INSN_FSUBD; goto extract_sfmt_faddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e80200)
+              { itype = FRVBF_INSN_FMULD; goto extract_sfmt_faddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e80240)
+              { itype = FRVBF_INSN_FDIVD; goto extract_sfmt_faddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x79fc0fc0) == 0x1e80280)
+              { itype = FRVBF_INSN_FCMPD; goto extract_sfmt_fcmpd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e802c0)
+              { itype = FRVBF_INSN_FMADDD; goto extract_sfmt_fmaddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e80300)
+              { itype = FRVBF_INSN_FMSUBD; goto extract_sfmt_fmaddd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e80380)
+              { itype = FRVBF_INSN_FMAD; goto extract_sfmt_fmas; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1e803c0)
+              { itype = FRVBF_INSN_FMSD; goto extract_sfmt_fmas; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -2099,71 +4118,251 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 6) & (63 << 0)));
           switch (val)
           {
-          case 0 : itype = FRVBF_INSN_MAND; goto extract_sfmt_mand;
-          case 1 : itype = FRVBF_INSN_MOR; goto extract_sfmt_mand;
-          case 2 : itype = FRVBF_INSN_MXOR; goto extract_sfmt_mand;
-          case 3 : itype = FRVBF_INSN_MNOT; goto extract_sfmt_mnot;
-          case 4 : itype = FRVBF_INSN_MROTLI; goto extract_sfmt_mrotli;
-          case 5 : itype = FRVBF_INSN_MROTRI; goto extract_sfmt_mrotli;
-          case 6 : itype = FRVBF_INSN_MWCUT; goto extract_sfmt_mwcut;
-          case 7 : itype = FRVBF_INSN_MWCUTI; goto extract_sfmt_mwcuti;
-          case 8 : itype = FRVBF_INSN_MAVEH; goto extract_sfmt_mand;
-          case 9 : itype = FRVBF_INSN_MSLLHI; goto extract_sfmt_msllhi;
-          case 10 : itype = FRVBF_INSN_MSRLHI; goto extract_sfmt_msllhi;
-          case 11 : itype = FRVBF_INSN_MSRAHI; goto extract_sfmt_msllhi;
-          case 12 : itype = FRVBF_INSN_MSATHS; goto extract_sfmt_msaths;
-          case 13 : itype = FRVBF_INSN_MSATHU; goto extract_sfmt_msaths;
-          case 14 : itype = FRVBF_INSN_MCMPSH; goto extract_sfmt_mcmpsh;
-          case 15 : itype = FRVBF_INSN_MCMPUH; goto extract_sfmt_mcmpsh;
-          case 16 : itype = FRVBF_INSN_MADDHSS; goto extract_sfmt_msaths;
-          case 17 : itype = FRVBF_INSN_MADDHUS; goto extract_sfmt_msaths;
-          case 18 : itype = FRVBF_INSN_MSUBHSS; goto extract_sfmt_msaths;
-          case 19 : itype = FRVBF_INSN_MSUBHUS; goto extract_sfmt_msaths;
-          case 20 : itype = FRVBF_INSN_MMULHS; goto extract_sfmt_mmulhs;
-          case 21 : itype = FRVBF_INSN_MMULHU; goto extract_sfmt_mmulhs;
-          case 22 : itype = FRVBF_INSN_MMACHS; goto extract_sfmt_mmachs;
-          case 23 : itype = FRVBF_INSN_MMACHU; goto extract_sfmt_mmachu;
-          case 24 : itype = FRVBF_INSN_MQADDHSS; goto extract_sfmt_mqsaths;
-          case 25 : itype = FRVBF_INSN_MQADDHUS; goto extract_sfmt_mqsaths;
-          case 26 : itype = FRVBF_INSN_MQSUBHSS; goto extract_sfmt_mqsaths;
-          case 27 : itype = FRVBF_INSN_MQSUBHUS; goto extract_sfmt_mqsaths;
-          case 28 : itype = FRVBF_INSN_MQMULHS; goto extract_sfmt_mqmulhs;
-          case 29 : itype = FRVBF_INSN_MQMULHU; goto extract_sfmt_mqmulhs;
-          case 30 : itype = FRVBF_INSN_MQMACHS; goto extract_sfmt_mqmachs;
-          case 31 : itype = FRVBF_INSN_MQMACHU; goto extract_sfmt_mqmachu;
-          case 32 : itype = FRVBF_INSN_MCPXRS; goto extract_sfmt_mcpxrs;
-          case 33 : itype = FRVBF_INSN_MCPXRU; goto extract_sfmt_mcpxrs;
-          case 34 : itype = FRVBF_INSN_MCPXIS; goto extract_sfmt_mcpxrs;
-          case 35 : itype = FRVBF_INSN_MCPXIU; goto extract_sfmt_mcpxrs;
-          case 36 : itype = FRVBF_INSN_MQCPXRS; goto extract_sfmt_mqcpxrs;
-          case 37 : itype = FRVBF_INSN_MQCPXRU; goto extract_sfmt_mqcpxrs;
-          case 38 : itype = FRVBF_INSN_MQCPXIS; goto extract_sfmt_mqcpxrs;
-          case 39 : itype = FRVBF_INSN_MQCPXIU; goto extract_sfmt_mqcpxrs;
-          case 40 : itype = FRVBF_INSN_MMULXHS; goto extract_sfmt_mmulhs;
-          case 41 : itype = FRVBF_INSN_MMULXHU; goto extract_sfmt_mmulhs;
-          case 42 : itype = FRVBF_INSN_MQMULXHS; goto extract_sfmt_mqmulhs;
-          case 43 : itype = FRVBF_INSN_MQMULXHU; goto extract_sfmt_mqmulhs;
-          case 44 : itype = FRVBF_INSN_MCUT; goto extract_sfmt_mcut;
-          case 45 : itype = FRVBF_INSN_MCUTSS; goto extract_sfmt_mcut;
-          case 46 : itype = FRVBF_INSN_MCUTI; goto extract_sfmt_mcuti;
-          case 47 : itype = FRVBF_INSN_MCUTSSI; goto extract_sfmt_mcuti;
-          case 48 : itype = FRVBF_INSN_MMRDHS; goto extract_sfmt_mmachs;
-          case 49 : itype = FRVBF_INSN_MMRDHU; goto extract_sfmt_mmachu;
-          case 50 : itype = FRVBF_INSN_MEXPDHW; goto extract_sfmt_mexpdhw;
-          case 51 : itype = FRVBF_INSN_MEXPDHD; goto extract_sfmt_mexpdhd;
-          case 52 : itype = FRVBF_INSN_MPACKH; goto extract_sfmt_mpackh;
-          case 53 : itype = FRVBF_INSN_MUNPACKH; goto extract_sfmt_munpackh;
-          case 54 : itype = FRVBF_INSN_MDPACKH; goto extract_sfmt_mdpackh;
-          case 55 : itype = FRVBF_INSN_MDUNPACKH; goto extract_sfmt_mdunpackh;
-          case 56 : itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh;
-          case 57 : itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob;
-          case 58 : itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe;
+          case 0 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0000)
+              { itype = FRVBF_INSN_MAND; goto extract_sfmt_mand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0040)
+              { itype = FRVBF_INSN_MOR; goto extract_sfmt_mand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0080)
+              { itype = FRVBF_INSN_MXOR; goto extract_sfmt_mand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0x1ffffc0) == 0x1ec00c0)
+              { itype = FRVBF_INSN_MNOT; goto extract_sfmt_mnot; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0100)
+              { itype = FRVBF_INSN_MROTLI; goto extract_sfmt_mrotli; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0140)
+              { itype = FRVBF_INSN_MROTRI; goto extract_sfmt_mrotli; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0180)
+              { itype = FRVBF_INSN_MWCUT; goto extract_sfmt_mwcut; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec01c0)
+              { itype = FRVBF_INSN_MWCUTI; goto extract_sfmt_mwcuti; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 8 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0200)
+              { itype = FRVBF_INSN_MAVEH; goto extract_sfmt_mand; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 9 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0240)
+              { itype = FRVBF_INSN_MSLLHI; goto extract_sfmt_msllhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 10 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0280)
+              { itype = FRVBF_INSN_MSRLHI; goto extract_sfmt_msllhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec02c0)
+              { itype = FRVBF_INSN_MSRAHI; goto extract_sfmt_msllhi; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 12 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0300)
+              { itype = FRVBF_INSN_MSATHS; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 13 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0340)
+              { itype = FRVBF_INSN_MSATHU; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 14 :
+            if ((entire_insn & 0x79fc0fc0) == 0x1ec0380)
+              { itype = FRVBF_INSN_MCMPSH; goto extract_sfmt_mcmpsh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 15 :
+            if ((entire_insn & 0x79fc0fc0) == 0x1ec03c0)
+              { itype = FRVBF_INSN_MCMPUH; goto extract_sfmt_mcmpsh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 16 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0400)
+              { itype = FRVBF_INSN_MADDHSS; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 17 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0440)
+              { itype = FRVBF_INSN_MADDHUS; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 18 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0480)
+              { itype = FRVBF_INSN_MSUBHSS; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 19 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec04c0)
+              { itype = FRVBF_INSN_MSUBHUS; goto extract_sfmt_msaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 20 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0500)
+              { itype = FRVBF_INSN_MMULHS; goto extract_sfmt_mmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 21 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0540)
+              { itype = FRVBF_INSN_MMULHU; goto extract_sfmt_mmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 22 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0580)
+              { itype = FRVBF_INSN_MMACHS; goto extract_sfmt_mmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 23 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec05c0)
+              { itype = FRVBF_INSN_MMACHU; goto extract_sfmt_mmachu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 24 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0600)
+              { itype = FRVBF_INSN_MQADDHSS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 25 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0640)
+              { itype = FRVBF_INSN_MQADDHUS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 26 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0680)
+              { itype = FRVBF_INSN_MQSUBHSS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 27 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec06c0)
+              { itype = FRVBF_INSN_MQSUBHUS; goto extract_sfmt_mqsaths; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 28 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0700)
+              { itype = FRVBF_INSN_MQMULHS; goto extract_sfmt_mqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 29 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0740)
+              { itype = FRVBF_INSN_MQMULHU; goto extract_sfmt_mqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 30 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0780)
+              { itype = FRVBF_INSN_MQMACHS; goto extract_sfmt_mqmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 31 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec07c0)
+              { itype = FRVBF_INSN_MQMACHU; goto extract_sfmt_mqmachu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 32 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0800)
+              { itype = FRVBF_INSN_MCPXRS; goto extract_sfmt_mcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 33 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0840)
+              { itype = FRVBF_INSN_MCPXRU; goto extract_sfmt_mcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 34 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0880)
+              { itype = FRVBF_INSN_MCPXIS; goto extract_sfmt_mcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 35 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec08c0)
+              { itype = FRVBF_INSN_MCPXIU; goto extract_sfmt_mcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 36 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0900)
+              { itype = FRVBF_INSN_MQCPXRS; goto extract_sfmt_mqcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 37 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0940)
+              { itype = FRVBF_INSN_MQCPXRU; goto extract_sfmt_mqcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 38 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0980)
+              { itype = FRVBF_INSN_MQCPXIS; goto extract_sfmt_mqcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 39 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec09c0)
+              { itype = FRVBF_INSN_MQCPXIU; goto extract_sfmt_mqcpxrs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 40 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0a00)
+              { itype = FRVBF_INSN_MMULXHS; goto extract_sfmt_mmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 41 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0a40)
+              { itype = FRVBF_INSN_MMULXHU; goto extract_sfmt_mmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 42 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0a80)
+              { itype = FRVBF_INSN_MQMULXHS; goto extract_sfmt_mqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 43 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0ac0)
+              { itype = FRVBF_INSN_MQMULXHU; goto extract_sfmt_mqmulhs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 44 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0b00)
+              { itype = FRVBF_INSN_MCUT; goto extract_sfmt_mcut; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 45 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0b40)
+              { itype = FRVBF_INSN_MCUTSS; goto extract_sfmt_mcut; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 46 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0b80)
+              { itype = FRVBF_INSN_MCUTI; goto extract_sfmt_mcuti; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 47 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0bc0)
+              { itype = FRVBF_INSN_MCUTSSI; goto extract_sfmt_mcuti; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 48 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0c00)
+              { itype = FRVBF_INSN_MMRDHS; goto extract_sfmt_mmachs; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 49 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0c40)
+              { itype = FRVBF_INSN_MMRDHU; goto extract_sfmt_mmachu; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 50 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0c80)
+              { itype = FRVBF_INSN_MEXPDHW; goto extract_sfmt_mexpdhw; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 51 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0cc0)
+              { itype = FRVBF_INSN_MEXPDHD; goto extract_sfmt_mexpdhd; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 52 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0d00)
+              { itype = FRVBF_INSN_MPACKH; goto extract_sfmt_mpackh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 53 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0d40)
+              { itype = FRVBF_INSN_MUNPACKH; goto extract_sfmt_munpackh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 54 :
+            if ((entire_insn & 0x1fc0fc0) == 0x1ec0d80)
+              { itype = FRVBF_INSN_MDPACKH; goto extract_sfmt_mdpackh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 55 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0dc0)
+              { itype = FRVBF_INSN_MDUNPACKH; goto extract_sfmt_mdunpackh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 56 :
+            if ((entire_insn & 0x1ffffc0) == 0x1ec0e00)
+              { itype = FRVBF_INSN_MBTOH; goto extract_sfmt_mbtoh; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 57 :
+            if ((entire_insn & 0x1ffffc0) == 0x1ec0e40)
+              { itype = FRVBF_INSN_MHTOB; goto extract_sfmt_mhtob; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 58 :
+            if ((entire_insn & 0x1ffffc0) == 0x1ec0e80)
+              { itype = FRVBF_INSN_MBTOHE; goto extract_sfmt_mbtohe; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 59 :
             {
               unsigned int val = (((insn >> 17) & (1 << 0)));
               switch (val)
               {
-              case 0 : itype = FRVBF_INSN_MCLRACC_0; goto extract_sfmt_mclracc_0;
+              case 0 :
+                if ((entire_insn & 0x1ffffff) == 0x1ec0ec0)
+                  { itype = FRVBF_INSN_MCLRACC_0; goto extract_sfmt_mclracc_0; }
+                itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               case 1 :
                 {
                   unsigned int val = (((insn >> 25) & (63 << 0)));
@@ -2231,25 +4430,55 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
                   case 59 : /* fall through */
                   case 60 : /* fall through */
                   case 61 : /* fall through */
-                  case 62 : itype = FRVBF_INSN_MCLRACC_1; goto extract_sfmt_mclracc_0;
-                  case 63 : itype = FRVBF_INSN_MNOP; goto extract_sfmt_rei;
+                  case 62 :
+                    if ((entire_insn & 0x1ffffff) == 0x1ee0ec0)
+                      { itype = FRVBF_INSN_MCLRACC_1; goto extract_sfmt_mclracc_0; }
+                    itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+                  case 63 :
+                    if ((entire_insn & 0x7fffffff) == 0x7fee0ec0)
+                      { itype = FRVBF_INSN_MNOP; goto extract_sfmt_rei; }
+                    itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
                   default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
                   }
                 }
               default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
               }
             }
-          case 60 : itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc;
-          case 61 : itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc;
-          case 62 : itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg;
-          case 63 : itype = FRVBF_INSN_MWTACCG; goto extract_sfmt_mwtaccg;
+          case 60 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0f00)
+              { itype = FRVBF_INSN_MRDACC; goto extract_sfmt_mrdacc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 61 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0f40)
+              { itype = FRVBF_INSN_MWTACC; goto extract_sfmt_mwtacc; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 62 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0f80)
+              { itype = FRVBF_INSN_MRDACCG; goto extract_sfmt_mrdaccg; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 63 :
+            if ((entire_insn & 0x1fc0fff) == 0x1ec0fc0)
+              { itype = FRVBF_INSN_MWTACCG; goto extract_sfmt_mwtaccg; }
+            itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 124 : itype = FRVBF_INSN_MCOP1; goto extract_sfmt_rei;
-      case 125 : itype = FRVBF_INSN_MCOP2; goto extract_sfmt_rei;
-      case 126 : itype = FRVBF_INSN_COP1; goto extract_sfmt_rei;
-      case 127 : itype = FRVBF_INSN_COP2; goto extract_sfmt_rei;
+      case 124 :
+        if ((entire_insn & 0x1fc0fc0) == 0x1f00000)
+          { itype = FRVBF_INSN_MCOP1; goto extract_sfmt_rei; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 125 :
+        if ((entire_insn & 0x1fc0fc0) == 0x1f40000)
+          { itype = FRVBF_INSN_MCOP2; goto extract_sfmt_rei; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 126 :
+        if ((entire_insn & 0x1fc0000) == 0x1f80000)
+          { itype = FRVBF_INSN_COP1; goto extract_sfmt_rei; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 127 :
+        if ((entire_insn & 0x1fc0000) == 0x1fc0000)
+          { itype = FRVBF_INSN_COP2; goto extract_sfmt_rei; }
+        itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
       }
     }
diff --git a/sim/frv/decode.h b/sim/frv/decode.h
index cb1e80d639b..4e04787e010 100644
--- a/sim/frv/decode.h
+++ b/sim/frv/decode.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
index ce5d492766d..8184485dc62 100644
--- a/sim/frv/frv-sim.h
+++ b/sim/frv/frv-sim.h
@@ -143,7 +143,7 @@ struct _device { int foo; };
 
 /* maintain the address of the start of the previous VLIW insn sequence.  */
 extern IADDR previous_vliw_pc;
-extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
+extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
 
 /* Hardware status.  */
 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in
index 24c34c9c651..88fed04eb09 100644
--- a/sim/frv/mloop.in
+++ b/sim/frv/mloop.in
@@ -456,7 +456,7 @@ cat <<EOF
   int first_insn_p = 1;
   int last_insn_p = 0;
   int ninsns;
-  CGEN_ATTR_VALUE_TYPE slot;
+  CGEN_ATTR_VALUE_ENUM_TYPE slot;
 
   /* If the timer is enabled, then enable model profiling.  This is because
      the timer needs accurate cycles counts to work properly.  */
diff --git a/sim/frv/model.c b/sim/frv/model.c
index 86f8020d740..5ef4765e708 100644
--- a/sim/frv/model.c
+++ b/sim/frv/model.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
diff --git a/sim/frv/pipeline.c b/sim/frv/pipeline.c
index 291a5dcce88..780e12745d9 100644
--- a/sim/frv/pipeline.c
+++ b/sim/frv/pipeline.c
@@ -61,7 +61,7 @@ frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
     {
       /* Clear the appropriate MSR fields depending on which slot
 	 this insn is in.  */
-      CGEN_ATTR_VALUE_TYPE preserve_ovf;
+      CGEN_ATTR_VALUE_ENUM_TYPE preserve_ovf;
       SI msr0 = GET_MSR (0);
 
       preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);
diff --git a/sim/frv/sem.c b/sim/frv/sem.c
index f609fdf7371..a7a764c8e6e 100644
--- a/sim/frv/sem.c
+++ b/sim/frv/sem.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2004 Free Software Foundation, Inc.
+Copyright 1996-2005 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -18,7 +18,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License along
 with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 */
 
@@ -3267,7 +3267,7 @@ SEM_FN_NAME (frvbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #undef FLD
 }
 
-/* ld: ld$pack @($GRi,$GRj),$GRk */
+/* ld: ld$pack $ldann($GRi,$GRj),$GRk */
 
 static SEM_PC
 SEM_FN_NAME (frvbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
@@ -3604,7 +3604,7 @@ if (tmp_do_op) {
 #undef FLD
 }
 
-/* ldd: ldd$pack @($GRi,$GRj),$GRdoublek */
+/* ldd: ldd$pack $lddann($GRi,$GRj),$GRdoublek */
 
 static SEM_PC
 SEM_FN_NAME (frvbf,ldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
@@ -11303,7 +11303,7 @@ frvbf_model_branch (current_cpu, pc, 2);
 #undef FLD
 }
 
-/* calll: calll$pack @($GRi,$GRj) */
+/* calll: calll$pack $callann($GRi,$GRj) */
 
 static SEM_PC
 SEM_FN_NAME (frvbf,calll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
@@ -16643,7 +16643,7 @@ SEM_FN_NAME (frvbf,fitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -16664,7 +16664,7 @@ SEM_FN_NAME (frvbf,fstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
@@ -16685,7 +16685,7 @@ SEM_FN_NAME (frvbf,fitod) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsidf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsidf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -16706,7 +16706,7 @@ SEM_FN_NAME (frvbf,fdtoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixdfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
@@ -16728,12 +16728,12 @@ SEM_FN_NAME (frvbf,fditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -16756,12 +16756,12 @@ SEM_FN_NAME (frvbf,fdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
   {
-    USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    USI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
@@ -16785,13 +16785,13 @@ SEM_FN_NAME (frvbf,nfditos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -16815,13 +16815,13 @@ SEM_FN_NAME (frvbf,nfdstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    USI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    USI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
@@ -16844,7 +16844,7 @@ SEM_FN_NAME (frvbf,cfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -16869,7 +16869,7 @@ SEM_FN_NAME (frvbf,cfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
@@ -16895,7 +16895,7 @@ SEM_FN_NAME (frvbf,nfitos) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->floatsisf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), GET_H_FR_INT (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -16919,7 +16919,7 @@ SEM_FN_NAME (frvbf,nfstoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SI opval = (* CGEN_CPU_FPU (current_cpu)->ops->fixsfsi) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SI opval = CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
   }
@@ -17036,7 +17036,7 @@ SEM_FN_NAME (frvbf,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->negsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17057,7 +17057,7 @@ SEM_FN_NAME (frvbf,fnegd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->negdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17079,12 +17079,12 @@ SEM_FN_NAME (frvbf,fdnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->negsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->negsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17107,7 +17107,7 @@ SEM_FN_NAME (frvbf,cfnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->negsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->negsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17131,7 +17131,7 @@ SEM_FN_NAME (frvbf,fabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->abssf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17152,7 +17152,7 @@ SEM_FN_NAME (frvbf,fabsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->absdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->absdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17174,12 +17174,12 @@ SEM_FN_NAME (frvbf,fdabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->abssf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->abssf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17202,7 +17202,7 @@ SEM_FN_NAME (frvbf,cfabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->abssf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->abssf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17226,7 +17226,7 @@ SEM_FN_NAME (frvbf,fsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17248,12 +17248,12 @@ SEM_FN_NAME (frvbf,fdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17277,13 +17277,13 @@ SEM_FN_NAME (frvbf,nfdsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17305,7 +17305,7 @@ SEM_FN_NAME (frvbf,fsqrtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17327,7 +17327,7 @@ SEM_FN_NAME (frvbf,cfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17353,7 +17353,7 @@ SEM_FN_NAME (frvbf,nfsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->sqrtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->sqrtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17375,7 +17375,7 @@ SEM_FN_NAME (frvbf,fadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17396,7 +17396,7 @@ SEM_FN_NAME (frvbf,fsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17417,7 +17417,7 @@ SEM_FN_NAME (frvbf,fmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17438,7 +17438,7 @@ SEM_FN_NAME (frvbf,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17459,7 +17459,7 @@ SEM_FN_NAME (frvbf,faddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17480,7 +17480,7 @@ SEM_FN_NAME (frvbf,fsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17501,7 +17501,7 @@ SEM_FN_NAME (frvbf,fmuld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17522,7 +17522,7 @@ SEM_FN_NAME (frvbf,fdivd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -17544,7 +17544,7 @@ SEM_FN_NAME (frvbf,cfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 4);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17569,7 +17569,7 @@ SEM_FN_NAME (frvbf,cfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 4);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17594,7 +17594,7 @@ SEM_FN_NAME (frvbf,cfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 4);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17619,7 +17619,7 @@ SEM_FN_NAME (frvbf,cfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 4);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -17645,7 +17645,7 @@ SEM_FN_NAME (frvbf,nfadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17669,7 +17669,7 @@ SEM_FN_NAME (frvbf,nfsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17693,7 +17693,7 @@ SEM_FN_NAME (frvbf,nfmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17717,7 +17717,7 @@ SEM_FN_NAME (frvbf,nfdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17738,7 +17738,7 @@ SEM_FN_NAME (frvbf,fcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17746,7 +17746,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17754,7 +17754,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17788,7 +17788,7 @@ SEM_FN_NAME (frvbf,fcmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17796,7 +17796,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtdf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17804,7 +17804,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqdf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj)))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17839,7 +17839,7 @@ SEM_FN_NAME (frvbf,cfcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17847,7 +17847,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17855,7 +17855,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17891,7 +17891,7 @@ SEM_FN_NAME (frvbf,fdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
 {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17899,7 +17899,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17907,7 +17907,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -17924,7 +17924,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H
 }
 }
 }
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
@@ -17932,7 +17932,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
@@ -17940,7 +17940,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
@@ -17976,7 +17976,7 @@ SEM_FN_NAME (frvbf,fmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -17997,7 +17997,7 @@ SEM_FN_NAME (frvbf,fmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18018,7 +18018,7 @@ SEM_FN_NAME (frvbf,fmaddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -18039,7 +18039,7 @@ SEM_FN_NAME (frvbf,fmsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
   {
-    DF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
+    DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FR_DOUBLE (FLD (f_FRi)), GET_H_FR_DOUBLE (FLD (f_FRj))), GET_H_FR_DOUBLE (FLD (f_FRk)));
     sim_queue_fn_df_write (current_cpu, frvbf_h_fr_double_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr_double", 'f', opval);
   }
@@ -18061,12 +18061,12 @@ SEM_FN_NAME (frvbf,fdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18090,13 +18090,13 @@ SEM_FN_NAME (frvbf,nfdmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1)))), GET_H_FR (((FLD (f_FRk)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18119,7 +18119,7 @@ SEM_FN_NAME (frvbf,cfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 5);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -18144,7 +18144,7 @@ SEM_FN_NAME (frvbf,cfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 5);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -18170,7 +18170,7 @@ SEM_FN_NAME (frvbf,nfmadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18194,7 +18194,7 @@ SEM_FN_NAME (frvbf,nfmsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj))), GET_H_FR (FLD (f_FRk)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18217,12 +18217,12 @@ SEM_FN_NAME (frvbf,fmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18245,12 +18245,12 @@ SEM_FN_NAME (frvbf,fmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18273,22 +18273,22 @@ SEM_FN_NAME (frvbf,fdmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18311,22 +18311,22 @@ SEM_FN_NAME (frvbf,fdmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18353,22 +18353,22 @@ frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2));
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18395,22 +18395,22 @@ frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 2));
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 3));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (2))), GET_H_FR (((FLD (f_FRj)) + (2))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (2)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (3))), GET_H_FR (((FLD (f_FRj)) + (3))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (3)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18434,13 +18434,13 @@ SEM_FN_NAME (frvbf,cfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 9);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     written |= (1 << 10);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -18467,13 +18467,13 @@ SEM_FN_NAME (frvbf,cfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     written |= (1 << 9);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     written |= (1 << 10);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
@@ -18499,12 +18499,12 @@ SEM_FN_NAME (frvbf,fmad) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->adddf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18527,12 +18527,12 @@ SEM_FN_NAME (frvbf,fmsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->muldf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi))), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRj)))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->subdf) (CGEN_CPU_FPU (current_cpu), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), (* CGEN_CPU_FPU (current_cpu)->ops->fextsfdf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1)))), CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRj)) + (1))))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18556,13 +18556,13 @@ SEM_FN_NAME (frvbf,nfmas) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18586,13 +18586,13 @@ SEM_FN_NAME (frvbf,nfmss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18615,12 +18615,12 @@ SEM_FN_NAME (frvbf,fdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18643,12 +18643,12 @@ SEM_FN_NAME (frvbf,fdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18671,12 +18671,12 @@ SEM_FN_NAME (frvbf,fdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18699,12 +18699,12 @@ SEM_FN_NAME (frvbf,fddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18727,12 +18727,12 @@ SEM_FN_NAME (frvbf,fdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18755,12 +18755,12 @@ SEM_FN_NAME (frvbf,fdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18784,13 +18784,13 @@ SEM_FN_NAME (frvbf,nfdmulcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18814,13 +18814,13 @@ SEM_FN_NAME (frvbf,nfdadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18844,13 +18844,13 @@ SEM_FN_NAME (frvbf,nfdsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18874,13 +18874,13 @@ SEM_FN_NAME (frvbf,nfdmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->mulsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18904,13 +18904,13 @@ SEM_FN_NAME (frvbf,nfddivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->divsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18934,13 +18934,13 @@ SEM_FN_NAME (frvbf,nfdsads) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->addsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, FLD (f_FRk), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
   {
-    SF opval = (* CGEN_CPU_FPU (current_cpu)->ops->subsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
+    SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))));
     sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, ((FLD (f_FRk)) + (1)), opval);
     TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
   }
@@ -18963,7 +18963,7 @@ SEM_FN_NAME (frvbf,nfdcmps) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 {
 frvbf_set_ne_index (current_cpu, FLD (f_FRk));
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -18971,7 +18971,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -18979,7 +18979,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (FLD (f_FRi)), GET_H_FR (FLD (f_FRj)))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[FLD (f_FCCi_2)]), opval);
@@ -18997,7 +18997,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H
 }
 }
 frvbf_set_ne_index (current_cpu, ADDSI (FLD (f_FRk), 1));
-if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 2;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
@@ -19005,7 +19005,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->gtsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 8;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
@@ -19013,7 +19013,7 @@ if ((* CGEN_CPU_FPU (current_cpu)->ops->eqsf) (CGEN_CPU_FPU (current_cpu), GET_H
     TRACE_RESULT (current_cpu, abuf, "fccr", 'x', opval);
   }
 } else {
-if ((* CGEN_CPU_FPU (current_cpu)->ops->ltsf) (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
+if (CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FR (((FLD (f_FRi)) + (1))), GET_H_FR (((FLD (f_FRj)) + (1))))) {
   {
     UQI opval = 4;
     sim_queue_qi_write (current_cpu, & CPU (h_fccr[((FLD (f_FCCi_2)) + (1))]), opval);
diff --git a/sim/frv/traps.c b/sim/frv/traps.c
index 3e9344696fe..63d4c9b9389 100644
--- a/sim/frv/traps.c
+++ b/sim/frv/traps.c
@@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "bfd.h"
 #include "libiberty.h"
 
-CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
+CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
 
 /* The semantic code invokes this for invalid (unrecognized) instructions.  */
 
diff --git a/sim/sh64/ChangeLog b/sim/sh64/ChangeLog
deleted file mode 100644
index 1f705ca9e70..00000000000
--- a/sim/sh64/ChangeLog
+++ /dev/null
@@ -1,392 +0,0 @@
-2005-05-02  Corinna Vinschen  <vinschen@redhat.com>
-
-	* sh-desc.h: Move extern declaration of sh_cgen_ifld_table after
-	inclusion of cgen.h.
-
-2005-04-15  Corinna Vinschen  <vinschen@redhat.com>
-
-	* configure.ac: New file.
-	* configure.in: Remove.
-	* configure: Regenerate.
-	* defs-media.h (sem_fields): Add missing sfmt_ldhil member.
-	* sim-if.c (sim_open): Use struct bfd instead of struct _bfd.
-	(sim_create_inferior): Ditto.
-
-2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
-
-	* configure: Regenerate for ../common/aclocal.m4 update.
-
-Fri Feb 21 19:49:45 2003  J"orn Rennecke <joern.rennecke@superh.com>
-
-	* sem-media-switch.c, sem-media.c: Regenerate.
-
-2002-06-24  Richard Sandiford  <rsandifo@redhat.com>
-
-        * sh64.c: Update path of "callback.h".
-
-2002-06-20  Elena Zannoni  <ezannoni@redhat.com>
-
-        * sh64.c: Include correct file for register numbers.
-
-Fri May 17 14:27:41 2002  J"orn Rennecke <joern.rennecke@superh.com>
-
-	* sim-if.c (sh64_disassemble_insn): Use  print_insn_sh instead of
-	print_insn_shl.
-
-2001-07-05  Ben Elliston  <bje@redhat.com>
-
-	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
-	(stamp-desc): Likewise.
-	(stamp-cpu): Likewise.
-	(stamp-defs-compact): Likewise.
-	(stamp-defs-media): Likewise.
-	(stamp-decode-compact): Likewise.
-	(stamp-decode-media): Likewise.
-
-2001-03-30  Ben Elliston  <bje@redhat.com>
-
-	* sim-if.c (sim_open): Set sh64_idesc_{media,compact} to NULL.
-	* sh64-sim.h (sh64_idesc_{compact,media}): Declare extern.
-	* sh64.c (sh64_idesc_{compact,media}): Make non-static.
-
-2001-01-30  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (SYS_argc, SYS_argn, SYS_argnlen): Define.
-	(trap_handler): Implement these syscalls.
-	(count_argc): New function.
-
-2001-01-24  Alexandre Oliva  <aoliva@redhat.com>
-
-	* sh64.c (trap_handler): Implement time.
-
-	* sh64.c (fetch_str): New function.
-	(trap_handler): Re-implement write, and implement lseek, read,
-	open and close.
-
-2001-01-18  Elena Zannoni  <ezannoni@kwikemart.cygnus.com>
-
-	* sh64.c (sh64_fetch_register): When fetching the PC, return the
- 	PC value and set the LSB according to the current ISA.
-
-2001-01-18  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (trap_handler): Use sim_engine_halt to indicate a program
-	has terminated, not exit!
-
-2001-01-12  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_fcnvds): Re-implement.
-
-	* sh64.c: Include "bfd.h".
-	(trap_handler): New function. Consolidate function bodies of
-	sh64_trapa and sh64_compact_trapa.
-	(sh64_trapa): Use it.
-	(sh64_compact_trapa): Likewise.
-
-2001-01-11  Ben Elliston  <bje@redhat.com>
-
-	* sem-media.c, sem-media-switch.c: Regenerate.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-
-	* sh64.c (sh64_trapa): Adhere to SH64 sys call conventions.
-
-	* cpu.h, sh-desc.c, sh-desc.h, sh-opc.h: Regenerate.
-	* decode-media.c, decode-media.h, defs-media.h: Likewise.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2001-01-10  Ben Elliston  <bje@redhat.com>
-
-	* sim-main.h (CIA_SET): Encode the current instruction set mode
-	when setting the cia.
-
-2001-01-08  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_store_register): Do not set insn set mode--allow
-	sh64_h_pc_set() to do it.
-	(shmedia_init_cpu): Do not initialise the insn set mode--let the
-	loader set it based on bit 0 of the executable's starting address.
-	(shcompact_init_cpu): Likewise.
-	* mloop-compact.c (sh64_compact_pbb_begin): Emit a warning message
-	about malformed programs which have illegal insns in delay slots.
-	(sh64_compact_pbb_cti_chain): Examine the least significant bit of
-	the new pc, not the current instruction set mode to determine if
-	the next pbb in the chain will consist of SHmedia instructions.
-	* mloop-media.c (sh64_media_pbb_cti_chain): Likewise for SHcompact
-	switches. Set bit 0 when setting the pc for the next SHmedia pbb.
-
-	* cpu.c, cpu.h: Regenerate.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-	* sh64.c (sh64_compact_trapa): Use sim_io_write_{stdout,error}(),
-	not stdio functions to emit output when executing write traps.
-
-2001-01-07  Alexandre Oliva  <aoliva@redhat.com>
-
-	* sh64.c (sh64_compact_trapa): Support writing to stderr.  Flush
-	output stream after each (compound) write.
-
-2001-01-06  Ben Elliston  <bje@redhat.com>
-
-	* sem-media.c, sem-media-switch.c: Regenerate.
-
-2001-01-04  Ben Elliston  <bje@redhat.com>
-
-	* sem-compact.c, sem-compact-switch.c: Regenerate.
-	* cpu.h: Regenerate.
-
-2001-01-03  Ben Elliston  <bje@redhat.com>
-
-	* cpu.c, cpu.h: Regenerate.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2001-01-02  Ben Elliston  <bje@redhat.com>
-
-	* sim-if.c (sh64_disassemble_insn): Set arch and mach fields using
-	BFD primitives.
-
-	* sem-compact.c, sem-compact-switch.c: Regenerate.
-
-2000-12-30  Alexandre Oliva  <aoliva@redhat.com>
-
-	* sh64.c (sh64_nsb): Re-implement correctly.
-
-2000-12-26  Alexandre Oliva  <aoliva@redhat.com>
-
-	* sh64.c (sh64_nsb): Re-implement.
-
-2000-12-27  Ben Elliston  <bje@redhat.com>
-
-	* cpu.c, cpu.h: Regenerate.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-	* sh-desc.c: Likewise.
-
-2000-12-26  Ben Elliston  <bje@redhat.com>
-
-	* mloop-compact.in, mloop-media.in: Remove.
-	* mloop-compact.c, mloop-media.c: New files.
-	* eng-compact.c, eng-media.c: Likewise.
-	* Makefile.in (mloop-compact.c): Remove target.
-	(stamp-mloop-compact): Likewise.
-	(mloop-media.c): Likewise.
-	(stamp-mloop-media): Likewise.
-	(sh64-clean): Update.
-	(stamp-mloop): Remove.
-
-2000-12-23  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_prepare_run): Rename from shmedia_prepare_run.
-	(shcompact_prepare_run): Remove.
-	(sh2_mach, sh3_mach, sh3e_mach, sh4_mach, sh5_mach): Update.
-
-2000-12-22  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_idesc_media, sh64_idesc_compact): New variables.
-	(sh64_dump): Remove.
-	(sh64_engine_run_full): Only compute idesc tables once.
-	(sh64_engine_run_fast): Likewise.
-	(shmedia_prepare_run): Do nothing.
-	(shcompact_prepare_run): Likewise.
-
-	* sem-compact.c, sem-compact-switch.c: Regenerate.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2000-12-19  Ben Elliston  <bje@redhat.com>
-
-	* sem-media.c, sem-media-switch.c: Regenerate.
-
-2000-12-15  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_store_register): When storing a new PC, set ISA
-	mode based on the value of bit 0.
-
-	* sh64.c: Include "sim-sh64.h" for GDB interfacing.
-	(sh64_fetch_register): Implement.
-	(sh64_store_register): Likewise.
-
-	* sh64-sim.h (sh64_fmacs): Declare.
-	(sh64_ftrcdl, sh64_ftrcdq, sh64_ftrcsl): Likewise.
-
-	* sem-media.c, sem-media-switch.c: Regenerate.
-
-2000-12-13  Ben Elliston  <bje@redhat.com>
-
-	* sh64-sim.h (sh64_compact_trapa): Renamed from sh64_trapa.
-	(sh64_trapa): Renamed from sh64_trap.
-	* sh64.c (sh64_trapa): Call sh64_compact_trapa for handling.
-	Apply renaming described above.
-
-	* decode-media.c, decode-media.h, defs-media.h: Regenerate.
-	* sem-media.c sem-media-switch.c: Likewise.
-	* sh-desc.c, sh-desc.h, sh-opc.h: Likewise.
-
-2000-12-12  Ben Elliston  <bje@redhat.com>
-
-	* cpu.c, cpu.h, sh-desc.c: Regenerate.
-	* sem-media.c, sem-media-switch.c: Likewise.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-	* sh64-sim.h (sh64_ftrvs): Declare.
-	* sh64.c (sh64_ftrvs): Bug fixes.
-
-	* sh64.c (sh64_fcmpgtd): Fix order of arguments to sim_fpu_is_gt.
-	(sh64_fcmpgts): Likewise.
-
-2000-12-11  Ben Elliston  <bje@redhat.com>
-
-	* decode-media.c, decode-media.h: Regenerate.
-	* defs-media.h: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-	* sh-desc.c: Likewise.
-
-2000-12-08  Ben Elliston  <bje@redhat.com>
-
-	* decode-media.c, decode-media.h: Regenerate.
-	* defs-media.h: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2000-12-07  Ben Elliston  <bje@redhat.com>
-
-	* decode-media.c, decode-media.h: Regenerate.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-	* defs-media.h: Regenete.
-	* decode-compact.c, decode-media.c: Likewise.
-
-2000-12-06  Ben Elliston  <bje@redhat.com>
-
-	* sh64.c (sh64_fcmpund): Return a BI.
-	(sh64_fcmpuns): Likewise.
-	(sh64_nsb): Treat source value as unsigned.
-	(sh64_compact_model_insn_before): New function.
-	(sh64_media_model_insn_before): Likewise.
-	(sh64_compact_model_insn_after): Likewise.
-	(sh64_media_model_insn_after): Likewise.
-	(sh_models): Use sh5_mach for "sh5".
-	* sh64-sim.h: Add missing function prototypes.
-
-	* cpu.c, cpu.h, defs-media.h, sh-desc.c: Regenerate.
-	* decode-media.c, decode-media.h: Likewise.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2000-12-05  Ben Elliston  <bje@redhat.com>
-
-	* mloop-compact.in, mloop-media.in: Use @prefix@.
-	* Makefile.in (stamp-mloop-compact): Pass -outfile-suffix option
-	to make generated files safe in the presence of parallel makes.
-	(stamp-mloop-media): Likewise.
-
-	* decode-media.c, defs-media.h: Regenerate.
-
-2000-12-04  Ben Elliston  <bje@redhat.com>
-
-	* sh64-sim.h: Add function prototypes from sh64.c.
-
-	* Makefile.in (SH64_OBJS): Add ISA variant objects.
-	(SIM_EXTRA_DEPS): Do not depend on opcodes headers.
-	(SH64_INCLUDE_DEPS): Update for ISA variants.
-	(stamp-mloop-compact, stamp-mloop-media): New targets.
-	(decode-compact.o, sem-compact.o): New rules.
-	(decode-media.o, sem-media.o): Likewise.
-	(sh64-clean): Update.
-	(stamp-all, stamp-mloop, stamp-decode, stamp-defs): New targets.
-	(stamp-desc, stamp-cpu): Likewise.
-	(stamp-defs-compact, stamp-defs-media): Likewise.
-	(stamp-decode-compact, stamp-decode-media): Likewise.	
-
-	* defs-compact.h, defs-media.h: Regenerate.
-
-2000-12-03  Ben Elliston  <bje@redhat.com>
-
-	* sh64-sim.h (sh64_fcmpeqd, sh64_fcmpeqs): Declare.
-	(sh64_fcmpged, sh64_fcmpges): Likewise.
-	(sh64_fcmpgtd, sh64_fcmpgts): Likewise.
-
-	* sh64.c (sh64_endian): New function.
-	(sh64_fcmpeqd, sh64_fcmpeqs): Return a BI.
-	(sh64_fcmpged, sh64_fcmpges): Likewise.
-	(sh64_fcmpgtd, sh64_fcmpgts): Likewise.
-	(sh64_trap): Implement a basic syscall facility.
-	(sh64_trapa): Exit with return code in R5, not 0.
-	(sh64_model_sh5_u_exec): Remove.
-	(sh64_engine_run_full): New function.
-	(sh64_engine_run_fast): Likewise.
-	(shmedia_prepare_run): Likewise.
-	(shcompact_prepare_run): Likewise.
-	(sh64_get_idata): Likewise.
-	(sh64_init_cpu): Likewise.
-	(shmedia_init_cpu): Likewise.
-	(shcompact_init_cpu): Likewise.
-	(sh64_model_init): Likewise.
-	(sh_models): Define.
-	(sh5_imp_properties): Likewise.
-	(sh2_mach, sh3_mach, sh4_mach, sh5_mach): Define.
-
-	* sem-compact.c, sem-compact-switch.c: Regenerate.
-
-2000-12-01  Ben Elliston  <bje@redhat.com>
-
-	* sh64-sim.h (sh64_endian): Declare.
-	* sim-main.h (sim_cia): Use UDI, not USI.
-	(WITH_PROFILE_MODEL_P): Remove.
-	* sim-if.c (sim_sh64_disassemble_insn): Remove.
-	(sh64_disassemble_insn): New function.
-	(sim_open): Use as this CPU's disassembler.
-	* eng.h: New file.
-	* decode.h (WITH_PROFILE_MODEL_P): Undefine.
-
-	* decode-compact.c, decode-media.c: Regenerate.
-	* defs-compact.h, defs-media.h: Likewise.
-	* sem-compact.c, sem-compact-switch.c: Likewise.
-	* sh-desc.c, sh-desc.h: Likewise.
-	* cpu.c, cpu.h, cpuall.h: Likewise.
-
-2000-11-30  Ben Elliston  <bje@redhat.com>
-
-	* arch.c, sh-desc.c, sh-desc.h: Regenerate.
-
-	* tconfig.in (SIM_HAVE_BIENDIAN): Define.
-	* configure.in (SIM_AC_OPTION_BIGENDIAN): Do not hard-wire a
-	target byte order, but default to big endian.
-	* configure: Regenerate.
-
-2000-11-27  Ben Elliston  <bje@redhat.com>
-
-	* sim-main.h (WITH_PROFILE_MODEL_P): Define.
-	* sh64-sim.h (ISM_COMPACT, ISM_MEDIA): New enums.
-
-	* sh-desc.c, sh-desc.h: Regenerate.
-	* arch.c, cpu.h, cpuall.h: Regenerate.
-	* decode.h (WITH_PROFILE_MODEL_P): Remove.
-
-	* mloop-compact.in, mloop-media.in: New files.
-	* decode.h: Likewise.
-
-2000-11-26  Ben Elliston  <bje@redhat.com>
-
-	* sem-compact.c, sem-compact-switch.c: Generate.
-	* sem-media.c, sem-media-switch.c: Likewise.
-
-2000-11-25  Ben Elliston  <bje@redhat.com>
-
-	* sh-desc.c, sh-desc.h, sh-opc.h: Generate.
-
-	* arch.c, arch.h, cpuall.h, cpu.c, cpu.h: Generate.
-	* decode-compact.c, decode-compact.h: Likewise.
-	* decode-media.c, decode-media.h: Likewise.
-	* sh64-sim.h: New file.
-	* sim-main.h: Likewise.
-
-2000-11-22  Ben Elliston  <bje@redhat.com>
-
-	* sim-if.c: New file.
-	* sh64.c: Likewise.
-
-2000-11-16  Ben Elliston  <bje@redhat.com>
-
-	* config.in: New file.
-	* tconfig.in: Likewise.
-	* configure.in: Likewise.
-	* configure: Generate.
-	* Makefile.in: New file.
diff --git a/sim/sh64/Makefile.in b/sim/sh64/Makefile.in
deleted file mode 100644
index b8cfb82c585..00000000000
--- a/sim/sh64/Makefile.in
+++ /dev/null
@@ -1,153 +0,0 @@
-# Makefile template for Configure for the SH64 simulator
-# Copyright (C) 2000 Free Software Foundation, Inc.
-# Contributed by Red Hat, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-## COMMON_PRE_CONFIG_FRAG
-
-SH64_OBJS = sh64.o cpu.o sh-desc.o \
-	decode-compact.o sem-compact.o mloop-compact.o \
-	decode-media.o sem-media.o mloop-media.o
-
-CONFIG_DEVICES = dv-sockser.o
-CONFIG_DEVICES =
-
-SIM_OBJS = \
-	$(SIM_NEW_COMMON_OBJS) \
-	sim-cpu.o \
-	sim-hload.o \
-	sim-hrw.o \
-	sim-model.o \
-	sim-reg.o \
-	cgen-utils.o cgen-trace.o cgen-scache.o \
-	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
-	sim-if.o arch.o \
-	$(SH64_OBJS) \
-	$(CONFIG_DEVICES)
-
-# Extra headers included by sim-main.h.
-SIM_EXTRA_DEPS = \
-	$(CGEN_INCLUDE_DEPS) \
-	arch.h cpuall.h sh64-sim.h
-
-SIM_EXTRA_CFLAGS =
-
-SIM_RUN_OBJS = nrun.o
-SIM_EXTRA_CLEAN = sh64-clean
-
-## COMMON_POST_CONFIG_FRAG
-
-arch = sh
-
-sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
-
-arch.o: arch.c $(SIM_MAIN_DEPS)
-
-devices.o: devices.c $(SIM_MAIN_DEPS)
-
-# SH64 objs
-
-SH64_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpu.h decode.h \
-	decode-compact.h eng-compact.h defs-compact.h \
-	decode-media.h eng-media.h defs-media.h
-
-sh64.o: sh64.c $(SH64_INCLUDE_DEPS)
-
-mloop-compact.o: mloop-compact.c sem-compact-switch.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/mloop-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
-
-mloop-media.o: mloop-media.c sem-media-switch.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/mloop-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
-
-cpu.o: cpu.c $(SH64_INCLUDE_DEPS)
-
-decode-compact.o: decode-compact.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/decode-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
-
-sem-compact.o: sem-compact.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/sem-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
-
-decode-media.o: decode-media.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/decode-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
-
-sem-media.o: sem-media.c $(SH64_INCLUDE_DEPS)
-	$(CC) -c $(srcdir)/sem-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
-
-sh64-clean:
-	rm -f tmp-*
-	rm -f stamp-defs-{compact,media}
-	rm -f stamp-arch stamp-desc stamp-cpu stamp-decode-{compact,media}
-
-# cgen support, enable with --enable-cgen-maint
-CGEN_MAINT = ; @true
-# The following line is commented in or out depending upon --enable-cgen-maint.
-@CGEN_MAINT@CGEN_MAINT =
-
-.PHONY: stamp-all stamp-decode stamp-defs
-
-stamp-all: stamp-arch stamp-desc stamp-cpu stamp-decode stamp-defs
-stamp-decode: stamp-decode-compact stamp-decode-media
-stamp-defs: stamp-defs-compact stamp-defs-media
-
-stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
-	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media \
-	  FLAGS="with-scache"
-	touch $@
-arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
-	@true
-
-stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
-	$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media
-	touch $@
-desc.h: $(CGEN_MAINT) stamp-desc
-	@true
-
-stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
-	$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
-	  cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache"
-	rm -f $(srcdir)/model.c
-	touch $@
-cpu.h: $(CGEN_MAINT) stamp-cpu
-	@true
-
-stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
-	$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
-	  cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact"
-	touch $@
-defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
-	@true
-
-stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
-	$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
-	  cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media"
-	touch $@
-defs-media.h: $(CGEN_MAINT) stamp-defs-media
-
-stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
-	$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
-	touch $@
-sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-compact
-	@true
-
-stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
-	$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
-	touch $@
-sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-media
-	@true
diff --git a/sim/sh64/arch.c b/sim/sh64/arch.c
deleted file mode 100644
index c1e8c772583..00000000000
--- a/sim/sh64/arch.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Simulator support for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#include "sim-main.h"
-#include "bfd.h"
-
-const MACH *sim_machs[] =
-{
-#ifdef HAVE_CPU_SH64
-  & sh2_mach,
-#endif
-#ifdef HAVE_CPU_SH64
-  & sh3_mach,
-#endif
-#ifdef HAVE_CPU_SH64
-  & sh3e_mach,
-#endif
-#ifdef HAVE_CPU_SH64
-  & sh4_mach,
-#endif
-#ifdef HAVE_CPU_SH64
-  & sh5_mach,
-#endif
-  0
-};
-
diff --git a/sim/sh64/arch.h b/sim/sh64/arch.h
deleted file mode 100644
index 30820a061a9..00000000000
--- a/sim/sh64/arch.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Simulator header for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH_ARCH_H
-#define SH_ARCH_H
-
-#define TARGET_BIG_ENDIAN 1
-
-/* Enum declaration for model types.  */
-typedef enum model_type {
-  MODEL_SH5, MODEL_MAX
-} MODEL_TYPE;
-
-#define MAX_MODELS ((int) MODEL_MAX)
-
-/* Enum declaration for unit types.  */
-typedef enum unit_type {
-  UNIT_NONE, UNIT_SH5_U_EXEC, UNIT_MAX
-} UNIT_TYPE;
-
-#define MAX_UNITS (1)
-
-#endif /* SH_ARCH_H */
diff --git a/sim/sh64/config.in b/sim/sh64/config.in
deleted file mode 100644
index 6ce594d7c90..00000000000
--- a/sim/sh64/config.in
+++ /dev/null
@@ -1,177 +0,0 @@
-/* config.in.  Generated automatically from configure.in by autoheader.  */
-
-/* Define if using alloca.c.  */
-#undef C_ALLOCA
-
-/* Define to empty if the keyword does not work.  */
-#undef const
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define if you have a working `mmap' system call.  */
-#undef HAVE_MMAP
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#undef inline
-
-/* Define to `long' if <sys/types.h> doesn't define.  */
-#undef off_t
-
-/* Define if you need to in order for stat and other things to work.  */
-#undef _POSIX_SOURCE
-
-/* Define as the return type of signal handlers (int or void).  */
-#undef RETSIGTYPE
-
-/* Define to `unsigned' if <sys/types.h> doesn't define.  */
-#undef size_t
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#undef STACK_DIRECTION
-
-/* Define if you have the ANSI C header files.  */
-#undef STDC_HEADERS
-
-/* Define if your processor stores words with the most significant
-   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
-#undef WORDS_BIGENDIAN
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
-
-/* Define if you have the __argz_count function.  */
-#undef HAVE___ARGZ_COUNT
-
-/* Define if you have the __argz_next function.  */
-#undef HAVE___ARGZ_NEXT
-
-/* Define if you have the __argz_stringify function.  */
-#undef HAVE___ARGZ_STRINGIFY
-
-/* Define if you have the __setfpucw function.  */
-#undef HAVE___SETFPUCW
-
-/* Define if you have the dcgettext function.  */
-#undef HAVE_DCGETTEXT
-
-/* Define if you have the getcwd function.  */
-#undef HAVE_GETCWD
-
-/* Define if you have the getpagesize function.  */
-#undef HAVE_GETPAGESIZE
-
-/* Define if you have the getrusage function.  */
-#undef HAVE_GETRUSAGE
-
-/* Define if you have the munmap function.  */
-#undef HAVE_MUNMAP
-
-/* Define if you have the putenv function.  */
-#undef HAVE_PUTENV
-
-/* Define if you have the setenv function.  */
-#undef HAVE_SETENV
-
-/* Define if you have the setlocale function.  */
-#undef HAVE_SETLOCALE
-
-/* Define if you have the sigaction function.  */
-#undef HAVE_SIGACTION
-
-/* Define if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if you have the strcasecmp function.  */
-#undef HAVE_STRCASECMP
-
-/* Define if you have the strchr function.  */
-#undef HAVE_STRCHR
-
-/* Define if you have the time function.  */
-#undef HAVE_TIME
-
-/* Define if you have the <argz.h> header file.  */
-#undef HAVE_ARGZ_H
-
-/* Define if you have the <dlfcn.h> header file.  */
-#undef HAVE_DLFCN_H
-
-/* Define if you have the <errno.h> header file.  */
-#undef HAVE_ERRNO_H
-
-/* Define if you have the <fcntl.h> header file.  */
-#undef HAVE_FCNTL_H
-
-/* Define if you have the <fpu_control.h> header file.  */
-#undef HAVE_FPU_CONTROL_H
-
-/* Define if you have the <limits.h> header file.  */
-#undef HAVE_LIMITS_H
-
-/* Define if you have the <locale.h> header file.  */
-#undef HAVE_LOCALE_H
-
-/* Define if you have the <malloc.h> header file.  */
-#undef HAVE_MALLOC_H
-
-/* Define if you have the <nl_types.h> header file.  */
-#undef HAVE_NL_TYPES_H
-
-/* Define if you have the <stdlib.h> header file.  */
-#undef HAVE_STDLIB_H
-
-/* Define if you have the <string.h> header file.  */
-#undef HAVE_STRING_H
-
-/* Define if you have the <strings.h> header file.  */
-#undef HAVE_STRINGS_H
-
-/* Define if you have the <sys/param.h> header file.  */
-#undef HAVE_SYS_PARAM_H
-
-/* Define if you have the <sys/resource.h> header file.  */
-#undef HAVE_SYS_RESOURCE_H
-
-/* Define if you have the <sys/stat.h> header file.  */
-#undef HAVE_SYS_STAT_H
-
-/* Define if you have the <sys/time.h> header file.  */
-#undef HAVE_SYS_TIME_H
-
-/* Define if you have the <time.h> header file.  */
-#undef HAVE_TIME_H
-
-/* Define if you have the <unistd.h> header file.  */
-#undef HAVE_UNISTD_H
-
-/* Define if you have the <values.h> header file.  */
-#undef HAVE_VALUES_H
-
-/* Define if you have the nsl library (-lnsl).  */
-#undef HAVE_LIBNSL
-
-/* Define if you have the socket library (-lsocket).  */
-#undef HAVE_LIBSOCKET
diff --git a/sim/sh64/configure b/sim/sh64/configure
deleted file mode 100755
index 2a6ab864694..00000000000
--- a/sim/sh64/configure
+++ /dev/null
@@ -1,9007 +0,0 @@
-#! /bin/sh
-# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59.
-#
-# Copyright (C) 2003 Free Software Foundation, Inc.
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
-	 /*)
-	   if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-	     $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-	     CONFIG_SHELL=$as_dir/$as_base
-	     export CONFIG_SHELL
-	     exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-	   fi;;
-	 esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
-  # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
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-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$0" |
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-  	  /^X\(\/\/\)$/{ s//\1/; q; }
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-\`configure' configures this package to adapt to many kinds of systems.
-
-Usage: $0 [OPTION]... [VAR=VALUE]...
-
-To assign environment variables (e.g., CC, CFLAGS...), specify them as
-VAR=VALUE.  See below for descriptions of some of the useful variables.
-
-Defaults for the options are specified in brackets.
-
-Configuration:
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-
-_ACEOF
-
-  cat <<_ACEOF
-Installation directories:
-  --prefix=PREFIX         install architecture-independent files in PREFIX
-			  [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-			  [PREFIX]
-
-By default, \`make install' will install all the files in
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-
-For better control, use the options below.
-
-Fine tuning of the installation directories:
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-  --sbindir=DIR          system admin executables [EPREFIX/sbin]
-  --libexecdir=DIR       program executables [EPREFIX/libexec]
-  --datadir=DIR          read-only architecture-independent data [PREFIX/share]
-  --sysconfdir=DIR       read-only single-machine data [PREFIX/etc]
-  --sharedstatedir=DIR   modifiable architecture-independent data [PREFIX/com]
-  --localstatedir=DIR    modifiable single-machine data [PREFIX/var]
-  --libdir=DIR           object code libraries [EPREFIX/lib]
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-_ACEOF
-
-  cat <<\_ACEOF
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-Program names:
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-  --program-suffix=SUFFIX            append SUFFIX to installed program names
-  --program-transform-name=PROGRAM   run sed PROGRAM on installed program names
-
-System types:
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-_ACEOF
-fi
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-if test -n "$ac_init_help"; then
-
-  cat <<\_ACEOF
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-Optional Features:
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-  --enable-sim-bswap			Use Host specific BSWAP instruction.
-  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator
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-  --enable-sim-stdio			Specify whether to use stdio for console input/output.
-  --enable-sim-trace=opts		Enable tracing flags
-  --enable-sim-profile=opts		Enable profiling flags
-  --enable-sim-endian=endian		Specify target byte endian orientation.
-  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses.
-  --enable-sim-hostendian=end		Specify host byte endian orientation.
-  --enable-sim-scache=size		Specify simulator execution cache size.
-  --enable-sim-default-model=model	Specify default model to simulate.
-  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment.
-  --enable-sim-inline=inlines		Specify which functions should be inlined.
-  --enable-cgen-maint=DIR    build cgen generated files
-
-Optional Packages:
-  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
-  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
-  --with-included-gettext use the GNU gettext library included here
-
-Some influential environment variables:
-  CC          C compiler command
-  CFLAGS      C compiler flags
-  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
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-  CPPFLAGS    C/C++ preprocessor flags, e.g. -I<include dir> if you have
-              headers in a nonstandard directory <include dir>
-  CPP         C preprocessor
-
-Use these variables to override the choices made by `configure' or to help
-it to find libraries and programs with nonstandard names/locations.
-
-_ACEOF
-fi
-
-if test "$ac_init_help" = "recursive"; then
-  # If there are subdirs, report their specific --help.
-  ac_popdir=`pwd`
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-    ac_builddir=.
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-if test "$ac_dir" != .; then
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-  ac_dir_suffix= ac_top_builddir=
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-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
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-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
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-# Do not use `cd foo && pwd` to compute absolute paths, because
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-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
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-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
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-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
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-esac
-
-    cd $ac_dir
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-    if test -f $ac_srcdir/configure.gnu; then
-      echo
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-      echo
-      $SHELL $ac_srcdir/configure  --help=recursive
-    elif test -f $ac_srcdir/configure.ac ||
-	   test -f $ac_srcdir/configure.in; then
-      echo
-      $ac_configure --help
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-      echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
-    fi
-    cd $ac_popdir
-  done
-fi
-
-test -n "$ac_init_help" && exit 0
-if $ac_init_version; then
-  cat <<\_ACEOF
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This configure script is free software; the Free Software Foundation
-gives unlimited permission to copy, distribute and modify it.
-_ACEOF
-  exit 0
-fi
-exec 5>config.log
-cat >&5 <<_ACEOF
-This file contains any messages produced by compilers while
-running configure, to aid debugging if configure makes a mistake.
-
-It was created by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
-
-  $ $0 $@
-
-_ACEOF
-{
-cat <<_ASUNAME
-## --------- ##
-## Platform. ##
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-
-hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
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-uname -r = `(uname -r) 2>/dev/null || echo unknown`
-uname -s = `(uname -s) 2>/dev/null || echo unknown`
-uname -v = `(uname -v) 2>/dev/null || echo unknown`
-
-/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
-/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
-
-/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
-/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
-/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
-hostinfo               = `(hostinfo) 2>/dev/null               || echo unknown`
-/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
-/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
-/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
-
-_ASUNAME
-
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
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-  IFS=$as_save_IFS
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-  echo "PATH: $as_dir"
-done
-
-} >&5
-
-cat >&5 <<_ACEOF
-
-
-## ----------- ##
-## Core tests. ##
-## ----------- ##
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-_ACEOF
-
-
-# Keep a trace of the command line.
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-	case $ac_arg in
-	  *=* | --config-cache | -C | -disable-* | --disable-* \
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-      ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'"
-      # Get rid of the leading space.
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-## ----------- ##
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-ac_signal=0
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-# confdefs.h avoids OS command line length limits that DEFS can exceed.
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-
-# Predefined preprocessor variables.
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-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_NAME "$PACKAGE_NAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_VERSION "$PACKAGE_VERSION"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_STRING "$PACKAGE_STRING"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
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-
-# Let the site file select an alternate cache file if it wants to.
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-# Check that the precious variables saved in the cache have kept the same
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-ac_cache_corrupted=false
-for ac_var in `(set) 2>&1 |
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-      ac_cache_corrupted=: ;;
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-echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
-	{ echo "$as_me:$LINENO:   former value:  $ac_old_val" >&5
-echo "$as_me:   former value:  $ac_old_val" >&2;}
-	{ echo "$as_me:$LINENO:   current value: $ac_new_val" >&5
-echo "$as_me:   current value: $ac_new_val" >&2;}
-	ac_cache_corrupted=:
-      fi;;
-  esac
-  # Pass precious variables to config.status.
-  if test "$ac_new_set" = set; then
-    case $ac_new_val in
-    *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
-    *) ac_arg=$ac_var=$ac_new_val ;;
-    esac
-    case " $ac_configure_args " in
-      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
-      *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
-    esac
-  fi
-done
-if $ac_cache_corrupted; then
-  { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
-echo "$as_me: error: changes in the environment can compromise the build" >&2;}
-  { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
-echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-          ac_config_headers="$ac_config_headers config.h:config.in"
-
-
-# This file contains common code used by all simulators.
-#
-# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be invoked before any target specific stuff.
-# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
-# It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# sinclude(../common/aclocal.m4)
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-#
-# SIM_AC_COMMON
-#
-# ... target specific stuff ...
-#
-# SIM_AC_OUTPUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-sim_inline="-DDEFAULT_INLINE=0"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-# This file is derived from `gettext.m4'.  The difference is that the
-# included macros assume Cygnus-style source and build trees.
-
-# Macro to add for using GNU gettext.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 3
-
-
-
-
-
-# Search path for a program which passes the given test.
-# Ulrich Drepper <drepper@cygnus.com>, 1996.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-
-
-# Check whether LC_MESSAGES is available in <locale.h>.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-
-
-
-
-
-
-# This file contains common code used by all simulators.
-#
-# common.m4 invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be included before any target specific
-# stuff.  SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
-# the Makefile.  It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-# AC_CONFIG_HEADER(config.h:config.in)
-#
-# sinclude(../common/aclocal.m4)
-# sinclude(../common/common.m4)
-#
-# ... target specific stuff ...
-
-ac_aux_dir=
-for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  elif test -f $ac_dir/shtool; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/shtool install -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&5
-echo "$as_me: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-ac_config_guess="$SHELL $ac_aux_dir/config.guess"
-ac_config_sub="$SHELL $ac_aux_dir/config.sub"
-ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
-
-# Make sure we can run config.sub.
-$ac_config_sub sun4 >/dev/null 2>&1 ||
-  { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
-echo "$as_me: error: cannot run $ac_config_sub" >&2;}
-   { (exit 1); exit 1; }; }
-
-echo "$as_me:$LINENO: checking build system type" >&5
-echo $ECHO_N "checking build system type... $ECHO_C" >&6
-if test "${ac_cv_build+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_build_alias=$build_alias
-test -z "$ac_cv_build_alias" &&
-  ac_cv_build_alias=`$ac_config_guess`
-test -z "$ac_cv_build_alias" &&
-  { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
-echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
-   { (exit 1); exit 1; }; }
-ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_build" >&5
-echo "${ECHO_T}$ac_cv_build" >&6
-build=$ac_cv_build
-build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking host system type" >&5
-echo $ECHO_N "checking host system type... $ECHO_C" >&6
-if test "${ac_cv_host+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_host_alias=$host_alias
-test -z "$ac_cv_host_alias" &&
-  ac_cv_host_alias=$ac_cv_build_alias
-ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_host" >&5
-echo "${ECHO_T}$ac_cv_host" >&6
-host=$ac_cv_host
-host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking target system type" >&5
-echo $ECHO_N "checking target system type... $ECHO_C" >&6
-if test "${ac_cv_target+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_target_alias=$target_alias
-test "x$ac_cv_target_alias" = "x" &&
-  ac_cv_target_alias=$ac_cv_host_alias
-ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_target" >&5
-echo "${ECHO_T}$ac_cv_target" >&6
-target=$ac_cv_target
-target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-# The aliases save the names the user supplied, while $host etc.
-# will get canonicalized.
-test -n "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
-  program_prefix=${target_alias}-
-test "$program_prefix" != NONE &&
-  program_transform_name="s,^,$program_prefix,;$program_transform_name"
-# Use a double $ so make ignores it.
-test "$program_suffix" != NONE &&
-  program_transform_name="s,\$,$program_suffix,;$program_transform_name"
-# Double any \ or $.  echo might interpret backslashes.
-# By default was `s,x,x', remove it if useless.
-cat <<\_ACEOF >conftest.sed
-s/[\\$]/&&/g;s/;s,x,x,$//
-_ACEOF
-program_transform_name=`echo $program_transform_name | sed -f conftest.sed`
-rm conftest.sed
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-fi
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  ac_prog_rejected=no
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
-       ac_prog_rejected=yes
-       continue
-     fi
-    ac_cv_prog_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# != 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
-  fi
-fi
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  for ac_prog in cl
-  do
-    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
-set dummy $ac_tool_prefix$ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-    test -n "$CC" && break
-  done
-fi
-if test -z "$CC"; then
-  ac_ct_CC=$CC
-  for ac_prog in cl
-do
-  # Extract the first word of "$ac_prog", so it can be a program name with args.
-set dummy $ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  test -n "$ac_ct_CC" && break
-done
-
-  CC=$ac_ct_CC
-fi
-
-fi
-
-
-test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&5
-echo "$as_me: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-
-# Provide some information about the compiler.
-echo "$as_me:$LINENO:" \
-     "checking for C compiler version" >&5
-ac_compiler=`set X $ac_compile; echo $2`
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
-  (eval $ac_compiler --version </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5
-  (eval $ac_compiler -v </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5
-  (eval $ac_compiler -V </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files a.out a.exe b.out"
-# Try to create an executable without -o first, disregard a.out.
-# It will help us diagnose broken compilers, and finding out an intuition
-# of exeext.
-echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
-echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6
-ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
-if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5
-  (eval $ac_link_default) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # Find the output, starting from the most likely.  This scheme is
-# not robust to junk in `.', hence go to wildcards (a.*) only as a last
-# resort.
-
-# Be careful to initialize this variable, since it used to be cached.
-# Otherwise an old cache value of `no' led to `EXEEXT = no' in a Makefile.
-ac_cv_exeext=
-# b.out is created by i960 compilers.
-for ac_file in a_out.exe a.exe conftest.exe a.out conftest a.* conftest.* b.out
-do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj )
-	;;
-    conftest.$ac_ext )
-	# This is the source file.
-	;;
-    [ab].out )
-	# We found the default executable, but exeext='' is most
-	# certainly right.
-	break;;
-    *.* )
-	ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	# FIXME: I believe we export ac_cv_exeext for Libtool,
-	# but it would be cool to find out if it's true.  Does anybody
-	# maintain Libtool? --akim.
-	export ac_cv_exeext
-	break;;
-    * )
-	break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: C compiler cannot create executables
-See \`config.log' for more details." >&5
-echo "$as_me: error: C compiler cannot create executables
-See \`config.log' for more details." >&2;}
-   { (exit 77); exit 77; }; }
-fi
-
-ac_exeext=$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_file" >&5
-echo "${ECHO_T}$ac_file" >&6
-
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether the C compiler works" >&5
-echo $ECHO_N "checking whether the C compiler works... $ECHO_C" >&6
-# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
-# If not cross compiling, check that we can run a simple program.
-if test "$cross_compiling" != yes; then
-  if { ac_try='./$ac_file'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-    cross_compiling=no
-  else
-    if test "$cross_compiling" = maybe; then
-	cross_compiling=yes
-    else
-	{ { echo "$as_me:$LINENO: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-    fi
-  fi
-fi
-echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-
-rm -f a.out a.exe conftest$ac_cv_exeext b.out
-ac_clean_files=$ac_clean_files_save
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
-echo $ECHO_N "checking whether we are cross compiling... $ECHO_C" >&6
-echo "$as_me:$LINENO: result: $cross_compiling" >&5
-echo "${ECHO_T}$cross_compiling" >&6
-
-echo "$as_me:$LINENO: checking for suffix of executables" >&5
-echo $ECHO_N "checking for suffix of executables... $ECHO_C" >&6
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # If both `conftest.exe' and `conftest' are `present' (well, observable)
-# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
-# work properly (i.e., refer to `conftest.exe'), while it won't with
-# `rm'.
-for ac_file in conftest.exe conftest conftest.*; do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;;
-    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	  export ac_cv_exeext
-	  break;;
-    * ) break;;
-  esac
-done
-else
-  { { echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
-echo "${ECHO_T}$ac_cv_exeext" >&6
-
-rm -f conftest.$ac_ext
-EXEEXT=$ac_cv_exeext
-ac_exeext=$EXEEXT
-echo "$as_me:$LINENO: checking for suffix of object files" >&5
-echo $ECHO_N "checking for suffix of object files... $ECHO_C" >&6
-if test "${ac_cv_objext+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.o conftest.obj
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  for ac_file in `(ls conftest.o conftest.obj; ls conftest.*) 2>/dev/null`; do
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg ) ;;
-    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
-       break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest.$ac_cv_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
-echo "${ECHO_T}$ac_cv_objext" >&6
-OBJEXT=$ac_cv_objext
-ac_objext=$OBJEXT
-echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
-echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6
-if test "${ac_cv_c_compiler_gnu+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-#ifndef __GNUC__
-       choke me
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_compiler_gnu=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_compiler_gnu=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_cv_c_compiler_gnu=$ac_compiler_gnu
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
-echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6
-GCC=`test $ac_compiler_gnu = yes && echo yes`
-ac_test_CFLAGS=${CFLAGS+set}
-ac_save_CFLAGS=$CFLAGS
-CFLAGS="-g"
-echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
-echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_g+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_g=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_prog_cc_g=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_g" >&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS=$ac_save_CFLAGS
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5
-echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_prog_cc_stdc=no
-ac_save_CC=$CC
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdarg.h>
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
-struct buf { int x; };
-FILE * (*rcsopen) (struct buf *, struct stat *, int);
-static char *e (p, i)
-     char **p;
-     int i;
-{
-  return p[i];
-}
-static char *f (char * (*g) (char **, int), char **p, ...)
-{
-  char *s;
-  va_list v;
-  va_start (v,p);
-  s = g (p, va_arg (v,int));
-  va_end (v);
-  return s;
-}
-
-/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
-   function prototypes and stuff, but not '\xHH' hex character constants.
-   These don't provoke an error unfortunately, instead are silently treated
-   as 'x'.  The following induces an error, until -std1 is added to get
-   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
-   array size at least.  It's necessary to write '\x00'==0 to get something
-   that's true only with -std1.  */
-int osf4_cc_array ['\x00' == 0 ? 1 : -1];
-
-int test (int i, double x);
-struct s1 {int (*f) (int a);};
-struct s2 {int (*f) (double a);};
-int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
-int argc;
-char **argv;
-int
-main ()
-{
-return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
-  ;
-  return 0;
-}
-_ACEOF
-# Don't try gcc -ansi; that turns off useful extensions and
-# breaks some systems' header files.
-# AIX			-qlanglvl=ansi
-# Ultrix and OSF/1	-std1
-# HP-UX 10.20 and later	-Ae
-# HP-UX older versions	-Aa -D_HPUX_SOURCE
-# SVR4			-Xc -D__EXTENSIONS__
-for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
-do
-  CC="$ac_save_CC $ac_arg"
-  rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_stdc=$ac_arg
-break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext
-done
-rm -f conftest.$ac_ext conftest.$ac_objext
-CC=$ac_save_CC
-
-fi
-
-case "x$ac_cv_prog_cc_stdc" in
-  x|xno)
-    echo "$as_me:$LINENO: result: none needed" >&5
-echo "${ECHO_T}none needed" >&6 ;;
-  *)
-    echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6
-    CC="$CC $ac_cv_prog_cc_stdc" ;;
-esac
-
-# Some people use a C++ compiler to compile C.  Since we use `exit',
-# in C++ we need to declare it.  In case someone uses the same compiler
-# for both compiling C and C++ we need to have the C++ compiler decide
-# the declaration of exit, since it's the most demanding environment.
-cat >conftest.$ac_ext <<_ACEOF
-#ifndef __cplusplus
-  choke me
-#endif
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  for ac_declaration in \
-   '' \
-   'extern "C" void std::exit (int) throw (); using std::exit;' \
-   'extern "C" void std::exit (int); using std::exit;' \
-   'extern "C" void exit (int) throw ();' \
-   'extern "C" void exit (int);' \
-   'void exit (int);'
-do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-#include <stdlib.h>
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-continue
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
-rm -f conftest*
-if test -n "$ac_declaration"; then
-  echo '#ifdef __cplusplus' >>confdefs.h
-  echo $ac_declaration      >>confdefs.h
-  echo '#endif'             >>confdefs.h
-fi
-
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-# Find a good install program.  We prefer a C program (faster),
-# so one script is as good as another.  But avoid the broken or
-# incompatible versions:
-# SysV /etc/install, /usr/sbin/install
-# SunOS /usr/etc/install
-# IRIX /sbin/install
-# AIX /bin/install
-# AmigaOS /C/install, which installs bootblocks on floppy discs
-# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
-# AFS /usr/afsws/bin/install, which mishandles nonexistent args
-# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
-# OS/2's system install, which has a completely different semantic
-# ./install, which can be erroneously created by make from ./install.sh.
-echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
-echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6
-if test -z "$INSTALL"; then
-if test "${ac_cv_path_install+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  # Account for people who put trailing slashes in PATH elements.
-case $as_dir/ in
-  ./ | .// | /cC/* | \
-  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
-  ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
-  /usr/ucb/* ) ;;
-  *)
-    # OSF1 and SCO ODT 3.0 have their own names for install.
-    # Don't use installbsd from OSF since it installs stuff as root
-    # by default.
-    for ac_prog in ginstall scoinst install; do
-      for ac_exec_ext in '' $ac_executable_extensions; do
-	if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
-	  if test $ac_prog = install &&
-	    grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # AIX install.  It has an incompatible calling convention.
-	    :
-	  elif test $ac_prog = install &&
-	    grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # program-specific install script used by HP pwplus--don't use.
-	    :
-	  else
-	    ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
-	    break 3
-	  fi
-	fi
-      done
-    done
-    ;;
-esac
-done
-
-
-fi
-  if test "${ac_cv_path_install+set}" = set; then
-    INSTALL=$ac_cv_path_install
-  else
-    # As a last resort, use the slow shell script.  We don't cache a
-    # path for INSTALL within a source directory, because that will
-    # break other packages using the cache if that directory is
-    # removed, or if the path is relative.
-    INSTALL=$ac_install_sh
-  fi
-fi
-echo "$as_me:$LINENO: result: $INSTALL" >&5
-echo "${ECHO_T}$INSTALL" >&6
-
-# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
-# It thinks the first close brace ends the variable substitution.
-test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
-
-test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
-
-test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
-
-
-# Put a plausible default for CC_FOR_BUILD in Makefile.
-if test "x$cross_compiling" = "xno"; then
-  CC_FOR_BUILD='$(CC)'
-else
-  CC_FOR_BUILD=gcc
-fi
-
-
-
-
-AR=${AR-ar}
-
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
-fi
-fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  RANLIB=$ac_ct_RANLIB
-else
-  RANLIB="$ac_cv_prog_RANLIB"
-fi
-
-
-ALL_LINGUAS=
-echo "$as_me:$LINENO: checking whether ${MAKE-make} sets \$(MAKE)" >&5
-echo $ECHO_N "checking whether ${MAKE-make} sets \$(MAKE)... $ECHO_C" >&6
-set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y,:./+-,___p_,'`
-if eval "test \"\${ac_cv_prog_make_${ac_make}_set+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.make <<\_ACEOF
-all:
-	@echo 'ac_maketemp="$(MAKE)"'
-_ACEOF
-# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
-eval `${MAKE-make} -f conftest.make 2>/dev/null | grep temp=`
-if test -n "$ac_maketemp"; then
-  eval ac_cv_prog_make_${ac_make}_set=yes
-else
-  eval ac_cv_prog_make_${ac_make}_set=no
-fi
-rm -f conftest.make
-fi
-if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
-  echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-  SET_MAKE=
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-  SET_MAKE="MAKE=${MAKE-make}"
-fi
-
-
-echo "$as_me:$LINENO: checking for library containing strerror" >&5
-echo $ECHO_N "checking for library containing strerror... $ECHO_C" >&6
-if test "${ac_cv_search_strerror+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_func_search_save_LIBS=$LIBS
-ac_cv_search_strerror=no
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char strerror ();
-int
-main ()
-{
-strerror ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_search_strerror="none required"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-if test "$ac_cv_search_strerror" = no; then
-  for ac_lib in cposix; do
-    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
-    cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char strerror ();
-int
-main ()
-{
-strerror ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_search_strerror="-l$ac_lib"
-break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-  done
-fi
-LIBS=$ac_func_search_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_search_strerror" >&5
-echo "${ECHO_T}$ac_cv_search_strerror" >&6
-if test "$ac_cv_search_strerror" != no; then
-  test "$ac_cv_search_strerror" = "none required" || LIBS="$ac_cv_search_strerror $LIBS"
-
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
-echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-  if test "${ac_cv_prog_CPP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-      # Double quotes because CPP needs to be expanded
-    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
-    do
-      ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  break
-fi
-
-    done
-    ac_cv_prog_CPP=$CPP
-
-fi
-  CPP=$ac_cv_prog_CPP
-else
-  ac_cv_prog_CPP=$CPP
-fi
-echo "$as_me:$LINENO: result: $CPP" >&5
-echo "${ECHO_T}$CPP" >&6
-ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  :
-else
-  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&5
-echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-echo "$as_me:$LINENO: checking for egrep" >&5
-echo $ECHO_N "checking for egrep... $ECHO_C" >&6
-if test "${ac_cv_prog_egrep+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
-    then ac_cv_prog_egrep='grep -E'
-    else ac_cv_prog_egrep='egrep'
-    fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
-echo "${ECHO_T}$ac_cv_prog_egrep" >&6
- EGREP=$ac_cv_prog_egrep
-
-
-echo "$as_me:$LINENO: checking for ANSI C header files" >&5
-echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
-if test "${ac_cv_header_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_header_stdc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_header_stdc=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <string.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "memchr" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "free" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-  if test "$cross_compiling" = yes; then
-  :
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ctype.h>
-#if ((' ' & 0x0FF) == 0x020)
-# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#else
-# define ISLOWER(c) \
-		   (('a' <= (c) && (c) <= 'i') \
-		     || ('j' <= (c) && (c) <= 'r') \
-		     || ('s' <= (c) && (c) <= 'z'))
-# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
-#endif
-
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int
-main ()
-{
-  int i;
-  for (i = 0; i < 256; i++)
-    if (XOR (islower (i), ISLOWER (i))
-	|| toupper (i) != TOUPPER (i))
-      exit(2);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_header_stdc=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
-echo "${ECHO_T}$ac_cv_header_stdc" >&6
-if test $ac_cv_header_stdc = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define STDC_HEADERS 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5
-echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6
-if test "${ac_cv_c_const+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-/* FIXME: Include the comments suggested by Paul. */
-#ifndef __cplusplus
-  /* Ultrix mips cc rejects this.  */
-  typedef int charset[2];
-  const charset x;
-  /* SunOS 4.1.1 cc rejects this.  */
-  char const *const *ccp;
-  char **p;
-  /* NEC SVR4.0.2 mips cc rejects this.  */
-  struct point {int x, y;};
-  static struct point const zero = {0,0};
-  /* AIX XL C 1.02.0.0 rejects this.
-     It does not let you subtract one const X* pointer from another in
-     an arm of an if-expression whose if-part is not a constant
-     expression */
-  const char *g = "string";
-  ccp = &g + (g ? g-g : 0);
-  /* HPUX 7.0 cc rejects these. */
-  ++ccp;
-  p = (char**) ccp;
-  ccp = (char const *const *) p;
-  { /* SCO 3.2v4 cc rejects this.  */
-    char *t;
-    char const *s = 0 ? (char *) 0 : (char const *) 0;
-
-    *t++ = 0;
-  }
-  { /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
-    int x[] = {25, 17};
-    const int *foo = &x[0];
-    ++foo;
-  }
-  { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
-    typedef const int *iptr;
-    iptr p = 0;
-    ++p;
-  }
-  { /* AIX XL C 1.02.0.0 rejects this saying
-       "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
-    struct s { int j; const int *ap[3]; };
-    struct s *b; b->j = 5;
-  }
-  { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
-    const int foo = 10;
-  }
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_const=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_const=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5
-echo "${ECHO_T}$ac_cv_c_const" >&6
-if test $ac_cv_c_const = no; then
-
-cat >>confdefs.h <<\_ACEOF
-#define const
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for inline" >&5
-echo $ECHO_N "checking for inline... $ECHO_C" >&6
-if test "${ac_cv_c_inline+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_c_inline=no
-for ac_kw in inline __inline__ __inline; do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifndef __cplusplus
-typedef int foo_t;
-static $ac_kw foo_t static_foo () {return 0; }
-$ac_kw foo_t foo () {return 0; }
-#endif
-
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_inline=$ac_kw; break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5
-echo "${ECHO_T}$ac_cv_c_inline" >&6
-
-
-case $ac_cv_c_inline in
-  inline | yes) ;;
-  *)
-    case $ac_cv_c_inline in
-      no) ac_val=;;
-      *) ac_val=$ac_cv_c_inline;;
-    esac
-    cat >>confdefs.h <<_ACEOF
-#ifndef __cplusplus
-#define inline $ac_val
-#endif
-_ACEOF
-    ;;
-esac
-
-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-
-
-
-
-
-
-
-
-
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-		  inttypes.h stdint.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_Header=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_Header=no"
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-echo "$as_me:$LINENO: checking for off_t" >&5
-echo $ECHO_N "checking for off_t... $ECHO_C" >&6
-if test "${ac_cv_type_off_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((off_t *) 0)
-  return 0;
-if (sizeof (off_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_off_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_off_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5
-echo "${ECHO_T}$ac_cv_type_off_t" >&6
-if test $ac_cv_type_off_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define off_t long
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for size_t" >&5
-echo $ECHO_N "checking for size_t... $ECHO_C" >&6
-if test "${ac_cv_type_size_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((size_t *) 0)
-  return 0;
-if (sizeof (size_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_size_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_size_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5
-echo "${ECHO_T}$ac_cv_type_size_t" >&6
-if test $ac_cv_type_size_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define size_t unsigned
-_ACEOF
-
-fi
-
-# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
-# for constant arguments.  Useless!
-echo "$as_me:$LINENO: checking for working alloca.h" >&5
-echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6
-if test "${ac_cv_working_alloca_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <alloca.h>
-int
-main ()
-{
-char *p = (char *) alloca (2 * sizeof (int));
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_working_alloca_h=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_working_alloca_h=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5
-echo "${ECHO_T}$ac_cv_working_alloca_h" >&6
-if test $ac_cv_working_alloca_h = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA_H 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for alloca" >&5
-echo $ECHO_N "checking for alloca... $ECHO_C" >&6
-if test "${ac_cv_func_alloca_works+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-#else
-# ifdef _MSC_VER
-#  include <malloc.h>
-#  define alloca _alloca
-# else
-#  if HAVE_ALLOCA_H
-#   include <alloca.h>
-#  else
-#   ifdef _AIX
- #pragma alloca
-#   else
-#    ifndef alloca /* predefined by HP cc +Olibcalls */
-char *alloca ();
-#    endif
-#   endif
-#  endif
-# endif
-#endif
-
-int
-main ()
-{
-char *p = (char *) alloca (1);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_alloca_works=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_func_alloca_works=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5
-echo "${ECHO_T}$ac_cv_func_alloca_works" >&6
-
-if test $ac_cv_func_alloca_works = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA 1
-_ACEOF
-
-else
-  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
-# that cause trouble.  Some versions do not even contain alloca or
-# contain a buggy version.  If you still want to use their alloca,
-# use ar to extract alloca.o from them instead of compiling alloca.c.
-
-ALLOCA=alloca.$ac_objext
-
-cat >>confdefs.h <<\_ACEOF
-#define C_ALLOCA 1
-_ACEOF
-
-
-echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5
-echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6
-if test "${ac_cv_os_cray+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#if defined(CRAY) && ! defined(CRAY2)
-webecray
-#else
-wenotbecray
-#endif
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "webecray" >/dev/null 2>&1; then
-  ac_cv_os_cray=yes
-else
-  ac_cv_os_cray=no
-fi
-rm -f conftest*
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5
-echo "${ECHO_T}$ac_cv_os_cray" >&6
-if test $ac_cv_os_cray = yes; then
-  for ac_func in _getb67 GETB67 getb67; do
-    as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-
-cat >>confdefs.h <<_ACEOF
-#define CRAY_STACKSEG_END $ac_func
-_ACEOF
-
-    break
-fi
-
-  done
-fi
-
-echo "$as_me:$LINENO: checking stack direction for C alloca" >&5
-echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6
-if test "${ac_cv_c_stack_direction+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_c_stack_direction=0
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-find_stack_direction ()
-{
-  static char *addr = 0;
-  auto char dummy;
-  if (addr == 0)
-    {
-      addr = &dummy;
-      return find_stack_direction ();
-    }
-  else
-    return (&dummy > addr) ? 1 : -1;
-}
-
-int
-main ()
-{
-  exit (find_stack_direction () < 0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_stack_direction=1
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_stack_direction=-1
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5
-echo "${ECHO_T}$ac_cv_c_stack_direction" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define STACK_DIRECTION $ac_cv_c_stack_direction
-_ACEOF
-
-
-fi
-
-
-
-for ac_header in stdlib.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-for ac_func in getpagesize
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-echo "$as_me:$LINENO: checking for working mmap" >&5
-echo $ECHO_N "checking for working mmap... $ECHO_C" >&6
-if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-/* malloc might have been renamed as rpl_malloc. */
-#undef malloc
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the file system buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propagated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#if !STDC_HEADERS && !HAVE_STDLIB_H
-char *malloc ();
-#endif
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#if !HAVE_GETPAGESIZE
-/* Assume that all systems that can run configure have sys/param.h.  */
-# if !HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  if HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-int
-main ()
-{
-  char *data, *data2, *data3;
-  int i, pagesize;
-  int fd;
-
-  pagesize = getpagesize ();
-
-  /* First, make a file with some known garbage in it. */
-  data = (char *) malloc (pagesize);
-  if (!data)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    *(data + i) = rand ();
-  umask (0);
-  fd = creat ("conftest.mmap", 0600);
-  if (fd < 0)
-    exit (1);
-  if (write (fd, data, pagesize) != pagesize)
-    exit (1);
-  close (fd);
-
-  /* Next, try to mmap the file at a fixed address which already has
-     something else allocated at it.  If we can, also make sure that
-     we see the same garbage.  */
-  fd = open ("conftest.mmap", O_RDWR);
-  if (fd < 0)
-    exit (1);
-  data2 = (char *) malloc (2 * pagesize);
-  if (!data2)
-    exit (1);
-  data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1);
-  if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE,
-		     MAP_PRIVATE | MAP_FIXED, fd, 0L))
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data2 + i))
-      exit (1);
-
-  /* Finally, make sure that changes to the mapped area do not
-     percolate back to the file as seen by read().  (This is a bug on
-     some variants of i386 svr4.0.)  */
-  for (i = 0; i < pagesize; ++i)
-    *(data2 + i) = *(data2 + i) + 1;
-  data3 = (char *) malloc (pagesize);
-  if (!data3)
-    exit (1);
-  if (read (fd, data3, pagesize) != pagesize)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data3 + i))
-      exit (1);
-  close (fd);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5
-echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_MMAP 1
-_ACEOF
-
-fi
-rm -f conftest.mmap
-
-
-
-
-
-
-
-
-
-
-
-for ac_header in argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-
-
-
-
-
-
-for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-
-for ac_func in stpcpy
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-     cat >>confdefs.h <<\_ACEOF
-#define HAVE_STPCPY 1
-_ACEOF
-
-   fi
-
-   if test $ac_cv_header_locale_h = yes; then
-    echo "$as_me:$LINENO: checking for LC_MESSAGES" >&5
-echo $ECHO_N "checking for LC_MESSAGES... $ECHO_C" >&6
-if test "${am_cv_val_LC_MESSAGES+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <locale.h>
-int
-main ()
-{
-return LC_MESSAGES
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  am_cv_val_LC_MESSAGES=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-am_cv_val_LC_MESSAGES=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $am_cv_val_LC_MESSAGES" >&5
-echo "${ECHO_T}$am_cv_val_LC_MESSAGES" >&6
-    if test $am_cv_val_LC_MESSAGES = yes; then
-      cat >>confdefs.h <<\_ACEOF
-#define HAVE_LC_MESSAGES 1
-_ACEOF
-
-    fi
-  fi
-   echo "$as_me:$LINENO: checking whether NLS is requested" >&5
-echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
-        # Check whether --enable-nls or --disable-nls was given.
-if test "${enable_nls+set}" = set; then
-  enableval="$enable_nls"
-  USE_NLS=$enableval
-else
-  USE_NLS=yes
-fi;
-    echo "$as_me:$LINENO: result: $USE_NLS" >&5
-echo "${ECHO_T}$USE_NLS" >&6
-
-
-    USE_INCLUDED_LIBINTL=no
-
-        if test "$USE_NLS" = "yes"; then
-      cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
-      echo "$as_me:$LINENO: checking whether included gettext is requested" >&5
-echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6
-
-# Check whether --with-included-gettext or --without-included-gettext was given.
-if test "${with_included_gettext+set}" = set; then
-  withval="$with_included_gettext"
-  nls_cv_force_use_gnu_gettext=$withval
-else
-  nls_cv_force_use_gnu_gettext=no
-fi;
-      echo "$as_me:$LINENO: result: $nls_cv_force_use_gnu_gettext" >&5
-echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-                        		nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=NONE
-
-	if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking libintl.h usability" >&5
-echo $ECHO_N "checking libintl.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <libintl.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking libintl.h presence" >&5
-echo $ECHO_N "checking libintl.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: libintl.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: libintl.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: libintl.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: libintl.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_libintl_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-
-fi
-if test $ac_cv_header_libintl_h = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libc" >&5
-echo $ECHO_N "checking for gettext in libc... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libc=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libc" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libc" >&6
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     echo "$as_me:$LINENO: checking for bindtextdomain in -lintl" >&5
-echo $ECHO_N "checking for bindtextdomain in -lintl... $ECHO_C" >&6
-if test "${ac_cv_lib_intl_bindtextdomain+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lintl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bindtextdomain ();
-int
-main ()
-{
-bindtextdomain ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_intl_bindtextdomain=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_intl_bindtextdomain=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_intl_bindtextdomain" >&5
-echo "${ECHO_T}$ac_cv_lib_intl_bindtextdomain" >&6
-if test $ac_cv_lib_intl_bindtextdomain = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libintl" >&5
-echo $ECHO_N "checking for gettext in libintl... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libintl+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libintl=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libintl=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libintl" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libintl" >&6
-fi
-
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-	      cat >>confdefs.h <<\_ACEOF
-#define HAVE_GETTEXT 1
-_ACEOF
-
-	      # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_MSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$as_me:$LINENO: result: $MSGFMT" >&5
-echo "${ECHO_T}$MSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-	      if test "$MSGFMT" != "no"; then
-
-for ac_func in dcgettext
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-		# Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_GMSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $GMSGFMT in
-  [\\/]* | ?:[\\/]*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT=$ac_cv_path_GMSGFMT
-
-if test -n "$GMSGFMT"; then
-  echo "$as_me:$LINENO: result: $GMSGFMT" >&5
-echo "${ECHO_T}$GMSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-		# Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_XGETTEXT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$as_me:$LINENO: result: $XGETTEXT" >&5
-echo "${ECHO_T}$XGETTEXT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-		cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  CATOBJEXT=.gmo
-		   DATADIRNAME=share
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-CATOBJEXT=.mo
-		   DATADIRNAME=lib
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-
-fi
-
-
-
-
-        if test "$CATOBJEXT" = "NONE"; then
-	  	  	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-                INTLOBJS="\$(GETTOBJS)"
-        # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_MSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$as_me:$LINENO: result: $MSGFMT" >&5
-echo "${ECHO_T}$MSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-        # Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_GMSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $GMSGFMT in
-  [\\/]* | ?:[\\/]*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT=$ac_cv_path_GMSGFMT
-
-if test -n "$GMSGFMT"; then
-  echo "$as_me:$LINENO: result: $GMSGFMT" >&5
-echo "${ECHO_T}$GMSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-        # Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_XGETTEXT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$as_me:$LINENO: result: $XGETTEXT" >&5
-echo "${ECHO_T}$XGETTEXT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-            if test "$XGETTEXT" != ":"; then
-			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  echo "$as_me:$LINENO: result: found xgettext programs is not GNU xgettext; ignore it" >&5
-echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
-    else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
-    fi
-
-                for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
-echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       echo "$as_me:$LINENO: result: $LINGUAS" >&5
-echo "${ECHO_T}$LINGUAS" >&6
-     fi
-
-          if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-            if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-
-
-            if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking linux/version.h usability" >&5
-echo $ECHO_N "checking linux/version.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <linux/version.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking linux/version.h presence" >&5
-echo $ECHO_N "checking linux/version.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <linux/version.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: linux/version.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: linux/version.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: linux/version.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: linux/version.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_linux_version_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-
-fi
-if test $ac_cv_header_linux_version_h = yes; then
-  msgformat=linux
-else
-  msgformat=xopen
-fi
-
-
-
-	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-            if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-
-
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-
-
-      l=
-
-
-            if test -d $srcdir/po; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
-
-
-# Check for common headers.
-# FIXME: Seems to me this can cause problems for i386-windows hosts.
-# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
-
-
-
-
-
-for ac_header in stdlib.h string.h strings.h unistd.h time.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in sys/time.h sys/resource.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in fcntl.h fpu_control.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-for ac_header in dlfcn.h errno.h sys/stat.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-for ac_func in getrusage time sigaction __setfpucw
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-# Check for socket libraries
-
-echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
-echo $ECHO_N "checking for bind in -lsocket... $ECHO_C" >&6
-if test "${ac_cv_lib_socket_bind+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lsocket  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bind ();
-int
-main ()
-{
-bind ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_socket_bind=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_socket_bind=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
-echo "${ECHO_T}$ac_cv_lib_socket_bind" >&6
-if test $ac_cv_lib_socket_bind = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBSOCKET 1
-_ACEOF
-
-  LIBS="-lsocket $LIBS"
-
-fi
-
-
-echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
-echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6
-if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lnsl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char gethostbyname ();
-int
-main ()
-{
-gethostbyname ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_nsl_gethostbyname=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_nsl_gethostbyname=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
-echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6
-if test $ac_cv_lib_nsl_gethostbyname = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBNSL 1
-_ACEOF
-
-  LIBS="-lnsl $LIBS"
-
-fi
-
-
-. ${srcdir}/../../bfd/configure.host
-
-
-
-USE_MAINTAINER_MODE=no
-# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
-if test "${enable_maintainer_mode+set}" = set; then
-  enableval="$enable_maintainer_mode"
-  case "${enableval}" in
-  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
-  no)	MAINT="#" ;;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
-echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; MAINT="#" ;;
-esac
-if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
-  echo "Setting maintainer mode" 6>&1
-fi
-else
-  MAINT="#"
-fi;
-
-
-# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
-if test "${enable_sim_bswap+set}" = set; then
-  enableval="$enable_sim_bswap"
-  case "${enableval}" in
-  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
-  no)	sim_bswap="-DWITH_BSWAP=0";;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
-echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_bswap="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
-  echo "Setting bswap flags = $sim_bswap" 6>&1
-fi
-else
-  sim_bswap=""
-fi;
-
-
-# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
-if test "${enable_sim_cflags+set}" = set; then
-  enableval="$enable_sim_cflags"
-  case "${enableval}" in
-  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
-  trace) { { echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
-echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_cflags="";;
-  no)	 sim_cflags="";;
-  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
-  echo "Setting sim cflags = $sim_cflags" 6>&1
-fi
-else
-  sim_cflags=""
-fi;
-
-
-# Check whether --enable-sim-debug or --disable-sim-debug was given.
-if test "${enable_sim_debug+set}" = set; then
-  enableval="$enable_sim_debug"
-  case "${enableval}" in
-  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
-  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
-  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
-  echo "Setting sim debug = $sim_debug" 6>&1
-fi
-else
-  sim_debug=""
-fi;
-
-
-# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
-if test "${enable_sim_stdio+set}" = set; then
-  enableval="$enable_sim_stdio"
-  case "${enableval}" in
-  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
-  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
-  *)	{ { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_stdio="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
-  echo "Setting stdio flags = $sim_stdio" 6>&1
-fi
-else
-  sim_stdio=""
-fi;
-
-
-# Check whether --enable-sim-trace or --disable-sim-trace was given.
-if test "${enable_sim_trace+set}" = set; then
-  enableval="$enable_sim_trace"
-  case "${enableval}" in
-  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
-  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
-  [-0-9]*)
-	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
-  [a-z]*)
-	sim_trace=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_trace" = x; then
-	    sim_trace="-DWITH_TRACE='(TRACE_$x"
-	  else
-	    sim_trace="${sim_trace}|TRACE_$x"
-	  fi
-	done
-	sim_trace="$sim_trace)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
-  echo "Setting sim trace = $sim_trace" 6>&1
-fi
-else
-  sim_trace=""
-fi;
-
-
-# Check whether --enable-sim-profile or --disable-sim-profile was given.
-if test "${enable_sim_profile+set}" = set; then
-  enableval="$enable_sim_profile"
-  case "${enableval}" in
-  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
-  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
-  [-0-9]*)
-	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
-  [a-z]*)
-	sim_profile=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_profile" = x; then
-	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
-	  else
-	    sim_profile="${sim_profile}|PROFILE_$x"
-	  fi
-	done
-	sim_profile="$sim_profile)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
-  echo "Setting sim profile = $sim_profile" 6>&1
-fi
-else
-  sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
-fi;
-
-
-echo "$as_me:$LINENO: checking return type of signal handlers" >&5
-echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6
-if test "${ac_cv_type_signal+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <signal.h>
-#ifdef signal
-# undef signal
-#endif
-#ifdef __cplusplus
-extern "C" void (*signal (int, void (*)(int)))(int);
-#else
-void (*signal ()) ();
-#endif
-
-int
-main ()
-{
-int i;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_signal=void
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_signal=int
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
-echo "${ECHO_T}$ac_cv_type_signal" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define RETSIGTYPE $ac_cv_type_signal
-_ACEOF
-
-
-
-
-
-sim_link_files=
-sim_link_links=
-
-sim_link_links=tconfig.h
-if test -f ${srcdir}/tconfig.in
-then
-  sim_link_files=tconfig.in
-else
-  sim_link_files=../common/tconfig.in
-fi
-
-# targ-vals.def points to the libc macro description file.
-case "${target}" in
-*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
-esac
-sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
-sim_link_links="${sim_link_links} targ-vals.def"
-
-
-
-wire_endian=""
-default_endian="BIG_ENDIAN"
-# Check whether --enable-sim-endian or --disable-sim-endian was given.
-if test "${enable_sim_endian+set}" = set; then
-  enableval="$enable_sim_endian"
-  case "${enableval}" in
-  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
-  yes)	 if test x"$wire_endian" != x; then
-	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-	 else
-           if test x"$default_endian" != x; then
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
-	   else
-	     echo "No hard-wired endian for target $target" 1>&6
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  no)	 if test x"$default_endian" != x; then
-	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-	 else
-	   if test x"$wire_endian" != x; then
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
-	   else
-	     echo "No default endian for target $target" 1>&6
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-endian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-endian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_endian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
-  echo "Setting endian flags = $sim_endian" 6>&1
-fi
-else
-  if test x"$default_endian" != x; then
-  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-else
-  if test x"$wire_endian" != x; then
-    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-  else
-    sim_endian=
-  fi
-fi
-fi;
-wire_alignment="STRICT_ALIGNMENT"
-default_alignment=""
-
-# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
-if test "${enable_sim_alignment+set}" = set; then
-  enableval="$enable_sim_alignment"
-  case "${enableval}" in
-  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
-  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
-  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
-  yes) if test x"$wire_alignment" != x; then
-	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-       else
-         if test x"$default_alignment" != x; then
-           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
-         else
-	   echo "No hard-wired alignment for target $target" 1>&6
-	   sim_alignment="-DWITH_ALIGNMENT=0"
-         fi
-       fi;;
-  no)  if test x"$default_alignment" != x; then
-	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-       else
-         if test x"$wire_alignment" != x; then
-	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
-         else
-           echo "No default alignment for target $target" 1>&6
-           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
-         fi
-       fi;;
-  *)   { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_alignment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
-  echo "Setting alignment flags = $sim_alignment" 6>&1
-fi
-else
-  if test x"$default_alignment" != x; then
-  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-else
-  if test x"$wire_alignment" != x; then
-    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-  else
-    sim_alignment=
-  fi
-fi
-fi;
-
-# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
-if test "${enable_sim_hostendian+set}" = set; then
-  enableval="$enable_sim_hostendian"
-  case "${enableval}" in
-  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
-  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_hostendian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
-  echo "Setting hostendian flags = $sim_hostendian" 6>&1
-fi
-else
-
-if test "x$cross_compiling" = "xno"; then
-  echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
-echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
-if test "${ac_cv_c_bigendian+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  # See if sys/param.h defines the BYTE_ORDER macro.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
- bogus endian macros
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  # It does; now see whether it defined to BIG_ENDIAN or not.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if BYTE_ORDER != BIG_ENDIAN
- not big endian
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_bigendian=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-# It does not; compile a test program.
-if test "$cross_compiling" = yes; then
-  # try to guess the endianness by grepping values into an object file
-  ac_cv_c_bigendian=unknown
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
-short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
-void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
-short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
-short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
-void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
-int
-main ()
-{
- _ascii (); _ebcdic ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
-  ac_cv_c_bigendian=yes
-fi
-if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
-  if test "$ac_cv_c_bigendian" = unknown; then
-    ac_cv_c_bigendian=no
-  else
-    # finding both strings is unlikely to happen, but who knows?
-    ac_cv_c_bigendian=unknown
-  fi
-fi
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-main ()
-{
-  /* Are we little or big endian?  From Harbison&Steele.  */
-  union
-  {
-    long l;
-    char c[sizeof (long)];
-  } u;
-  u.l = 1;
-  exit (u.c[sizeof (long) - 1] == 1);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=no
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_bigendian=yes
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
-echo "${ECHO_T}$ac_cv_c_bigendian" >&6
-case $ac_cv_c_bigendian in
-  yes)
-
-cat >>confdefs.h <<\_ACEOF
-#define WORDS_BIGENDIAN 1
-_ACEOF
- ;;
-  no)
-     ;;
-  *)
-    { { echo "$as_me:$LINENO: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&5
-echo "$as_me: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-
-  if test $ac_cv_c_bigendian = yes; then
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
-  else
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
-  fi
-else
-  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
-fi
-fi;
-
-default_sim_scache="16384"
-# Check whether --enable-sim-scache or --disable-sim-scache was given.
-if test "${enable_sim_scache+set}" = set; then
-  enableval="$enable_sim_scache"
-  case "${enableval}" in
-  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
-  no)	sim_scache="-DWITH_SCACHE=0" ;;
-  [0-9]*) sim_scache="-DWITH_SCACHE=${enableval}";;
-  *)	{ { echo "$as_me:$LINENO: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&5
-echo "$as_me: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&2;}
-   { (exit 1); exit 1; }; };
-	sim_scache="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
-  echo "Setting scache size = $sim_scache" 6>&1
-fi
-else
-  sim_scache="-DWITH_SCACHE=${default_sim_scache}"
-fi;
-
-
-default_sim_default_model="sh5"
-# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
-if test "${enable_sim_default_model+set}" = set; then
-  enableval="$enable_sim_default_model"
-  case "${enableval}" in
-  yes|no) { { echo "$as_me:$LINENO: error: \"Missing argument to --enable-sim-default-model\"" >&5
-echo "$as_me: error: \"Missing argument to --enable-sim-default-model\"" >&2;}
-   { (exit 1); exit 1; }; };;
-  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
-  echo "Setting default model = $sim_default_model" 6>&1
-fi
-else
-  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
-fi;
-
-
-# Check whether --enable-sim-environment or --disable-sim-environment was given.
-if test "${enable_sim_environment+set}" = set; then
-  enableval="$enable_sim_environment"
-  case "${enableval}" in
-  all | ALL)             sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
-  user | USER)           sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
-  virtual | VIRTUAL)     sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
-  operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
-  *)   { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&2;}
-   { (exit 1); exit 1; }; };
-       sim_environment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
-  echo "Setting sim environment = $sim_environment" 6>&1
-fi
-else
-  sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
-fi;
-
-default_sim_inline=""
-# Check whether --enable-sim-inline or --disable-sim-inline was given.
-if test "${enable_sim_inline+set}" = set; then
-  enableval="$enable_sim_inline"
-  sim_inline=""
-case "$enableval" in
-  no)		sim_inline="-DDEFAULT_INLINE=0";;
-  0)		sim_inline="-DDEFAULT_INLINE=0";;
-  yes | 2)	sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
-  1)		sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
-  *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-       new_flag=""
-       case "$x" in
-	 *_INLINE=*)	new_flag="-D$x";;
-	 *=*)		new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
-	 *_INLINE)	new_flag="-D$x=ALL_C_INLINE";;
-	 *)		new_flag="-D$x""_INLINE=ALL_C_INLINE";;
-       esac
-       if test x"$sim_inline" = x""; then
-	 sim_inline="$new_flag"
-       else
-	 sim_inline="$sim_inline $new_flag"
-       fi
-     done;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
-  echo "Setting inline flags = $sim_inline" 6>&1
-fi
-else
-
-if test "x$cross_compiling" = "xno"; then
-  if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
-    sim_inline="${default_sim_inline}"
-    if test x"$silent" != x"yes"; then
-      echo "Setting inline flags = $sim_inline" 6>&1
-    fi
-  else
-    sim_inline=""
-  fi
-else
-  sim_inline="-DDEFAULT_INLINE=0"
-fi
-fi;
-
-cgen_maint=no
-cgen=guile
-cgendir='$(srcdir)/../../cgen'
-# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
-if test "${enable_cgen_maint+set}" = set; then
-  enableval="$enable_cgen_maint"
-  case "${enableval}" in
-  yes)	cgen_maint=yes ;;
-  no)	cgen_maint=no ;;
-  *)
-	# argument is cgen install directory (not implemented yet).
-	# Having a `share' directory might be more appropriate for the .scm,
-	# .cpu, etc. files.
-	cgendir=${cgen_maint}/lib/cgen
-	cgen=guile
-	;;
-esac
-fi; if test x${cgen_maint} != xno ; then
-  CGEN_MAINT=''
-else
-  CGEN_MAINT='#'
-fi
-
-
-
-
-
-
-ac_sources="$sim_link_files"
-ac_dests="$sim_link_links"
-while test -n "$ac_sources"; do
-  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
-  set $ac_sources; ac_source=$1; shift; ac_sources=$*
-  ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
-done
-          ac_config_links="$ac_config_links $ac_config_links_1"
-
-cgen_breaks=""
-if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
-cgen_breaks="break cgen_rtx_error";
-fi
-
-          ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
-
-          ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
-
-          ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
-
-          ac_config_commands="$ac_config_commands Makefile"
-
-          ac_config_commands="$ac_config_commands stamp-h"
-
-cat >confcache <<\_ACEOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs, see configure's option --config-cache.
-# It is not useful on other systems.  If it contains results you don't
-# want to keep, you may remove or edit it.
-#
-# config.status only pays attention to the cache file if you give it
-# the --recheck option to rerun configure.
-#
-# `ac_cv_env_foo' variables (set or unset) will be overridden when
-# loading this file, other *unset* `ac_cv_foo' will be assigned the
-# following values.
-
-_ACEOF
-
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-{
-  (set) 2>&1 |
-    case `(ac_space=' '; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      # `set' does not quote correctly, so add quotes (double-quote
-      # substitution turns \\\\ into \\, and sed turns \\ into \).
-      sed -n \
-	"s/'/'\\\\''/g;
-	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
-      ;;
-    *)
-      # `set' quotes correctly as required by POSIX, so do not add quotes.
-      sed -n \
-	"s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
-      ;;
-    esac;
-} |
-  sed '
-     t clear
-     : clear
-     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
-     t end
-     /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
-     : end' >>confcache
-if diff $cache_file confcache >/dev/null 2>&1; then :; else
-  if test -w $cache_file; then
-    test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
-    cat confcache >$cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# VPATH may cause trouble with some makes, so we remove $(srcdir),
-# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
-# trailing colons and then remove the whole line if VPATH becomes empty
-# (actually we leave an empty line to preserve line numbers).
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[	 ]*VPATH[	 ]*=/{
-s/:*\$(srcdir):*/:/;
-s/:*\${srcdir}:*/:/;
-s/:*@srcdir@:*/:/;
-s/^\([^=]*=[	 ]*\):*/\1/;
-s/:*$//;
-s/^[^=]*=[	 ]*$//;
-}'
-fi
-
-DEFS=-DHAVE_CONFIG_H
-
-ac_libobjs=
-ac_ltlibobjs=
-for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
-  # 1. Remove the extension, and $U if already installed.
-  ac_i=`echo "$ac_i" |
-	 sed 's/\$U\././;s/\.o$//;s/\.obj$//'`
-  # 2. Add them.
-  ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext"
-  ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo'
-done
-LIBOBJS=$ac_libobjs
-
-LTLIBOBJS=$ac_ltlibobjs
-
-
-
-: ${CONFIG_STATUS=./config.status}
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files $CONFIG_STATUS"
-{ echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
-echo "$as_me: creating $CONFIG_STATUS" >&6;}
-cat >$CONFIG_STATUS <<_ACEOF
-#! $SHELL
-# Generated by $as_me.
-# Run this file to recreate the current configuration.
-# Compiler output produced by configure, useful for debugging
-# configure, is in config.log if it exists.
-
-debug=false
-ac_cs_recheck=false
-ac_cs_silent=false
-SHELL=\${CONFIG_SHELL-$SHELL}
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { { echo "$as_me:$LINENO: error: cannot find myself; rerun with an absolute path" >&5
-echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
-	 /*)
-	   if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-	     $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-	     CONFIG_SHELL=$as_dir/$as_base
-	     export CONFIG_SHELL
-	     exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-	   fi;;
-	 esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
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-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
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-  chmod +x $as_me.lineno ||
-    { { echo "$as_me:$LINENO: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&5
-echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2;}
-   { (exit 1); exit 1; }; }
-
-  # Don't try to exec as it changes $[0], causing all sort of problems
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-
-
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
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-' ECHO_T='	' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
-esac
-
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-rm -f conf$$ conf$$.exe conf$$.file
-echo >conf$$.file
-if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
-    as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
-elif ln conf$$.file conf$$ 2>/dev/null; then
-  as_ln_s=ln
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-  as_ln_s='cp -p'
-fi
-rm -f conf$$ conf$$.exe conf$$.file
-
-if mkdir -p . 2>/dev/null; then
-  as_mkdir_p=:
-else
-  test -d ./-p && rmdir ./-p
-  as_mkdir_p=false
-fi
-
-as_executable_p="test -f"
-
-# Sed expression to map a string onto a valid CPP name.
-as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
-
-# Sed expression to map a string onto a valid variable name.
-as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
-
-
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS=" 	$as_nl"
-
-# CDPATH.
-$as_unset CDPATH
-
-exec 6>&1
-
-# Open the log real soon, to keep \$[0] and so on meaningful, and to
-# report actual input values of CONFIG_FILES etc. instead of their
-# values after options handling.  Logging --version etc. is OK.
-exec 5>>config.log
-{
-  echo
-  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
-## Running $as_me. ##
-_ASBOX
-} >&5
-cat >&5 <<_CSEOF
-
-This file was extended by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
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-  CONFIG_FILES    = $CONFIG_FILES
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-  $ $0 $@
-
-_CSEOF
-echo "on `(hostname || uname -n) 2>/dev/null | sed 1q`" >&5
-echo >&5
-_ACEOF
-
-# Files that config.status was made for.
-if test -n "$ac_config_files"; then
-  echo "config_files=\"$ac_config_files\"" >>$CONFIG_STATUS
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-
-if test -n "$ac_config_headers"; then
-  echo "config_headers=\"$ac_config_headers\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_links"; then
-  echo "config_links=\"$ac_config_links\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_commands"; then
-  echo "config_commands=\"$ac_config_commands\"" >>$CONFIG_STATUS
-fi
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-ac_cs_usage="\
-\`$as_me' instantiates files from templates according to the
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-
-Usage: $0 [OPTIONS] [FILE]...
-
-  -h, --help       print this help, then exit
-  -V, --version    print version number, then exit
-  -q, --quiet      do not print progress messages
-  -d, --debug      don't remove temporary files
-      --recheck    update $as_me by reconfiguring in the same conditions
-  --file=FILE[:TEMPLATE]
-		   instantiate the configuration file FILE
-  --header=FILE[:TEMPLATE]
-		   instantiate the configuration header FILE
-
-Configuration files:
-$config_files
-
-Configuration headers:
-$config_headers
-
-Configuration links:
-$config_links
-
-Configuration commands:
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-
-cat >>$CONFIG_STATUS <<_ACEOF
-ac_cs_version="\\
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-Copyright (C) 2003 Free Software Foundation, Inc.
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-srcdir=$srcdir
-INSTALL="$INSTALL"
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-# If no file are specified by the user, then we need to provide default
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-ac_need_defaults=:
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-  -*)
-    ac_option=$1
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-    ac_shift=shift
-    ;;
-  *) # This is not an option, so the user has probably given explicit
-     # arguments.
-     ac_option=$1
-     ac_need_defaults=false;;
-  esac
-
-  case $ac_option in
-  # Handling of the options.
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
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-    ac_cs_recheck=: ;;
-  --version | --vers* | -V )
-    echo "$ac_cs_version"; exit 0 ;;
-  --he | --h)
-    # Conflict between --help and --header
-    { { echo "$as_me:$LINENO: error: ambiguous option: $1
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-echo "$as_me: error: ambiguous option: $1
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-   { (exit 1); exit 1; }; };;
-  --help | --hel | -h )
-    echo "$ac_cs_usage"; exit 0 ;;
-  --debug | --d* | -d )
-    debug=: ;;
-  --file | --fil | --fi | --f )
-    $ac_shift
-    CONFIG_FILES="$CONFIG_FILES $ac_optarg"
-    ac_need_defaults=false;;
-  --header | --heade | --head | --hea )
-    $ac_shift
-    CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
-    ac_need_defaults=false;;
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
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-    ac_cs_silent=: ;;
-
-  # This is an error.
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-   { (exit 1); exit 1; }; } ;;
-
-  *) ac_config_targets="$ac_config_targets $1" ;;
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-ac_configure_extra_args=
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-if $ac_cs_silent; then
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-  ac_configure_extra_args="$ac_configure_extra_args --silent"
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-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-if \$ac_cs_recheck; then
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-
-
-
-
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_config_target in $ac_config_targets
-do
-  case "$ac_config_target" in
-  # Handling of arguments.
-  "Makefile.sim" ) CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
-  "Make-common.sim" ) CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
-  ".gdbinit" ) CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
-  "$ac_config_links_1" ) CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
-  "Makefile" ) CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
-  "stamp-h" ) CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
-  "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
-  *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
-echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# If the user did not use the arguments to specify the items to instantiate,
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-# We use the long form for the default assignment because of an extremely
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-if $ac_need_defaults; then
-  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
-  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
-  test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
-  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
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-
-# Have a temporary directory for convenience.  Make it in the build tree
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-# Create a temporary directory, and hook for its removal unless debugging.
-$debug ||
-{
-  trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
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-}
-
-# Create a (secure) tmp directory for tmp files.
-
-{
-  tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
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-{
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-{
-   echo "$me: cannot create a temporary directory in ." >&2
-   { (exit 1); exit 1; }
-}
-
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-
-#
-# CONFIG_FILES section.
-#
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-# No need to generate the scripts if there are no CONFIG_FILES.
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-s,@INCLUDE_LOCALE_H@,$INCLUDE_LOCALE_H,;t t
-s,@GT_NO@,$GT_NO,;t t
-s,@GT_YES@,$GT_YES,;t t
-s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t
-s,@l@,$l,;t t
-s,@MAINT@,$MAINT,;t t
-s,@sim_bswap@,$sim_bswap,;t t
-s,@sim_cflags@,$sim_cflags,;t t
-s,@sim_debug@,$sim_debug,;t t
-s,@sim_stdio@,$sim_stdio,;t t
-s,@sim_trace@,$sim_trace,;t t
-s,@sim_profile@,$sim_profile,;t t
-s,@CGEN_MAINT@,$CGEN_MAINT,;t t
-s,@cgendir@,$cgendir,;t t
-s,@cgen@,$cgen,;t t
-s,@cgen_breaks@,$cgen_breaks,;t t
-s,@LIBOBJS@,$LIBOBJS,;t t
-s,@LTLIBOBJS@,$LTLIBOBJS,;t t
-CEOF
-
-_ACEOF
-
-  cat >>$CONFIG_STATUS <<\_ACEOF
-  # Split the substitutions into bite-sized pieces for seds with
-  # small command number limits, like on Digital OSF/1 and HP-UX.
-  ac_max_sed_lines=48
-  ac_sed_frag=1 # Number of current file.
-  ac_beg=1 # First line for current file.
-  ac_end=$ac_max_sed_lines # Line after last line for current file.
-  ac_more_lines=:
-  ac_sed_cmds=
-  while $ac_more_lines; do
-    if test $ac_beg -gt 1; then
-      sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    else
-      sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    fi
-    if test ! -s $tmp/subs.frag; then
-      ac_more_lines=false
-    else
-      # The purpose of the label and of the branching condition is to
-      # speed up the sed processing (if there are no `@' at all, there
-      # is no need to browse any of the substitutions).
-      # These are the two extra sed commands mentioned above.
-      (echo ':t
-  /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
-      if test -z "$ac_sed_cmds"; then
-	ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
-      else
-	ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
-      fi
-      ac_sed_frag=`expr $ac_sed_frag + 1`
-      ac_beg=$ac_end
-      ac_end=`expr $ac_end + $ac_max_sed_lines`
-    fi
-  done
-  if test -z "$ac_sed_cmds"; then
-    ac_sed_cmds=cat
-  fi
-fi # test -n "$CONFIG_FILES"
-
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
-  ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_file" : 'X\(//\)[^/]' \| \
-	 X"$ac_file" : 'X\(//\)$' \| \
-	 X"$ac_file" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $INSTALL in
-  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
-  *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
-  esac
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    configure_input=
-  else
-    configure_input="$ac_file.  "
-  fi
-  configure_input=$configure_input"Generated from `echo $ac_file_in |
-				     sed 's,.*/,,'` by configure."
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 echo "$f";;
-      *) # Relative
-	 if test -f "$f"; then
-	   # Build tree
-	   echo "$f"
-	 elif test -f "$srcdir/$f"; then
-	   # Source tree
-	   echo "$srcdir/$f"
-	 else
-	   # /dev/null tree
-	   { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-  sed "$ac_vpsub
-$extrasub
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-:t
-/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
-s,@configure_input@,$configure_input,;t t
-s,@srcdir@,$ac_srcdir,;t t
-s,@abs_srcdir@,$ac_abs_srcdir,;t t
-s,@top_srcdir@,$ac_top_srcdir,;t t
-s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
-s,@builddir@,$ac_builddir,;t t
-s,@abs_builddir@,$ac_abs_builddir,;t t
-s,@top_builddir@,$ac_top_builddir,;t t
-s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
-s,@INSTALL@,$ac_INSTALL,;t t
-" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
-  rm -f $tmp/stdin
-  if test x"$ac_file" != x-; then
-    mv $tmp/out $ac_file
-  else
-    cat $tmp/out
-    rm -f $tmp/out
-  fi
-
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_HEADER section.
-#
-
-# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
-# NAME is the cpp macro being defined and VALUE is the value it is being given.
-#
-# ac_d sets the value in "#define NAME VALUE" lines.
-ac_dA='s,^\([	 ]*\)#\([	 ]*define[	 ][	 ]*\)'
-ac_dB='[	 ].*$,\1#\2'
-ac_dC=' '
-ac_dD=',;t'
-# ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
-ac_uA='s,^\([	 ]*\)#\([	 ]*\)undef\([	 ][	 ]*\)'
-ac_uB='$,\1#\2define\3'
-ac_uC=' '
-ac_uD=',;t'
-
-for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  test x"$ac_file" != x- && { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 # Do quote $f, to prevent DOS paths from being IFS'd.
-	 echo "$f";;
-      *) # Relative
-	 if test -f "$f"; then
-	   # Build tree
-	   echo "$f"
-	 elif test -f "$srcdir/$f"; then
-	   # Source tree
-	   echo "$srcdir/$f"
-	 else
-	   # /dev/null tree
-	   { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-  # Remove the trailing spaces.
-  sed 's/[	 ]*$//' $ac_file_inputs >$tmp/in
-
-_ACEOF
-
-# Transform confdefs.h into two sed scripts, `conftest.defines' and
-# `conftest.undefs', that substitutes the proper values into
-# config.h.in to produce config.h.  The first handles `#define'
-# templates, and the second `#undef' templates.
-# And first: Protect against being on the right side of a sed subst in
-# config.status.  Protect against being in an unquoted here document
-# in config.status.
-rm -f conftest.defines conftest.undefs
-# Using a here document instead of a string reduces the quoting nightmare.
-# Putting comments in sed scripts is not portable.
-#
-# `end' is used to avoid that the second main sed command (meant for
-# 0-ary CPP macros) applies to n-ary macro definitions.
-# See the Autoconf documentation for `clear'.
-cat >confdef2sed.sed <<\_ACEOF
-s/[\\&,]/\\&/g
-s,[\\$`],\\&,g
-t clear
-: clear
-s,^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 (][^	 (]*\)\(([^)]*)\)[	 ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp
-t end
-s,^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 ][^	 ]*\)[	 ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp
-: end
-_ACEOF
-# If some macros were called several times there might be several times
-# the same #defines, which is useless.  Nevertheless, we may not want to
-# sort them, since we want the *last* AC-DEFINE to be honored.
-uniq confdefs.h | sed -n -f confdef2sed.sed >conftest.defines
-sed 's/ac_d/ac_u/g' conftest.defines >conftest.undefs
-rm -f confdef2sed.sed
-
-# This sed command replaces #undef with comments.  This is necessary, for
-# example, in the case of _POSIX_SOURCE, which is predefined and required
-# on some systems where configure will not decide to define it.
-cat >>conftest.undefs <<\_ACEOF
-s,^[	 ]*#[	 ]*undef[	 ][	 ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */,
-_ACEOF
-
-# Break up conftest.defines because some shells have a limit on the size
-# of here documents, and old seds have small limits too (100 cmds).
-echo '  # Handle all the #define templates only if necessary.' >>$CONFIG_STATUS
-echo '  if grep "^[	 ]*#[	 ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS
-echo '  # If there are no defines, we may have an empty if/fi' >>$CONFIG_STATUS
-echo '  :' >>$CONFIG_STATUS
-rm -f conftest.tail
-while grep . conftest.defines >/dev/null
-do
-  # Write a limited-size here document to $tmp/defines.sed.
-  echo '  cat >$tmp/defines.sed <<CEOF' >>$CONFIG_STATUS
-  # Speed up: don't consider the non `#define' lines.
-  echo '/^[	 ]*#[	 ]*define/!b' >>$CONFIG_STATUS
-  # Work around the forget-to-reset-the-flag bug.
-  echo 't clr' >>$CONFIG_STATUS
-  echo ': clr' >>$CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.defines >>$CONFIG_STATUS
-  echo 'CEOF
-  sed -f $tmp/defines.sed $tmp/in >$tmp/out
-  rm -f $tmp/in
-  mv $tmp/out $tmp/in
-' >>$CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.defines >conftest.tail
-  rm -f conftest.defines
-  mv conftest.tail conftest.defines
-done
-rm -f conftest.defines
-echo '  fi # grep' >>$CONFIG_STATUS
-echo >>$CONFIG_STATUS
-
-# Break up conftest.undefs because some shells have a limit on the size
-# of here documents, and old seds have small limits too (100 cmds).
-echo '  # Handle all the #undef templates' >>$CONFIG_STATUS
-rm -f conftest.tail
-while grep . conftest.undefs >/dev/null
-do
-  # Write a limited-size here document to $tmp/undefs.sed.
-  echo '  cat >$tmp/undefs.sed <<CEOF' >>$CONFIG_STATUS
-  # Speed up: don't consider the non `#undef'
-  echo '/^[	 ]*#[	 ]*undef/!b' >>$CONFIG_STATUS
-  # Work around the forget-to-reset-the-flag bug.
-  echo 't clr' >>$CONFIG_STATUS
-  echo ': clr' >>$CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.undefs >>$CONFIG_STATUS
-  echo 'CEOF
-  sed -f $tmp/undefs.sed $tmp/in >$tmp/out
-  rm -f $tmp/in
-  mv $tmp/out $tmp/in
-' >>$CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.undefs >conftest.tail
-  rm -f conftest.undefs
-  mv conftest.tail conftest.undefs
-done
-rm -f conftest.undefs
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    echo "/* Generated by configure.  */" >$tmp/config.h
-  else
-    echo "/* $ac_file.  Generated by configure.  */" >$tmp/config.h
-  fi
-  cat $tmp/in >>$tmp/config.h
-  rm -f $tmp/in
-  if test x"$ac_file" != x-; then
-    if diff $ac_file $tmp/config.h >/dev/null 2>&1; then
-      { echo "$as_me:$LINENO: $ac_file is unchanged" >&5
-echo "$as_me: $ac_file is unchanged" >&6;}
-    else
-      ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_file" : 'X\(//\)[^/]' \| \
-	 X"$ac_file" : 'X\(//\)$' \| \
-	 X"$ac_file" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-      { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-      rm -f $ac_file
-      mv $tmp/config.h $ac_file
-    fi
-  else
-    cat $tmp/config.h
-    rm -f $tmp/config.h
-  fi
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_LINKS section.
-#
-
-for ac_file in : $CONFIG_LINKS; do test "x$ac_file" = x: && continue
-  ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
-  ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
-
-  { echo "$as_me:$LINENO: linking $srcdir/$ac_source to $ac_dest" >&5
-echo "$as_me: linking $srcdir/$ac_source to $ac_dest" >&6;}
-
-  if test ! -r $srcdir/$ac_source; then
-    { { echo "$as_me:$LINENO: error: $srcdir/$ac_source: file not found" >&5
-echo "$as_me: error: $srcdir/$ac_source: file not found" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  rm -f $ac_dest
-
-  # Make relative symlinks.
-  ac_dest_dir=`(dirname "$ac_dest") 2>/dev/null ||
-$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_dest" : 'X\(//\)[^/]' \| \
-	 X"$ac_dest" : 'X\(//\)$' \| \
-	 X"$ac_dest" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dest_dir"
-  else
-    as_dir="$ac_dest_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dest_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dest_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dest_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dest_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dest_dir";;
-*)
-  case "$ac_dest_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dest_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dest_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $srcdir in
-  [\\/$]* | ?:[\\/]* ) ac_rel_source=$srcdir/$ac_source ;;
-      *) ac_rel_source=$ac_top_builddir$srcdir/$ac_source ;;
-  esac
-
-  # Try a symlink, then a hard link, then a copy.
-  ln -s $ac_rel_source $ac_dest 2>/dev/null ||
-    ln $srcdir/$ac_source $ac_dest 2>/dev/null ||
-    cp -p $srcdir/$ac_source $ac_dest ||
-    { { echo "$as_me:$LINENO: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&5
-echo "$as_me: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&2;}
-   { (exit 1); exit 1; }; }
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_COMMANDS section.
-#
-for ac_file in : $CONFIG_COMMANDS; do test "x$ac_file" = x: && continue
-  ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
-  ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
-  ac_dir=`(dirname "$ac_dest") 2>/dev/null ||
-$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_dest" : 'X\(//\)[^/]' \| \
-	 X"$ac_dest" : 'X\(//\)$' \| \
-	 X"$ac_dest" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  { echo "$as_me:$LINENO: executing $ac_dest commands" >&5
-echo "$as_me: executing $ac_dest commands" >&6;}
-  case $ac_dest in
-    Makefile ) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
- rm -f Makesim1.tmp Makesim2.tmp Makefile
- sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
- sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
- sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
-	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
-	<Makefile.sim >Makefile
- rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
- ;;
-    stamp-h ) echo > stamp-h ;;
-  esac
-done
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-{ (exit 0); exit 0; }
-_ACEOF
-chmod +x $CONFIG_STATUS
-ac_clean_files=$ac_clean_files_save
-
-
-# configure is writing to config.log, and then calls config.status.
-# config.status does its own redirection, appending to config.log.
-# Unfortunately, on DOS this fails, as config.log is still kept open
-# by configure, so config.status won't be able to write to it; its
-# output is simply discarded.  So we exec the FD to /dev/null,
-# effectively closing config.log, so it can be properly (re)opened and
-# appended to by config.status.  When coming back to configure, we
-# need to make the FD available again.
-if test "$no_create" != yes; then
-  ac_cs_success=:
-  ac_config_status_args=
-  test "$silent" = yes &&
-    ac_config_status_args="$ac_config_status_args --quiet"
-  exec 5>/dev/null
-  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
-  exec 5>>config.log
-  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
-  # would make configure fail if this is the last instruction.
-  $ac_cs_success || { (exit 1); exit 1; }
-fi
-
-
diff --git a/sim/sh64/configure.ac b/sim/sh64/configure.ac
deleted file mode 100644
index 91102086eaf..00000000000
--- a/sim/sh64/configure.ac
+++ /dev/null
@@ -1,19 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-AC_PREREQ(2.59)dnl
-AC_INIT(Makefile.in)
-AC_CONFIG_HEADER(config.h:config.in)
-
-sinclude(../common/aclocal.m4)
-
-sinclude(../common/common.m4)
-
-SIM_AC_OPTION_ENDIAN([], BIG_ENDIAN)
-SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
-SIM_AC_OPTION_HOSTENDIAN
-SIM_AC_OPTION_SCACHE(16384)
-SIM_AC_OPTION_DEFAULT_MODEL(sh5)
-SIM_AC_OPTION_ENVIRONMENT
-SIM_AC_OPTION_INLINE()
-SIM_AC_OPTION_CGEN_MAINT
-
-SIM_AC_OUTPUT
diff --git a/sim/sh64/cpu.c b/sim/sh64/cpu.c
deleted file mode 100644
index bf3e2b2f7c3..00000000000
--- a/sim/sh64/cpu.c
+++ /dev/null
@@ -1,533 +0,0 @@
-/* Misc. support for CPU family sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "cgen-ops.h"
-
-/* Get the value of h-pc.  */
-
-UDI
-sh64_h_pc_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PC ();
-}
-
-/* Set a value for h-pc.  */
-
-void
-sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval)
-{
-  SET_H_PC (newval);
-}
-
-/* Get the value of h-gr.  */
-
-DI
-sh64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_GR (regno);
-}
-
-/* Set a value for h-gr.  */
-
-void
-sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_GR (regno, newval);
-}
-
-/* Get the value of h-grc.  */
-
-SI
-sh64_h_grc_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_GRC (regno);
-}
-
-/* Set a value for h-grc.  */
-
-void
-sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  SET_H_GRC (regno, newval);
-}
-
-/* Get the value of h-cr.  */
-
-DI
-sh64_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-sr.  */
-
-SI
-sh64_h_sr_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_sr);
-}
-
-/* Set a value for h-sr.  */
-
-void
-sh64_h_sr_set (SIM_CPU *current_cpu, SI newval)
-{
-  CPU (h_sr) = newval;
-}
-
-/* Get the value of h-fpscr.  */
-
-SI
-sh64_h_fpscr_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_fpscr);
-}
-
-/* Set a value for h-fpscr.  */
-
-void
-sh64_h_fpscr_set (SIM_CPU *current_cpu, SI newval)
-{
-  CPU (h_fpscr) = newval;
-}
-
-/* Get the value of h-frbit.  */
-
-BI
-sh64_h_frbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_FRBIT ();
-}
-
-/* Set a value for h-frbit.  */
-
-void
-sh64_h_frbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_FRBIT (newval);
-}
-
-/* Get the value of h-szbit.  */
-
-BI
-sh64_h_szbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_SZBIT ();
-}
-
-/* Set a value for h-szbit.  */
-
-void
-sh64_h_szbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_SZBIT (newval);
-}
-
-/* Get the value of h-prbit.  */
-
-BI
-sh64_h_prbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PRBIT ();
-}
-
-/* Set a value for h-prbit.  */
-
-void
-sh64_h_prbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_PRBIT (newval);
-}
-
-/* Get the value of h-sbit.  */
-
-BI
-sh64_h_sbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_SBIT ();
-}
-
-/* Set a value for h-sbit.  */
-
-void
-sh64_h_sbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_SBIT (newval);
-}
-
-/* Get the value of h-mbit.  */
-
-BI
-sh64_h_mbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_MBIT ();
-}
-
-/* Set a value for h-mbit.  */
-
-void
-sh64_h_mbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_MBIT (newval);
-}
-
-/* Get the value of h-qbit.  */
-
-BI
-sh64_h_qbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_QBIT ();
-}
-
-/* Set a value for h-qbit.  */
-
-void
-sh64_h_qbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_QBIT (newval);
-}
-
-/* Get the value of h-fr.  */
-
-SF
-sh64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_fr[regno]);
-}
-
-/* Set a value for h-fr.  */
-
-void
-sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  CPU (h_fr[regno]) = newval;
-}
-
-/* Get the value of h-fp.  */
-
-DF
-sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_fp[regno]);
-}
-
-/* Set a value for h-fp.  */
-
-void
-sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, DF newval)
-{
-  CPU (h_fp[regno]) = newval;
-}
-
-/* Get the value of h-fv.  */
-
-SF
-sh64_h_fv_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_FV (regno);
-}
-
-/* Set a value for h-fv.  */
-
-void
-sh64_h_fv_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  SET_H_FV (regno, newval);
-}
-
-/* Get the value of h-fmtx.  */
-
-SF
-sh64_h_fmtx_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_FMTX (regno);
-}
-
-/* Set a value for h-fmtx.  */
-
-void
-sh64_h_fmtx_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  SET_H_FMTX (regno, newval);
-}
-
-/* Get the value of h-dr.  */
-
-DF
-sh64_h_dr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_DR (regno);
-}
-
-/* Set a value for h-dr.  */
-
-void
-sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval)
-{
-  SET_H_DR (regno, newval);
-}
-
-/* Get the value of h-tr.  */
-
-DI
-sh64_h_tr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_tr[regno]);
-}
-
-/* Set a value for h-tr.  */
-
-void
-sh64_h_tr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  CPU (h_tr[regno]) = newval;
-}
-
-/* Get the value of h-endian.  */
-
-BI
-sh64_h_endian_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ENDIAN ();
-}
-
-/* Set a value for h-endian.  */
-
-void
-sh64_h_endian_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_ENDIAN (newval);
-}
-
-/* Get the value of h-ism.  */
-
-BI
-sh64_h_ism_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ISM ();
-}
-
-/* Set a value for h-ism.  */
-
-void
-sh64_h_ism_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_ISM (newval);
-}
-
-/* Get the value of h-frc.  */
-
-SF
-sh64_h_frc_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_FRC (regno);
-}
-
-/* Set a value for h-frc.  */
-
-void
-sh64_h_frc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  SET_H_FRC (regno, newval);
-}
-
-/* Get the value of h-drc.  */
-
-DF
-sh64_h_drc_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_DRC (regno);
-}
-
-/* Set a value for h-drc.  */
-
-void
-sh64_h_drc_set (SIM_CPU *current_cpu, UINT regno, DF newval)
-{
-  SET_H_DRC (regno, newval);
-}
-
-/* Get the value of h-xf.  */
-
-SF
-sh64_h_xf_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_XF (regno);
-}
-
-/* Set a value for h-xf.  */
-
-void
-sh64_h_xf_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  SET_H_XF (regno, newval);
-}
-
-/* Get the value of h-xd.  */
-
-DF
-sh64_h_xd_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_XD (regno);
-}
-
-/* Set a value for h-xd.  */
-
-void
-sh64_h_xd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
-{
-  SET_H_XD (regno, newval);
-}
-
-/* Get the value of h-fvc.  */
-
-SF
-sh64_h_fvc_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_FVC (regno);
-}
-
-/* Set a value for h-fvc.  */
-
-void
-sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
-{
-  SET_H_FVC (regno, newval);
-}
-
-/* Get the value of h-fpccr.  */
-
-SI
-sh64_h_fpccr_get (SIM_CPU *current_cpu)
-{
-  return GET_H_FPCCR ();
-}
-
-/* Set a value for h-fpccr.  */
-
-void
-sh64_h_fpccr_set (SIM_CPU *current_cpu, SI newval)
-{
-  SET_H_FPCCR (newval);
-}
-
-/* Get the value of h-gbr.  */
-
-SI
-sh64_h_gbr_get (SIM_CPU *current_cpu)
-{
-  return GET_H_GBR ();
-}
-
-/* Set a value for h-gbr.  */
-
-void
-sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval)
-{
-  SET_H_GBR (newval);
-}
-
-/* Get the value of h-pr.  */
-
-SI
-sh64_h_pr_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PR ();
-}
-
-/* Set a value for h-pr.  */
-
-void
-sh64_h_pr_set (SIM_CPU *current_cpu, SI newval)
-{
-  SET_H_PR (newval);
-}
-
-/* Get the value of h-macl.  */
-
-SI
-sh64_h_macl_get (SIM_CPU *current_cpu)
-{
-  return GET_H_MACL ();
-}
-
-/* Set a value for h-macl.  */
-
-void
-sh64_h_macl_set (SIM_CPU *current_cpu, SI newval)
-{
-  SET_H_MACL (newval);
-}
-
-/* Get the value of h-mach.  */
-
-SI
-sh64_h_mach_get (SIM_CPU *current_cpu)
-{
-  return GET_H_MACH ();
-}
-
-/* Set a value for h-mach.  */
-
-void
-sh64_h_mach_set (SIM_CPU *current_cpu, SI newval)
-{
-  SET_H_MACH (newval);
-}
-
-/* Get the value of h-tbit.  */
-
-BI
-sh64_h_tbit_get (SIM_CPU *current_cpu)
-{
-  return GET_H_TBIT ();
-}
-
-/* Set a value for h-tbit.  */
-
-void
-sh64_h_tbit_set (SIM_CPU *current_cpu, BI newval)
-{
-  SET_H_TBIT (newval);
-}
-
-/* Record trace results for INSN.  */
-
-void
-sh64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h
deleted file mode 100644
index 6e0d35880f9..00000000000
--- a/sim/sh64/cpu.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/* CPU family header for sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_SH64_H
-#define CPU_SH64_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 1
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 1
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* Program counter */
-  UDI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) \
-do { \
-{\
-CPU (h_ism) = ANDDI ((x), 1);\
-CPU (h_pc) = ANDDI ((x), INVDI (1));\
-}\
-;} while (0)
-  /* General purpose integer registers */
-  DI h_gr[64];
-#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
-#define SET_H_GR(index, x) \
-do { \
-if ((((index)) != (63))) {\
-CPU (h_gr[(index)]) = (x);\
-} else {\
-((void) 0); /*nop*/\
-}\
-;} while (0)
-  /* Control registers */
-  DI h_cr[64];
-#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
-#define SET_H_CR(index, x) \
-do { \
-if ((((index)) == (0))) {\
-CPU (h_sr) = (x);\
-} else {\
-CPU (h_cr[(index)]) = (x);\
-}\
-;} while (0)
-  /* Status register */
-  SI h_sr;
-#define GET_H_SR() CPU (h_sr)
-#define SET_H_SR(x) (CPU (h_sr) = (x))
-  /* Floating point status and control register */
-  SI h_fpscr;
-#define GET_H_FPSCR() CPU (h_fpscr)
-#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
-  /* Single precision floating point registers */
-  SF h_fr[64];
-#define GET_H_FR(a1) CPU (h_fr)[a1]
-#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
-  /* Single precision floating point register pairs */
-  DF h_fp[32];
-#define GET_H_FP(a1) CPU (h_fp)[a1]
-#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
-  /* Branch target registers */
-  DI h_tr[8];
-#define GET_H_TR(a1) CPU (h_tr)[a1]
-#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
-  /* Current instruction set mode */
-  BI h_ism;
-#define GET_H_ISM() CPU (h_ism)
-#define SET_H_ISM(x) \
-do { \
-cgen_rtx_error (current_cpu, "cannot set ism directly");\
-;} while (0)
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} SH64_CPU_DATA;
-
-/* Virtual regs.  */
-
-#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
-#define SET_H_GRC(index, x) \
-do { \
-CPU (h_gr[(index)]) = EXTSIDI ((x));\
-;} while (0)
-#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
-#define SET_H_FRBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
-;} while (0)
-#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
-#define SET_H_SZBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
-;} while (0)
-#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
-#define SET_H_PRBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
-;} while (0)
-#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
-#define SET_H_SBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
-;} while (0)
-#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
-#define SET_H_MBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
-;} while (0)
-#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
-#define SET_H_QBIT(x) \
-do { \
-CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
-;} while (0)
-#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
-#define SET_H_FV(index, x) \
-do { \
-CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
-;} while (0)
-#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
-#define SET_H_FMTX(index, x) \
-do { \
-CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
-;} while (0)
-#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
-#define SET_H_DR(index, x) \
-do { \
-{\
-CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
-CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
-}\
-;} while (0)
-#define GET_H_ENDIAN() sh64_endian (current_cpu)
-#define SET_H_ENDIAN(x) \
-do { \
-cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
-;} while (0)
-#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
-#define SET_H_FRC(index, x) \
-do { \
-CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
-;} while (0)
-#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
-#define SET_H_DRC(index, x) \
-do { \
-SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
-;} while (0)
-#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
-#define SET_H_XF(index, x) \
-do { \
-CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
-;} while (0)
-#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
-#define SET_H_XD(index, x) \
-do { \
-SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
-;} while (0)
-#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
-#define SET_H_FVC(index, x) \
-do { \
-CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
-;} while (0)
-#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
-#define SET_H_FPCCR(x) \
-do { \
-{\
-CPU (h_fpscr) = (x);\
-SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
-SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
-SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
-}\
-;} while (0)
-#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
-#define SET_H_GBR(x) \
-do { \
-CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
-;} while (0)
-#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
-#define SET_H_PR(x) \
-do { \
-CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
-;} while (0)
-#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
-#define SET_H_MACL(x) \
-do { \
-CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
-;} while (0)
-#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
-#define SET_H_MACH(x) \
-do { \
-CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
-;} while (0)
-#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
-#define SET_H_TBIT(x) \
-do { \
-CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
-;} while (0)
-
-/* Cover fns for register access.  */
-UDI sh64_h_pc_get (SIM_CPU *);
-void sh64_h_pc_set (SIM_CPU *, UDI);
-DI sh64_h_gr_get (SIM_CPU *, UINT);
-void sh64_h_gr_set (SIM_CPU *, UINT, DI);
-SI sh64_h_grc_get (SIM_CPU *, UINT);
-void sh64_h_grc_set (SIM_CPU *, UINT, SI);
-DI sh64_h_cr_get (SIM_CPU *, UINT);
-void sh64_h_cr_set (SIM_CPU *, UINT, DI);
-SI sh64_h_sr_get (SIM_CPU *);
-void sh64_h_sr_set (SIM_CPU *, SI);
-SI sh64_h_fpscr_get (SIM_CPU *);
-void sh64_h_fpscr_set (SIM_CPU *, SI);
-BI sh64_h_frbit_get (SIM_CPU *);
-void sh64_h_frbit_set (SIM_CPU *, BI);
-BI sh64_h_szbit_get (SIM_CPU *);
-void sh64_h_szbit_set (SIM_CPU *, BI);
-BI sh64_h_prbit_get (SIM_CPU *);
-void sh64_h_prbit_set (SIM_CPU *, BI);
-BI sh64_h_sbit_get (SIM_CPU *);
-void sh64_h_sbit_set (SIM_CPU *, BI);
-BI sh64_h_mbit_get (SIM_CPU *);
-void sh64_h_mbit_set (SIM_CPU *, BI);
-BI sh64_h_qbit_get (SIM_CPU *);
-void sh64_h_qbit_set (SIM_CPU *, BI);
-SF sh64_h_fr_get (SIM_CPU *, UINT);
-void sh64_h_fr_set (SIM_CPU *, UINT, SF);
-DF sh64_h_fp_get (SIM_CPU *, UINT);
-void sh64_h_fp_set (SIM_CPU *, UINT, DF);
-SF sh64_h_fv_get (SIM_CPU *, UINT);
-void sh64_h_fv_set (SIM_CPU *, UINT, SF);
-SF sh64_h_fmtx_get (SIM_CPU *, UINT);
-void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
-DF sh64_h_dr_get (SIM_CPU *, UINT);
-void sh64_h_dr_set (SIM_CPU *, UINT, DF);
-DI sh64_h_tr_get (SIM_CPU *, UINT);
-void sh64_h_tr_set (SIM_CPU *, UINT, DI);
-BI sh64_h_endian_get (SIM_CPU *);
-void sh64_h_endian_set (SIM_CPU *, BI);
-BI sh64_h_ism_get (SIM_CPU *);
-void sh64_h_ism_set (SIM_CPU *, BI);
-SF sh64_h_frc_get (SIM_CPU *, UINT);
-void sh64_h_frc_set (SIM_CPU *, UINT, SF);
-DF sh64_h_drc_get (SIM_CPU *, UINT);
-void sh64_h_drc_set (SIM_CPU *, UINT, DF);
-SF sh64_h_xf_get (SIM_CPU *, UINT);
-void sh64_h_xf_set (SIM_CPU *, UINT, SF);
-DF sh64_h_xd_get (SIM_CPU *, UINT);
-void sh64_h_xd_set (SIM_CPU *, UINT, DF);
-SF sh64_h_fvc_get (SIM_CPU *, UINT);
-void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
-SI sh64_h_fpccr_get (SIM_CPU *);
-void sh64_h_fpccr_set (SIM_CPU *, SI);
-SI sh64_h_gbr_get (SIM_CPU *);
-void sh64_h_gbr_set (SIM_CPU *, SI);
-SI sh64_h_pr_get (SIM_CPU *);
-void sh64_h_pr_set (SIM_CPU *, SI);
-SI sh64_h_macl_get (SIM_CPU *);
-void sh64_h_macl_set (SIM_CPU *, SI);
-SI sh64_h_mach_get (SIM_CPU *);
-void sh64_h_mach_set (SIM_CPU *, SI);
-BI sh64_h_tbit_get (SIM_CPU *);
-void sh64_h_tbit_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN sh64_fetch_register;
-extern CPUREG_STORE_FN sh64_store_register;
-
-typedef struct {
-  int empty;
-} MODEL_SH5_DATA;
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_SH64_H */
diff --git a/sim/sh64/cpuall.h b/sim/sh64/cpuall.h
deleted file mode 100644
index ba6a1e5d714..00000000000
--- a/sim/sh64/cpuall.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Simulator CPU header for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH_CPUALL_H
-#define SH_CPUALL_H
-
-/* Include files for each cpu family.  */
-
-#ifdef WANT_CPU_SH64
-#include "eng.h"
-#include "cgen-engine.h"
-#include "cpu.h"
-#include "decode.h"
-#endif
-
-extern const MACH sh2_mach;
-extern const MACH sh3_mach;
-extern const MACH sh3e_mach;
-extern const MACH sh4_mach;
-extern const MACH sh5_mach;
-
-#ifndef WANT_CPU
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-};
-#endif
-
-#ifndef WANT_CPU
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-#endif
-
-#endif /* SH_CPUALL_H */
diff --git a/sim/sh64/decode-compact.c b/sim/sh64/decode-compact.c
deleted file mode 100644
index ce85438323c..00000000000
--- a/sim/sh64/decode-compact.c
+++ /dev/null
@@ -1,2640 +0,0 @@
-/* Simulator instruction decoder for sh64_compact.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN_MAX];
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem sh64_compact_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, SH64_COMPACT_INSN_X_AFTER, SH64_COMPACT_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, SH64_COMPACT_INSN_X_BEFORE, SH64_COMPACT_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, SH64_COMPACT_INSN_X_CTI_CHAIN, SH64_COMPACT_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, SH64_COMPACT_INSN_X_CHAIN, SH64_COMPACT_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, SH64_COMPACT_INSN_X_BEGIN, SH64_COMPACT_SFMT_EMPTY },
-  { SH_INSN_ADD_COMPACT, SH64_COMPACT_INSN_ADD_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
-  { SH_INSN_ADDI_COMPACT, SH64_COMPACT_INSN_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT },
-  { SH_INSN_ADDC_COMPACT, SH64_COMPACT_INSN_ADDC_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT },
-  { SH_INSN_ADDV_COMPACT, SH64_COMPACT_INSN_ADDV_COMPACT, SH64_COMPACT_SFMT_ADDV_COMPACT },
-  { SH_INSN_AND_COMPACT, SH64_COMPACT_INSN_AND_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
-  { SH_INSN_ANDI_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT },
-  { SH_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
-  { SH_INSN_BF_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
-  { SH_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
-  { SH_INSN_BRA_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT },
-  { SH_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT },
-  { SH_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT },
-  { SH_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT },
-  { SH_INSN_BSRF_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT },
-  { SH_INSN_BT_COMPACT, SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
-  { SH_INSN_BTS_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
-  { SH_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT },
-  { SH_INSN_CLRS_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT },
-  { SH_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT },
-  { SH_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT },
-  { SH_INSN_CMPGE_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_CMPPL_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT },
-  { SH_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT },
-  { SH_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT },
-  { SH_INSN_DIV0U_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT },
-  { SH_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT },
-  { SH_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT },
-  { SH_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT },
-  { SH_INSN_DT_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_EXTUW_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
-  { SH_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
-  { SH_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT },
-  { SH_INSN_FCMPGT_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT },
-  { SH_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT },
-  { SH_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT },
-  { SH_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
-  { SH_INSN_FIPR_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT },
-  { SH_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDS_COMPACT },
-  { SH_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT },
-  { SH_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT },
-  { SH_INSN_FLOAT_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT },
-  { SH_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT },
-  { SH_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV1_COMPACT },
-  { SH_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT },
-  { SH_INSN_FMOV3_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT },
-  { SH_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT },
-  { SH_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT },
-  { SH_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT },
-  { SH_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT },
-  { SH_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
-  { SH_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
-  { SH_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT },
-  { SH_INSN_FSCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSCHG_COMPACT },
-  { SH_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
-  { SH_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT },
-  { SH_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
-  { SH_INSN_FTRC_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT },
-  { SH_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT },
-  { SH_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_SFMT_JMP_COMPACT },
-  { SH_INSN_JSR_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT },
-  { SH_INSN_LDC_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT },
-  { SH_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT },
-  { SH_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT },
-  { SH_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT },
-  { SH_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT },
-  { SH_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT },
-  { SH_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT },
-  { SH_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT },
-  { SH_INSN_LDS_MACL_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT },
-  { SH_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT },
-  { SH_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT },
-  { SH_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_LDSL_PR_COMPACT },
-  { SH_INSN_MACL_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT },
-  { SH_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT },
-  { SH_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT },
-  { SH_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT },
-  { SH_INSN_MOVB1_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
-  { SH_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
-  { SH_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
-  { SH_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB4_COMPACT },
-  { SH_INSN_MOVB5_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT },
-  { SH_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
-  { SH_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT },
-  { SH_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
-  { SH_INSN_MOVB9_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT },
-  { SH_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT },
-  { SH_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
-  { SH_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
-  { SH_INSN_MOVL3_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
-  { SH_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT },
-  { SH_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT },
-  { SH_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
-  { SH_INSN_MOVL7_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT },
-  { SH_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
-  { SH_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT },
-  { SH_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT },
-  { SH_INSN_MOVL11_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL11_COMPACT },
-  { SH_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
-  { SH_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
-  { SH_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
-  { SH_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT },
-  { SH_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT },
-  { SH_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
-  { SH_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT },
-  { SH_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
-  { SH_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT },
-  { SH_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW10_COMPACT },
-  { SH_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT },
-  { SH_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT },
-  { SH_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT },
-  { SH_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT },
-  { SH_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
-  { SH_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
-  { SH_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
-  { SH_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT },
-  { SH_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
-  { SH_INSN_NOT_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT },
-  { SH_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
-  { SH_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
-  { SH_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
-  { SH_INSN_OR_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
-  { SH_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT },
-  { SH_INSN_ORB_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
-  { SH_INSN_PREF_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
-  { SH_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT },
-  { SH_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT },
-  { SH_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_ROTR_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_RTS_COMPACT, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT },
-  { SH_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT },
-  { SH_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT },
-  { SH_INSN_SHAD_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT },
-  { SH_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT },
-  { SH_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
-  { SH_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
-  { SH_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT },
-  { SH_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT },
-  { SH_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT },
-  { SH_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT },
-  { SH_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT },
-  { SH_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT },
-  { SH_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT },
-  { SH_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT },
-  { SH_INSN_STS_MACL_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STS_MACL_COMPACT },
-  { SH_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT },
-  { SH_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT },
-  { SH_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT },
-  { SH_INSN_SUB_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
-  { SH_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT },
-  { SH_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_SFMT_ADDV_COMPACT },
-  { SH_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_SWAPW_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
-  { SH_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_SFMT_TASB_COMPACT },
-  { SH_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT },
-  { SH_INSN_TST_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
-  { SH_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT },
-  { SH_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT },
-  { SH_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
-  { SH_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_SFMT_XORI_COMPACT },
-  { SH_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
-  { SH_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
-};
-
-static const struct insn_sem sh64_compact_insn_sem_invalid = {
-  VIRTUAL_INSN_X_INVALID, SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_SFMT_EMPTY
-};
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
-
-  id->num = t->index;
-  id->sfmt = t->sfmt;
-  if ((int) t->type <= 0)
-    id->idata = & cgen_virtual_insn_table[- (int) t->type];
-  else
-    id->idata = & insn_table[t->type];
-  id->attrs = CGEN_INSN_ATTRS (id->idata);
-  /* Oh my god, a magic number.  */
-  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-
-  /* Semantic pointers are initialized elsewhere.  */
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-sh64_compact_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = SH64_COMPACT_INSN_MAX;
-  IDESC *table = sh64_compact_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & sh64_compact_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = sh64_compact_insn_sem, tend = t + sizeof (sh64_compact_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder.  */
-  SH64_COMPACT_INSN_TYPE itype;
-
-  {
-    CGEN_INSN_INT insn = base_insn;
-
-    {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 0) & (15 << 0)));
-      switch (val)
-      {
-      case 2 : itype = SH64_COMPACT_INSN_STC_GBR_COMPACT; goto extract_sfmt_stc_gbr_compact;      case 3 :
-        {
-          unsigned int val = (((insn >> 4) & (15 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_BSRF_COMPACT; goto extract_sfmt_bsrf_compact;          case 2 : itype = SH64_COMPACT_INSN_BRAF_COMPACT; goto extract_sfmt_braf_compact;          case 8 : itype = SH64_COMPACT_INSN_PREF_COMPACT; goto extract_sfmt_nop_compact;          case 9 : itype = SH64_COMPACT_INSN_OCBI_COMPACT; goto extract_sfmt_nop_compact;          case 10 : itype = SH64_COMPACT_INSN_OCBP_COMPACT; goto extract_sfmt_nop_compact;          case 11 : itype = SH64_COMPACT_INSN_OCBWB_COMPACT; goto extract_sfmt_nop_compact;          case 12 : itype = SH64_COMPACT_INSN_MOVCAL_COMPACT; goto extract_sfmt_movcal_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 4 : itype = SH64_COMPACT_INSN_MOVB3_COMPACT; goto extract_sfmt_movb3_compact;      case 5 : itype = SH64_COMPACT_INSN_MOVW3_COMPACT; goto extract_sfmt_movb3_compact;      case 6 : itype = SH64_COMPACT_INSN_MOVL3_COMPACT; goto extract_sfmt_movb3_compact;      case 7 : itype = SH64_COMPACT_INSN_MULL_COMPACT; goto extract_sfmt_mull_compact;      case 8 :
-        {
-          unsigned int val = (((insn >> 4) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_CLRT_COMPACT; goto extract_sfmt_clrt_compact;          case 1 : itype = SH64_COMPACT_INSN_SETT_COMPACT; goto extract_sfmt_clrt_compact;          case 2 : itype = SH64_COMPACT_INSN_CLRMAC_COMPACT; goto extract_sfmt_clrmac_compact;          case 4 : itype = SH64_COMPACT_INSN_CLRS_COMPACT; goto extract_sfmt_clrs_compact;          case 5 : itype = SH64_COMPACT_INSN_SETS_COMPACT; goto extract_sfmt_clrs_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 9 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_NOP_COMPACT; goto extract_sfmt_nop_compact;          case 1 : itype = SH64_COMPACT_INSN_DIV0U_COMPACT; goto extract_sfmt_div0u_compact;          case 2 : itype = SH64_COMPACT_INSN_MOVT_COMPACT; goto extract_sfmt_movt_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 10 :
-        {
-          unsigned int val = (((insn >> 4) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_STS_MACH_COMPACT; goto extract_sfmt_sts_mach_compact;          case 1 : itype = SH64_COMPACT_INSN_STS_MACL_COMPACT; goto extract_sfmt_sts_macl_compact;          case 2 : itype = SH64_COMPACT_INSN_STS_PR_COMPACT; goto extract_sfmt_sts_pr_compact;          case 5 : itype = SH64_COMPACT_INSN_STS_FPUL_COMPACT; goto extract_sfmt_sts_fpul_compact;          case 6 : itype = SH64_COMPACT_INSN_STS_FPSCR_COMPACT; goto extract_sfmt_sts_fpscr_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 11 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_RTS_COMPACT; goto extract_sfmt_rts_compact;          case 3 : itype = SH64_COMPACT_INSN_BRK_COMPACT; goto extract_sfmt_brk_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 12 : itype = SH64_COMPACT_INSN_MOVB8_COMPACT; goto extract_sfmt_movb8_compact;      case 13 : itype = SH64_COMPACT_INSN_MOVW8_COMPACT; goto extract_sfmt_movb8_compact;      case 14 : itype = SH64_COMPACT_INSN_MOVL8_COMPACT; goto extract_sfmt_movb8_compact;      case 15 : itype = SH64_COMPACT_INSN_MACL_COMPACT; goto extract_sfmt_macl_compact;      case 16 : /* fall through */
-      case 17 : /* fall through */
-      case 18 : /* fall through */
-      case 19 : /* fall through */
-      case 20 : /* fall through */
-      case 21 : /* fall through */
-      case 22 : /* fall through */
-      case 23 : /* fall through */
-      case 24 : /* fall through */
-      case 25 : /* fall through */
-      case 26 : /* fall through */
-      case 27 : /* fall through */
-      case 28 : /* fall through */
-      case 29 : /* fall through */
-      case 30 : /* fall through */
-      case 31 : itype = SH64_COMPACT_INSN_MOVL5_COMPACT; goto extract_sfmt_movl5_compact;      case 32 : itype = SH64_COMPACT_INSN_MOVB1_COMPACT; goto extract_sfmt_movb1_compact;      case 33 : itype = SH64_COMPACT_INSN_MOVW1_COMPACT; goto extract_sfmt_movb1_compact;      case 34 : itype = SH64_COMPACT_INSN_MOVL1_COMPACT; goto extract_sfmt_movb1_compact;      case 36 : itype = SH64_COMPACT_INSN_MOVB2_COMPACT; goto extract_sfmt_movb2_compact;      case 37 : itype = SH64_COMPACT_INSN_MOVW2_COMPACT; goto extract_sfmt_movb2_compact;      case 38 : itype = SH64_COMPACT_INSN_MOVL2_COMPACT; goto extract_sfmt_movb2_compact;      case 39 : itype = SH64_COMPACT_INSN_DIV0S_COMPACT; goto extract_sfmt_div0s_compact;      case 40 : itype = SH64_COMPACT_INSN_TST_COMPACT; goto extract_sfmt_cmpeq_compact;      case 41 : itype = SH64_COMPACT_INSN_AND_COMPACT; goto extract_sfmt_and_compact;      case 42 : itype = SH64_COMPACT_INSN_XOR_COMPACT; goto extract_sfmt_and_compact;      case 43 : itype = SH64_COMPACT_INSN_OR_COMPACT; goto extract_sfmt_and_compact;      case 44 : itype = SH64_COMPACT_INSN_CMPSTR_COMPACT; goto extract_sfmt_cmpeq_compact;      case 45 : itype = SH64_COMPACT_INSN_XTRCT_COMPACT; goto extract_sfmt_add_compact;      case 46 : itype = SH64_COMPACT_INSN_MULUW_COMPACT; goto extract_sfmt_mull_compact;      case 47 : itype = SH64_COMPACT_INSN_MULSW_COMPACT; goto extract_sfmt_mull_compact;      case 48 : itype = SH64_COMPACT_INSN_CMPEQ_COMPACT; goto extract_sfmt_cmpeq_compact;      case 50 : itype = SH64_COMPACT_INSN_CMPHS_COMPACT; goto extract_sfmt_cmpeq_compact;      case 51 : itype = SH64_COMPACT_INSN_CMPGE_COMPACT; goto extract_sfmt_cmpeq_compact;      case 52 : itype = SH64_COMPACT_INSN_DIV1_COMPACT; goto extract_sfmt_div1_compact;      case 53 : itype = SH64_COMPACT_INSN_DMULUL_COMPACT; goto extract_sfmt_dmulsl_compact;      case 54 : itype = SH64_COMPACT_INSN_CMPHI_COMPACT; goto extract_sfmt_cmpeq_compact;      case 55 : itype = SH64_COMPACT_INSN_CMPGT_COMPACT; goto extract_sfmt_cmpeq_compact;      case 56 : itype = SH64_COMPACT_INSN_SUB_COMPACT; goto extract_sfmt_add_compact;      case 58 : itype = SH64_COMPACT_INSN_SUBC_COMPACT; goto extract_sfmt_addc_compact;      case 59 : itype = SH64_COMPACT_INSN_SUBV_COMPACT; goto extract_sfmt_addv_compact;      case 60 : itype = SH64_COMPACT_INSN_ADD_COMPACT; goto extract_sfmt_add_compact;      case 61 : itype = SH64_COMPACT_INSN_DMULSL_COMPACT; goto extract_sfmt_dmulsl_compact;      case 62 : itype = SH64_COMPACT_INSN_ADDC_COMPACT; goto extract_sfmt_addc_compact;      case 63 : itype = SH64_COMPACT_INSN_ADDV_COMPACT; goto extract_sfmt_addv_compact;      case 64 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_SHLL_COMPACT; goto extract_sfmt_dt_compact;          case 1 : itype = SH64_COMPACT_INSN_DT_COMPACT; goto extract_sfmt_dt_compact;          case 2 : itype = SH64_COMPACT_INSN_SHAL_COMPACT; goto extract_sfmt_dt_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 65 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_SHLR_COMPACT; goto extract_sfmt_dt_compact;          case 1 : itype = SH64_COMPACT_INSN_CMPPZ_COMPACT; goto extract_sfmt_cmppl_compact;          case 2 : itype = SH64_COMPACT_INSN_SHAR_COMPACT; goto extract_sfmt_dt_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 66 :
-        {
-          unsigned int val = (((insn >> 4) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_STSL_MACH_COMPACT; goto extract_sfmt_stsl_mach_compact;          case 1 : itype = SH64_COMPACT_INSN_STSL_MACL_COMPACT; goto extract_sfmt_stsl_macl_compact;          case 2 : itype = SH64_COMPACT_INSN_STSL_PR_COMPACT; goto extract_sfmt_stsl_pr_compact;          case 5 : itype = SH64_COMPACT_INSN_STSL_FPUL_COMPACT; goto extract_sfmt_stsl_fpul_compact;          case 6 : itype = SH64_COMPACT_INSN_STSL_FPSCR_COMPACT; goto extract_sfmt_stsl_fpscr_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 67 : itype = SH64_COMPACT_INSN_STCL_GBR_COMPACT; goto extract_sfmt_stcl_gbr_compact;      case 68 :
-        {
-          unsigned int val = (((insn >> 5) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_ROTL_COMPACT; goto extract_sfmt_dt_compact;          case 1 : itype = SH64_COMPACT_INSN_ROTCL_COMPACT; goto extract_sfmt_rotcl_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 69 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_ROTR_COMPACT; goto extract_sfmt_dt_compact;          case 1 : itype = SH64_COMPACT_INSN_CMPPL_COMPACT; goto extract_sfmt_cmppl_compact;          case 2 : itype = SH64_COMPACT_INSN_ROTCR_COMPACT; goto extract_sfmt_rotcl_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 70 :
-        {
-          unsigned int val = (((insn >> 4) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_LDSL_MACH_COMPACT; goto extract_sfmt_ldsl_mach_compact;          case 1 : itype = SH64_COMPACT_INSN_LDSL_MACL_COMPACT; goto extract_sfmt_ldsl_macl_compact;          case 2 : itype = SH64_COMPACT_INSN_LDSL_PR_COMPACT; goto extract_sfmt_ldsl_pr_compact;          case 5 : itype = SH64_COMPACT_INSN_LDSL_FPUL_COMPACT; goto extract_sfmt_ldsl_fpul_compact;          case 6 : itype = SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT; goto extract_sfmt_ldsl_fpscr_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 71 : itype = SH64_COMPACT_INSN_LDCL_COMPACT; goto extract_sfmt_ldcl_compact;      case 72 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_SHLL2_COMPACT; goto extract_sfmt_shll2_compact;          case 1 : itype = SH64_COMPACT_INSN_SHLL8_COMPACT; goto extract_sfmt_shll2_compact;          case 2 : itype = SH64_COMPACT_INSN_SHLL16_COMPACT; goto extract_sfmt_shll2_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 73 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_SHLR2_COMPACT; goto extract_sfmt_shll2_compact;          case 1 : itype = SH64_COMPACT_INSN_SHLR8_COMPACT; goto extract_sfmt_shll2_compact;          case 2 : itype = SH64_COMPACT_INSN_SHLR16_COMPACT; goto extract_sfmt_shll2_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 74 :
-        {
-          unsigned int val = (((insn >> 4) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_LDS_MACH_COMPACT; goto extract_sfmt_lds_mach_compact;          case 1 : itype = SH64_COMPACT_INSN_LDS_MACL_COMPACT; goto extract_sfmt_lds_macl_compact;          case 2 : itype = SH64_COMPACT_INSN_LDS_PR_COMPACT; goto extract_sfmt_lds_pr_compact;          case 5 : itype = SH64_COMPACT_INSN_LDS_FPUL_COMPACT; goto extract_sfmt_lds_fpul_compact;          case 6 : itype = SH64_COMPACT_INSN_LDS_FPSCR_COMPACT; goto extract_sfmt_lds_fpscr_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 75 :
-        {
-          unsigned int val = (((insn >> 4) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_JSR_COMPACT; goto extract_sfmt_bsrf_compact;          case 1 : itype = SH64_COMPACT_INSN_TASB_COMPACT; goto extract_sfmt_tasb_compact;          case 2 : itype = SH64_COMPACT_INSN_JMP_COMPACT; goto extract_sfmt_jmp_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 76 : itype = SH64_COMPACT_INSN_SHAD_COMPACT; goto extract_sfmt_shad_compact;      case 77 : itype = SH64_COMPACT_INSN_SHLD_COMPACT; goto extract_sfmt_shad_compact;      case 78 : itype = SH64_COMPACT_INSN_LDC_COMPACT; goto extract_sfmt_ldc_compact;      case 79 : itype = SH64_COMPACT_INSN_MACW_COMPACT; goto extract_sfmt_macw_compact;      case 80 : /* fall through */
-      case 81 : /* fall through */
-      case 82 : /* fall through */
-      case 83 : /* fall through */
-      case 84 : /* fall through */
-      case 85 : /* fall through */
-      case 86 : /* fall through */
-      case 87 : /* fall through */
-      case 88 : /* fall through */
-      case 89 : /* fall through */
-      case 90 : /* fall through */
-      case 91 : /* fall through */
-      case 92 : /* fall through */
-      case 93 : /* fall through */
-      case 94 : /* fall through */
-      case 95 : itype = SH64_COMPACT_INSN_MOVL11_COMPACT; goto extract_sfmt_movl11_compact;      case 96 : itype = SH64_COMPACT_INSN_MOVB6_COMPACT; goto extract_sfmt_movb6_compact;      case 97 : itype = SH64_COMPACT_INSN_MOVW6_COMPACT; goto extract_sfmt_movb6_compact;      case 98 : itype = SH64_COMPACT_INSN_MOVL6_COMPACT; goto extract_sfmt_movb6_compact;      case 99 : itype = SH64_COMPACT_INSN_MOV_COMPACT; goto extract_sfmt_mov_compact;      case 100 : itype = SH64_COMPACT_INSN_MOVB7_COMPACT; goto extract_sfmt_movb7_compact;      case 101 : itype = SH64_COMPACT_INSN_MOVW7_COMPACT; goto extract_sfmt_movb7_compact;      case 102 : itype = SH64_COMPACT_INSN_MOVL7_COMPACT; goto extract_sfmt_movl7_compact;      case 103 : itype = SH64_COMPACT_INSN_NOT_COMPACT; goto extract_sfmt_mov_compact;      case 104 : itype = SH64_COMPACT_INSN_SWAPB_COMPACT; goto extract_sfmt_extsb_compact;      case 105 : itype = SH64_COMPACT_INSN_SWAPW_COMPACT; goto extract_sfmt_extsb_compact;      case 106 : itype = SH64_COMPACT_INSN_NEGC_COMPACT; goto extract_sfmt_negc_compact;      case 107 : itype = SH64_COMPACT_INSN_NEG_COMPACT; goto extract_sfmt_extsb_compact;      case 108 : itype = SH64_COMPACT_INSN_EXTUB_COMPACT; goto extract_sfmt_extsb_compact;      case 109 : itype = SH64_COMPACT_INSN_EXTUW_COMPACT; goto extract_sfmt_extsb_compact;      case 110 : itype = SH64_COMPACT_INSN_EXTSB_COMPACT; goto extract_sfmt_extsb_compact;      case 111 : itype = SH64_COMPACT_INSN_EXTSW_COMPACT; goto extract_sfmt_extsb_compact;      case 112 : /* fall through */
-      case 113 : /* fall through */
-      case 114 : /* fall through */
-      case 115 : /* fall through */
-      case 116 : /* fall through */
-      case 117 : /* fall through */
-      case 118 : /* fall through */
-      case 119 : /* fall through */
-      case 120 : /* fall through */
-      case 121 : /* fall through */
-      case 122 : /* fall through */
-      case 123 : /* fall through */
-      case 124 : /* fall through */
-      case 125 : /* fall through */
-      case 126 : /* fall through */
-      case 127 : itype = SH64_COMPACT_INSN_ADDI_COMPACT; goto extract_sfmt_addi_compact;      case 128 : /* fall through */
-      case 129 : /* fall through */
-      case 130 : /* fall through */
-      case 131 : /* fall through */
-      case 132 : /* fall through */
-      case 133 : /* fall through */
-      case 134 : /* fall through */
-      case 135 : /* fall through */
-      case 136 : /* fall through */
-      case 137 : /* fall through */
-      case 138 : /* fall through */
-      case 139 : /* fall through */
-      case 140 : /* fall through */
-      case 141 : /* fall through */
-      case 142 : /* fall through */
-      case 143 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_MOVB5_COMPACT; goto extract_sfmt_movb5_compact;          case 1 : itype = SH64_COMPACT_INSN_MOVW5_COMPACT; goto extract_sfmt_movw5_compact;          case 4 : itype = SH64_COMPACT_INSN_MOVB10_COMPACT; goto extract_sfmt_movb10_compact;          case 5 : itype = SH64_COMPACT_INSN_MOVW11_COMPACT; goto extract_sfmt_movw11_compact;          case 8 : itype = SH64_COMPACT_INSN_CMPEQI_COMPACT; goto extract_sfmt_cmpeqi_compact;          case 9 : itype = SH64_COMPACT_INSN_BT_COMPACT; goto extract_sfmt_bf_compact;          case 11 : itype = SH64_COMPACT_INSN_BF_COMPACT; goto extract_sfmt_bf_compact;          case 13 : itype = SH64_COMPACT_INSN_BTS_COMPACT; goto extract_sfmt_bf_compact;          case 15 : itype = SH64_COMPACT_INSN_BFS_COMPACT; goto extract_sfmt_bf_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 144 : /* fall through */
-      case 145 : /* fall through */
-      case 146 : /* fall through */
-      case 147 : /* fall through */
-      case 148 : /* fall through */
-      case 149 : /* fall through */
-      case 150 : /* fall through */
-      case 151 : /* fall through */
-      case 152 : /* fall through */
-      case 153 : /* fall through */
-      case 154 : /* fall through */
-      case 155 : /* fall through */
-      case 156 : /* fall through */
-      case 157 : /* fall through */
-      case 158 : /* fall through */
-      case 159 : itype = SH64_COMPACT_INSN_MOVW10_COMPACT; goto extract_sfmt_movw10_compact;      case 160 : /* fall through */
-      case 161 : /* fall through */
-      case 162 : /* fall through */
-      case 163 : /* fall through */
-      case 164 : /* fall through */
-      case 165 : /* fall through */
-      case 166 : /* fall through */
-      case 167 : /* fall through */
-      case 168 : /* fall through */
-      case 169 : /* fall through */
-      case 170 : /* fall through */
-      case 171 : /* fall through */
-      case 172 : /* fall through */
-      case 173 : /* fall through */
-      case 174 : /* fall through */
-      case 175 : itype = SH64_COMPACT_INSN_BRA_COMPACT; goto extract_sfmt_bra_compact;      case 176 : /* fall through */
-      case 177 : /* fall through */
-      case 178 : /* fall through */
-      case 179 : /* fall through */
-      case 180 : /* fall through */
-      case 181 : /* fall through */
-      case 182 : /* fall through */
-      case 183 : /* fall through */
-      case 184 : /* fall through */
-      case 185 : /* fall through */
-      case 186 : /* fall through */
-      case 187 : /* fall through */
-      case 188 : /* fall through */
-      case 189 : /* fall through */
-      case 190 : /* fall through */
-      case 191 : itype = SH64_COMPACT_INSN_BSR_COMPACT; goto extract_sfmt_bsr_compact;      case 192 : /* fall through */
-      case 193 : /* fall through */
-      case 194 : /* fall through */
-      case 195 : /* fall through */
-      case 196 : /* fall through */
-      case 197 : /* fall through */
-      case 198 : /* fall through */
-      case 199 : /* fall through */
-      case 200 : /* fall through */
-      case 201 : /* fall through */
-      case 202 : /* fall through */
-      case 203 : /* fall through */
-      case 204 : /* fall through */
-      case 205 : /* fall through */
-      case 206 : /* fall through */
-      case 207 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_MOVB4_COMPACT; goto extract_sfmt_movb4_compact;          case 1 : itype = SH64_COMPACT_INSN_MOVW4_COMPACT; goto extract_sfmt_movw4_compact;          case 2 : itype = SH64_COMPACT_INSN_MOVL4_COMPACT; goto extract_sfmt_movl4_compact;          case 3 : itype = SH64_COMPACT_INSN_TRAPA_COMPACT; goto extract_sfmt_trapa_compact;          case 4 : itype = SH64_COMPACT_INSN_MOVB9_COMPACT; goto extract_sfmt_movb9_compact;          case 5 : itype = SH64_COMPACT_INSN_MOVW9_COMPACT; goto extract_sfmt_movw9_compact;          case 6 : itype = SH64_COMPACT_INSN_MOVL9_COMPACT; goto extract_sfmt_movl9_compact;          case 7 : itype = SH64_COMPACT_INSN_MOVA_COMPACT; goto extract_sfmt_mova_compact;          case 8 : itype = SH64_COMPACT_INSN_TSTI_COMPACT; goto extract_sfmt_tsti_compact;          case 9 : itype = SH64_COMPACT_INSN_ANDI_COMPACT; goto extract_sfmt_andi_compact;          case 10 : itype = SH64_COMPACT_INSN_XORI_COMPACT; goto extract_sfmt_xori_compact;          case 11 : itype = SH64_COMPACT_INSN_ORI_COMPACT; goto extract_sfmt_andi_compact;          case 12 : itype = SH64_COMPACT_INSN_TSTB_COMPACT; goto extract_sfmt_tstb_compact;          case 13 : itype = SH64_COMPACT_INSN_ANDB_COMPACT; goto extract_sfmt_andb_compact;          case 14 : itype = SH64_COMPACT_INSN_XORB_COMPACT; goto extract_sfmt_andb_compact;          case 15 : itype = SH64_COMPACT_INSN_ORB_COMPACT; goto extract_sfmt_andb_compact;          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 208 : /* fall through */
-      case 209 : /* fall through */
-      case 210 : /* fall through */
-      case 211 : /* fall through */
-      case 212 : /* fall through */
-      case 213 : /* fall through */
-      case 214 : /* fall through */
-      case 215 : /* fall through */
-      case 216 : /* fall through */
-      case 217 : /* fall through */
-      case 218 : /* fall through */
-      case 219 : /* fall through */
-      case 220 : /* fall through */
-      case 221 : /* fall through */
-      case 222 : /* fall through */
-      case 223 : itype = SH64_COMPACT_INSN_MOVL10_COMPACT; goto extract_sfmt_movl10_compact;      case 224 : /* fall through */
-      case 225 : /* fall through */
-      case 226 : /* fall through */
-      case 227 : /* fall through */
-      case 228 : /* fall through */
-      case 229 : /* fall through */
-      case 230 : /* fall through */
-      case 231 : /* fall through */
-      case 232 : /* fall through */
-      case 233 : /* fall through */
-      case 234 : /* fall through */
-      case 235 : /* fall through */
-      case 236 : /* fall through */
-      case 237 : /* fall through */
-      case 238 : /* fall through */
-      case 239 : itype = SH64_COMPACT_INSN_MOVI_COMPACT; goto extract_sfmt_movi_compact;      case 240 : itype = SH64_COMPACT_INSN_FADD_COMPACT; goto extract_sfmt_fadd_compact;      case 241 : itype = SH64_COMPACT_INSN_FSUB_COMPACT; goto extract_sfmt_fadd_compact;      case 242 : itype = SH64_COMPACT_INSN_FMUL_COMPACT; goto extract_sfmt_fadd_compact;      case 243 : itype = SH64_COMPACT_INSN_FDIV_COMPACT; goto extract_sfmt_fadd_compact;      case 244 : itype = SH64_COMPACT_INSN_FCMPEQ_COMPACT; goto extract_sfmt_fcmpeq_compact;      case 245 : itype = SH64_COMPACT_INSN_FCMPGT_COMPACT; goto extract_sfmt_fcmpeq_compact;      case 246 : itype = SH64_COMPACT_INSN_FMOV4_COMPACT; goto extract_sfmt_fmov4_compact;      case 247 : itype = SH64_COMPACT_INSN_FMOV7_COMPACT; goto extract_sfmt_fmov7_compact;      case 248 : itype = SH64_COMPACT_INSN_FMOV2_COMPACT; goto extract_sfmt_fmov2_compact;      case 249 : itype = SH64_COMPACT_INSN_FMOV3_COMPACT; goto extract_sfmt_fmov3_compact;      case 250 : itype = SH64_COMPACT_INSN_FMOV5_COMPACT; goto extract_sfmt_fmov5_compact;      case 251 : itype = SH64_COMPACT_INSN_FMOV6_COMPACT; goto extract_sfmt_fmov6_compact;      case 252 : itype = SH64_COMPACT_INSN_FMOV1_COMPACT; goto extract_sfmt_fmov1_compact;      case 253 :
-        {
-          unsigned int val = (((insn >> 4) & (15 << 0)));
-          switch (val)
-          {
-          case 0 : itype = SH64_COMPACT_INSN_FSTS_COMPACT; goto extract_sfmt_fsts_compact;          case 1 : itype = SH64_COMPACT_INSN_FLDS_COMPACT; goto extract_sfmt_flds_compact;          case 2 : itype = SH64_COMPACT_INSN_FLOAT_COMPACT; goto extract_sfmt_float_compact;          case 3 : itype = SH64_COMPACT_INSN_FTRC_COMPACT; goto extract_sfmt_ftrc_compact;          case 4 : itype = SH64_COMPACT_INSN_FNEG_COMPACT; goto extract_sfmt_fabs_compact;          case 5 : itype = SH64_COMPACT_INSN_FABS_COMPACT; goto extract_sfmt_fabs_compact;          case 6 : itype = SH64_COMPACT_INSN_FSQRT_COMPACT; goto extract_sfmt_fabs_compact;          case 8 : itype = SH64_COMPACT_INSN_FLDI0_COMPACT; goto extract_sfmt_fldi0_compact;          case 9 : itype = SH64_COMPACT_INSN_FLDI1_COMPACT; goto extract_sfmt_fldi0_compact;          case 10 : itype = SH64_COMPACT_INSN_FCNVSD_COMPACT; goto extract_sfmt_fcnvsd_compact;          case 11 : itype = SH64_COMPACT_INSN_FCNVDS_COMPACT; goto extract_sfmt_fcnvds_compact;          case 14 : itype = SH64_COMPACT_INSN_FIPR_COMPACT; goto extract_sfmt_fipr_compact;          case 15 :
-            {
-              unsigned int val = (((insn >> 9) & (1 << 0)));
-              switch (val)
-              {
-              case 0 : itype = SH64_COMPACT_INSN_FTRV_COMPACT; goto extract_sfmt_ftrv_compact;              case 1 :
-                {
-                  unsigned int val = (((insn >> 11) & (1 << 0)));
-                  switch (val)
-                  {
-                  case 0 : itype = SH64_COMPACT_INSN_FSCHG_COMPACT; goto extract_sfmt_fschg_compact;                  case 1 : itype = SH64_COMPACT_INSN_FRCHG_COMPACT; goto extract_sfmt_frchg_compact;                  default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-                  }
-                }
-              default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-              }
-            }
-          default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 254 : itype = SH64_COMPACT_INSN_FMAC_COMPACT; goto extract_sfmt_fmac_compact;      default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
-      }
-    }
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract_sfmt_empty:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addi_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_rn;
-    UINT f_imm8;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addc_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_and_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_andi_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_andb_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bf_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bf_compact", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-    SI f_disp12;
-
-    f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp12) = f_disp12;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_braf_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_braf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_brk_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bsr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-    SI f_disp12;
-
-    f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp12) = f_disp12;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsr_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bsrf_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsrf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrmac_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrmac_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrs_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrs_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrt_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrt_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpeq_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpeqi_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeqi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmppl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmppl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div0s_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0s_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div0u_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0u_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div1_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_dmulsl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmulsl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_dt_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_extsb_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extsb_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fabs_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabs_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fadd_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadd_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcmpeq_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcnvds_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-    SI f_dn;
-
-    f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dn) = f_dn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcnvsd_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-    SI f_dn;
-
-    f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dn) = f_dn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fipr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-    SI f_vn;
-    SI f_vm;
-
-    f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2));
-    f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_vm) = f_vm;
-  FLD (f_vn) = f_vn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fipr_compact", "f_vm 0x%x", 'x', f_vm, "f_vn 0x%x", 'x', f_vn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_flds_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldi0_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldi0_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_float_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_float_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmac_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmac_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov1_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov2_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov2_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov3_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov3_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov4_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov4_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov5_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov5_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov6_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmov7_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_frchg_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_frchg_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fschg_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fschg_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fsts_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ftrc_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ftrv_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-    SI f_vn;
-
-    f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_vn) = f_vn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrv_compact", "f_vn 0x%x", 'x', f_vn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jmp_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldc_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldcl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lds_fpscr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldsl_fpscr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lds_fpul_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldsl_fpul_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lds_mach_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldsl_mach_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lds_macl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldsl_macl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lds_pr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldsl_pr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_macl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_macw_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macw_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mov_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movi_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_rn;
-    UINT f_imm8;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb1_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb2_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb3_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb4_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb4_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb5_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-    UINT f_rm;
-    UINT f_imm4;
-
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-    f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4) = f_imm4;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb5_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb6_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb7_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb8_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb8_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb9_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb9_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movb10_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-    UINT f_rm;
-    UINT f_imm4;
-
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-    f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4) = f_imm4;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb10_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl4_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-    SI f_imm8x4;
-
-    f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x4) = f_imm8x4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl4_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl5_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-    SI f_imm4x4;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-    f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4x4) = f_imm4x4;
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl5_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl7_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl9_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-    SI f_imm8x4;
-
-    f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x4) = f_imm8x4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl9_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl10_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-    UINT f_rn;
-    SI f_imm8x4;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x4) = f_imm8x4;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl10_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movl11_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-    SI f_imm4x4;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-    f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4x4) = f_imm4x4;
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl11_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movw4_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    SI f_imm8x2;
-
-    f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x2) = f_imm8x2;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw4_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movw5_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw5_compact.f
-    UINT f_rn;
-    SI f_imm4x2;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4x2) = f_imm4x2;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw5_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movw9_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    SI f_imm8x2;
-
-    f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x2) = f_imm8x2;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw9_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movw10_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-    SI f_imm8x2;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x2) = f_imm8x2;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw10_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movw11_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw11_compact.f
-    UINT f_rm;
-    SI f_imm4x2;
-
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-    f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm4x2) = f_imm4x2;
-  FLD (f_rm) = f_rm;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw11_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rm 0x%x", 'x', f_rm, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mova_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-    SI f_imm8x4;
-
-    f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8x4) = f_imm8x4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mova_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movcal_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movcal_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movt_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mull_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mull_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_negc_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_nop_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rotcl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rotcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rts_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rts_compact", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_shad_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-    UINT f_rn;
-    UINT f_rm;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-    f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rm) = f_rm;
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shad_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_shll2_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shll2_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stc_gbr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stcl_gbr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcl_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sts_fpscr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stsl_fpscr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sts_fpul_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stsl_fpul_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sts_mach_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stsl_mach_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sts_macl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stsl_macl_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sts_pr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stsl_pr_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_tasb_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-    UINT f_rn;
-
-    f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_rn) = f_rn;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tasb_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_trapa_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_tsti_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tsti_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_tstb_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tstb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_xori_compact:
-  {
-    const IDESC *idesc = &sh64_compact_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-    UINT f_imm8;
-
-    f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm8) = f_imm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
-}
diff --git a/sim/sh64/decode-compact.h b/sim/sh64/decode-compact.h
deleted file mode 100644
index 8ca92a9d05d..00000000000
--- a/sim/sh64/decode-compact.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Decode header for sh64_compact.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH64_COMPACT_DECODE_H
-#define SH64_COMPACT_DECODE_H
-
-extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-extern void sh64_compact_init_idesc_table (SIM_CPU *);
-extern void sh64_compact_sem_init_idesc_table (SIM_CPU *);
-extern void sh64_compact_semf_init_idesc_table (SIM_CPU *);
-
-/* Enum declaration for instructions in cpu family sh64.  */
-typedef enum sh64_compact_insn_type {
-  SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_INSN_X_AFTER, SH64_COMPACT_INSN_X_BEFORE, SH64_COMPACT_INSN_X_CTI_CHAIN
- , SH64_COMPACT_INSN_X_CHAIN, SH64_COMPACT_INSN_X_BEGIN, SH64_COMPACT_INSN_ADD_COMPACT, SH64_COMPACT_INSN_ADDI_COMPACT
- , SH64_COMPACT_INSN_ADDC_COMPACT, SH64_COMPACT_INSN_ADDV_COMPACT, SH64_COMPACT_INSN_AND_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT
- , SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT
- , SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT
- , SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT
- , SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT
- , SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT
- , SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT
- , SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT
- , SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT
- , SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT
- , SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT
- , SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT
- , SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT
- , SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT
- , SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT
- , SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT
- , SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT
- , SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT
- , SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT
- , SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT
- , SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT
- , SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT
- , SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT
- , SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT
- , SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT
- , SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT
- , SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT
- , SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT
- , SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT
- , SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT
- , SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT
- , SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT
- , SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT
- , SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT
- , SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT
- , SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT
- , SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT
- , SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT
- , SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT
- , SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT
- , SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT
- , SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT
- , SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT
- , SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT
- , SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_MAX
-} SH64_COMPACT_INSN_TYPE;
-
-/* Enum declaration for semantic formats in cpu family sh64.  */
-typedef enum sh64_compact_sfmt_type {
-  SH64_COMPACT_SFMT_EMPTY, SH64_COMPACT_SFMT_ADD_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT
- , SH64_COMPACT_SFMT_ADDV_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT
- , SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT
- , SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT
- , SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT
- , SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT
- , SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT
- , SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT
- , SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT
- , SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT
- , SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT
- , SH64_COMPACT_SFMT_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT
- , SH64_COMPACT_SFMT_JMP_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT
- , SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT
- , SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT
- , SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT
- , SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT
- , SH64_COMPACT_SFMT_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT
- , SH64_COMPACT_SFMT_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT
- , SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT
- , SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT
- , SH64_COMPACT_SFMT_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT
- , SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT
- , SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT
- , SH64_COMPACT_SFMT_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT
- , SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT
- , SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT
- , SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT
- , SH64_COMPACT_SFMT_XORI_COMPACT
-} SH64_COMPACT_SFMT_TYPE;
-
-/* Function unit handlers (user written).  */
-
-extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* SH64_COMPACT_DECODE_H */
diff --git a/sim/sh64/decode-media.c b/sim/sh64/decode-media.c
deleted file mode 100644
index f1471f332bb..00000000000
--- a/sim/sh64/decode-media.c
+++ /dev/null
@@ -1,2109 +0,0 @@
-/* Simulator instruction decoder for sh64_media.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC sh64_media_insn_data[SH64_MEDIA_INSN_MAX];
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem sh64_media_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, SH64_MEDIA_INSN_X_CTI_CHAIN, SH64_MEDIA_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_SFMT_EMPTY },
-  { SH_INSN_ADD, SH64_MEDIA_INSN_ADD, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ADDL, SH64_MEDIA_INSN_ADDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ADDI, SH64_MEDIA_INSN_ADDI, SH64_MEDIA_SFMT_ADDI },
-  { SH_INSN_ADDIL, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_SFMT_ADDI },
-  { SH_INSN_ADDZL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ALLOCO, SH64_MEDIA_INSN_ALLOCO, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_AND, SH64_MEDIA_INSN_AND, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ANDC, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ANDI, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_SFMT_ADDI },
-  { SH_INSN_BEQ, SH64_MEDIA_INSN_BEQ, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BEQI, SH64_MEDIA_INSN_BEQI, SH64_MEDIA_SFMT_BEQI },
-  { SH_INSN_BGE, SH64_MEDIA_INSN_BGE, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BGEU, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BGT, SH64_MEDIA_INSN_BGT, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BGTU, SH64_MEDIA_INSN_BGTU, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BLINK, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_SFMT_BLINK },
-  { SH_INSN_BNE, SH64_MEDIA_INSN_BNE, SH64_MEDIA_SFMT_BEQ },
-  { SH_INSN_BNEI, SH64_MEDIA_INSN_BNEI, SH64_MEDIA_SFMT_BEQI },
-  { SH_INSN_BRK, SH64_MEDIA_INSN_BRK, SH64_MEDIA_SFMT_BRK },
-  { SH_INSN_BYTEREV, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_SFMT_BYTEREV },
-  { SH_INSN_CMPEQ, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_CMPGT, SH64_MEDIA_INSN_CMPGT, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_CMPGTU, SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_CMVEQ, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_SFMT_CMVEQ },
-  { SH_INSN_CMVNE, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_SFMT_CMVEQ },
-  { SH_INSN_FABSD, SH64_MEDIA_INSN_FABSD, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FABSS, SH64_MEDIA_INSN_FABSS, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FADDD, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_SFMT_FADDD },
-  { SH_INSN_FADDS, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_SFMT_FADDS },
-  { SH_INSN_FCMPEQD, SH64_MEDIA_INSN_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQD },
-  { SH_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_SFMT_FCMPEQS },
-  { SH_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_SFMT_FCMPEQD },
-  { SH_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_SFMT_FCMPEQS },
-  { SH_INSN_FCMPGTD, SH64_MEDIA_INSN_FCMPGTD, SH64_MEDIA_SFMT_FCMPEQD },
-  { SH_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_SFMT_FCMPEQS },
-  { SH_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_SFMT_FCMPEQD },
-  { SH_INSN_FCMPUNS, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_SFMT_FCMPEQS },
-  { SH_INSN_FCNVDS, SH64_MEDIA_INSN_FCNVDS, SH64_MEDIA_SFMT_FCNVDS },
-  { SH_INSN_FCNVSD, SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_SFMT_FCNVSD },
-  { SH_INSN_FDIVD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_SFMT_FADDD },
-  { SH_INSN_FDIVS, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_SFMT_FADDS },
-  { SH_INSN_FGETSCR, SH64_MEDIA_INSN_FGETSCR, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_FIPRS, SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_SFMT_FIPRS },
-  { SH_INSN_FLDD, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_SFMT_FLDD },
-  { SH_INSN_FLDP, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_SFMT_FLDP },
-  { SH_INSN_FLDS, SH64_MEDIA_INSN_FLDS, SH64_MEDIA_SFMT_FLDS },
-  { SH_INSN_FLDXD, SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_SFMT_FLDXD },
-  { SH_INSN_FLDXP, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_SFMT_FLDXP },
-  { SH_INSN_FLDXS, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_SFMT_FLDXS },
-  { SH_INSN_FLOATLD, SH64_MEDIA_INSN_FLOATLD, SH64_MEDIA_SFMT_FCNVSD },
-  { SH_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FLOATQS, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_SFMT_FCNVDS },
-  { SH_INSN_FMACS, SH64_MEDIA_INSN_FMACS, SH64_MEDIA_SFMT_FMACS },
-  { SH_INSN_FMOVD, SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_SFMT_FMOVDQ },
-  { SH_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_SFMT_FMOVLS },
-  { SH_INSN_FMOVQD, SH64_MEDIA_INSN_FMOVQD, SH64_MEDIA_SFMT_FMOVQD },
-  { SH_INSN_FMOVS, SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FMOVSL, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_SFMT_FMOVSL },
-  { SH_INSN_FMULD, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_SFMT_FADDD },
-  { SH_INSN_FMULS, SH64_MEDIA_INSN_FMULS, SH64_MEDIA_SFMT_FADDS },
-  { SH_INSN_FNEGD, SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FNEGS, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FPUTSCR, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_FSQRTD, SH64_MEDIA_INSN_FSQRTD, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FSQRTS, SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FSTD, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_SFMT_FSTD },
-  { SH_INSN_FSTP, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_SFMT_FSTP },
-  { SH_INSN_FSTS, SH64_MEDIA_INSN_FSTS, SH64_MEDIA_SFMT_FSTS },
-  { SH_INSN_FSTXD, SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_SFMT_FSTXD },
-  { SH_INSN_FSTXP, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_SFMT_FSTXP },
-  { SH_INSN_FSTXS, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_SFMT_FSTXS },
-  { SH_INSN_FSUBD, SH64_MEDIA_INSN_FSUBD, SH64_MEDIA_SFMT_FADDD },
-  { SH_INSN_FSUBS, SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_SFMT_FADDS },
-  { SH_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_SFMT_FCNVDS },
-  { SH_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_SFMT_FABSS },
-  { SH_INSN_FTRCDQ, SH64_MEDIA_INSN_FTRCDQ, SH64_MEDIA_SFMT_FABSD },
-  { SH_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_SFMT_FCNVSD },
-  { SH_INSN_FTRVS, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_SFMT_FTRVS },
-  { SH_INSN_GETCFG, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_GETCON, SH64_MEDIA_INSN_GETCON, SH64_MEDIA_SFMT_GETCON },
-  { SH_INSN_GETTR, SH64_MEDIA_INSN_GETTR, SH64_MEDIA_SFMT_GETTR },
-  { SH_INSN_ICBI, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_LDB, SH64_MEDIA_INSN_LDB, SH64_MEDIA_SFMT_LDB },
-  { SH_INSN_LDL, SH64_MEDIA_INSN_LDL, SH64_MEDIA_SFMT_LDL },
-  { SH_INSN_LDQ, SH64_MEDIA_INSN_LDQ, SH64_MEDIA_SFMT_LDQ },
-  { SH_INSN_LDUB, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_SFMT_LDB },
-  { SH_INSN_LDUW, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_SFMT_LDUW },
-  { SH_INSN_LDW, SH64_MEDIA_INSN_LDW, SH64_MEDIA_SFMT_LDUW },
-  { SH_INSN_LDHIL, SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_LDHIQ, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_LDLOL, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_LDLOQ, SH64_MEDIA_INSN_LDLOQ, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_LDXB, SH64_MEDIA_INSN_LDXB, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_LDXL, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_LDXQ, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_LDXUB, SH64_MEDIA_INSN_LDXUB, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_LDXUW, SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_LDXW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_SFMT_LDXB },
-  { SH_INSN_MABSL, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_SFMT_BYTEREV },
-  { SH_INSN_MABSW, SH64_MEDIA_INSN_MABSW, SH64_MEDIA_SFMT_BYTEREV },
-  { SH_INSN_MADDL, SH64_MEDIA_INSN_MADDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MADDW, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MADDSL, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MADDSUB, SH64_MEDIA_INSN_MADDSUB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MADDSW, SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPEQW, SH64_MEDIA_INSN_MCMPEQW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCMV, SH64_MEDIA_INSN_MCMV, SH64_MEDIA_SFMT_MCMV },
-  { SH_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MCNVSWUB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR1, SH64_MEDIA_INSN_MEXTR1, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR5, SH64_MEDIA_INSN_MEXTR5, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MEXTR7, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_SFMT_MCMV },
-  { SH_INSN_MMACNFX_WL, SH64_MEDIA_INSN_MMACNFX_WL, SH64_MEDIA_SFMT_MCMV },
-  { SH_INSN_MMULL, SH64_MEDIA_INSN_MMULL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULW, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULFXW, SH64_MEDIA_INSN_MMULFXW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MMULSUMWQ, SH64_MEDIA_INSN_MMULSUMWQ, SH64_MEDIA_SFMT_MCMV },
-  { SH_INSN_MOVI, SH64_MEDIA_INSN_MOVI, SH64_MEDIA_SFMT_MOVI },
-  { SH_INSN_MPERMW, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_SFMT_MPERMW },
-  { SH_INSN_MSADUBQ, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_SFMT_MCMV },
-  { SH_INSN_MSHALDSL, SH64_MEDIA_INSN_MSHALDSL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHARDSQ, SH64_MEDIA_INSN_MSHARDSQ, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFLOB, SH64_MEDIA_INSN_MSHFLOB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHLLDW, SH64_MEDIA_INSN_MSHLLDW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSHLRDW, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSUBL, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSUBW, SH64_MEDIA_INSN_MSUBW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MSUBSW, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MULSL, SH64_MEDIA_INSN_MULSL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_MULUL, SH64_MEDIA_INSN_MULUL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_NOP, SH64_MEDIA_INSN_NOP, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_NSB, SH64_MEDIA_INSN_NSB, SH64_MEDIA_SFMT_BYTEREV },
-  { SH_INSN_OCBI, SH64_MEDIA_INSN_OCBI, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_OCBP, SH64_MEDIA_INSN_OCBP, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_OCBWB, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_OR, SH64_MEDIA_INSN_OR, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_ORI, SH64_MEDIA_INSN_ORI, SH64_MEDIA_SFMT_ORI },
-  { SH_INSN_PREFI, SH64_MEDIA_INSN_PREFI, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_PTA, SH64_MEDIA_INSN_PTA, SH64_MEDIA_SFMT_PTA },
-  { SH_INSN_PTABS, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_SFMT_PTABS },
-  { SH_INSN_PTB, SH64_MEDIA_INSN_PTB, SH64_MEDIA_SFMT_PTA },
-  { SH_INSN_PTREL, SH64_MEDIA_INSN_PTREL, SH64_MEDIA_SFMT_PTREL },
-  { SH_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_PUTCON, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_SFMT_PUTCON },
-  { SH_INSN_RTE, SH64_MEDIA_INSN_RTE, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_SHARD, SH64_MEDIA_INSN_SHARD, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHARDL, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHARI, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_SFMT_SHARI },
-  { SH_INSN_SHARIL, SH64_MEDIA_INSN_SHARIL, SH64_MEDIA_SFMT_SHARIL },
-  { SH_INSN_SHLLD, SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHLLI, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_SFMT_SHARI },
-  { SH_INSN_SHLLIL, SH64_MEDIA_INSN_SHLLIL, SH64_MEDIA_SFMT_SHARIL },
-  { SH_INSN_SHLRD, SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SHLRI, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_SFMT_SHARI },
-  { SH_INSN_SHLRIL, SH64_MEDIA_INSN_SHLRIL, SH64_MEDIA_SFMT_SHARIL },
-  { SH_INSN_SHORI, SH64_MEDIA_INSN_SHORI, SH64_MEDIA_SFMT_SHORI },
-  { SH_INSN_SLEEP, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_STB, SH64_MEDIA_INSN_STB, SH64_MEDIA_SFMT_STB },
-  { SH_INSN_STL, SH64_MEDIA_INSN_STL, SH64_MEDIA_SFMT_STL },
-  { SH_INSN_STQ, SH64_MEDIA_INSN_STQ, SH64_MEDIA_SFMT_STQ },
-  { SH_INSN_STW, SH64_MEDIA_INSN_STW, SH64_MEDIA_SFMT_STW },
-  { SH_INSN_STHIL, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_SFMT_STHIL },
-  { SH_INSN_STHIQ, SH64_MEDIA_INSN_STHIQ, SH64_MEDIA_SFMT_STHIL },
-  { SH_INSN_STLOL, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_STLOQ, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_STXB, SH64_MEDIA_INSN_STXB, SH64_MEDIA_SFMT_STXB },
-  { SH_INSN_STXL, SH64_MEDIA_INSN_STXL, SH64_MEDIA_SFMT_STXB },
-  { SH_INSN_STXQ, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_SFMT_STXB },
-  { SH_INSN_STXW, SH64_MEDIA_INSN_STXW, SH64_MEDIA_SFMT_STXB },
-  { SH_INSN_SUB, SH64_MEDIA_INSN_SUB, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SUBL, SH64_MEDIA_INSN_SUBL, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_SWAPQ, SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_SFMT_SWAPQ },
-  { SH_INSN_SYNCI, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_SYNCO, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_SFMT_ALLOCO },
-  { SH_INSN_TRAPA, SH64_MEDIA_INSN_TRAPA, SH64_MEDIA_SFMT_TRAPA },
-  { SH_INSN_XOR, SH64_MEDIA_INSN_XOR, SH64_MEDIA_SFMT_ADD },
-  { SH_INSN_XORI, SH64_MEDIA_INSN_XORI, SH64_MEDIA_SFMT_XORI },
-};
-
-static const struct insn_sem sh64_media_insn_sem_invalid = {
-  VIRTUAL_INSN_X_INVALID, SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_SFMT_EMPTY
-};
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
-
-  id->num = t->index;
-  id->sfmt = t->sfmt;
-  if ((int) t->type <= 0)
-    id->idata = & cgen_virtual_insn_table[- (int) t->type];
-  else
-    id->idata = & insn_table[t->type];
-  id->attrs = CGEN_INSN_ATTRS (id->idata);
-  /* Oh my god, a magic number.  */
-  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-
-  /* Semantic pointers are initialized elsewhere.  */
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-sh64_media_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = SH64_MEDIA_INSN_MAX;
-  IDESC *table = sh64_media_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & sh64_media_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = sh64_media_insn_sem, tend = t + sizeof (sh64_media_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder.  */
-  SH64_MEDIA_INSN_TYPE itype;
-
-  {
-    CGEN_INSN_INT insn = base_insn;
-
-    {
-      unsigned int val = (((insn >> 22) & (63 << 4)) | ((insn >> 16) & (15 << 0)));
-      switch (val)
-      {
-      case 1 : itype = SH64_MEDIA_INSN_CMPEQ; goto extract_sfmt_add;      case 3 : itype = SH64_MEDIA_INSN_CMPGT; goto extract_sfmt_add;      case 7 : itype = SH64_MEDIA_INSN_CMPGTU; goto extract_sfmt_add;      case 8 : itype = SH64_MEDIA_INSN_ADDL; goto extract_sfmt_add;      case 9 : itype = SH64_MEDIA_INSN_ADD; goto extract_sfmt_add;      case 10 : itype = SH64_MEDIA_INSN_SUBL; goto extract_sfmt_add;      case 11 : itype = SH64_MEDIA_INSN_SUB; goto extract_sfmt_add;      case 12 : itype = SH64_MEDIA_INSN_ADDZL; goto extract_sfmt_add;      case 13 : itype = SH64_MEDIA_INSN_NSB; goto extract_sfmt_byterev;      case 14 : itype = SH64_MEDIA_INSN_MULUL; goto extract_sfmt_add;      case 15 : itype = SH64_MEDIA_INSN_BYTEREV; goto extract_sfmt_byterev;      case 16 : itype = SH64_MEDIA_INSN_SHLLDL; goto extract_sfmt_add;      case 17 : itype = SH64_MEDIA_INSN_SHLLD; goto extract_sfmt_add;      case 18 : itype = SH64_MEDIA_INSN_SHLRDL; goto extract_sfmt_add;      case 19 : itype = SH64_MEDIA_INSN_SHLRD; goto extract_sfmt_add;      case 22 : itype = SH64_MEDIA_INSN_SHARDL; goto extract_sfmt_add;      case 23 : itype = SH64_MEDIA_INSN_SHARD; goto extract_sfmt_add;      case 25 : itype = SH64_MEDIA_INSN_OR; goto extract_sfmt_add;      case 27 : itype = SH64_MEDIA_INSN_AND; goto extract_sfmt_add;      case 29 : itype = SH64_MEDIA_INSN_XOR; goto extract_sfmt_add;      case 30 : itype = SH64_MEDIA_INSN_MULSL; goto extract_sfmt_add;      case 31 : itype = SH64_MEDIA_INSN_ANDC; goto extract_sfmt_add;      case 33 : itype = SH64_MEDIA_INSN_MADDW; goto extract_sfmt_add;      case 34 : itype = SH64_MEDIA_INSN_MADDL; goto extract_sfmt_add;      case 36 : itype = SH64_MEDIA_INSN_MADDSUB; goto extract_sfmt_add;      case 37 : itype = SH64_MEDIA_INSN_MADDSW; goto extract_sfmt_add;      case 38 : itype = SH64_MEDIA_INSN_MADDSL; goto extract_sfmt_add;      case 41 : itype = SH64_MEDIA_INSN_MSUBW; goto extract_sfmt_add;      case 42 : itype = SH64_MEDIA_INSN_MSUBL; goto extract_sfmt_add;      case 44 : itype = SH64_MEDIA_INSN_MSUBSUB; goto extract_sfmt_add;      case 45 : itype = SH64_MEDIA_INSN_MSUBSW; goto extract_sfmt_add;      case 46 : itype = SH64_MEDIA_INSN_MSUBSL; goto extract_sfmt_add;      case 49 : itype = SH64_MEDIA_INSN_MSHLLDW; goto extract_sfmt_add;      case 50 : itype = SH64_MEDIA_INSN_MSHLLDL; goto extract_sfmt_add;      case 53 : itype = SH64_MEDIA_INSN_MSHALDSW; goto extract_sfmt_add;      case 54 : itype = SH64_MEDIA_INSN_MSHALDSL; goto extract_sfmt_add;      case 57 : itype = SH64_MEDIA_INSN_MSHARDW; goto extract_sfmt_add;      case 58 : itype = SH64_MEDIA_INSN_MSHARDL; goto extract_sfmt_add;      case 59 : itype = SH64_MEDIA_INSN_MSHARDSQ; goto extract_sfmt_add;      case 61 : itype = SH64_MEDIA_INSN_MSHLRDW; goto extract_sfmt_add;      case 62 : itype = SH64_MEDIA_INSN_MSHLRDL; goto extract_sfmt_add;      case 86 : itype = SH64_MEDIA_INSN_FIPRS; goto extract_sfmt_fiprs;      case 94 : itype = SH64_MEDIA_INSN_FTRVS; goto extract_sfmt_ftrvs;      case 96 : itype = SH64_MEDIA_INSN_FABSS; goto extract_sfmt_fabss;      case 97 : itype = SH64_MEDIA_INSN_FABSD; goto extract_sfmt_fabsd;      case 98 : itype = SH64_MEDIA_INSN_FNEGS; goto extract_sfmt_fabss;      case 99 : itype = SH64_MEDIA_INSN_FNEGD; goto extract_sfmt_fabsd;      case 112 : itype = SH64_MEDIA_INSN_FMOVLS; goto extract_sfmt_fmovls;      case 113 : itype = SH64_MEDIA_INSN_FMOVQD; goto extract_sfmt_fmovqd;      case 114 : itype = SH64_MEDIA_INSN_FGETSCR; goto extract_sfmt_alloco;      case 120 : itype = SH64_MEDIA_INSN_FLDXS; goto extract_sfmt_fldxs;      case 121 : itype = SH64_MEDIA_INSN_FLDXD; goto extract_sfmt_fldxd;      case 125 : itype = SH64_MEDIA_INSN_FLDXP; goto extract_sfmt_fldxp;      case 129 : itype = SH64_MEDIA_INSN_CMVEQ; goto extract_sfmt_cmveq;      case 131 : itype = SH64_MEDIA_INSN_SWAPQ; goto extract_sfmt_swapq;      case 133 : itype = SH64_MEDIA_INSN_CMVNE; goto extract_sfmt_cmveq;      case 159 : itype = SH64_MEDIA_INSN_GETCON; goto extract_sfmt_getcon;      case 160 : itype = SH64_MEDIA_INSN_MCMPEQB; goto extract_sfmt_add;      case 161 : itype = SH64_MEDIA_INSN_MCMPEQW; goto extract_sfmt_add;      case 162 : itype = SH64_MEDIA_INSN_MCMPEQL; goto extract_sfmt_add;      case 164 : itype = SH64_MEDIA_INSN_MCMPGTUB; goto extract_sfmt_add;      case 165 : itype = SH64_MEDIA_INSN_MCMPGTW; goto extract_sfmt_add;      case 166 : itype = SH64_MEDIA_INSN_MCMPGTL; goto extract_sfmt_add;      case 167 : itype = SH64_MEDIA_INSN_MEXTR1; goto extract_sfmt_add;      case 169 : itype = SH64_MEDIA_INSN_MABSW; goto extract_sfmt_byterev;      case 170 : itype = SH64_MEDIA_INSN_MABSL; goto extract_sfmt_byterev;      case 171 : itype = SH64_MEDIA_INSN_MEXTR2; goto extract_sfmt_add;      case 173 : itype = SH64_MEDIA_INSN_MPERMW; goto extract_sfmt_mpermw;      case 175 : itype = SH64_MEDIA_INSN_MEXTR3; goto extract_sfmt_add;      case 176 : itype = SH64_MEDIA_INSN_MSHFLOB; goto extract_sfmt_add;      case 177 : itype = SH64_MEDIA_INSN_MSHFLOW; goto extract_sfmt_add;      case 178 : itype = SH64_MEDIA_INSN_MSHFLOL; goto extract_sfmt_add;      case 179 : itype = SH64_MEDIA_INSN_MEXTR4; goto extract_sfmt_add;      case 180 : itype = SH64_MEDIA_INSN_MSHFHIB; goto extract_sfmt_add;      case 181 : itype = SH64_MEDIA_INSN_MSHFHIW; goto extract_sfmt_add;      case 182 : itype = SH64_MEDIA_INSN_MSHFHIL; goto extract_sfmt_add;      case 183 : itype = SH64_MEDIA_INSN_MEXTR5; goto extract_sfmt_add;      case 187 : itype = SH64_MEDIA_INSN_MEXTR6; goto extract_sfmt_add;      case 191 : itype = SH64_MEDIA_INSN_MEXTR7; goto extract_sfmt_add;      case 192 : itype = SH64_MEDIA_INSN_FMOVSL; goto extract_sfmt_fmovsl;      case 193 : itype = SH64_MEDIA_INSN_FMOVDQ; goto extract_sfmt_fmovdq;      case 194 : itype = SH64_MEDIA_INSN_FPUTSCR; goto extract_sfmt_alloco;      case 200 : itype = SH64_MEDIA_INSN_FCMPEQS; goto extract_sfmt_fcmpeqs;      case 201 : itype = SH64_MEDIA_INSN_FCMPEQD; goto extract_sfmt_fcmpeqd;      case 202 : itype = SH64_MEDIA_INSN_FCMPUNS; goto extract_sfmt_fcmpeqs;      case 203 : itype = SH64_MEDIA_INSN_FCMPUND; goto extract_sfmt_fcmpeqd;      case 204 : itype = SH64_MEDIA_INSN_FCMPGTS; goto extract_sfmt_fcmpeqs;      case 205 : itype = SH64_MEDIA_INSN_FCMPGTD; goto extract_sfmt_fcmpeqd;      case 206 : itype = SH64_MEDIA_INSN_FCMPGES; goto extract_sfmt_fcmpeqs;      case 207 : itype = SH64_MEDIA_INSN_FCMPGED; goto extract_sfmt_fcmpeqd;      case 208 : itype = SH64_MEDIA_INSN_FADDS; goto extract_sfmt_fadds;      case 209 : itype = SH64_MEDIA_INSN_FADDD; goto extract_sfmt_faddd;      case 210 : itype = SH64_MEDIA_INSN_FSUBS; goto extract_sfmt_fadds;      case 211 : itype = SH64_MEDIA_INSN_FSUBD; goto extract_sfmt_faddd;      case 212 : itype = SH64_MEDIA_INSN_FDIVS; goto extract_sfmt_fadds;      case 213 : itype = SH64_MEDIA_INSN_FDIVD; goto extract_sfmt_faddd;      case 214 : itype = SH64_MEDIA_INSN_FMULS; goto extract_sfmt_fadds;      case 215 : itype = SH64_MEDIA_INSN_FMULD; goto extract_sfmt_faddd;      case 222 : itype = SH64_MEDIA_INSN_FMACS; goto extract_sfmt_fmacs;      case 224 : itype = SH64_MEDIA_INSN_FMOVS; goto extract_sfmt_fabss;      case 225 : itype = SH64_MEDIA_INSN_FMOVD; goto extract_sfmt_fabsd;      case 228 : itype = SH64_MEDIA_INSN_FSQRTS; goto extract_sfmt_fabss;      case 229 : itype = SH64_MEDIA_INSN_FSQRTD; goto extract_sfmt_fabsd;      case 230 : itype = SH64_MEDIA_INSN_FCNVSD; goto extract_sfmt_fcnvsd;      case 231 : itype = SH64_MEDIA_INSN_FCNVDS; goto extract_sfmt_fcnvds;      case 232 : itype = SH64_MEDIA_INSN_FTRCSL; goto extract_sfmt_fabss;      case 233 : itype = SH64_MEDIA_INSN_FTRCDQ; goto extract_sfmt_fabsd;      case 234 : itype = SH64_MEDIA_INSN_FTRCSQ; goto extract_sfmt_fcnvsd;      case 235 : itype = SH64_MEDIA_INSN_FTRCDL; goto extract_sfmt_fcnvds;      case 236 : itype = SH64_MEDIA_INSN_FLOATLS; goto extract_sfmt_fabss;      case 237 : itype = SH64_MEDIA_INSN_FLOATQD; goto extract_sfmt_fabsd;      case 238 : itype = SH64_MEDIA_INSN_FLOATLD; goto extract_sfmt_fcnvsd;      case 239 : itype = SH64_MEDIA_INSN_FLOATQS; goto extract_sfmt_fcnvds;      case 248 : itype = SH64_MEDIA_INSN_FSTXS; goto extract_sfmt_fstxs;      case 249 : itype = SH64_MEDIA_INSN_FSTXD; goto extract_sfmt_fstxd;      case 253 : itype = SH64_MEDIA_INSN_FSTXP; goto extract_sfmt_fstxp;      case 256 : itype = SH64_MEDIA_INSN_LDXB; goto extract_sfmt_ldxb;      case 257 : itype = SH64_MEDIA_INSN_LDXW; goto extract_sfmt_ldxb;      case 258 : itype = SH64_MEDIA_INSN_LDXL; goto extract_sfmt_ldxb;      case 259 : itype = SH64_MEDIA_INSN_LDXQ; goto extract_sfmt_ldxb;      case 260 : itype = SH64_MEDIA_INSN_LDXUB; goto extract_sfmt_ldxb;      case 261 : itype = SH64_MEDIA_INSN_LDXUW; goto extract_sfmt_ldxb;      case 273 : itype = SH64_MEDIA_INSN_BLINK; goto extract_sfmt_blink;      case 277 : itype = SH64_MEDIA_INSN_GETTR; goto extract_sfmt_gettr;      case 288 : itype = SH64_MEDIA_INSN_MSADUBQ; goto extract_sfmt_mcmv;      case 289 : itype = SH64_MEDIA_INSN_MMACFXWL; goto extract_sfmt_mcmv;      case 291 : itype = SH64_MEDIA_INSN_MCMV; goto extract_sfmt_mcmv;      case 293 : itype = SH64_MEDIA_INSN_MMACNFX_WL; goto extract_sfmt_mcmv;      case 297 : itype = SH64_MEDIA_INSN_MMULSUMWQ; goto extract_sfmt_mcmv;      case 305 : itype = SH64_MEDIA_INSN_MMULW; goto extract_sfmt_add;      case 306 : itype = SH64_MEDIA_INSN_MMULL; goto extract_sfmt_add;      case 309 : itype = SH64_MEDIA_INSN_MMULFXW; goto extract_sfmt_add;      case 310 : itype = SH64_MEDIA_INSN_MMULFXL; goto extract_sfmt_add;      case 312 : itype = SH64_MEDIA_INSN_MCNVSWB; goto extract_sfmt_add;      case 313 : itype = SH64_MEDIA_INSN_MMULFXRPW; goto extract_sfmt_add;      case 314 : itype = SH64_MEDIA_INSN_MMULLOWL; goto extract_sfmt_add;      case 316 : itype = SH64_MEDIA_INSN_MCNVSWUB; goto extract_sfmt_add;      case 317 : itype = SH64_MEDIA_INSN_MCNVSLW; goto extract_sfmt_add;      case 318 : itype = SH64_MEDIA_INSN_MMULHIWL; goto extract_sfmt_add;      case 384 : itype = SH64_MEDIA_INSN_STXB; goto extract_sfmt_stxb;      case 385 : itype = SH64_MEDIA_INSN_STXW; goto extract_sfmt_stxb;      case 386 : itype = SH64_MEDIA_INSN_STXL; goto extract_sfmt_stxb;      case 387 : itype = SH64_MEDIA_INSN_STXQ; goto extract_sfmt_stxb;      case 401 : itype = SH64_MEDIA_INSN_BEQ; goto extract_sfmt_beq;      case 403 : itype = SH64_MEDIA_INSN_BGE; goto extract_sfmt_beq;      case 405 : itype = SH64_MEDIA_INSN_BNE; goto extract_sfmt_beq;      case 407 : itype = SH64_MEDIA_INSN_BGT; goto extract_sfmt_beq;      case 411 : itype = SH64_MEDIA_INSN_BGEU; goto extract_sfmt_beq;      case 415 : itype = SH64_MEDIA_INSN_BGTU; goto extract_sfmt_beq;      case 417 : itype = SH64_MEDIA_INSN_PTABS; goto extract_sfmt_ptabs;      case 421 : itype = SH64_MEDIA_INSN_PTREL; goto extract_sfmt_ptrel;      case 432 : itype = SH64_MEDIA_INSN_NOP; goto extract_sfmt_alloco;      case 433 : itype = SH64_MEDIA_INSN_TRAPA; goto extract_sfmt_trapa;      case 434 : itype = SH64_MEDIA_INSN_SYNCI; goto extract_sfmt_alloco;      case 435 : itype = SH64_MEDIA_INSN_RTE; goto extract_sfmt_alloco;      case 437 : itype = SH64_MEDIA_INSN_BRK; goto extract_sfmt_brk;      case 438 : itype = SH64_MEDIA_INSN_SYNCO; goto extract_sfmt_alloco;      case 439 : itype = SH64_MEDIA_INSN_SLEEP; goto extract_sfmt_alloco;      case 447 : itype = SH64_MEDIA_INSN_PUTCON; goto extract_sfmt_putcon;      case 512 : /* fall through */
-      case 513 : /* fall through */
-      case 514 : /* fall through */
-      case 515 : /* fall through */
-      case 516 : /* fall through */
-      case 517 : /* fall through */
-      case 518 : /* fall through */
-      case 519 : /* fall through */
-      case 520 : /* fall through */
-      case 521 : /* fall through */
-      case 522 : /* fall through */
-      case 523 : /* fall through */
-      case 524 : /* fall through */
-      case 525 : /* fall through */
-      case 526 : /* fall through */
-      case 527 : itype = SH64_MEDIA_INSN_LDB; goto extract_sfmt_ldb;      case 528 : /* fall through */
-      case 529 : /* fall through */
-      case 530 : /* fall through */
-      case 531 : /* fall through */
-      case 532 : /* fall through */
-      case 533 : /* fall through */
-      case 534 : /* fall through */
-      case 535 : /* fall through */
-      case 536 : /* fall through */
-      case 537 : /* fall through */
-      case 538 : /* fall through */
-      case 539 : /* fall through */
-      case 540 : /* fall through */
-      case 541 : /* fall through */
-      case 542 : /* fall through */
-      case 543 : itype = SH64_MEDIA_INSN_LDW; goto extract_sfmt_lduw;      case 544 : /* fall through */
-      case 545 : /* fall through */
-      case 546 : /* fall through */
-      case 547 : /* fall through */
-      case 548 : /* fall through */
-      case 549 : /* fall through */
-      case 550 : /* fall through */
-      case 551 : /* fall through */
-      case 552 : /* fall through */
-      case 553 : /* fall through */
-      case 554 : /* fall through */
-      case 555 : /* fall through */
-      case 556 : /* fall through */
-      case 557 : /* fall through */
-      case 558 : /* fall through */
-      case 559 : itype = SH64_MEDIA_INSN_LDL; goto extract_sfmt_ldl;      case 560 : /* fall through */
-      case 561 : /* fall through */
-      case 562 : /* fall through */
-      case 563 : /* fall through */
-      case 564 : /* fall through */
-      case 565 : /* fall through */
-      case 566 : /* fall through */
-      case 567 : /* fall through */
-      case 568 : /* fall through */
-      case 569 : /* fall through */
-      case 570 : /* fall through */
-      case 571 : /* fall through */
-      case 572 : /* fall through */
-      case 573 : /* fall through */
-      case 574 : /* fall through */
-      case 575 : itype = SH64_MEDIA_INSN_LDQ; goto extract_sfmt_ldq;      case 576 : /* fall through */
-      case 577 : /* fall through */
-      case 578 : /* fall through */
-      case 579 : /* fall through */
-      case 580 : /* fall through */
-      case 581 : /* fall through */
-      case 582 : /* fall through */
-      case 583 : /* fall through */
-      case 584 : /* fall through */
-      case 585 : /* fall through */
-      case 586 : /* fall through */
-      case 587 : /* fall through */
-      case 588 : /* fall through */
-      case 589 : /* fall through */
-      case 590 : /* fall through */
-      case 591 : itype = SH64_MEDIA_INSN_LDUB; goto extract_sfmt_ldb;      case 592 : /* fall through */
-      case 593 : /* fall through */
-      case 594 : /* fall through */
-      case 595 : /* fall through */
-      case 596 : /* fall through */
-      case 597 : /* fall through */
-      case 598 : /* fall through */
-      case 599 : /* fall through */
-      case 600 : /* fall through */
-      case 601 : /* fall through */
-      case 602 : /* fall through */
-      case 603 : /* fall through */
-      case 604 : /* fall through */
-      case 605 : /* fall through */
-      case 606 : /* fall through */
-      case 607 : itype = SH64_MEDIA_INSN_FLDS; goto extract_sfmt_flds;      case 608 : /* fall through */
-      case 609 : /* fall through */
-      case 610 : /* fall through */
-      case 611 : /* fall through */
-      case 612 : /* fall through */
-      case 613 : /* fall through */
-      case 614 : /* fall through */
-      case 615 : /* fall through */
-      case 616 : /* fall through */
-      case 617 : /* fall through */
-      case 618 : /* fall through */
-      case 619 : /* fall through */
-      case 620 : /* fall through */
-      case 621 : /* fall through */
-      case 622 : /* fall through */
-      case 623 : itype = SH64_MEDIA_INSN_FLDP; goto extract_sfmt_fldp;      case 624 : /* fall through */
-      case 625 : /* fall through */
-      case 626 : /* fall through */
-      case 627 : /* fall through */
-      case 628 : /* fall through */
-      case 629 : /* fall through */
-      case 630 : /* fall through */
-      case 631 : /* fall through */
-      case 632 : /* fall through */
-      case 633 : /* fall through */
-      case 634 : /* fall through */
-      case 635 : /* fall through */
-      case 636 : /* fall through */
-      case 637 : /* fall through */
-      case 638 : /* fall through */
-      case 639 : itype = SH64_MEDIA_INSN_FLDD; goto extract_sfmt_fldd;      case 640 : /* fall through */
-      case 641 : /* fall through */
-      case 642 : /* fall through */
-      case 643 : /* fall through */
-      case 644 : /* fall through */
-      case 645 : /* fall through */
-      case 646 : /* fall through */
-      case 647 : /* fall through */
-      case 648 : /* fall through */
-      case 649 : /* fall through */
-      case 650 : /* fall through */
-      case 651 : /* fall through */
-      case 652 : /* fall through */
-      case 653 : /* fall through */
-      case 654 : /* fall through */
-      case 655 : itype = SH64_MEDIA_INSN_STB; goto extract_sfmt_stb;      case 656 : /* fall through */
-      case 657 : /* fall through */
-      case 658 : /* fall through */
-      case 659 : /* fall through */
-      case 660 : /* fall through */
-      case 661 : /* fall through */
-      case 662 : /* fall through */
-      case 663 : /* fall through */
-      case 664 : /* fall through */
-      case 665 : /* fall through */
-      case 666 : /* fall through */
-      case 667 : /* fall through */
-      case 668 : /* fall through */
-      case 669 : /* fall through */
-      case 670 : /* fall through */
-      case 671 : itype = SH64_MEDIA_INSN_STW; goto extract_sfmt_stw;      case 672 : /* fall through */
-      case 673 : /* fall through */
-      case 674 : /* fall through */
-      case 675 : /* fall through */
-      case 676 : /* fall through */
-      case 677 : /* fall through */
-      case 678 : /* fall through */
-      case 679 : /* fall through */
-      case 680 : /* fall through */
-      case 681 : /* fall through */
-      case 682 : /* fall through */
-      case 683 : /* fall through */
-      case 684 : /* fall through */
-      case 685 : /* fall through */
-      case 686 : /* fall through */
-      case 687 : itype = SH64_MEDIA_INSN_STL; goto extract_sfmt_stl;      case 688 : /* fall through */
-      case 689 : /* fall through */
-      case 690 : /* fall through */
-      case 691 : /* fall through */
-      case 692 : /* fall through */
-      case 693 : /* fall through */
-      case 694 : /* fall through */
-      case 695 : /* fall through */
-      case 696 : /* fall through */
-      case 697 : /* fall through */
-      case 698 : /* fall through */
-      case 699 : /* fall through */
-      case 700 : /* fall through */
-      case 701 : /* fall through */
-      case 702 : /* fall through */
-      case 703 : itype = SH64_MEDIA_INSN_STQ; goto extract_sfmt_stq;      case 704 : /* fall through */
-      case 705 : /* fall through */
-      case 706 : /* fall through */
-      case 707 : /* fall through */
-      case 708 : /* fall through */
-      case 709 : /* fall through */
-      case 710 : /* fall through */
-      case 711 : /* fall through */
-      case 712 : /* fall through */
-      case 713 : /* fall through */
-      case 714 : /* fall through */
-      case 715 : /* fall through */
-      case 716 : /* fall through */
-      case 717 : /* fall through */
-      case 718 : /* fall through */
-      case 719 : itype = SH64_MEDIA_INSN_LDUW; goto extract_sfmt_lduw;      case 720 : /* fall through */
-      case 721 : /* fall through */
-      case 722 : /* fall through */
-      case 723 : /* fall through */
-      case 724 : /* fall through */
-      case 725 : /* fall through */
-      case 726 : /* fall through */
-      case 727 : /* fall through */
-      case 728 : /* fall through */
-      case 729 : /* fall through */
-      case 730 : /* fall through */
-      case 731 : /* fall through */
-      case 732 : /* fall through */
-      case 733 : /* fall through */
-      case 734 : /* fall through */
-      case 735 : itype = SH64_MEDIA_INSN_FSTS; goto extract_sfmt_fsts;      case 736 : /* fall through */
-      case 737 : /* fall through */
-      case 738 : /* fall through */
-      case 739 : /* fall through */
-      case 740 : /* fall through */
-      case 741 : /* fall through */
-      case 742 : /* fall through */
-      case 743 : /* fall through */
-      case 744 : /* fall through */
-      case 745 : /* fall through */
-      case 746 : /* fall through */
-      case 747 : /* fall through */
-      case 748 : /* fall through */
-      case 749 : /* fall through */
-      case 750 : /* fall through */
-      case 751 : itype = SH64_MEDIA_INSN_FSTP; goto extract_sfmt_fstp;      case 752 : /* fall through */
-      case 753 : /* fall through */
-      case 754 : /* fall through */
-      case 755 : /* fall through */
-      case 756 : /* fall through */
-      case 757 : /* fall through */
-      case 758 : /* fall through */
-      case 759 : /* fall through */
-      case 760 : /* fall through */
-      case 761 : /* fall through */
-      case 762 : /* fall through */
-      case 763 : /* fall through */
-      case 764 : /* fall through */
-      case 765 : /* fall through */
-      case 766 : /* fall through */
-      case 767 : itype = SH64_MEDIA_INSN_FSTD; goto extract_sfmt_fstd;      case 770 : itype = SH64_MEDIA_INSN_LDLOL; goto extract_sfmt_alloco;      case 771 : itype = SH64_MEDIA_INSN_LDLOQ; goto extract_sfmt_alloco;      case 774 : itype = SH64_MEDIA_INSN_LDHIL; goto extract_sfmt_alloco;      case 775 : itype = SH64_MEDIA_INSN_LDHIQ; goto extract_sfmt_alloco;      case 783 : itype = SH64_MEDIA_INSN_GETCFG; goto extract_sfmt_alloco;      case 784 : itype = SH64_MEDIA_INSN_SHLLIL; goto extract_sfmt_sharil;      case 785 : itype = SH64_MEDIA_INSN_SHLLI; goto extract_sfmt_shari;      case 786 : itype = SH64_MEDIA_INSN_SHLRIL; goto extract_sfmt_sharil;      case 787 : itype = SH64_MEDIA_INSN_SHLRI; goto extract_sfmt_shari;      case 790 : itype = SH64_MEDIA_INSN_SHARIL; goto extract_sfmt_sharil;      case 791 : itype = SH64_MEDIA_INSN_SHARI; goto extract_sfmt_shari;      case 797 : itype = SH64_MEDIA_INSN_XORI; goto extract_sfmt_xori;      case 800 : /* fall through */
-      case 801 : /* fall through */
-      case 802 : /* fall through */
-      case 803 : /* fall through */
-      case 804 : /* fall through */
-      case 805 : /* fall through */
-      case 806 : /* fall through */
-      case 807 : /* fall through */
-      case 808 : /* fall through */
-      case 809 : /* fall through */
-      case 810 : /* fall through */
-      case 811 : /* fall through */
-      case 812 : /* fall through */
-      case 813 : /* fall through */
-      case 814 : /* fall through */
-      case 815 : itype = SH64_MEDIA_INSN_SHORI; goto extract_sfmt_shori;      case 816 : /* fall through */
-      case 817 : /* fall through */
-      case 818 : /* fall through */
-      case 819 : /* fall through */
-      case 820 : /* fall through */
-      case 821 : /* fall through */
-      case 822 : /* fall through */
-      case 823 : /* fall through */
-      case 824 : /* fall through */
-      case 825 : /* fall through */
-      case 826 : /* fall through */
-      case 827 : /* fall through */
-      case 828 : /* fall through */
-      case 829 : /* fall through */
-      case 830 : /* fall through */
-      case 831 : itype = SH64_MEDIA_INSN_MOVI; goto extract_sfmt_movi;      case 832 : /* fall through */
-      case 833 : /* fall through */
-      case 834 : /* fall through */
-      case 835 : /* fall through */
-      case 836 : /* fall through */
-      case 837 : /* fall through */
-      case 838 : /* fall through */
-      case 839 : /* fall through */
-      case 840 : /* fall through */
-      case 841 : /* fall through */
-      case 842 : /* fall through */
-      case 843 : /* fall through */
-      case 844 : /* fall through */
-      case 845 : /* fall through */
-      case 846 : /* fall through */
-      case 847 : itype = SH64_MEDIA_INSN_ADDI; goto extract_sfmt_addi;      case 848 : /* fall through */
-      case 849 : /* fall through */
-      case 850 : /* fall through */
-      case 851 : /* fall through */
-      case 852 : /* fall through */
-      case 853 : /* fall through */
-      case 854 : /* fall through */
-      case 855 : /* fall through */
-      case 856 : /* fall through */
-      case 857 : /* fall through */
-      case 858 : /* fall through */
-      case 859 : /* fall through */
-      case 860 : /* fall through */
-      case 861 : /* fall through */
-      case 862 : /* fall through */
-      case 863 : itype = SH64_MEDIA_INSN_ADDIL; goto extract_sfmt_addi;      case 864 : /* fall through */
-      case 865 : /* fall through */
-      case 866 : /* fall through */
-      case 867 : /* fall through */
-      case 868 : /* fall through */
-      case 869 : /* fall through */
-      case 870 : /* fall through */
-      case 871 : /* fall through */
-      case 872 : /* fall through */
-      case 873 : /* fall through */
-      case 874 : /* fall through */
-      case 875 : /* fall through */
-      case 876 : /* fall through */
-      case 877 : /* fall through */
-      case 878 : /* fall through */
-      case 879 : itype = SH64_MEDIA_INSN_ANDI; goto extract_sfmt_addi;      case 880 : /* fall through */
-      case 881 : /* fall through */
-      case 882 : /* fall through */
-      case 883 : /* fall through */
-      case 884 : /* fall through */
-      case 885 : /* fall through */
-      case 886 : /* fall through */
-      case 887 : /* fall through */
-      case 888 : /* fall through */
-      case 889 : /* fall through */
-      case 890 : /* fall through */
-      case 891 : /* fall through */
-      case 892 : /* fall through */
-      case 893 : /* fall through */
-      case 894 : /* fall through */
-      case 895 : itype = SH64_MEDIA_INSN_ORI; goto extract_sfmt_ori;      case 897 : itype = SH64_MEDIA_INSN_PREFI; goto extract_sfmt_alloco;      case 898 : itype = SH64_MEDIA_INSN_STLOL; goto extract_sfmt_alloco;      case 899 : itype = SH64_MEDIA_INSN_STLOQ; goto extract_sfmt_alloco;      case 900 : itype = SH64_MEDIA_INSN_ALLOCO; goto extract_sfmt_alloco;      case 901 : itype = SH64_MEDIA_INSN_ICBI; goto extract_sfmt_alloco;      case 902 : itype = SH64_MEDIA_INSN_STHIL; goto extract_sfmt_sthil;      case 903 : itype = SH64_MEDIA_INSN_STHIQ; goto extract_sfmt_sthil;      case 904 : itype = SH64_MEDIA_INSN_OCBP; goto extract_sfmt_alloco;      case 905 : itype = SH64_MEDIA_INSN_OCBI; goto extract_sfmt_alloco;      case 908 : itype = SH64_MEDIA_INSN_OCBWB; goto extract_sfmt_alloco;      case 911 : itype = SH64_MEDIA_INSN_PUTCFG; goto extract_sfmt_alloco;      case 913 : itype = SH64_MEDIA_INSN_BEQI; goto extract_sfmt_beqi;      case 917 : itype = SH64_MEDIA_INSN_BNEI; goto extract_sfmt_beqi;      case 928 : /* fall through */
-      case 929 : /* fall through */
-      case 930 : /* fall through */
-      case 931 : /* fall through */
-      case 932 : /* fall through */
-      case 933 : /* fall through */
-      case 934 : /* fall through */
-      case 935 : /* fall through */
-      case 936 : /* fall through */
-      case 937 : /* fall through */
-      case 938 : /* fall through */
-      case 939 : /* fall through */
-      case 940 : /* fall through */
-      case 941 : /* fall through */
-      case 942 : /* fall through */
-      case 943 : itype = SH64_MEDIA_INSN_PTA; goto extract_sfmt_pta;      case 944 : /* fall through */
-      case 945 : /* fall through */
-      case 946 : /* fall through */
-      case 947 : /* fall through */
-      case 948 : /* fall through */
-      case 949 : /* fall through */
-      case 950 : /* fall through */
-      case 951 : /* fall through */
-      case 952 : /* fall through */
-      case 953 : /* fall through */
-      case 954 : /* fall through */
-      case 955 : /* fall through */
-      case 956 : /* fall through */
-      case 957 : /* fall through */
-      case 958 : /* fall through */
-      case 959 : itype = SH64_MEDIA_INSN_PTB; goto extract_sfmt_pta;      default : itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty;
-      }
-    }
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract_sfmt_empty:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addi:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_left;
-    INT f_disp10;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10) = f_disp10;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_alloco:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_alloco", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_tra;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_tra) = f_tra;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beqi:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beqi.f
-    UINT f_left;
-    INT f_imm6;
-    UINT f_tra;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
-    f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm6) = f_imm6;
-  FLD (f_left) = f_left;
-  FLD (f_tra) = f_tra;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqi", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_tra 0x%x", 'x', f_tra, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_blink:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_blink.f
-    UINT f_trb;
-    UINT f_dest;
-
-    f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_trb) = f_trb;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blink", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_brk:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_byterev:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_byterev", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmveq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmveq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fabsd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fabss:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabss", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_faddd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_faddd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fadds:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadds", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcmpeqd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcmpeqs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcnvds:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fcnvsd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fiprs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fiprs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldp:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_flds:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_flds.f
-    UINT f_left;
-    SI f_disp10x4;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x4) = f_disp10x4;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldxd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldxp:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fldxs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmacs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmacs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmovdq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovdq", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmovls:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovls", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmovqd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovqd", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fmovsl:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-    UINT f_left_right;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-  f_left_right = f_left;
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left_right) = f_left_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovsl", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fstd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fstp:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fsts:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_flds.f
-    UINT f_left;
-    SI f_disp10x4;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x4) = f_disp10x4;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fstxd:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxd", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fstxp:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_fstxs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ftrvs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrvs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_getcon:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_getcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_gettr:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_blink.f
-    UINT f_trb;
-    UINT f_dest;
-
-    f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_trb) = f_trb;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_gettr", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_left;
-    INT f_disp10;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10) = f_disp10;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldl:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_flds.f
-    UINT f_left;
-    SI f_disp10x4;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x4) = f_disp10x4;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lduw:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_lduw.f
-    UINT f_left;
-    SI f_disp10x2;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x2) = f_disp10x2;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lduw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldxb:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxb", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mcmv:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcmv", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_movi:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_movi.f
-    INT f_imm16;
-    UINT f_dest;
-
-    f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm16) = f_imm16;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi", "f_imm16 0x%x", 'x', f_imm16, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mpermw:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpermw", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ori:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ori.f
-    UINT f_left;
-    INT f_imm10;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm10) = f_imm10;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_imm10 0x%x", 'x', f_imm10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_pta:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_pta.f
-    DI f_disp16;
-    UINT f_tra;
-
-    f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc));
-    f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp16) = f_disp16;
-  FLD (f_tra) = f_tra;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pta", "f_disp16 0x%x", 'x', f_disp16, "f_tra 0x%x", 'x', f_tra, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ptabs:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_right;
-    UINT f_tra;
-
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_right) = f_right;
-  FLD (f_tra) = f_tra;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptabs", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ptrel:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_right;
-    UINT f_tra;
-
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_right) = f_right;
-  FLD (f_tra) = f_tra;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptrel", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_putcon:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_putcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_shari:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shari.f
-    UINT f_left;
-    UINT f_uimm6;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_uimm6) = f_uimm6;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shari", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sharil:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shari.f
-    UINT f_left;
-    UINT f_uimm6;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  FLD (f_uimm6) = f_uimm6;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sharil", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_shori:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_shori.f
-    UINT f_uimm16;
-    UINT f_dest;
-
-    f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_uimm16) = f_uimm16;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shori", "f_dest 0x%x", 'x', f_dest, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_left;
-    INT f_disp10;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10) = f_disp10;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_disp10 0x%x", 'x', f_disp10, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stl:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_flds.f
-    UINT f_left;
-    SI f_disp10x4;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x4) = f_disp10x4;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_fldd.f
-    UINT f_left;
-    SI f_disp10x8;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x8) = f_disp10x8;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stw:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_lduw.f
-    UINT f_left;
-    SI f_disp10x2;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1));
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp10x2) = f_disp10x2;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sthil:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_sthil.f
-    UINT f_left;
-    INT f_disp6;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_disp6) = f_disp6;
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthil", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stxb:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxb", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_swapq:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_left;
-    UINT f_right;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_dest) = f_dest;
-  FLD (f_left) = f_left;
-  FLD (f_right) = f_right;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swapq", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_trapa:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_left) = f_left;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa", "f_left 0x%x", 'x', f_left, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_xori:
-  {
-    const IDESC *idesc = &sh64_media_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_xori.f
-    UINT f_left;
-    INT f_imm6;
-    UINT f_dest;
-
-    f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
-    f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
-    f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_imm6) = f_imm6;
-  FLD (f_left) = f_left;
-  FLD (f_dest) = f_dest;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
-}
diff --git a/sim/sh64/decode-media.h b/sim/sh64/decode-media.h
deleted file mode 100644
index 8a84d4e6fe1..00000000000
--- a/sim/sh64/decode-media.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Decode header for sh64_media.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH64_MEDIA_DECODE_H
-#define SH64_MEDIA_DECODE_H
-
-extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-extern void sh64_media_init_idesc_table (SIM_CPU *);
-extern void sh64_media_sem_init_idesc_table (SIM_CPU *);
-extern void sh64_media_semf_init_idesc_table (SIM_CPU *);
-
-/* Enum declaration for instructions in cpu family sh64.  */
-typedef enum sh64_media_insn_type {
-  SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_INSN_X_CTI_CHAIN
- , SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_INSN_ADD, SH64_MEDIA_INSN_ADDL
- , SH64_MEDIA_INSN_ADDI, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_INSN_ALLOCO
- , SH64_MEDIA_INSN_AND, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_INSN_BEQ
- , SH64_MEDIA_INSN_BEQI, SH64_MEDIA_INSN_BGE, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_INSN_BGT
- , SH64_MEDIA_INSN_BGTU, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_INSN_BNE, SH64_MEDIA_INSN_BNEI
- , SH64_MEDIA_INSN_BRK, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_INSN_CMPGT
- , SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_INSN_FABSD
- , SH64_MEDIA_INSN_FABSS, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_INSN_FCMPEQD
- , SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGTD
- , SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_INSN_FCNVDS
- , SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_INSN_FGETSCR
- , SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_INSN_FLDS
- , SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_INSN_FLOATLD
- , SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_INSN_FMACS
- , SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVQD
- , SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_INSN_FMULS
- , SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_INSN_FSQRTD
- , SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_INSN_FSTS
- , SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_INSN_FSUBD
- , SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCDQ
- , SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_INSN_GETCON
- , SH64_MEDIA_INSN_GETTR, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_INSN_LDB, SH64_MEDIA_INSN_LDL
- , SH64_MEDIA_INSN_LDQ, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_INSN_LDW
- , SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_INSN_LDLOQ
- , SH64_MEDIA_INSN_LDXB, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_INSN_LDXUB
- , SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_INSN_MABSW
- , SH64_MEDIA_INSN_MADDL, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_INSN_MADDSUB
- , SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQW
- , SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMV
- , SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_INSN_MEXTR1
- , SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR5
- , SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACNFX_WL
- , SH64_MEDIA_INSN_MMULL, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXW
- , SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULSUMWQ
- , SH64_MEDIA_INSN_MOVI, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_INSN_MSHALDSL
- , SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDSQ
- , SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFLOB
- , SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDW
- , SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_INSN_MSUBW
- , SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_INSN_MULSL
- , SH64_MEDIA_INSN_MULUL, SH64_MEDIA_INSN_NOP, SH64_MEDIA_INSN_NSB, SH64_MEDIA_INSN_OCBI
- , SH64_MEDIA_INSN_OCBP, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_INSN_OR, SH64_MEDIA_INSN_ORI
- , SH64_MEDIA_INSN_PREFI, SH64_MEDIA_INSN_PTA, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_INSN_PTB
- , SH64_MEDIA_INSN_PTREL, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_INSN_RTE
- , SH64_MEDIA_INSN_SHARD, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_INSN_SHARIL
- , SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_INSN_SHLLIL
- , SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_INSN_SHLRIL
- , SH64_MEDIA_INSN_SHORI, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_INSN_STB, SH64_MEDIA_INSN_STL
- , SH64_MEDIA_INSN_STQ, SH64_MEDIA_INSN_STW, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_INSN_STHIQ
- , SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL
- , SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL
- , SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA
- , SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN_MAX
-} SH64_MEDIA_INSN_TYPE;
-
-/* Enum declaration for semantic formats in cpu family sh64.  */
-typedef enum sh64_media_sfmt_type {
-  SH64_MEDIA_SFMT_EMPTY, SH64_MEDIA_SFMT_ADD, SH64_MEDIA_SFMT_ADDI, SH64_MEDIA_SFMT_ALLOCO
- , SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BRK
- , SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD, SH64_MEDIA_SFMT_FABSS
- , SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQS
- , SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD
- , SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP
- , SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS
- , SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTP
- , SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXP, SH64_MEDIA_SFMT_FSTXS
- , SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB
- , SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDXB
- , SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI, SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_ORI
- , SH64_MEDIA_SFMT_PTA, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCON
- , SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHARIL, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB
- , SH64_MEDIA_SFMT_STL, SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL
- , SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI
-} SH64_MEDIA_SFMT_TYPE;
-
-/* Function unit handlers (user written).  */
-
-extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* SH64_MEDIA_DECODE_H */
diff --git a/sim/sh64/decode.h b/sim/sh64/decode.h
deleted file mode 100644
index 2582807d8d1..00000000000
--- a/sim/sh64/decode.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef DECODE_H
-#define DECODE_H
-
-#undef WITH_PROFILE_MODEL_P
-
-#ifdef WANT_ISA_COMPACT
-#include "decode-compact.h"
-#include "defs-compact.h"
-#endif /* WANT_ISA_COMPACT */
-
-#ifdef WANT_ISA_MEDIA
-#include "decode-media.h"
-#include "defs-media.h"
-#endif /* WANT_ISA_MEDIA */
-
-#endif /* DECODE_H */
diff --git a/sim/sh64/defs-compact.h b/sim/sh64/defs-compact.h
deleted file mode 100644
index fb0b7e41640..00000000000
--- a/sim/sh64/defs-compact.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/* ISA definitions header for compact.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef DEFS_SH64_COMPACT_H
-#define DEFS_SH64_COMPACT_H
-
-/* Instruction argument buffer.  */
-
-union sem_fields {
-  struct { /* no operands */
-    int empty;
-  } fmt_empty;
-  struct { /*  */
-    SI f_dn;
-  } sfmt_fcnvds_compact;
-  struct { /*  */
-    IADDR i_disp12;
-  } sfmt_bra_compact;
-  struct { /*  */
-    IADDR i_disp8;
-  } sfmt_bf_compact;
-  struct { /*  */
-    SI f_imm4x2;
-    UINT f_rm;
-  } sfmt_movw11_compact;
-  struct { /*  */
-    SI f_imm8x2;
-    UINT f_rn;
-  } sfmt_movw10_compact;
-  struct { /*  */
-    SI f_imm4x2;
-    UINT f_rn;
-  } sfmt_movw5_compact;
-  struct { /*  */
-    SI f_imm8x4;
-    UINT f_rn;
-  } sfmt_movl10_compact;
-  struct { /*  */
-    UINT f_imm4;
-    UINT f_rm;
-  } sfmt_movb5_compact;
-  struct { /*  */
-    SI f_vm;
-    SI f_vn;
-  } sfmt_fipr_compact;
-  struct { /*  */
-    UINT f_imm8;
-    UINT f_rn;
-  } sfmt_addi_compact;
-  struct { /*  */
-    SI f_imm4x4;
-    UINT f_rm;
-    UINT f_rn;
-  } sfmt_movl5_compact;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-    SCACHE *branch_target;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_ADDI_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_imm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_AND_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_ANDI_COMPACT_VARS \
-  UINT f_op8; \
-  UINT f_imm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ANDI_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_ANDB_COMPACT_VARS \
-  UINT f_op8; \
-  UINT f_imm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ANDB_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_BF_COMPACT_VARS \
-  UINT f_op8; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BF_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4)))); \
-
-#define EXTRACT_IFMT_BRA_COMPACT_VARS \
-  UINT f_op4; \
-  SI f_disp12; \
-  unsigned int length;
-#define EXTRACT_IFMT_BRA_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); \
-
-#define EXTRACT_IFMT_BRAF_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_sub8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BRAF_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_BRK_COMPACT_VARS \
-  UINT f_op16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BRK_COMPACT_CODE \
-  length = 2; \
-  f_op16 = EXTRACT_LSB0_UINT (insn, 16, 15, 16); \
-
-#define EXTRACT_IFMT_FABS_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_sub8; \
-  unsigned int length;
-#define EXTRACT_IFMT_FABS_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_FADD_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_FADD_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_FCNVDS_COMPACT_VARS \
-  UINT f_op4; \
-  SI f_dn; \
-  UINT f_8_1; \
-  UINT f_sub8; \
-  unsigned int length;
-#define EXTRACT_IFMT_FCNVDS_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); \
-  f_8_1 = EXTRACT_LSB0_UINT (insn, 16, 8, 1); \
-  f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_FIPR_COMPACT_VARS \
-  UINT f_op4; \
-  SI f_vn; \
-  SI f_vm; \
-  UINT f_sub8; \
-  unsigned int length;
-#define EXTRACT_IFMT_FIPR_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
-  f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2)); \
-  f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_FLDS_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_sub8; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDS_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
-
-#define EXTRACT_IFMT_FMAC_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMAC_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_FMOV2_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMOV2_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_FMOV5_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  UINT f_sub4; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMOV5_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_FTRV_COMPACT_VARS \
-  UINT f_op4; \
-  SI f_vn; \
-  UINT f_sub10; \
-  unsigned int length;
-#define EXTRACT_IFMT_FTRV_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
-  f_sub10 = EXTRACT_LSB0_UINT (insn, 16, 9, 10); \
-
-#define EXTRACT_IFMT_MOVB5_COMPACT_VARS \
-  UINT f_op8; \
-  UINT f_rm; \
-  UINT f_imm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVB5_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
-
-#define EXTRACT_IFMT_MOVL4_COMPACT_VARS \
-  UINT f_op8; \
-  SI f_imm8x4; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVL4_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
-
-#define EXTRACT_IFMT_MOVL5_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  UINT f_rm; \
-  SI f_imm4x4; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVL5_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); \
-
-#define EXTRACT_IFMT_MOVL10_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  SI f_imm8x4; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVL10_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
-
-#define EXTRACT_IFMT_MOVW4_COMPACT_VARS \
-  UINT f_op8; \
-  SI f_imm8x2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVW4_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
-
-#define EXTRACT_IFMT_MOVW5_COMPACT_VARS \
-  UINT f_op8; \
-  UINT f_rn; \
-  SI f_imm4x2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVW5_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
-
-#define EXTRACT_IFMT_MOVW10_COMPACT_VARS \
-  UINT f_op4; \
-  UINT f_rn; \
-  SI f_imm8x2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVW10_COMPACT_CODE \
-  length = 2; \
-  f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
-  f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
-  f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
-
-#define EXTRACT_IFMT_MOVW11_COMPACT_VARS \
-  UINT f_op8; \
-  UINT f_rm; \
-  SI f_imm4x2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVW11_COMPACT_CODE \
-  length = 2; \
-  f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
-  f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
-  f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
-
-#endif /* DEFS_SH64_COMPACT_H */
diff --git a/sim/sh64/defs-media.h b/sim/sh64/defs-media.h
deleted file mode 100644
index 7e749f9d5b5..00000000000
--- a/sim/sh64/defs-media.h
+++ /dev/null
@@ -1,926 +0,0 @@
-/* ISA definitions header for media.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef DEFS_SH64_MEDIA_H
-#define DEFS_SH64_MEDIA_H
-
-/* Instruction argument buffer.  */
-
-union sem_fields {
-  struct { /* no operands */
-    int empty;
-  } fmt_empty;
-  struct { /*  */
-    UINT f_dest;
-    UINT f_uimm16;
-  } sfmt_shori;
-  struct { /*  */
-    DI f_disp16;
-    UINT f_tra;
-  } sfmt_pta;
-  struct { /*  */
-    INT f_imm16;
-    UINT f_dest;
-  } sfmt_movi;
-  struct { /*  */
-    UINT f_dest;
-    UINT f_left_right;
-  } sfmt_fabsd;
-  struct { /*  */
-    UINT f_dest;
-    UINT f_trb;
-  } sfmt_blink;
-  struct { /*  */
-    INT f_imm6;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_xori;
-  struct { /*  */
-    INT f_disp6;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_sthil;
-  struct { /*  */
-    UINT f_dest;
-    UINT f_left;
-    UINT f_uimm6;
-  } sfmt_shari;
-  struct { /*  */
-    INT f_imm10;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_ori;
-  struct { /*  */
-    SI f_disp10x2;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_lduw;
-  struct { /*  */
-    SI f_disp10x4;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_flds;
-  struct { /*  */
-    SI f_disp10x8;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_fldd;
-  struct { /*  */
-    INT f_imm6;
-    UINT f_left;
-    UINT f_tra;
-  } sfmt_beqi;
-  struct { /*  */
-    UINT f_left;
-    UINT f_right;
-    UINT f_tra;
-  } sfmt_beq;
-  struct { /*  */
-    INT f_disp10;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_addi;
-  struct { /*  */
-    UINT f_dest;
-    UINT f_left;
-    UINT f_right;
-  } sfmt_add;
-  struct {
-    INT f_disp6;
-    UINT f_dest;
-    UINT f_left;
-  } sfmt_ldhil;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-    SCACHE *branch_target;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  INT f_disp10; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_ALLOCO_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  SI f_disp6x32; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_ALLOCO_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_likely; \
-  UINT f_8_2; \
-  UINT f_tra; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
-  f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
-  f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_BEQI_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  INT f_imm6; \
-  UINT f_likely; \
-  UINT f_8_2; \
-  UINT f_tra; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
-  f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
-  f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
-  f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_BLINK_VARS \
-  UINT f_op; \
-  UINT f_25; \
-  UINT f_trb; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_BLINK_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 3); \
-  f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_BRK_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_BRK_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_BYTEREV_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_BYTEREV_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FABSD_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FABSD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FABSS_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FABSS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FADDD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FADDD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FADDS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FADDS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FCMPEQD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FCMPEQD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FCMPEQS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FCMPEQS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FCNVDS_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FCNVDS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FCNVSD_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FCNVSD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FGETSCR_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FGETSCR_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FIPRS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FIPRS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FLDD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x8; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FLDP_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x8; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDP_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FLDS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x4; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FLDXD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDXD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FLDXP_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FLDXP_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FMOVDQ_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMOVDQ_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FMOVLS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMOVLS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FMOVSL_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FMOVSL_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FPUTSCR_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_left; \
-  UINT f_right; \
-  UINT f_left_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FPUTSCR_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_left_right = f_left;\
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FSTXD_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FSTXD_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_FTRVS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_FTRVS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_GETCFG_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  INT f_disp6; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_GETCFG_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_GETCON_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_GETCON_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_LDL_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x4; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDL_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_LDQ_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x8; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDQ_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_MMACNFX_WL_VARS \
-  UINT f_op; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_MMACNFX_WL_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_MOVI_VARS \
-  UINT f_op; \
-  INT f_imm16; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_MOVI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_ORI_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  INT f_imm10; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_ORI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_PREFI_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  SI f_disp6x32; \
-  UINT f_right; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_PREFI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_PTA_VARS \
-  UINT f_op; \
-  DI f_disp16; \
-  UINT f_likely; \
-  UINT f_8_2; \
-  UINT f_tra; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_PTA_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc)); \
-  f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
-  f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
-  f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_PTABS_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_likely; \
-  UINT f_8_2; \
-  UINT f_tra; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_PTABS_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
-  f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
-  f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_PUTCON_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_PUTCON_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_SHARI_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_uimm6; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_SHARI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_SHORI_VARS \
-  UINT f_op; \
-  UINT f_uimm16; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_SHORI_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_STW_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  SI f_disp10x2; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_STW_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#define EXTRACT_IFMT_TRAPA_VARS \
-  UINT f_op; \
-  UINT f_left; \
-  UINT f_ext; \
-  UINT f_right; \
-  UINT f_dest; \
-  UINT f_rsvd; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAPA_CODE \
-  length = 4; \
-  f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
-  f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
-  f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
-  f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
-  f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-
-#endif /* DEFS_SH64_MEDIA_H */
diff --git a/sim/sh64/eng-compact.h b/sim/sh64/eng-compact.h
deleted file mode 100644
index 521b2f8a977..00000000000
--- a/sim/sh64/eng-compact.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* engine configuration for sh64 */
-
-/* WITH_FAST: non-zero if a fast version of the engine is available
-   in addition to the full-featured version.  */
-#define WITH_FAST 1
-
-/* WITH_SCACHE_PBB_SH64_COMPACT: non-zero if the pbb engine was selected.  */
-#define WITH_SCACHE_PBB_SH64_COMPACT 1
-
-/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn.  */
-#define HAVE_PARALLEL_INSNS 0
-#define WITH_PARALLEL_READ 0
-#define WITH_PARALLEL_WRITE 0
-#define WITH_PARALLEL_GENWRITE 0
-
-/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
-   implemented as a switch().  */
-#define WITH_SEM_SWITCH_FULL 0
-
-/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
-   implemented as a switch().  */
-#define WITH_SEM_SWITCH_FAST 1
-
-/* Functions defined in the generated mainloop.c file
-   (which doesn't necessarily have that file name).  */
-
-extern ENGINE_FN sh64_compact_engine_run_full;
-extern ENGINE_FN sh64_compact_engine_run_fast;
-
-extern SEM_PC sh64_compact_pbb_begin (SIM_CPU *, int);
-extern SEM_PC sh64_compact_pbb_chain (SIM_CPU *, SEM_ARG);
-extern SEM_PC sh64_compact_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
-extern void sh64_compact_pbb_before (SIM_CPU *, SCACHE *);
-extern void sh64_compact_pbb_after (SIM_CPU *, SCACHE *);
diff --git a/sim/sh64/eng-media.h b/sim/sh64/eng-media.h
deleted file mode 100644
index db1c21da640..00000000000
--- a/sim/sh64/eng-media.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* engine configuration for sh64 */
-
-/* WITH_FAST: non-zero if a fast version of the engine is available
-   in addition to the full-featured version.  */
-#define WITH_FAST 1
-
-/* WITH_SCACHE_PBB_SH64_MEDIA: non-zero if the pbb engine was selected.  */
-#define WITH_SCACHE_PBB_SH64_MEDIA 1
-
-/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn.  */
-#define HAVE_PARALLEL_INSNS 0
-#define WITH_PARALLEL_READ 0
-#define WITH_PARALLEL_WRITE 0
-#define WITH_PARALLEL_GENWRITE 0
-
-/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
-   implemented as a switch().  */
-#define WITH_SEM_SWITCH_FULL 0
-
-/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
-   implemented as a switch().  */
-#define WITH_SEM_SWITCH_FAST 1
-
-/* Functions defined in the generated mainloop.c file
-   (which doesn't necessarily have that file name).  */
-
-extern ENGINE_FN sh64_media_engine_run_full;
-extern ENGINE_FN sh64_media_engine_run_fast;
-
-extern SEM_PC sh64_media_pbb_begin (SIM_CPU *, int);
-extern SEM_PC sh64_media_pbb_chain (SIM_CPU *, SEM_ARG);
-extern SEM_PC sh64_media_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
-extern void sh64_media_pbb_before (SIM_CPU *, SCACHE *);
-extern void sh64_media_pbb_after (SIM_CPU *, SCACHE *);
diff --git a/sim/sh64/eng.h b/sim/sh64/eng.h
deleted file mode 100644
index fb9d8c566b1..00000000000
--- a/sim/sh64/eng.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Engine declarations.
-   Copyright (C) 2000 Free Software Foundation, Inc.
-   Contributed by Red Hat, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-/* Include declarations for SHmedia and SHcompact ISAs. */
-
-#include "eng-compact.h"
-#include "eng-media.h"
diff --git a/sim/sh64/mloop-compact.c b/sim/sh64/mloop-compact.c
deleted file mode 100644
index fb6b55202cf..00000000000
--- a/sim/sh64/mloop-compact.c
+++ /dev/null
@@ -1,635 +0,0 @@
-/* This file is generated by the genmloop script.  DO NOT EDIT! */
-
-/* Enable switch() support in cgen headers.  */
-#define SEM_IN_SWITCH
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "bfd.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-#include "sim-assert.h"
-
-/* Fill in the administrative ARGBUF fields required by all insns,
-   virtual and real.  */
-
-static INLINE void
-sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
-		    PCADDR pc, int fast_p)
-{
-#if WITH_SCACHE
-  SEM_SET_CODE (abuf, idesc, fast_p);
-  ARGBUF_ADDR (abuf) = pc;
-#endif
-  ARGBUF_IDESC (abuf) = idesc;
-}
-
-/* Fill in tracing/profiling fields of an ARGBUF.  */
-
-static INLINE void
-sh64_compact_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
-		       int trace_p, int profile_p)
-{
-  ARGBUF_TRACE_P (abuf) = trace_p;
-  ARGBUF_PROFILE_P (abuf) = profile_p;
-}
-
-#if WITH_SCACHE_PBB
-
-/* Emit the "x-before" handler.
-   x-before is emitted before each insn (serial or parallel).
-   This is as opposed to x-after which is only emitted at the end of a group
-   of parallel insns.  */
-
-static INLINE void
-sh64_compact_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
-{
-  ARGBUF *abuf = &sc[0].argbuf;
-  const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
-
-  abuf->fields.before.first_p = first_p;
-  sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
-  /* no need to set trace_p,profile_p */
-}
-
-/* Emit the "x-after" handler.
-   x-after is emitted after a serial insn or at the end of a group of
-   parallel insns.  */
-
-static INLINE void
-sh64_compact_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
-{
-  ARGBUF *abuf = &sc[0].argbuf;
-  const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
-
-  sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
-  /* no need to set trace_p,profile_p */
-}
-
-#endif /* WITH_SCACHE_PBB */
-
-
-static INLINE const IDESC *
-extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
-         int fast_p)
-{
-  const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
-
-  sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  if (! fast_p)
-    {
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      sh64_compact_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
-    }
-  return id;
-}
-
-static INLINE SEM_PC
-execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
-{
-  SEM_PC vpc;
-
-  if (fast_p)
-    {
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
-#endif
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FAST */
-    }
-  else
-    {
-#if ! WITH_SEM_SWITCH_FULL
-      ARGBUF *abuf = &sc->argbuf;
-      const IDESC *idesc = abuf->idesc;
-#if WITH_SCACHE_PBB
-      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
-#else
-      int virtual_p = 0;
-#endif
-
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-before */
-	  if (ARGBUF_PROFILE_P (abuf))
-	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
-	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    sh64_compact_model_insn_before (current_cpu, 1 /*first_p*/);
-	  TRACE_INSN_INIT (current_cpu, abuf, 1);
-	  TRACE_INSN (current_cpu, idesc->idata,
-		      (const struct argbuf *) abuf, abuf->addr);
-	}
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
-#endif
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-after */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    {
-	      int cycles;
-
-	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
-	      sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
-	    }
-	  TRACE_INSN_FINI (current_cpu, abuf, 1);
-	}
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FULL */
-    }
-
-  return vpc;
-}
-
-
-/* Record address of cti terminating a pbb.  */
-#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
-/* Record number of [real] insns in pbb.  */
-#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
-
-/* Fetch and extract a pseudo-basic-block.
-   FAST_P is non-zero if no tracing/profiling/etc. is wanted.  */
-
-INLINE SEM_PC
-sh64_compact_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
-{
-  SEM_PC new_vpc;
-  PCADDR pc;
-  SCACHE *sc;
-  int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
-
-  pc = GET_H_PC ();
-
-  new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
-  if (! new_vpc)
-    {
-      /* Leading '_' to avoid collision with mainloop.in.  */
-      int _insn_count = 0;
-      SCACHE *orig_sc = sc;
-      SCACHE *_cti_sc = NULL;
-      int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
-
-      /* First figure out how many instructions to compile.
-	 MAX_INSNS is the size of the allocated buffer, which includes space
-	 for before/after handlers if they're being used.
-	 SLICE_INSNS is the maxinum number of real insns that can be
-	 executed.  Zero means "as many as we want".  */
-      /* ??? max_insns is serving two incompatible roles.
-	 1) Number of slots available in scache buffer.
-	 2) Number of real insns to execute.
-	 They're incompatible because there are virtual insns emitted too
-	 (chain,cti-chain,before,after handlers).  */
-
-      if (slice_insns == 1)
-	{
-	  /* No need to worry about extra slots required for virtual insns
-	     and parallel exec support because MAX_CHAIN_LENGTH is
-	     guaranteed to be big enough to execute at least 1 insn!  */
-	  max_insns = 1;
-	}
-      else
-	{
-	  /* Allow enough slop so that while compiling insns, if max_insns > 0
-	     then there's guaranteed to be enough space to emit one real insn.
-	     MAX_CHAIN_LENGTH is typically much longer than
-	     the normal number of insns between cti's anyway.  */
-	  max_insns -= (1 /* one for the trailing chain insn */
-			+ (FAST_P
-			   ? 0
-			   : (1 + MAX_PARALLEL_INSNS) /* before+after */)
-			+ (MAX_PARALLEL_INSNS > 1
-			   ? (MAX_PARALLEL_INSNS * 2)
-			   : 0));
-
-	  /* Account for before/after handlers.  */
-	  if (! FAST_P)
-	    slice_insns *= 3;
-
-	  if (slice_insns > 0
-	      && slice_insns < max_insns)
-	    max_insns = slice_insns;
-	}
-
-      new_vpc = sc;
-
-      /* SC,PC must be updated to point passed the last entry used.
-	 SET_CTI_VPC must be called if pbb is terminated by a cti.
-	 SET_INSN_COUNT must be called to record number of real insns in
-	 pbb [could be computed by us of course, extra cpu but perhaps
-	 negligible enough].  */
-
-/* begin extract-pbb */
-{
-  const IDESC *idesc;
-  int icount = 0;
-
- while (max_insns > 0)
-    {
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      
-      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
-      SEM_SKIP_COMPILE (current_cpu, sc, 1);
-      ++sc;
-      --max_insns;
-      ++icount;
-      pc += idesc->length;
-
-      if (IDESC_CTI_P (idesc))
-        {
-          SET_CTI_VPC (sc - 1);
-
-          if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
-            {
-              USI insn = GETIMEMUHI (current_cpu, pc);
-	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
-
-              if (IDESC_CTI_P (idesc) ||
-	          CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_ILLSLOT))
-	        {
-		  SIM_DESC sd = CPU_STATE (current_cpu);
-                  sim_io_eprintf (CPU_STATE (current_cpu),
-		    "malformed program, `%s' insn in delay slot\n",
-                    CGEN_INSN_NAME (idesc->idata));    
-		  sim_engine_halt (sd, current_cpu, NULL, pc,
-  				   sim_stopped, SIM_SIGILL);
-                }
-	      else
-                { 
-                  ++sc;
-	          --max_insns;
-	          ++icount;
-	          pc += idesc->length;
-                }
-            }
-	  break;
-      }
-    }
-
- Finish:
-  SET_INSN_COUNT (icount);
-}
-/* end extract-pbb */
-
-      /* The last one is a pseudo-insn to link to the next chain.
-	 It is also used to record the insn count for this chain.  */
-      {
-	const IDESC *id;
-
-	/* Was pbb terminated by a cti?  */
-	if (_cti_sc)
-	  {
-	    id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CTI_CHAIN];
-	  }
-	else
-	  {
-	    id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CHAIN];
-	  }
-	SEM_SET_CODE (&sc->argbuf, id, FAST_P);
-	sc->argbuf.idesc = id;
-	sc->argbuf.addr = pc;
-	sc->argbuf.fields.chain.insn_count = _insn_count;
-	sc->argbuf.fields.chain.next = 0;
-	sc->argbuf.fields.chain.branch_target = 0;
-	++sc;
-      }
-
-      /* Update the pointer to the next free entry, may not have used as
-	 many entries as was asked for.  */
-      CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
-      /* Record length of chain if profiling.
-	 This includes virtual insns since they count against
-	 max_insns too.  */
-      if (! FAST_P)
-	PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
-    }
-
-  return new_vpc;
-}
-
-/* Chain to the next block from a non-cti terminated previous block.  */
-
-INLINE SEM_PC
-sh64_compact_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-
-  PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
-
-  SET_H_PC (abuf->addr);
-
-
-  /* If not running forever, exit back to main loop.  */
-  if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
-      /* Also exit back to main loop if there's an event.
-         Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
-	 at the "right" time, but then that was what was asked for.
-	 There is no silver bullet for simulator engines.
-         ??? Clearly this needs a cleaner interface.
-	 At present it's just so Ctrl-C works.  */
-      || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
-    CPU_RUNNING_P (current_cpu) = 0;
-
-  /* If chained to next block, go straight to it.  */
-  if (abuf->fields.chain.next)
-    return abuf->fields.chain.next;
-  /* See if next block has already been compiled.  */
-  abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
-  if (abuf->fields.chain.next)
-    return abuf->fields.chain.next;
-  /* Nope, so next insn is a virtual insn to invoke the compiler
-     (begin a pbb).  */
-  return CPU_SCACHE_PBB_BEGIN (current_cpu);
-}
-
-/* Chain to the next block from a cti terminated previous block.
-   BR_TYPE indicates whether the branch was taken and whether we can cache
-   the vpc of the branch target.
-   NEW_PC is the target's branch address, and is only valid if
-   BR_TYPE != SEM_BRANCH_UNTAKEN.  */
-
-INLINE SEM_PC
-sh64_compact_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
-		     SEM_BRANCH_TYPE br_type, PCADDR new_pc)
-{
-  SEM_PC *new_vpc_ptr;
-
-  PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
-
-  /* If we have switched ISAs, exit back to main loop.
-     Set idesc to 0 to cause the engine to point to the right insn table.  */
-  if (new_pc & 1)
-  {
-    /* Switch to SHmedia.  */
-    CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
-    CPU_RUNNING_P (current_cpu) = 0;
-  }
-
-  /* If not running forever, exit back to main loop.  */
-  if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
-      /* Also exit back to main loop if there's an event.
-         Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
-	 at the "right" time, but then that was what was asked for.
-	 There is no silver bullet for simulator engines.
-         ??? Clearly this needs a cleaner interface.
-	 At present it's just so Ctrl-C works.  */
-      || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
-    CPU_RUNNING_P (current_cpu) = 0;
-
-  /* Restart compiler if we branched to an uncacheable address
-     (e.g. "j reg").  */
-  if (br_type == SEM_BRANCH_UNCACHEABLE)
-    {
-      SET_H_PC (new_pc);
-      return CPU_SCACHE_PBB_BEGIN (current_cpu);
-    }
-
-  /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
-     next chain ptr.  */
-  if (br_type == SEM_BRANCH_UNTAKEN)
-    {
-      ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-      new_pc = abuf->addr;
-      SET_H_PC (new_pc);
-      new_vpc_ptr = &abuf->fields.chain.next;
-    }
-  else
-    {
-      ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-      SET_H_PC (new_pc);
-      new_vpc_ptr = &abuf->fields.chain.branch_target;
-    }
-
-  /* If chained to next block, go straight to it.  */
-  if (*new_vpc_ptr)
-    return *new_vpc_ptr;
-  /* See if next block has already been compiled.  */
-  *new_vpc_ptr = scache_lookup (current_cpu, new_pc);
-  if (*new_vpc_ptr)
-    return *new_vpc_ptr;
-  /* Nope, so next insn is a virtual insn to invoke the compiler
-     (begin a pbb).  */
-  return CPU_SCACHE_PBB_BEGIN (current_cpu);
-}
-
-/* x-before handler.
-   This is called before each insn.  */
-
-void
-sh64_compact_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
-{
-  SEM_ARG sem_arg = sc;
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int first_p = abuf->fields.before.first_p;
-  const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
-  const IDESC *cur_idesc = cur_abuf->idesc;
-  PCADDR pc = cur_abuf->addr;
-
-  if (ARGBUF_PROFILE_P (cur_abuf))
-    PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
-
-  /* If this isn't the first insn, finish up the previous one.  */
-
-  if (! first_p)
-    {
-      if (PROFILE_MODEL_P (current_cpu))
-	{
-	  const SEM_ARG prev_sem_arg = sc - 1;
-	  const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
-	  const IDESC *prev_idesc = prev_abuf->idesc;
-	  int cycles;
-
-	  /* ??? May want to measure all insns if doing insn tracing.  */
-	  if (ARGBUF_PROFILE_P (prev_abuf))
-	    {
-	      cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
-	      sh64_compact_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
-	    }
-	}
-
-      TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
-    }
-
-  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
-  if (PROFILE_MODEL_P (current_cpu)
-      && ARGBUF_PROFILE_P (cur_abuf))
-    sh64_compact_model_insn_before (current_cpu, first_p);
-
-  TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
-  TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
-}
-
-/* x-after handler.
-   This is called after a serial insn or at the end of a group of parallel
-   insns.  */
-
-void
-sh64_compact_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
-{
-  SEM_ARG sem_arg = sc;
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  const SEM_ARG prev_sem_arg = sc - 1;
-  const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
-
-  /* ??? May want to measure all insns if doing insn tracing.  */
-  if (PROFILE_MODEL_P (current_cpu)
-      && ARGBUF_PROFILE_P (prev_abuf))
-    {
-      const IDESC *prev_idesc = prev_abuf->idesc;
-      int cycles;
-
-      cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
-      sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
-    }
-  TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
-}
-
-#define FAST_P 0
-
-void
-sh64_compact_engine_run_full (SIM_CPU *current_cpu)
-{
-  SIM_DESC current_state = CPU_STATE (current_cpu);
-  SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
-  /* virtual program counter */
-  SEM_PC vpc;
-#if WITH_SEM_SWITCH_FULL
-  /* For communication between cti's and cti-chain.  */
-  SEM_BRANCH_TYPE pbb_br_type;
-  PCADDR pbb_br_npc;
-#endif
-
-
-  if (! CPU_IDESC_SEM_INIT_P (current_cpu))
-    {
-      /* ??? 'twould be nice to move this up a level and only call it once.
-	 On the other hand, in the "let's go fast" case the test is only done
-	 once per pbb (since we only return to the main loop at the end of
-	 a pbb).  And in the "let's run until we're done" case we don't return
-	 until the program exits.  */
-
-#if WITH_SEM_SWITCH_FULL
-#if defined (__GNUC__)
-/* ??? Later maybe paste sem-switch.c in when building mainloop.c.  */
-#define DEFINE_LABELS
-#include "sem-compact-switch.c"
-#endif
-#else
-      sh64_compact_sem_init_idesc_table (current_cpu);
-#endif
-
-      /* Initialize the "begin (compile) a pbb" virtual insn.  */
-      vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
-      SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
-			 & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
-      vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
-
-      CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
-    }
-
-  CPU_RUNNING_P (current_cpu) = 1;
-  /* ??? In the case where we're returning to the main loop after every
-     pbb we don't want to call pbb_begin each time (which hashes on the pc
-     and does a table lookup).  A way to speed this up is to save vpc
-     between calls.  */
-  vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
-
-  do
-    {
-/* begin full-exec-pbb */
-{
-#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
-#define DEFINE_SWITCH
-#include "sem-compact-switch.c"
-#else
-  vpc = execute (current_cpu, vpc, FAST_P);
-#endif
-}
-/* end full-exec-pbb */
-    }
-  while (CPU_RUNNING_P (current_cpu));
-}
-
-#undef FAST_P
-
-
-#define FAST_P 1
-
-void
-sh64_compact_engine_run_fast (SIM_CPU *current_cpu)
-{
-  SIM_DESC current_state = CPU_STATE (current_cpu);
-  SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
-  /* virtual program counter */
-  SEM_PC vpc;
-#if WITH_SEM_SWITCH_FAST
-  /* For communication between cti's and cti-chain.  */
-  SEM_BRANCH_TYPE pbb_br_type;
-  PCADDR pbb_br_npc;
-#endif
-
-
-  if (! CPU_IDESC_SEM_INIT_P (current_cpu))
-    {
-      /* ??? 'twould be nice to move this up a level and only call it once.
-	 On the other hand, in the "let's go fast" case the test is only done
-	 once per pbb (since we only return to the main loop at the end of
-	 a pbb).  And in the "let's run until we're done" case we don't return
-	 until the program exits.  */
-
-#if WITH_SEM_SWITCH_FAST
-#if defined (__GNUC__)
-/* ??? Later maybe paste sem-switch.c in when building mainloop.c.  */
-#define DEFINE_LABELS
-#include "sem-compact-switch.c"
-#endif
-#else
-      sh64_compact_semf_init_idesc_table (current_cpu);
-#endif
-
-      /* Initialize the "begin (compile) a pbb" virtual insn.  */
-      vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
-      SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
-			 & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
-      vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
-
-      CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
-    }
-
-  CPU_RUNNING_P (current_cpu) = 1;
-  /* ??? In the case where we're returning to the main loop after every
-     pbb we don't want to call pbb_begin each time (which hashes on the pc
-     and does a table lookup).  A way to speed this up is to save vpc
-     between calls.  */
-  vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
-
-  do
-    {
-/* begin fast-exec-pbb */
-{
-#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
-#define DEFINE_SWITCH
-#include "sem-compact-switch.c"
-#else
-  vpc = execute (current_cpu, vpc, FAST_P);
-#endif
-}
-/* end fast-exec-pbb */
-    }
-  while (CPU_RUNNING_P (current_cpu));
-}
-
-#undef FAST_P
-
diff --git a/sim/sh64/mloop-media.c b/sim/sh64/mloop-media.c
deleted file mode 100644
index 03c5df534c5..00000000000
--- a/sim/sh64/mloop-media.c
+++ /dev/null
@@ -1,624 +0,0 @@
-/* This file is generated by the genmloop script.  DO NOT EDIT! */
-
-/* Enable switch() support in cgen headers.  */
-#define SEM_IN_SWITCH
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "bfd.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-#include "sim-assert.h"
-
-/* Fill in the administrative ARGBUF fields required by all insns,
-   virtual and real.  */
-
-static INLINE void
-sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
-		    PCADDR pc, int fast_p)
-{
-#if WITH_SCACHE
-  SEM_SET_CODE (abuf, idesc, fast_p);
-  ARGBUF_ADDR (abuf) = pc;
-#endif
-  ARGBUF_IDESC (abuf) = idesc;
-}
-
-/* Fill in tracing/profiling fields of an ARGBUF.  */
-
-static INLINE void
-sh64_media_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
-		       int trace_p, int profile_p)
-{
-  ARGBUF_TRACE_P (abuf) = trace_p;
-  ARGBUF_PROFILE_P (abuf) = profile_p;
-}
-
-#if WITH_SCACHE_PBB
-
-/* Emit the "x-before" handler.
-   x-before is emitted before each insn (serial or parallel).
-   This is as opposed to x-after which is only emitted at the end of a group
-   of parallel insns.  */
-
-static INLINE void
-sh64_media_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
-{
-  ARGBUF *abuf = &sc[0].argbuf;
-  const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
-
-  abuf->fields.before.first_p = first_p;
-  sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
-  /* no need to set trace_p,profile_p */
-}
-
-/* Emit the "x-after" handler.
-   x-after is emitted after a serial insn or at the end of a group of
-   parallel insns.  */
-
-static INLINE void
-sh64_media_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
-{
-  ARGBUF *abuf = &sc[0].argbuf;
-  const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
-
-  sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
-  /* no need to set trace_p,profile_p */
-}
-
-#endif /* WITH_SCACHE_PBB */
-
-
-static INLINE const IDESC *
-extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
-         int fast_p)
-{
-  const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
-
-  sh64_media_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  if (! fast_p)
-    {
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      sh64_media_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
-    }
-  return id;
-}
-
-static INLINE SEM_PC
-execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
-{
-  SEM_PC vpc;
-
-  if (fast_p)
-    {
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
-#endif
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FAST */
-    }
-  else
-    {
-#if ! WITH_SEM_SWITCH_FULL
-      ARGBUF *abuf = &sc->argbuf;
-      const IDESC *idesc = abuf->idesc;
-#if WITH_SCACHE_PBB
-      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
-#else
-      int virtual_p = 0;
-#endif
-
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-before */
-	  if (ARGBUF_PROFILE_P (abuf))
-	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
-	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    sh64_media_model_insn_before (current_cpu, 1 /*first_p*/);
-	  TRACE_INSN_INIT (current_cpu, abuf, 1);
-	  TRACE_INSN (current_cpu, idesc->idata,
-		      (const struct argbuf *) abuf, abuf->addr);
-	}
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
-#endif
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-after */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    {
-	      int cycles;
-
-	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
-	      sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
-	    }
-	  TRACE_INSN_FINI (current_cpu, abuf, 1);
-	}
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FULL */
-    }
-
-  return vpc;
-}
-
-
-/* Record address of cti terminating a pbb.  */
-#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
-/* Record number of [real] insns in pbb.  */
-#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
-
-/* Fetch and extract a pseudo-basic-block.
-   FAST_P is non-zero if no tracing/profiling/etc. is wanted.  */
-
-INLINE SEM_PC
-sh64_media_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
-{
-  SEM_PC new_vpc;
-  PCADDR pc;
-  SCACHE *sc;
-  int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
-
-  pc = GET_H_PC ();
-
-  new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
-  if (! new_vpc)
-    {
-      /* Leading '_' to avoid collision with mainloop.in.  */
-      int _insn_count = 0;
-      SCACHE *orig_sc = sc;
-      SCACHE *_cti_sc = NULL;
-      int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
-
-      /* First figure out how many instructions to compile.
-	 MAX_INSNS is the size of the allocated buffer, which includes space
-	 for before/after handlers if they're being used.
-	 SLICE_INSNS is the maxinum number of real insns that can be
-	 executed.  Zero means "as many as we want".  */
-      /* ??? max_insns is serving two incompatible roles.
-	 1) Number of slots available in scache buffer.
-	 2) Number of real insns to execute.
-	 They're incompatible because there are virtual insns emitted too
-	 (chain,cti-chain,before,after handlers).  */
-
-      if (slice_insns == 1)
-	{
-	  /* No need to worry about extra slots required for virtual insns
-	     and parallel exec support because MAX_CHAIN_LENGTH is
-	     guaranteed to be big enough to execute at least 1 insn!  */
-	  max_insns = 1;
-	}
-      else
-	{
-	  /* Allow enough slop so that while compiling insns, if max_insns > 0
-	     then there's guaranteed to be enough space to emit one real insn.
-	     MAX_CHAIN_LENGTH is typically much longer than
-	     the normal number of insns between cti's anyway.  */
-	  max_insns -= (1 /* one for the trailing chain insn */
-			+ (FAST_P
-			   ? 0
-			   : (1 + MAX_PARALLEL_INSNS) /* before+after */)
-			+ (MAX_PARALLEL_INSNS > 1
-			   ? (MAX_PARALLEL_INSNS * 2)
-			   : 0));
-
-	  /* Account for before/after handlers.  */
-	  if (! FAST_P)
-	    slice_insns *= 3;
-
-	  if (slice_insns > 0
-	      && slice_insns < max_insns)
-	    max_insns = slice_insns;
-	}
-
-      new_vpc = sc;
-
-      /* SC,PC must be updated to point passed the last entry used.
-	 SET_CTI_VPC must be called if pbb is terminated by a cti.
-	 SET_INSN_COUNT must be called to record number of real insns in
-	 pbb [could be computed by us of course, extra cpu but perhaps
-	 negligible enough].  */
-
-/* begin extract-pbb */
-{
-  const IDESC *idesc;
-  int icount = 0;
-
- while (max_insns > 0)
-    {
-      USI insn = GETIMEMUSI (current_cpu, pc);
-      
-      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
-      SEM_SKIP_COMPILE (current_cpu, sc, 1);
-      ++sc;
-      --max_insns;
-      ++icount;
-      pc += idesc->length;
-
-      if (IDESC_CTI_P (idesc))
-        {
-          SET_CTI_VPC (sc - 1);
-
-          if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
-            {
-              USI insn = GETIMEMUSI (current_cpu, pc);
-	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
-
-              ++sc;
-	      --max_insns;
-	      ++icount;
-	      pc += idesc->length;
-            }
-	  break;
-        }
-    }
-
- Finish:
-  SET_INSN_COUNT (icount);
-}
-/* end extract-pbb */
-
-      /* The last one is a pseudo-insn to link to the next chain.
-	 It is also used to record the insn count for this chain.  */
-      {
-	const IDESC *id;
-
-	/* Was pbb terminated by a cti?  */
-	if (_cti_sc)
-	  {
-	    id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CTI_CHAIN];
-	  }
-	else
-	  {
-	    id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CHAIN];
-	  }
-	SEM_SET_CODE (&sc->argbuf, id, FAST_P);
-	sc->argbuf.idesc = id;
-	sc->argbuf.addr = pc;
-	sc->argbuf.fields.chain.insn_count = _insn_count;
-	sc->argbuf.fields.chain.next = 0;
-	sc->argbuf.fields.chain.branch_target = 0;
-	++sc;
-      }
-
-      /* Update the pointer to the next free entry, may not have used as
-	 many entries as was asked for.  */
-      CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
-      /* Record length of chain if profiling.
-	 This includes virtual insns since they count against
-	 max_insns too.  */
-      if (! FAST_P)
-	PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
-    }
-
-  return new_vpc;
-}
-
-/* Chain to the next block from a non-cti terminated previous block.  */
-
-INLINE SEM_PC
-sh64_media_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-
-  PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
-
-  SET_H_PC (abuf->addr | 1);
-
-  /* If not running forever, exit back to main loop.  */
-  if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
-      /* Also exit back to main loop if there's an event.
-         Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
-	 at the "right" time, but then that was what was asked for.
-	 There is no silver bullet for simulator engines.
-         ??? Clearly this needs a cleaner interface.
-	 At present it's just so Ctrl-C works.  */
-      || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
-    CPU_RUNNING_P (current_cpu) = 0;
-
-  /* If chained to next block, go straight to it.  */
-  if (abuf->fields.chain.next)
-    return abuf->fields.chain.next;
-  /* See if next block has already been compiled.  */
-  abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
-  if (abuf->fields.chain.next)
-    return abuf->fields.chain.next;
-  /* Nope, so next insn is a virtual insn to invoke the compiler
-     (begin a pbb).  */
-  return CPU_SCACHE_PBB_BEGIN (current_cpu);
-}
-
-/* Chain to the next block from a cti terminated previous block.
-   BR_TYPE indicates whether the branch was taken and whether we can cache
-   the vpc of the branch target.
-   NEW_PC is the target's branch address, and is only valid if
-   BR_TYPE != SEM_BRANCH_UNTAKEN.  */
-
-INLINE SEM_PC
-sh64_media_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
-		     SEM_BRANCH_TYPE br_type, PCADDR new_pc)
-{
-  SEM_PC *new_vpc_ptr;
-
-  PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
-
-  /* If we have switched ISAs, exit back to main loop.
-     Set idesc to 0 to cause the engine to point to the right insn table.  */
-  if ((new_pc & 1) == 0)
-  {
-    /* Switch to SHcompact.  */
-    CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
-    CPU_RUNNING_P (current_cpu) = 0;
-  }
-  
-  /* If not running forever, exit back to main loop.  */
-  if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
-      /* Also exit back to main loop if there's an event.
-         Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
-	 at the "right" time, but then that was what was asked for.
-	 There is no silver bullet for simulator engines.
-         ??? Clearly this needs a cleaner interface.
-	 At present it's just so Ctrl-C works.  */
-      || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
-    CPU_RUNNING_P (current_cpu) = 0;
-
-  /* Restart compiler if we branched to an uncacheable address
-     (e.g. "j reg").  */
-  if (br_type == SEM_BRANCH_UNCACHEABLE)
-    {
-      SET_H_PC (new_pc);
-      return CPU_SCACHE_PBB_BEGIN (current_cpu);
-    }
-
-  /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
-     next chain ptr.  */
-  if (br_type == SEM_BRANCH_UNTAKEN)
-    {
-      ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-      new_pc = abuf->addr;
-      /* Set bit 0 to stay in SHmedia mode.  */
-      SET_H_PC (new_pc | 1);
-      new_vpc_ptr = &abuf->fields.chain.next;
-    }
-  else
-    {
-      ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-      SET_H_PC (new_pc);
-      new_vpc_ptr = &abuf->fields.chain.branch_target;
-    }
-
-  /* If chained to next block, go straight to it.  */
-  if (*new_vpc_ptr)
-    return *new_vpc_ptr;
-  /* See if next block has already been compiled.  */
-  *new_vpc_ptr = scache_lookup (current_cpu, new_pc);
-  if (*new_vpc_ptr)
-    return *new_vpc_ptr;
-  /* Nope, so next insn is a virtual insn to invoke the compiler
-     (begin a pbb).  */
-  return CPU_SCACHE_PBB_BEGIN (current_cpu);
-}
-
-/* x-before handler.
-   This is called before each insn.  */
-
-void
-sh64_media_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
-{
-  SEM_ARG sem_arg = sc;
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int first_p = abuf->fields.before.first_p;
-  const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
-  const IDESC *cur_idesc = cur_abuf->idesc;
-  PCADDR pc = cur_abuf->addr;
-
-  if (ARGBUF_PROFILE_P (cur_abuf))
-    PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
-
-  /* If this isn't the first insn, finish up the previous one.  */
-
-  if (! first_p)
-    {
-      if (PROFILE_MODEL_P (current_cpu))
-	{
-	  const SEM_ARG prev_sem_arg = sc - 1;
-	  const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
-	  const IDESC *prev_idesc = prev_abuf->idesc;
-	  int cycles;
-
-	  /* ??? May want to measure all insns if doing insn tracing.  */
-	  if (ARGBUF_PROFILE_P (prev_abuf))
-	    {
-	      cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
-	      sh64_media_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
-	    }
-	}
-
-      TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
-    }
-
-  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
-  if (PROFILE_MODEL_P (current_cpu)
-      && ARGBUF_PROFILE_P (cur_abuf))
-    sh64_media_model_insn_before (current_cpu, first_p);
-
-  TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
-  TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
-}
-
-/* x-after handler.
-   This is called after a serial insn or at the end of a group of parallel
-   insns.  */
-
-void
-sh64_media_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
-{
-  SEM_ARG sem_arg = sc;
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  const SEM_ARG prev_sem_arg = sc - 1;
-  const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
-
-  /* ??? May want to measure all insns if doing insn tracing.  */
-  if (PROFILE_MODEL_P (current_cpu)
-      && ARGBUF_PROFILE_P (prev_abuf))
-    {
-      const IDESC *prev_idesc = prev_abuf->idesc;
-      int cycles;
-
-      cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
-      sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
-    }
-  TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
-}
-
-#define FAST_P 0
-
-void
-sh64_media_engine_run_full (SIM_CPU *current_cpu)
-{
-  SIM_DESC current_state = CPU_STATE (current_cpu);
-  SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
-  /* virtual program counter */
-  SEM_PC vpc;
-#if WITH_SEM_SWITCH_FULL
-  /* For communication between cti's and cti-chain.  */
-  SEM_BRANCH_TYPE pbb_br_type;
-  PCADDR pbb_br_npc;
-#endif
-
-
-  if (! CPU_IDESC_SEM_INIT_P (current_cpu))
-    {
-      /* ??? 'twould be nice to move this up a level and only call it once.
-	 On the other hand, in the "let's go fast" case the test is only done
-	 once per pbb (since we only return to the main loop at the end of
-	 a pbb).  And in the "let's run until we're done" case we don't return
-	 until the program exits.  */
-
-#if WITH_SEM_SWITCH_FULL
-#if defined (__GNUC__)
-/* ??? Later maybe paste sem-switch.c in when building mainloop.c.  */
-#define DEFINE_LABELS
-#include "sem-media-switch.c"
-#endif
-#else
-      sh64_media_sem_init_idesc_table (current_cpu);
-#endif
-
-      /* Initialize the "begin (compile) a pbb" virtual insn.  */
-      vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
-      SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
-			 & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
-      vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
-
-      CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
-    }
-
-  CPU_RUNNING_P (current_cpu) = 1;
-  /* ??? In the case where we're returning to the main loop after every
-     pbb we don't want to call pbb_begin each time (which hashes on the pc
-     and does a table lookup).  A way to speed this up is to save vpc
-     between calls.  */
-  vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
-
-  do
-    {
-/* begin full-exec-pbb */
-{
-#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
-#define DEFINE_SWITCH
-#define WITH_ISA_COMPACT
-#include "sem-media-switch.c"
-#else
-  vpc = execute (current_cpu, vpc, FAST_P);
-#endif
-}
-/* end full-exec-pbb */
-    }
-  while (CPU_RUNNING_P (current_cpu));
-}
-
-#undef FAST_P
-
-
-#define FAST_P 1
-
-void
-sh64_media_engine_run_fast (SIM_CPU *current_cpu)
-{
-  SIM_DESC current_state = CPU_STATE (current_cpu);
-  SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
-  /* virtual program counter */
-  SEM_PC vpc;
-#if WITH_SEM_SWITCH_FAST
-  /* For communication between cti's and cti-chain.  */
-  SEM_BRANCH_TYPE pbb_br_type;
-  PCADDR pbb_br_npc;
-#endif
-
-
-  if (! CPU_IDESC_SEM_INIT_P (current_cpu))
-    {
-      /* ??? 'twould be nice to move this up a level and only call it once.
-	 On the other hand, in the "let's go fast" case the test is only done
-	 once per pbb (since we only return to the main loop at the end of
-	 a pbb).  And in the "let's run until we're done" case we don't return
-	 until the program exits.  */
-
-#if WITH_SEM_SWITCH_FAST
-#if defined (__GNUC__)
-/* ??? Later maybe paste sem-switch.c in when building mainloop.c.  */
-#define DEFINE_LABELS
-#include "sem-media-switch.c"
-#endif
-#else
-      sh64_media_semf_init_idesc_table (current_cpu);
-#endif
-
-      /* Initialize the "begin (compile) a pbb" virtual insn.  */
-      vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
-      SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
-			 & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
-      vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
-
-      CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
-    }
-
-  CPU_RUNNING_P (current_cpu) = 1;
-  /* ??? In the case where we're returning to the main loop after every
-     pbb we don't want to call pbb_begin each time (which hashes on the pc
-     and does a table lookup).  A way to speed this up is to save vpc
-     between calls.  */
-  vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
-
-  do
-    {
-/* begin fast-exec-pbb */
-{
-#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
-#define DEFINE_SWITCH
-#define WITH_ISA_COMPACT
-#include "sem-media-switch.c"
-#else
-  vpc = execute (current_cpu, vpc, FAST_P);
-#endif
-}
-/* end fast-exec-pbb */
-    }
-  while (CPU_RUNNING_P (current_cpu));
-}
-
-#undef FAST_P
-
diff --git a/sim/sh64/sem-compact-switch.c b/sim/sh64/sem-compact-switch.c
deleted file mode 100644
index 59270e83905..00000000000
--- a/sim/sh64/sem-compact-switch.c
+++ /dev/null
@@ -1,4941 +0,0 @@
-/* Simulator instruction semantics for sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { SH64_COMPACT_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { SH64_COMPACT_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { SH64_COMPACT_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { SH64_COMPACT_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { SH64_COMPACT_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { SH64_COMPACT_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { SH64_COMPACT_INSN_ADD_COMPACT, && case_sem_INSN_ADD_COMPACT },
-    { SH64_COMPACT_INSN_ADDI_COMPACT, && case_sem_INSN_ADDI_COMPACT },
-    { SH64_COMPACT_INSN_ADDC_COMPACT, && case_sem_INSN_ADDC_COMPACT },
-    { SH64_COMPACT_INSN_ADDV_COMPACT, && case_sem_INSN_ADDV_COMPACT },
-    { SH64_COMPACT_INSN_AND_COMPACT, && case_sem_INSN_AND_COMPACT },
-    { SH64_COMPACT_INSN_ANDI_COMPACT, && case_sem_INSN_ANDI_COMPACT },
-    { SH64_COMPACT_INSN_ANDB_COMPACT, && case_sem_INSN_ANDB_COMPACT },
-    { SH64_COMPACT_INSN_BF_COMPACT, && case_sem_INSN_BF_COMPACT },
-    { SH64_COMPACT_INSN_BFS_COMPACT, && case_sem_INSN_BFS_COMPACT },
-    { SH64_COMPACT_INSN_BRA_COMPACT, && case_sem_INSN_BRA_COMPACT },
-    { SH64_COMPACT_INSN_BRAF_COMPACT, && case_sem_INSN_BRAF_COMPACT },
-    { SH64_COMPACT_INSN_BRK_COMPACT, && case_sem_INSN_BRK_COMPACT },
-    { SH64_COMPACT_INSN_BSR_COMPACT, && case_sem_INSN_BSR_COMPACT },
-    { SH64_COMPACT_INSN_BSRF_COMPACT, && case_sem_INSN_BSRF_COMPACT },
-    { SH64_COMPACT_INSN_BT_COMPACT, && case_sem_INSN_BT_COMPACT },
-    { SH64_COMPACT_INSN_BTS_COMPACT, && case_sem_INSN_BTS_COMPACT },
-    { SH64_COMPACT_INSN_CLRMAC_COMPACT, && case_sem_INSN_CLRMAC_COMPACT },
-    { SH64_COMPACT_INSN_CLRS_COMPACT, && case_sem_INSN_CLRS_COMPACT },
-    { SH64_COMPACT_INSN_CLRT_COMPACT, && case_sem_INSN_CLRT_COMPACT },
-    { SH64_COMPACT_INSN_CMPEQ_COMPACT, && case_sem_INSN_CMPEQ_COMPACT },
-    { SH64_COMPACT_INSN_CMPEQI_COMPACT, && case_sem_INSN_CMPEQI_COMPACT },
-    { SH64_COMPACT_INSN_CMPGE_COMPACT, && case_sem_INSN_CMPGE_COMPACT },
-    { SH64_COMPACT_INSN_CMPGT_COMPACT, && case_sem_INSN_CMPGT_COMPACT },
-    { SH64_COMPACT_INSN_CMPHI_COMPACT, && case_sem_INSN_CMPHI_COMPACT },
-    { SH64_COMPACT_INSN_CMPHS_COMPACT, && case_sem_INSN_CMPHS_COMPACT },
-    { SH64_COMPACT_INSN_CMPPL_COMPACT, && case_sem_INSN_CMPPL_COMPACT },
-    { SH64_COMPACT_INSN_CMPPZ_COMPACT, && case_sem_INSN_CMPPZ_COMPACT },
-    { SH64_COMPACT_INSN_CMPSTR_COMPACT, && case_sem_INSN_CMPSTR_COMPACT },
-    { SH64_COMPACT_INSN_DIV0S_COMPACT, && case_sem_INSN_DIV0S_COMPACT },
-    { SH64_COMPACT_INSN_DIV0U_COMPACT, && case_sem_INSN_DIV0U_COMPACT },
-    { SH64_COMPACT_INSN_DIV1_COMPACT, && case_sem_INSN_DIV1_COMPACT },
-    { SH64_COMPACT_INSN_DMULSL_COMPACT, && case_sem_INSN_DMULSL_COMPACT },
-    { SH64_COMPACT_INSN_DMULUL_COMPACT, && case_sem_INSN_DMULUL_COMPACT },
-    { SH64_COMPACT_INSN_DT_COMPACT, && case_sem_INSN_DT_COMPACT },
-    { SH64_COMPACT_INSN_EXTSB_COMPACT, && case_sem_INSN_EXTSB_COMPACT },
-    { SH64_COMPACT_INSN_EXTSW_COMPACT, && case_sem_INSN_EXTSW_COMPACT },
-    { SH64_COMPACT_INSN_EXTUB_COMPACT, && case_sem_INSN_EXTUB_COMPACT },
-    { SH64_COMPACT_INSN_EXTUW_COMPACT, && case_sem_INSN_EXTUW_COMPACT },
-    { SH64_COMPACT_INSN_FABS_COMPACT, && case_sem_INSN_FABS_COMPACT },
-    { SH64_COMPACT_INSN_FADD_COMPACT, && case_sem_INSN_FADD_COMPACT },
-    { SH64_COMPACT_INSN_FCMPEQ_COMPACT, && case_sem_INSN_FCMPEQ_COMPACT },
-    { SH64_COMPACT_INSN_FCMPGT_COMPACT, && case_sem_INSN_FCMPGT_COMPACT },
-    { SH64_COMPACT_INSN_FCNVDS_COMPACT, && case_sem_INSN_FCNVDS_COMPACT },
-    { SH64_COMPACT_INSN_FCNVSD_COMPACT, && case_sem_INSN_FCNVSD_COMPACT },
-    { SH64_COMPACT_INSN_FDIV_COMPACT, && case_sem_INSN_FDIV_COMPACT },
-    { SH64_COMPACT_INSN_FIPR_COMPACT, && case_sem_INSN_FIPR_COMPACT },
-    { SH64_COMPACT_INSN_FLDS_COMPACT, && case_sem_INSN_FLDS_COMPACT },
-    { SH64_COMPACT_INSN_FLDI0_COMPACT, && case_sem_INSN_FLDI0_COMPACT },
-    { SH64_COMPACT_INSN_FLDI1_COMPACT, && case_sem_INSN_FLDI1_COMPACT },
-    { SH64_COMPACT_INSN_FLOAT_COMPACT, && case_sem_INSN_FLOAT_COMPACT },
-    { SH64_COMPACT_INSN_FMAC_COMPACT, && case_sem_INSN_FMAC_COMPACT },
-    { SH64_COMPACT_INSN_FMOV1_COMPACT, && case_sem_INSN_FMOV1_COMPACT },
-    { SH64_COMPACT_INSN_FMOV2_COMPACT, && case_sem_INSN_FMOV2_COMPACT },
-    { SH64_COMPACT_INSN_FMOV3_COMPACT, && case_sem_INSN_FMOV3_COMPACT },
-    { SH64_COMPACT_INSN_FMOV4_COMPACT, && case_sem_INSN_FMOV4_COMPACT },
-    { SH64_COMPACT_INSN_FMOV5_COMPACT, && case_sem_INSN_FMOV5_COMPACT },
-    { SH64_COMPACT_INSN_FMOV6_COMPACT, && case_sem_INSN_FMOV6_COMPACT },
-    { SH64_COMPACT_INSN_FMOV7_COMPACT, && case_sem_INSN_FMOV7_COMPACT },
-    { SH64_COMPACT_INSN_FMUL_COMPACT, && case_sem_INSN_FMUL_COMPACT },
-    { SH64_COMPACT_INSN_FNEG_COMPACT, && case_sem_INSN_FNEG_COMPACT },
-    { SH64_COMPACT_INSN_FRCHG_COMPACT, && case_sem_INSN_FRCHG_COMPACT },
-    { SH64_COMPACT_INSN_FSCHG_COMPACT, && case_sem_INSN_FSCHG_COMPACT },
-    { SH64_COMPACT_INSN_FSQRT_COMPACT, && case_sem_INSN_FSQRT_COMPACT },
-    { SH64_COMPACT_INSN_FSTS_COMPACT, && case_sem_INSN_FSTS_COMPACT },
-    { SH64_COMPACT_INSN_FSUB_COMPACT, && case_sem_INSN_FSUB_COMPACT },
-    { SH64_COMPACT_INSN_FTRC_COMPACT, && case_sem_INSN_FTRC_COMPACT },
-    { SH64_COMPACT_INSN_FTRV_COMPACT, && case_sem_INSN_FTRV_COMPACT },
-    { SH64_COMPACT_INSN_JMP_COMPACT, && case_sem_INSN_JMP_COMPACT },
-    { SH64_COMPACT_INSN_JSR_COMPACT, && case_sem_INSN_JSR_COMPACT },
-    { SH64_COMPACT_INSN_LDC_COMPACT, && case_sem_INSN_LDC_COMPACT },
-    { SH64_COMPACT_INSN_LDCL_COMPACT, && case_sem_INSN_LDCL_COMPACT },
-    { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, && case_sem_INSN_LDS_FPSCR_COMPACT },
-    { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, && case_sem_INSN_LDSL_FPSCR_COMPACT },
-    { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, && case_sem_INSN_LDS_FPUL_COMPACT },
-    { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, && case_sem_INSN_LDSL_FPUL_COMPACT },
-    { SH64_COMPACT_INSN_LDS_MACH_COMPACT, && case_sem_INSN_LDS_MACH_COMPACT },
-    { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, && case_sem_INSN_LDSL_MACH_COMPACT },
-    { SH64_COMPACT_INSN_LDS_MACL_COMPACT, && case_sem_INSN_LDS_MACL_COMPACT },
-    { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, && case_sem_INSN_LDSL_MACL_COMPACT },
-    { SH64_COMPACT_INSN_LDS_PR_COMPACT, && case_sem_INSN_LDS_PR_COMPACT },
-    { SH64_COMPACT_INSN_LDSL_PR_COMPACT, && case_sem_INSN_LDSL_PR_COMPACT },
-    { SH64_COMPACT_INSN_MACL_COMPACT, && case_sem_INSN_MACL_COMPACT },
-    { SH64_COMPACT_INSN_MACW_COMPACT, && case_sem_INSN_MACW_COMPACT },
-    { SH64_COMPACT_INSN_MOV_COMPACT, && case_sem_INSN_MOV_COMPACT },
-    { SH64_COMPACT_INSN_MOVI_COMPACT, && case_sem_INSN_MOVI_COMPACT },
-    { SH64_COMPACT_INSN_MOVB1_COMPACT, && case_sem_INSN_MOVB1_COMPACT },
-    { SH64_COMPACT_INSN_MOVB2_COMPACT, && case_sem_INSN_MOVB2_COMPACT },
-    { SH64_COMPACT_INSN_MOVB3_COMPACT, && case_sem_INSN_MOVB3_COMPACT },
-    { SH64_COMPACT_INSN_MOVB4_COMPACT, && case_sem_INSN_MOVB4_COMPACT },
-    { SH64_COMPACT_INSN_MOVB5_COMPACT, && case_sem_INSN_MOVB5_COMPACT },
-    { SH64_COMPACT_INSN_MOVB6_COMPACT, && case_sem_INSN_MOVB6_COMPACT },
-    { SH64_COMPACT_INSN_MOVB7_COMPACT, && case_sem_INSN_MOVB7_COMPACT },
-    { SH64_COMPACT_INSN_MOVB8_COMPACT, && case_sem_INSN_MOVB8_COMPACT },
-    { SH64_COMPACT_INSN_MOVB9_COMPACT, && case_sem_INSN_MOVB9_COMPACT },
-    { SH64_COMPACT_INSN_MOVB10_COMPACT, && case_sem_INSN_MOVB10_COMPACT },
-    { SH64_COMPACT_INSN_MOVL1_COMPACT, && case_sem_INSN_MOVL1_COMPACT },
-    { SH64_COMPACT_INSN_MOVL2_COMPACT, && case_sem_INSN_MOVL2_COMPACT },
-    { SH64_COMPACT_INSN_MOVL3_COMPACT, && case_sem_INSN_MOVL3_COMPACT },
-    { SH64_COMPACT_INSN_MOVL4_COMPACT, && case_sem_INSN_MOVL4_COMPACT },
-    { SH64_COMPACT_INSN_MOVL5_COMPACT, && case_sem_INSN_MOVL5_COMPACT },
-    { SH64_COMPACT_INSN_MOVL6_COMPACT, && case_sem_INSN_MOVL6_COMPACT },
-    { SH64_COMPACT_INSN_MOVL7_COMPACT, && case_sem_INSN_MOVL7_COMPACT },
-    { SH64_COMPACT_INSN_MOVL8_COMPACT, && case_sem_INSN_MOVL8_COMPACT },
-    { SH64_COMPACT_INSN_MOVL9_COMPACT, && case_sem_INSN_MOVL9_COMPACT },
-    { SH64_COMPACT_INSN_MOVL10_COMPACT, && case_sem_INSN_MOVL10_COMPACT },
-    { SH64_COMPACT_INSN_MOVL11_COMPACT, && case_sem_INSN_MOVL11_COMPACT },
-    { SH64_COMPACT_INSN_MOVW1_COMPACT, && case_sem_INSN_MOVW1_COMPACT },
-    { SH64_COMPACT_INSN_MOVW2_COMPACT, && case_sem_INSN_MOVW2_COMPACT },
-    { SH64_COMPACT_INSN_MOVW3_COMPACT, && case_sem_INSN_MOVW3_COMPACT },
-    { SH64_COMPACT_INSN_MOVW4_COMPACT, && case_sem_INSN_MOVW4_COMPACT },
-    { SH64_COMPACT_INSN_MOVW5_COMPACT, && case_sem_INSN_MOVW5_COMPACT },
-    { SH64_COMPACT_INSN_MOVW6_COMPACT, && case_sem_INSN_MOVW6_COMPACT },
-    { SH64_COMPACT_INSN_MOVW7_COMPACT, && case_sem_INSN_MOVW7_COMPACT },
-    { SH64_COMPACT_INSN_MOVW8_COMPACT, && case_sem_INSN_MOVW8_COMPACT },
-    { SH64_COMPACT_INSN_MOVW9_COMPACT, && case_sem_INSN_MOVW9_COMPACT },
-    { SH64_COMPACT_INSN_MOVW10_COMPACT, && case_sem_INSN_MOVW10_COMPACT },
-    { SH64_COMPACT_INSN_MOVW11_COMPACT, && case_sem_INSN_MOVW11_COMPACT },
-    { SH64_COMPACT_INSN_MOVA_COMPACT, && case_sem_INSN_MOVA_COMPACT },
-    { SH64_COMPACT_INSN_MOVCAL_COMPACT, && case_sem_INSN_MOVCAL_COMPACT },
-    { SH64_COMPACT_INSN_MOVT_COMPACT, && case_sem_INSN_MOVT_COMPACT },
-    { SH64_COMPACT_INSN_MULL_COMPACT, && case_sem_INSN_MULL_COMPACT },
-    { SH64_COMPACT_INSN_MULSW_COMPACT, && case_sem_INSN_MULSW_COMPACT },
-    { SH64_COMPACT_INSN_MULUW_COMPACT, && case_sem_INSN_MULUW_COMPACT },
-    { SH64_COMPACT_INSN_NEG_COMPACT, && case_sem_INSN_NEG_COMPACT },
-    { SH64_COMPACT_INSN_NEGC_COMPACT, && case_sem_INSN_NEGC_COMPACT },
-    { SH64_COMPACT_INSN_NOP_COMPACT, && case_sem_INSN_NOP_COMPACT },
-    { SH64_COMPACT_INSN_NOT_COMPACT, && case_sem_INSN_NOT_COMPACT },
-    { SH64_COMPACT_INSN_OCBI_COMPACT, && case_sem_INSN_OCBI_COMPACT },
-    { SH64_COMPACT_INSN_OCBP_COMPACT, && case_sem_INSN_OCBP_COMPACT },
-    { SH64_COMPACT_INSN_OCBWB_COMPACT, && case_sem_INSN_OCBWB_COMPACT },
-    { SH64_COMPACT_INSN_OR_COMPACT, && case_sem_INSN_OR_COMPACT },
-    { SH64_COMPACT_INSN_ORI_COMPACT, && case_sem_INSN_ORI_COMPACT },
-    { SH64_COMPACT_INSN_ORB_COMPACT, && case_sem_INSN_ORB_COMPACT },
-    { SH64_COMPACT_INSN_PREF_COMPACT, && case_sem_INSN_PREF_COMPACT },
-    { SH64_COMPACT_INSN_ROTCL_COMPACT, && case_sem_INSN_ROTCL_COMPACT },
-    { SH64_COMPACT_INSN_ROTCR_COMPACT, && case_sem_INSN_ROTCR_COMPACT },
-    { SH64_COMPACT_INSN_ROTL_COMPACT, && case_sem_INSN_ROTL_COMPACT },
-    { SH64_COMPACT_INSN_ROTR_COMPACT, && case_sem_INSN_ROTR_COMPACT },
-    { SH64_COMPACT_INSN_RTS_COMPACT, && case_sem_INSN_RTS_COMPACT },
-    { SH64_COMPACT_INSN_SETS_COMPACT, && case_sem_INSN_SETS_COMPACT },
-    { SH64_COMPACT_INSN_SETT_COMPACT, && case_sem_INSN_SETT_COMPACT },
-    { SH64_COMPACT_INSN_SHAD_COMPACT, && case_sem_INSN_SHAD_COMPACT },
-    { SH64_COMPACT_INSN_SHAL_COMPACT, && case_sem_INSN_SHAL_COMPACT },
-    { SH64_COMPACT_INSN_SHAR_COMPACT, && case_sem_INSN_SHAR_COMPACT },
-    { SH64_COMPACT_INSN_SHLD_COMPACT, && case_sem_INSN_SHLD_COMPACT },
-    { SH64_COMPACT_INSN_SHLL_COMPACT, && case_sem_INSN_SHLL_COMPACT },
-    { SH64_COMPACT_INSN_SHLL2_COMPACT, && case_sem_INSN_SHLL2_COMPACT },
-    { SH64_COMPACT_INSN_SHLL8_COMPACT, && case_sem_INSN_SHLL8_COMPACT },
-    { SH64_COMPACT_INSN_SHLL16_COMPACT, && case_sem_INSN_SHLL16_COMPACT },
-    { SH64_COMPACT_INSN_SHLR_COMPACT, && case_sem_INSN_SHLR_COMPACT },
-    { SH64_COMPACT_INSN_SHLR2_COMPACT, && case_sem_INSN_SHLR2_COMPACT },
-    { SH64_COMPACT_INSN_SHLR8_COMPACT, && case_sem_INSN_SHLR8_COMPACT },
-    { SH64_COMPACT_INSN_SHLR16_COMPACT, && case_sem_INSN_SHLR16_COMPACT },
-    { SH64_COMPACT_INSN_STC_GBR_COMPACT, && case_sem_INSN_STC_GBR_COMPACT },
-    { SH64_COMPACT_INSN_STCL_GBR_COMPACT, && case_sem_INSN_STCL_GBR_COMPACT },
-    { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, && case_sem_INSN_STS_FPSCR_COMPACT },
-    { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, && case_sem_INSN_STSL_FPSCR_COMPACT },
-    { SH64_COMPACT_INSN_STS_FPUL_COMPACT, && case_sem_INSN_STS_FPUL_COMPACT },
-    { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, && case_sem_INSN_STSL_FPUL_COMPACT },
-    { SH64_COMPACT_INSN_STS_MACH_COMPACT, && case_sem_INSN_STS_MACH_COMPACT },
-    { SH64_COMPACT_INSN_STSL_MACH_COMPACT, && case_sem_INSN_STSL_MACH_COMPACT },
-    { SH64_COMPACT_INSN_STS_MACL_COMPACT, && case_sem_INSN_STS_MACL_COMPACT },
-    { SH64_COMPACT_INSN_STSL_MACL_COMPACT, && case_sem_INSN_STSL_MACL_COMPACT },
-    { SH64_COMPACT_INSN_STS_PR_COMPACT, && case_sem_INSN_STS_PR_COMPACT },
-    { SH64_COMPACT_INSN_STSL_PR_COMPACT, && case_sem_INSN_STSL_PR_COMPACT },
-    { SH64_COMPACT_INSN_SUB_COMPACT, && case_sem_INSN_SUB_COMPACT },
-    { SH64_COMPACT_INSN_SUBC_COMPACT, && case_sem_INSN_SUBC_COMPACT },
-    { SH64_COMPACT_INSN_SUBV_COMPACT, && case_sem_INSN_SUBV_COMPACT },
-    { SH64_COMPACT_INSN_SWAPB_COMPACT, && case_sem_INSN_SWAPB_COMPACT },
-    { SH64_COMPACT_INSN_SWAPW_COMPACT, && case_sem_INSN_SWAPW_COMPACT },
-    { SH64_COMPACT_INSN_TASB_COMPACT, && case_sem_INSN_TASB_COMPACT },
-    { SH64_COMPACT_INSN_TRAPA_COMPACT, && case_sem_INSN_TRAPA_COMPACT },
-    { SH64_COMPACT_INSN_TST_COMPACT, && case_sem_INSN_TST_COMPACT },
-    { SH64_COMPACT_INSN_TSTI_COMPACT, && case_sem_INSN_TSTI_COMPACT },
-    { SH64_COMPACT_INSN_TSTB_COMPACT, && case_sem_INSN_TSTB_COMPACT },
-    { SH64_COMPACT_INSN_XOR_COMPACT, && case_sem_INSN_XOR_COMPACT },
-    { SH64_COMPACT_INSN_XORI_COMPACT, && case_sem_INSN_XORI_COMPACT },
-    { SH64_COMPACT_INSN_XORB_COMPACT, && case_sem_INSN_XORB_COMPACT },
-    { SH64_COMPACT_INSN_XTRCT_COMPACT, && case_sem_INSN_XTRCT_COMPACT },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-    {
-#if FAST_P
-      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-    }
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    sh64_compact_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    sh64_compact_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-#ifdef DEFINE_SWITCH
-    vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    vpc = sh64_compact_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = sh64_compact_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD_COMPACT) : /* add $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI_COMPACT) : /* add #$imm8, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDC_COMPACT) : /* addc $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV_COMPACT) : /* addv $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_t;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND_COMPACT) : /* and $rm64, $rn64 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ANDI_COMPACT) : /* and #$uimm8, r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ANDB_COMPACT) : /* and.b #$imm8, @(r0, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BF_COMPACT) : /* bf $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_TBIT ())) {
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BFS_COMPACT) : /* bf/s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_TBIT ())) {
-{
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA_COMPACT) : /* bra $disp12 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = FLD (i_disp12);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRAF_COMPACT) : /* braf $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRK_COMPACT) : /* brk */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-sh64_break (current_cpu, pc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BSR_COMPACT) : /* bsr $disp12 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = FLD (i_disp12);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BSRF_COMPACT) : /* bsrf $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BT_COMPACT) : /* bt $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_TBIT ()) {
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BTS_COMPACT) : /* bt/s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_TBIT ()) {
-{
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRMAC_COMPACT) : /* clrmac */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = 0;
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-  {
-    SI opval = 0;
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRS_COMPACT) : /* clrs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 0;
-    SET_H_SBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRT_COMPACT) : /* clrt */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 0;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQ_COMPACT) : /* cmp/eq $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQI_COMPACT) : /* cmp/eq #$imm8, r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPGE_COMPACT) : /* cmp/ge $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPGT_COMPACT) : /* cmp/gt $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPHI_COMPACT) : /* cmp/hi $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPHS_COMPACT) : /* cmp/hs $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPPL_COMPACT) : /* cmp/pl $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPPZ_COMPACT) : /* cmp/pz $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPSTR_COMPACT) : /* cmp/str $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  SI tmp_temp;
-  tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-  tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t);
-  {
-    BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV0S_COMPACT) : /* div0s $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31);
-    SET_H_MBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
-  }
-  {
-    BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV0U_COMPACT) : /* div0u */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 0;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-  {
-    BI opval = 0;
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    BI opval = 0;
-    SET_H_MBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV1_COMPACT) : /* div1 $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_oldq;
-  SI tmp_tmp0;
-  UQI tmp_tmp1;
-  tmp_oldq = GET_H_QBIT ();
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ()));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (NOTBI (tmp_oldq)) {
-if (NOTBI (GET_H_MBIT ())) {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-} else {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-}
-} else {
-if (NOTBI (GET_H_MBIT ())) {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-} else {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-}
-}
-  {
-    BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DMULSL_COMPACT) : /* dmuls.l $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_result;
-  tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn))));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DMULUL_COMPACT) : /* dmulu.l $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_result;
-  tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn))));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DT_COMPACT) : /* dt $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_EXTSB_COMPACT) : /* exts.b $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_EXTSW_COMPACT) : /* exts.w $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_EXTUB_COMPACT) : /* extu.b $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_EXTUW_COMPACT) : /* extu.w $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FABS_COMPACT) : /* fabs $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FADD_COMPACT) : /* fadd $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPEQ_COMPACT) : /* fcmp/eq $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPGT_COMPACT) : /* fcmp/gt $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCNVDS_COMPACT) : /* fcnvds $drn, fpul */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCNVSD_COMPACT) : /* fcnvsd fpul, $drn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_DRC (FLD (f_dn), opval);
-    TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FDIV_COMPACT) : /* fdiv $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FIPR_COMPACT) : /* fipr $fvm, $fvn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_m;
-  QI tmp_n;
-  SF tmp_res;
-  tmp_m = FLD (f_vm);
-  tmp_n = FLD (f_vn);
-  tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn)));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 3), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = GET_H_FRC (FLD (f_rn));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDI0_COMPACT) : /* fldi0 $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fldi0 (current_cpu);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDI1_COMPACT) : /* fldi1 $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fldi1 (current_cpu);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLOAT_COMPACT) : /* float fpul, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMAC_COMPACT) : /* fmac fr0, $frm, $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $frm, $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-{
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-} else {
-{
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $frm, @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $frm, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-} else {
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $frm, @(r0, $rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMUL_COMPACT) : /* fmul $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FNEG_COMPACT) : /* fneg $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FRCHG_COMPACT) : /* frchg */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = NOTBI (GET_H_FRBIT ());
-    SET_H_FRBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSCHG_COMPACT) : /* fschg */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = NOTBI (GET_H_SZBIT ());
-    SET_H_SZBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSQRT_COMPACT) : /* fsqrt $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTS_COMPACT) : /* fsts fpul, $frn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = CPU (h_fr[((UINT) 32)]);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSUB_COMPACT) : /* fsub $fsdm, $fsdn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRC_COMPACT) : /* ftrc $fsdn, fpul */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn)))));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRV_COMPACT) : /* ftrv xmtrx, $fvn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_n;
-  SF tmp_res;
-  tmp_n = FLD (f_vn);
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (tmp_n, opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 2), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 3), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP_COMPACT) : /* jmp @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = GET_H_GRC (FLD (f_rn));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JSR_COMPACT) : /* jsr @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = GET_H_GRC (FLD (f_rn));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDC_COMPACT) : /* ldc $rn, gbr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_GBR (opval);
-    TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDCL_COMPACT) : /* ldc.l @${rn}+, gbr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_GBR (opval);
-    TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDS_FPSCR_COMPACT) : /* lds $rn, fpscr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_FPCCR (opval);
-    TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDSL_FPSCR_COMPACT) : /* lds.l @${rn}+, fpscr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_FPCCR (opval);
-    TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDS_FPUL_COMPACT) : /* lds $rn, fpul */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDSL_FPUL_COMPACT) : /* lds.l @${rn}+, fpul */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDS_MACH_COMPACT) : /* lds $rn, mach */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDSL_MACH_COMPACT) : /* lds.l @${rn}+, mach */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDS_MACL_COMPACT) : /* lds $rn, macl */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDSL_MACL_COMPACT) : /* lds.l @${rn}+, macl */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDS_PR_COMPACT) : /* lds $rn, pr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDSL_PR_COMPACT) : /* lds.l @${rn}+, pr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACL_COMPACT) : /* mac.l @${rm}+, @${rn}+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmpry;
-  DI tmp_mac;
-  DI tmp_result;
-  SI tmp_x;
-  SI tmp_y;
-  tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rn), FLD (f_rm))) {
-{
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-  tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-  tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y));
-  tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
-  tmp_result = ADDDI (tmp_mac, tmp_tmpry);
-{
-if (GET_H_SBIT ()) {
-{
-  SI tmp_min;
-  SI tmp_max;
-  tmp_max = SRLDI (INVDI (0), 16);
-  tmp_min = SRLDI (INVDI (0), 15);
-if (GTDI (tmp_result, tmp_max)) {
-  tmp_result = tmp_max;
-} else {
-if (LTDI (tmp_result, tmp_min)) {
-  tmp_result = tmp_min;
-}
-}
-}
-}
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACW_COMPACT) : /* mac.w @${rm}+, @${rn}+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_tmpry;
-  DI tmp_mac;
-  DI tmp_result;
-  HI tmp_x;
-  HI tmp_y;
-  tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rn), FLD (f_rm))) {
-{
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-  tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-  tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y));
-if (GET_H_SBIT ()) {
-{
-if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) {
-  {
-    SI opval = 1;
-    SET_H_MACH (opval);
-    written |= (1 << 9);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-}
-  {
-    SI opval = ADDSI (tmp_tmpry, GET_H_MACL ());
-    SET_H_MACL (opval);
-    written |= (1 << 10);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-} else {
-{
-  tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
-  tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    written |= (1 << 9);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    written |= (1 << 10);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOV_COMPACT) : /* mov $rm64, $rn64 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = GET_H_GR (FLD (f_rm));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVI_COMPACT) : /* mov #$imm8, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB1_COMPACT) : /* mov.b $rm, @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB2_COMPACT) : /* mov.b $rm, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB3_COMPACT) : /* mov.b $rm, @(r0,$rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB4_COMPACT) : /* mov.b r0, @($imm8, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8));
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB5_COMPACT) : /* mov.b r0, @($imm4, $rm) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4));
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB6_COMPACT) : /* mov.b @$rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB7_COMPACT) : /* mov.b @${rm}+, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_data;
-  tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = EXTQISI (tmp_data);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-  {
-    SI opval = EXTQISI (tmp_data);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB8_COMPACT) : /* mov.b @(r0, $rm), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB9_COMPACT) : /* mov.b @($imm8, gbr), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVB10_COMPACT) : /* mov.b @($imm4, $rm), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL1_COMPACT) : /* mov.l $rm, @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL2_COMPACT) : /* mov.l $rm, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL3_COMPACT) : /* mov.l $rm, @(r0, $rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL4_COMPACT) : /* mov.l r0, @($imm8x4, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (((UINT) 0));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL5_COMPACT) : /* mov.l $rm, @($imm4x4, $rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL6_COMPACT) : /* mov.l @$rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL7_COMPACT) : /* mov.l @${rm}+, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL8_COMPACT) : /* mov.l @(r0, $rm), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL9_COMPACT) : /* mov.l @($imm8x4, gbr), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL10_COMPACT) : /* mov.l @($imm8x4, pc), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVL11_COMPACT) : /* mov.l @($imm4x4, $rm), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW1_COMPACT) : /* mov.w $rm, @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW2_COMPACT) : /* mov.w $rm, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2);
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW3_COMPACT) : /* mov.w $rm, @(r0, $rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW4_COMPACT) : /* mov.w r0, @($imm8x2, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rn) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW6_COMPACT) : /* mov.w @$rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW7_COMPACT) : /* mov.w @${rm}+, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_data;
-  tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = EXTHISI (tmp_data);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-  {
-    SI opval = EXTHISI (tmp_data);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW8_COMPACT) : /* mov.w @(r0, $rm), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW9_COMPACT) : /* mov.w @($imm8x2, gbr), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW10_COMPACT) : /* mov.w @($imm8x2, pc), $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVW11_COMPACT) : /* mov.w @($imm4x2, $rm), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw11_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVA_COMPACT) : /* mova @($imm8x4, pc), r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVCAL_COMPACT) : /* movca.l r0, @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (((UINT) 0));
-    SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVT_COMPACT) : /* movt $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTBISI (GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULL_COMPACT) : /* mul.l $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULSW_COMPACT) : /* muls.w $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULUW_COMPACT) : /* mulu.w $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG_COMPACT) : /* neg $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEGC_COMPACT) : /* negc $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP_COMPACT) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT_COMPACT) : /* not $rm64, $rn64 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = INVDI (GET_H_GR (FLD (f_rm)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBI_COMPACT) : /* ocbi @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBP_COMPACT) : /* ocbp @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBWB_COMPACT) : /* ocbwb @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR_COMPACT) : /* or $rm64, $rn64 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ORI_COMPACT) : /* or #$uimm8, r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ORB_COMPACT) : /* or.b #$imm8, @(r0, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PREF_COMPACT) : /* pref @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ROTCL_COMPACT) : /* rotcl $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_temp;
-  tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_temp) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ROTCR_COMPACT) : /* rotcr $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_lsbit;
-  SI tmp_temp;
-  tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
-  tmp_temp = GET_H_TBIT ();
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_lsbit) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ROTL_COMPACT) : /* rotl $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_temp;
-  tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_temp) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ROTR_COMPACT) : /* rotr $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_lsbit;
-  SI tmp_temp;
-  tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
-  tmp_temp = tmp_lsbit;
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_lsbit) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTS_COMPACT) : /* rts */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = GET_H_PR ();
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETS_COMPACT) : /* sets */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 1;
-    SET_H_SBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETT_COMPACT) : /* sett */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 1;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHAD_COMPACT) : /* shad $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_shamt;
-  tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
-if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (NEQI (tmp_shamt, 0)) {
-  {
-    SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) {
-  {
-    SI opval = NEGSI (1);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-  {
-    SI opval = 0;
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHAL_COMPACT) : /* shal $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHAR_COMPACT) : /* shar $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLD_COMPACT) : /* shld $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_shamt;
-  tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
-if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (NEQI (tmp_shamt, 0)) {
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-  {
-    SI opval = 0;
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLL_COMPACT) : /* shll $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLL2_COMPACT) : /* shll2 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLL8_COMPACT) : /* shll8 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLL16_COMPACT) : /* shll16 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLR_COMPACT) : /* shlr $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLR2_COMPACT) : /* shlr2 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLR8_COMPACT) : /* shlr8 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLR16_COMPACT) : /* shlr16 $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STC_GBR_COMPACT) : /* stc gbr, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GBR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STCL_GBR_COMPACT) : /* stc.l gbr, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_GBR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STS_FPSCR_COMPACT) : /* sts fpscr, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_FPCCR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STSL_FPSCR_COMPACT) : /* sts.l fpscr, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_FPCCR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STS_FPUL_COMPACT) : /* sts fpul, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)]));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STSL_FPUL_COMPACT) : /* sts.l fpul, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SF opval = CPU (h_fr[((UINT) 32)]);
-    SETMEMSF (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STS_MACH_COMPACT) : /* sts mach, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_MACH ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STSL_MACH_COMPACT) : /* sts.l mach, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_MACH ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STS_MACL_COMPACT) : /* sts macl, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_MACL ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STSL_MACL_COMPACT) : /* sts.l macl, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_MACL ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STS_PR_COMPACT) : /* sts pr, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_PR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STSL_PR_COMPACT) : /* sts.l pr, @-$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_PR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB_COMPACT) : /* sub $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBC_COMPACT) : /* subc $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV_COMPACT) : /* subv $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SWAPB_COMPACT) : /* swap.b $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  UHI tmp_top_half;
-  UQI tmp_byte1;
-  UQI tmp_byte0;
-  tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0);
-  tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2);
-  tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3);
-  {
-    SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SWAPW_COMPACT) : /* swap.w $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TASB_COMPACT) : /* tas.b @$rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  UQI tmp_byte;
-  tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-  tmp_byte = ORQI (tmp_byte, 128);
-  {
-    UQI opval = tmp_byte;
-    SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAPA_COMPACT) : /* trapa #$uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-sh64_compact_trapa (current_cpu, FLD (f_imm8), pc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TST_COMPACT) : /* tst $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TSTI_COMPACT) : /* tst #$uimm8, r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TSTB_COMPACT) : /* tst.b #$imm8, @(r0, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  {
-    BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR_COMPACT) : /* xor $rm64, $rn64 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XORI_COMPACT) : /* xor #$uimm8, r0 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XORB_COMPACT) : /* xor.b #$imm8, @(r0, gbr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XTRCT_COMPACT) : /* xtrct $rm, $rn */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/sh64/sem-compact.c b/sim/sh64/sem-compact.c
deleted file mode 100644
index fae6877772a..00000000000
--- a/sim/sh64/sem-compact.c
+++ /dev/null
@@ -1,5290 +0,0 @@
-/* Simulator instruction semantics for sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-/* This is used so that we can compile two copies of the semantic code,
-   one with full feature support and one without that runs fast(er).
-   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */
-#if FAST_P
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#else
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
-#endif
-
-/* x-invalid: --invalid-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-after: --after-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    sh64_compact_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-before: --before-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    sh64_compact_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-cti-chain: --cti-chain-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-#ifdef DEFINE_SWITCH
-    vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-chain: --chain-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-    vpc = sh64_compact_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-begin: --begin-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_COMPACT
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = sh64_compact_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add-compact: add $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,add_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addi-compact: add #$imm8, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,addi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addc-compact: addc $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,addc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* addv-compact: addv $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,addv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_t;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* and-compact: and $rm64, $rn64 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,and_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* andi-compact: and #$uimm8, r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,andi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* andb-compact: and.b #$imm8, @(r0, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,andb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* bf-compact: bf $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_TBIT ())) {
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bfs-compact: bf/s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bfs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_TBIT ())) {
-{
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bra-compact: bra $disp12 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bra_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = FLD (i_disp12);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* braf-compact: braf $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,braf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* brk-compact: brk */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,brk_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-sh64_break (current_cpu, pc);
-
-  return vpc;
-#undef FLD
-}
-
-/* bsr-compact: bsr $disp12 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bra_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = FLD (i_disp12);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bsrf-compact: bsrf $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bsrf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bt-compact: bt $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_TBIT ()) {
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bts-compact: bt/s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,bts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bf_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_TBIT ()) {
-{
-  {
-    UDI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* clrmac-compact: clrmac */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,clrmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = 0;
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-  {
-    SI opval = 0;
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* clrs-compact: clrs */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,clrs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 0;
-    SET_H_SBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* clrt-compact: clrt */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,clrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 0;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpeq-compact: cmp/eq $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpeqi-compact: cmp/eq #$imm8, r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmpeqi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpge-compact: cmp/ge $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmpge_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpgt-compact: cmp/gt $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmphi-compact: cmp/hi $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmphi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmphs-compact: cmp/hs $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmphs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmppl-compact: cmp/pl $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmppl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmppz-compact: cmp/pz $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmppz_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpstr-compact: cmp/str $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,cmpstr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  SI tmp_temp;
-  tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-  tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t);
-  tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t);
-  {
-    BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* div0s-compact: div0s $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,div0s_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31);
-    SET_H_MBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
-  }
-  {
-    BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* div0u-compact: div0u */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,div0u_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 0;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-  {
-    BI opval = 0;
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    BI opval = 0;
-    SET_H_MBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* div1-compact: div1 $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,div1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_oldq;
-  SI tmp_tmp0;
-  UQI tmp_tmp1;
-  tmp_oldq = GET_H_QBIT ();
-  {
-    BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ()));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (NOTBI (tmp_oldq)) {
-if (NOTBI (GET_H_MBIT ())) {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-} else {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-}
-} else {
-if (NOTBI (GET_H_MBIT ())) {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-} else {
-{
-  tmp_tmp0 = GET_H_GRC (FLD (f_rn));
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
-if (NOTBI (GET_H_QBIT ())) {
-  {
-    BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = ((tmp_tmp1) ? (1) : (0));
-    SET_H_QBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
-  }
-}
-}
-}
-}
-  {
-    BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* dmulsl-compact: dmuls.l $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,dmulsl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_result;
-  tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn))));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* dmulul-compact: dmulu.l $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,dmulul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_result;
-  tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn))));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* dt-compact: dt $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,dt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0);
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* extsb-compact: exts.b $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,extsb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* extsw-compact: exts.w $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,extsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* extub-compact: extu.b $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,extub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* extuw-compact: extu.w $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,extuw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fabs-compact: fabs $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fabs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fadd-compact: fadd $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fadd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fcmpeq-compact: fcmp/eq $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fcmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fcmpgt-compact: fcmp/gt $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fcmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-} else {
-  {
-    BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_TBIT (opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fcnvds-compact: fcnvds $drn, fpul */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fcnvds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcnvsd-compact: fcnvsd fpul, $drn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fcnvsd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_DRC (FLD (f_dn), opval);
-    TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fdiv-compact: fdiv $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fdiv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fipr-compact: fipr $fvm, $fvn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fipr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_m;
-  QI tmp_n;
-  SF tmp_res;
-  tmp_m = FLD (f_vm);
-  tmp_n = FLD (f_vn);
-  tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn)));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 3), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* flds-compact: flds $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,flds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = GET_H_FRC (FLD (f_rn));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fldi0-compact: fldi0 $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fldi0_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fldi0 (current_cpu);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fldi1-compact: fldi1 $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fldi1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fldi1 (current_cpu);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* float-compact: float fpul, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,float_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)]));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmac-compact: fmac fr0, $frm, $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmov1-compact: fmov $frm, $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov2-compact: fmov @$rm, $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov3-compact: fmov @${rm}+, frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-{
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-} else {
-{
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov4-compact: fmov @(r0, $rm), $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov5-compact: fmov $frm, @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov6-compact: fmov $frm, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-} else {
-{
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmov7-compact: fmov $frm, @(r0, $rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmov7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (GET_H_SZBIT ())) {
-  {
-    SF opval = GET_H_FRC (FLD (f_rm));
-    SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
-  {
-    DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
-    SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-} else {
-  {
-    DF opval = GET_H_DR (FLD (f_rm));
-    SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fmul-compact: fmul $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fmul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fneg-compact: fneg $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fneg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* frchg-compact: frchg */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,frchg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = NOTBI (GET_H_FRBIT ());
-    SET_H_FRBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fschg-compact: fschg */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fschg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = NOTBI (GET_H_SZBIT ());
-    SET_H_SZBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fsqrt-compact: fsqrt $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fsqrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fsts-compact: fsts fpul, $frn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fsts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = CPU (h_fr[((UINT) 32)]);
-    SET_H_FRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fsub-compact: fsub $fsdm, $fsdn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,fsub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (GET_H_PRBIT ()) {
-  {
-    DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
-    SET_H_DR (FLD (f_rn), opval);
-    written |= (1 << 8);
-    TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
-  }
-} else {
-  {
-    SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
-    SET_H_FRC (FLD (f_rn), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* ftrc-compact: ftrc $fsdn, fpul */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ftrc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn)))));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrv-compact: ftrv xmtrx, $fvn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ftrv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fipr_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_n;
-  SF tmp_res;
-  tmp_n = FLD (f_vn);
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (tmp_n, opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 2), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval);
-  }
-  tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2))));
-  tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3))));
-  {
-    SF opval = tmp_res;
-    SET_H_FRC (ADDQI (tmp_n, 3), opval);
-    TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* jmp-compact: jmp @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,jmp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = GET_H_GRC (FLD (f_rn));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* jsr-compact: jsr @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,jsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-{
-  {
-    SI opval = ADDDI (pc, 4);
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    UDI opval = GET_H_GRC (FLD (f_rn));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* ldc-compact: ldc $rn, gbr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_GBR (opval);
-    TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldcl-compact: ldc.l @${rn}+, gbr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_GBR (opval);
-    TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* lds-fpscr-compact: lds $rn, fpscr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,lds_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_FPCCR (opval);
-    TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldsl-fpscr-compact: lds.l @${rn}+, fpscr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_FPCCR (opval);
-    TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* lds-fpul-compact: lds $rn, fpul */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,lds_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldsl-fpul-compact: lds.l @${rn}+, fpul */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    CPU (h_fr[((UINT) 32)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* lds-mach-compact: lds $rn, mach */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,lds_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldsl-mach-compact: lds.l @${rn}+, mach */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* lds-macl-compact: lds $rn, macl */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,lds_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldsl-macl-compact: lds.l @${rn}+, macl */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* lds-pr-compact: lds $rn, pr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,lds_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldsl-pr-compact: lds.l @${rn}+, pr */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ldsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-    SET_H_PR (opval);
-    TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* macl-compact: mac.l @${rm}+, @${rn}+ */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmpry;
-  DI tmp_mac;
-  DI tmp_result;
-  SI tmp_x;
-  SI tmp_y;
-  tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rn), FLD (f_rm))) {
-{
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-  tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-  tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y));
-  tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
-  tmp_result = ADDDI (tmp_mac, tmp_tmpry);
-{
-if (GET_H_SBIT ()) {
-{
-  SI tmp_min;
-  SI tmp_max;
-  tmp_max = SRLDI (INVDI (0), 16);
-  tmp_min = SRLDI (INVDI (0), 15);
-if (GTDI (tmp_result, tmp_max)) {
-  tmp_result = tmp_max;
-} else {
-if (LTDI (tmp_result, tmp_min)) {
-  tmp_result = tmp_min;
-}
-}
-}
-}
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* macw-compact: mac.w @${rm}+, @${rn}+ */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,macw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_tmpry;
-  DI tmp_mac;
-  DI tmp_result;
-  HI tmp_x;
-  HI tmp_y;
-  tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rn), FLD (f_rm))) {
-{
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-  tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 11);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-  tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y));
-if (GET_H_SBIT ()) {
-{
-if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) {
-  {
-    SI opval = 1;
-    SET_H_MACH (opval);
-    written |= (1 << 9);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-}
-  {
-    SI opval = ADDSI (tmp_tmpry, GET_H_MACL ());
-    SET_H_MACL (opval);
-    written |= (1 << 10);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-} else {
-{
-  tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
-  tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry));
-  {
-    SI opval = SUBWORDDISI (tmp_result, 0);
-    SET_H_MACH (opval);
-    written |= (1 << 9);
-    TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
-  }
-  {
-    SI opval = SUBWORDDISI (tmp_result, 1);
-    SET_H_MACL (opval);
-    written |= (1 << 10);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* mov-compact: mov $rm64, $rn64 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,mov_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = GET_H_GR (FLD (f_rm));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movi-compact: mov #$imm8, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb1-compact: mov.b $rm, @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb2-compact: mov.b $rm, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movb3-compact: mov.b $rm, @(r0,$rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
-    SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb4-compact: mov.b r0, @($imm8, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8));
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movb5-compact: mov.b r0, @($imm4, $rm) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4));
-  {
-    UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movb6-compact: mov.b @$rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb7-compact: mov.b @${rm}+, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_data;
-  tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = EXTQISI (tmp_data);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-  {
-    SI opval = EXTQISI (tmp_data);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* movb8-compact: mov.b @(r0, $rm), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb9-compact: mov.b @($imm8, gbr), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movb10-compact: mov.b @($imm4, $rm), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movb10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movb5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl1-compact: mov.l $rm, @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl2-compact: mov.l $rm, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movl3-compact: mov.l $rm, @(r0, $rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl4-compact: mov.l r0, @($imm8x4, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (((UINT) 0));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl5-compact: mov.l $rm, @($imm4x4, $rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (FLD (f_rm));
-    SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl6-compact: mov.l @$rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl7-compact: mov.l @${rm}+, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = GET_H_GRC (FLD (f_rn));
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* movl8-compact: mov.l @(r0, $rm), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl9-compact: mov.l @($imm8x4, gbr), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl10-compact: mov.l @($imm8x4, pc), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movl11-compact: mov.l @($imm4x4, $rm), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movl11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw1-compact: mov.w $rm, @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw2-compact: mov.w $rm, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2);
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movw3-compact: mov.w $rm, @(r0, $rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw4-compact: mov.w r0, @($imm8x2, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw5-compact: mov.w r0, @($imm4x2, $rn) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
-    SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw6-compact: mov.w @$rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw7-compact: mov.w @${rm}+, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_data;
-  tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
-if (EQSI (FLD (f_rm), FLD (f_rn))) {
-  {
-    SI opval = EXTHISI (tmp_data);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-} else {
-  {
-    SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
-    SET_H_GRC (FLD (f_rm), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
-  }
-}
-  {
-    SI opval = EXTHISI (tmp_data);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* movw8-compact: mov.w @(r0, $rm), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw9-compact: mov.w @($imm8x2, gbr), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw10-compact: mov.w @($imm8x2, pc), $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2))));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movw11-compact: mov.w @($imm4x2, $rm), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movw11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw11_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2))));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mova-compact: mova @($imm8x4, pc), r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,mova_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movcal-compact: movca.l r0, @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movcal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GRC (((UINT) 0));
-    SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* movt-compact: movt $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,movt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTBISI (GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mull-compact: mul.l $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,mull_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulsw-compact: muls.w $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,mulsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* muluw-compact: mulu.w $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,muluw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
-    SET_H_MACL (opval);
-    TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* neg-compact: neg $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,neg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* negc-compact: negc $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,negc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* nop-compact: nop */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,nop_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* not-compact: not $rm64, $rn64 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,not_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = INVDI (GET_H_GR (FLD (f_rm)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbi-compact: ocbi @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ocbi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbp-compact: ocbp @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ocbp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbwb-compact: ocbwb @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ocbwb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* or-compact: or $rm64, $rn64 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,or_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ori-compact: or #$uimm8, r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,ori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GRC (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* orb-compact: or.b #$imm8, @(r0, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,orb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* pref-compact: pref @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,pref_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* rotcl-compact: rotcl $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,rotcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_temp;
-  tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_temp) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rotcr-compact: rotcr $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,rotcr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_lsbit;
-  SI tmp_temp;
-  tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
-  tmp_temp = GET_H_TBIT ();
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_lsbit) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rotl-compact: rotl $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,rotl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_temp;
-  tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_temp) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rotr-compact: rotr $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,rotr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_lsbit;
-  SI tmp_temp;
-  tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
-  tmp_temp = tmp_lsbit;
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_lsbit) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rts-compact: rts */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,rts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    UDI opval = GET_H_PR ();
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* sets-compact: sets */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sets_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 1;
-    SET_H_SBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sett-compact: sett */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sett_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = 1;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shad-compact: shad $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shad_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_shamt;
-  tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
-if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (NEQI (tmp_shamt, 0)) {
-  {
-    SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) {
-  {
-    SI opval = NEGSI (1);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-  {
-    SI opval = 0;
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* shal-compact: shal $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* shar-compact: shar $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shar_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* shld-compact: shld $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shld_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_shamt;
-  tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
-if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-if (NEQI (tmp_shamt, 0)) {
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-} else {
-  {
-    SI opval = 0;
-    SET_H_GRC (FLD (f_rn), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* shll-compact: shll $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shll_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* shll2-compact: shll2 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shll2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shll8-compact: shll8 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shll8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shll16-compact: shll16 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shll16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlr-compact: shlr $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shlr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* shlr2-compact: shlr2 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shlr2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlr8-compact: shlr8 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shlr8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlr16-compact: shlr16 $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,shlr16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16);
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stc-gbr-compact: stc gbr, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stc_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_GBR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stcl-gbr-compact: stc.l gbr, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stcl_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_GBR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sts-fpscr-compact: sts fpscr, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sts_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_FPCCR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stsl-fpscr-compact: sts.l fpscr, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_FPCCR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sts-fpul-compact: sts fpul, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sts_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)]));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stsl-fpul-compact: sts.l fpul, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SF opval = CPU (h_fr[((UINT) 32)]);
-    SETMEMSF (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sts-mach-compact: sts mach, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sts_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_MACH ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stsl-mach-compact: sts.l mach, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_MACH ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sts-macl-compact: sts macl, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sts_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_MACL ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stsl-macl-compact: sts.l macl, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_MACL ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sts-pr-compact: sts pr, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sts_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_PR ();
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stsl-pr-compact: sts.l pr, @-$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,stsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
-  {
-    SI opval = GET_H_PR ();
-    SETMEMSI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_addr;
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sub-compact: sub $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,sub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* subc-compact: subc $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,subc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_flag;
-  tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-  {
-    SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = tmp_flag;
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* subv-compact: subv $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,subv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  BI tmp_t;
-  tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
-  {
-    SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-  {
-    BI opval = ((tmp_t) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* swapb-compact: swap.b $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,swapb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  UHI tmp_top_half;
-  UQI tmp_byte1;
-  UQI tmp_byte0;
-  tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0);
-  tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2);
-  tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3);
-  {
-    SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* swapw-compact: swap.w $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,swapw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* tasb-compact: tas.b @$rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,tasb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movw10_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  UQI tmp_byte;
-  tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
-  {
-    BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-  tmp_byte = ORQI (tmp_byte, 128);
-  {
-    UQI opval = tmp_byte;
-    SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* trapa-compact: trapa #$uimm8 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,trapa_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-sh64_compact_trapa (current_cpu, FLD (f_imm8), pc);
-
-  return vpc;
-#undef FLD
-}
-
-/* tst-compact: tst $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,tst_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* tsti-compact: tst #$uimm8, r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,tsti_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* tstb-compact: tst.b #$imm8, @(r0, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,tstb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  {
-    BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0));
-    SET_H_TBIT (opval);
-    TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* xor-compact: xor $rm64, $rn64 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,xor_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm)));
-    SET_H_GR (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xori-compact: xor #$uimm8, r0 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,xori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
-    SET_H_GR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xorb-compact: xor.b #$imm8, @(r0, gbr) */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,xorb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_addr;
-  UQI tmp_data;
-  tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
-  tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
-  {
-    UQI opval = tmp_data;
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* xtrct-compact: xtrct $rm, $rn */
-
-static SEM_PC
-SEM_FN_NAME (sh64_compact,xtrct_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movl5_compact.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16));
-    SET_H_GRC (FLD (f_rn), opval);
-    TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* Table of all semantic fns.  */
-
-static const struct sem_fn_desc sem_fns[] = {
-  { SH64_COMPACT_INSN_X_INVALID, SEM_FN_NAME (sh64_compact,x_invalid) },
-  { SH64_COMPACT_INSN_X_AFTER, SEM_FN_NAME (sh64_compact,x_after) },
-  { SH64_COMPACT_INSN_X_BEFORE, SEM_FN_NAME (sh64_compact,x_before) },
-  { SH64_COMPACT_INSN_X_CTI_CHAIN, SEM_FN_NAME (sh64_compact,x_cti_chain) },
-  { SH64_COMPACT_INSN_X_CHAIN, SEM_FN_NAME (sh64_compact,x_chain) },
-  { SH64_COMPACT_INSN_X_BEGIN, SEM_FN_NAME (sh64_compact,x_begin) },
-  { SH64_COMPACT_INSN_ADD_COMPACT, SEM_FN_NAME (sh64_compact,add_compact) },
-  { SH64_COMPACT_INSN_ADDI_COMPACT, SEM_FN_NAME (sh64_compact,addi_compact) },
-  { SH64_COMPACT_INSN_ADDC_COMPACT, SEM_FN_NAME (sh64_compact,addc_compact) },
-  { SH64_COMPACT_INSN_ADDV_COMPACT, SEM_FN_NAME (sh64_compact,addv_compact) },
-  { SH64_COMPACT_INSN_AND_COMPACT, SEM_FN_NAME (sh64_compact,and_compact) },
-  { SH64_COMPACT_INSN_ANDI_COMPACT, SEM_FN_NAME (sh64_compact,andi_compact) },
-  { SH64_COMPACT_INSN_ANDB_COMPACT, SEM_FN_NAME (sh64_compact,andb_compact) },
-  { SH64_COMPACT_INSN_BF_COMPACT, SEM_FN_NAME (sh64_compact,bf_compact) },
-  { SH64_COMPACT_INSN_BFS_COMPACT, SEM_FN_NAME (sh64_compact,bfs_compact) },
-  { SH64_COMPACT_INSN_BRA_COMPACT, SEM_FN_NAME (sh64_compact,bra_compact) },
-  { SH64_COMPACT_INSN_BRAF_COMPACT, SEM_FN_NAME (sh64_compact,braf_compact) },
-  { SH64_COMPACT_INSN_BRK_COMPACT, SEM_FN_NAME (sh64_compact,brk_compact) },
-  { SH64_COMPACT_INSN_BSR_COMPACT, SEM_FN_NAME (sh64_compact,bsr_compact) },
-  { SH64_COMPACT_INSN_BSRF_COMPACT, SEM_FN_NAME (sh64_compact,bsrf_compact) },
-  { SH64_COMPACT_INSN_BT_COMPACT, SEM_FN_NAME (sh64_compact,bt_compact) },
-  { SH64_COMPACT_INSN_BTS_COMPACT, SEM_FN_NAME (sh64_compact,bts_compact) },
-  { SH64_COMPACT_INSN_CLRMAC_COMPACT, SEM_FN_NAME (sh64_compact,clrmac_compact) },
-  { SH64_COMPACT_INSN_CLRS_COMPACT, SEM_FN_NAME (sh64_compact,clrs_compact) },
-  { SH64_COMPACT_INSN_CLRT_COMPACT, SEM_FN_NAME (sh64_compact,clrt_compact) },
-  { SH64_COMPACT_INSN_CMPEQ_COMPACT, SEM_FN_NAME (sh64_compact,cmpeq_compact) },
-  { SH64_COMPACT_INSN_CMPEQI_COMPACT, SEM_FN_NAME (sh64_compact,cmpeqi_compact) },
-  { SH64_COMPACT_INSN_CMPGE_COMPACT, SEM_FN_NAME (sh64_compact,cmpge_compact) },
-  { SH64_COMPACT_INSN_CMPGT_COMPACT, SEM_FN_NAME (sh64_compact,cmpgt_compact) },
-  { SH64_COMPACT_INSN_CMPHI_COMPACT, SEM_FN_NAME (sh64_compact,cmphi_compact) },
-  { SH64_COMPACT_INSN_CMPHS_COMPACT, SEM_FN_NAME (sh64_compact,cmphs_compact) },
-  { SH64_COMPACT_INSN_CMPPL_COMPACT, SEM_FN_NAME (sh64_compact,cmppl_compact) },
-  { SH64_COMPACT_INSN_CMPPZ_COMPACT, SEM_FN_NAME (sh64_compact,cmppz_compact) },
-  { SH64_COMPACT_INSN_CMPSTR_COMPACT, SEM_FN_NAME (sh64_compact,cmpstr_compact) },
-  { SH64_COMPACT_INSN_DIV0S_COMPACT, SEM_FN_NAME (sh64_compact,div0s_compact) },
-  { SH64_COMPACT_INSN_DIV0U_COMPACT, SEM_FN_NAME (sh64_compact,div0u_compact) },
-  { SH64_COMPACT_INSN_DIV1_COMPACT, SEM_FN_NAME (sh64_compact,div1_compact) },
-  { SH64_COMPACT_INSN_DMULSL_COMPACT, SEM_FN_NAME (sh64_compact,dmulsl_compact) },
-  { SH64_COMPACT_INSN_DMULUL_COMPACT, SEM_FN_NAME (sh64_compact,dmulul_compact) },
-  { SH64_COMPACT_INSN_DT_COMPACT, SEM_FN_NAME (sh64_compact,dt_compact) },
-  { SH64_COMPACT_INSN_EXTSB_COMPACT, SEM_FN_NAME (sh64_compact,extsb_compact) },
-  { SH64_COMPACT_INSN_EXTSW_COMPACT, SEM_FN_NAME (sh64_compact,extsw_compact) },
-  { SH64_COMPACT_INSN_EXTUB_COMPACT, SEM_FN_NAME (sh64_compact,extub_compact) },
-  { SH64_COMPACT_INSN_EXTUW_COMPACT, SEM_FN_NAME (sh64_compact,extuw_compact) },
-  { SH64_COMPACT_INSN_FABS_COMPACT, SEM_FN_NAME (sh64_compact,fabs_compact) },
-  { SH64_COMPACT_INSN_FADD_COMPACT, SEM_FN_NAME (sh64_compact,fadd_compact) },
-  { SH64_COMPACT_INSN_FCMPEQ_COMPACT, SEM_FN_NAME (sh64_compact,fcmpeq_compact) },
-  { SH64_COMPACT_INSN_FCMPGT_COMPACT, SEM_FN_NAME (sh64_compact,fcmpgt_compact) },
-  { SH64_COMPACT_INSN_FCNVDS_COMPACT, SEM_FN_NAME (sh64_compact,fcnvds_compact) },
-  { SH64_COMPACT_INSN_FCNVSD_COMPACT, SEM_FN_NAME (sh64_compact,fcnvsd_compact) },
-  { SH64_COMPACT_INSN_FDIV_COMPACT, SEM_FN_NAME (sh64_compact,fdiv_compact) },
-  { SH64_COMPACT_INSN_FIPR_COMPACT, SEM_FN_NAME (sh64_compact,fipr_compact) },
-  { SH64_COMPACT_INSN_FLDS_COMPACT, SEM_FN_NAME (sh64_compact,flds_compact) },
-  { SH64_COMPACT_INSN_FLDI0_COMPACT, SEM_FN_NAME (sh64_compact,fldi0_compact) },
-  { SH64_COMPACT_INSN_FLDI1_COMPACT, SEM_FN_NAME (sh64_compact,fldi1_compact) },
-  { SH64_COMPACT_INSN_FLOAT_COMPACT, SEM_FN_NAME (sh64_compact,float_compact) },
-  { SH64_COMPACT_INSN_FMAC_COMPACT, SEM_FN_NAME (sh64_compact,fmac_compact) },
-  { SH64_COMPACT_INSN_FMOV1_COMPACT, SEM_FN_NAME (sh64_compact,fmov1_compact) },
-  { SH64_COMPACT_INSN_FMOV2_COMPACT, SEM_FN_NAME (sh64_compact,fmov2_compact) },
-  { SH64_COMPACT_INSN_FMOV3_COMPACT, SEM_FN_NAME (sh64_compact,fmov3_compact) },
-  { SH64_COMPACT_INSN_FMOV4_COMPACT, SEM_FN_NAME (sh64_compact,fmov4_compact) },
-  { SH64_COMPACT_INSN_FMOV5_COMPACT, SEM_FN_NAME (sh64_compact,fmov5_compact) },
-  { SH64_COMPACT_INSN_FMOV6_COMPACT, SEM_FN_NAME (sh64_compact,fmov6_compact) },
-  { SH64_COMPACT_INSN_FMOV7_COMPACT, SEM_FN_NAME (sh64_compact,fmov7_compact) },
-  { SH64_COMPACT_INSN_FMUL_COMPACT, SEM_FN_NAME (sh64_compact,fmul_compact) },
-  { SH64_COMPACT_INSN_FNEG_COMPACT, SEM_FN_NAME (sh64_compact,fneg_compact) },
-  { SH64_COMPACT_INSN_FRCHG_COMPACT, SEM_FN_NAME (sh64_compact,frchg_compact) },
-  { SH64_COMPACT_INSN_FSCHG_COMPACT, SEM_FN_NAME (sh64_compact,fschg_compact) },
-  { SH64_COMPACT_INSN_FSQRT_COMPACT, SEM_FN_NAME (sh64_compact,fsqrt_compact) },
-  { SH64_COMPACT_INSN_FSTS_COMPACT, SEM_FN_NAME (sh64_compact,fsts_compact) },
-  { SH64_COMPACT_INSN_FSUB_COMPACT, SEM_FN_NAME (sh64_compact,fsub_compact) },
-  { SH64_COMPACT_INSN_FTRC_COMPACT, SEM_FN_NAME (sh64_compact,ftrc_compact) },
-  { SH64_COMPACT_INSN_FTRV_COMPACT, SEM_FN_NAME (sh64_compact,ftrv_compact) },
-  { SH64_COMPACT_INSN_JMP_COMPACT, SEM_FN_NAME (sh64_compact,jmp_compact) },
-  { SH64_COMPACT_INSN_JSR_COMPACT, SEM_FN_NAME (sh64_compact,jsr_compact) },
-  { SH64_COMPACT_INSN_LDC_COMPACT, SEM_FN_NAME (sh64_compact,ldc_compact) },
-  { SH64_COMPACT_INSN_LDCL_COMPACT, SEM_FN_NAME (sh64_compact,ldcl_compact) },
-  { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpscr_compact) },
-  { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) },
-  { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpul_compact) },
-  { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_fpul_compact) },
-  { SH64_COMPACT_INSN_LDS_MACH_COMPACT, SEM_FN_NAME (sh64_compact,lds_mach_compact) },
-  { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_mach_compact) },
-  { SH64_COMPACT_INSN_LDS_MACL_COMPACT, SEM_FN_NAME (sh64_compact,lds_macl_compact) },
-  { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_macl_compact) },
-  { SH64_COMPACT_INSN_LDS_PR_COMPACT, SEM_FN_NAME (sh64_compact,lds_pr_compact) },
-  { SH64_COMPACT_INSN_LDSL_PR_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_pr_compact) },
-  { SH64_COMPACT_INSN_MACL_COMPACT, SEM_FN_NAME (sh64_compact,macl_compact) },
-  { SH64_COMPACT_INSN_MACW_COMPACT, SEM_FN_NAME (sh64_compact,macw_compact) },
-  { SH64_COMPACT_INSN_MOV_COMPACT, SEM_FN_NAME (sh64_compact,mov_compact) },
-  { SH64_COMPACT_INSN_MOVI_COMPACT, SEM_FN_NAME (sh64_compact,movi_compact) },
-  { SH64_COMPACT_INSN_MOVB1_COMPACT, SEM_FN_NAME (sh64_compact,movb1_compact) },
-  { SH64_COMPACT_INSN_MOVB2_COMPACT, SEM_FN_NAME (sh64_compact,movb2_compact) },
-  { SH64_COMPACT_INSN_MOVB3_COMPACT, SEM_FN_NAME (sh64_compact,movb3_compact) },
-  { SH64_COMPACT_INSN_MOVB4_COMPACT, SEM_FN_NAME (sh64_compact,movb4_compact) },
-  { SH64_COMPACT_INSN_MOVB5_COMPACT, SEM_FN_NAME (sh64_compact,movb5_compact) },
-  { SH64_COMPACT_INSN_MOVB6_COMPACT, SEM_FN_NAME (sh64_compact,movb6_compact) },
-  { SH64_COMPACT_INSN_MOVB7_COMPACT, SEM_FN_NAME (sh64_compact,movb7_compact) },
-  { SH64_COMPACT_INSN_MOVB8_COMPACT, SEM_FN_NAME (sh64_compact,movb8_compact) },
-  { SH64_COMPACT_INSN_MOVB9_COMPACT, SEM_FN_NAME (sh64_compact,movb9_compact) },
-  { SH64_COMPACT_INSN_MOVB10_COMPACT, SEM_FN_NAME (sh64_compact,movb10_compact) },
-  { SH64_COMPACT_INSN_MOVL1_COMPACT, SEM_FN_NAME (sh64_compact,movl1_compact) },
-  { SH64_COMPACT_INSN_MOVL2_COMPACT, SEM_FN_NAME (sh64_compact,movl2_compact) },
-  { SH64_COMPACT_INSN_MOVL3_COMPACT, SEM_FN_NAME (sh64_compact,movl3_compact) },
-  { SH64_COMPACT_INSN_MOVL4_COMPACT, SEM_FN_NAME (sh64_compact,movl4_compact) },
-  { SH64_COMPACT_INSN_MOVL5_COMPACT, SEM_FN_NAME (sh64_compact,movl5_compact) },
-  { SH64_COMPACT_INSN_MOVL6_COMPACT, SEM_FN_NAME (sh64_compact,movl6_compact) },
-  { SH64_COMPACT_INSN_MOVL7_COMPACT, SEM_FN_NAME (sh64_compact,movl7_compact) },
-  { SH64_COMPACT_INSN_MOVL8_COMPACT, SEM_FN_NAME (sh64_compact,movl8_compact) },
-  { SH64_COMPACT_INSN_MOVL9_COMPACT, SEM_FN_NAME (sh64_compact,movl9_compact) },
-  { SH64_COMPACT_INSN_MOVL10_COMPACT, SEM_FN_NAME (sh64_compact,movl10_compact) },
-  { SH64_COMPACT_INSN_MOVL11_COMPACT, SEM_FN_NAME (sh64_compact,movl11_compact) },
-  { SH64_COMPACT_INSN_MOVW1_COMPACT, SEM_FN_NAME (sh64_compact,movw1_compact) },
-  { SH64_COMPACT_INSN_MOVW2_COMPACT, SEM_FN_NAME (sh64_compact,movw2_compact) },
-  { SH64_COMPACT_INSN_MOVW3_COMPACT, SEM_FN_NAME (sh64_compact,movw3_compact) },
-  { SH64_COMPACT_INSN_MOVW4_COMPACT, SEM_FN_NAME (sh64_compact,movw4_compact) },
-  { SH64_COMPACT_INSN_MOVW5_COMPACT, SEM_FN_NAME (sh64_compact,movw5_compact) },
-  { SH64_COMPACT_INSN_MOVW6_COMPACT, SEM_FN_NAME (sh64_compact,movw6_compact) },
-  { SH64_COMPACT_INSN_MOVW7_COMPACT, SEM_FN_NAME (sh64_compact,movw7_compact) },
-  { SH64_COMPACT_INSN_MOVW8_COMPACT, SEM_FN_NAME (sh64_compact,movw8_compact) },
-  { SH64_COMPACT_INSN_MOVW9_COMPACT, SEM_FN_NAME (sh64_compact,movw9_compact) },
-  { SH64_COMPACT_INSN_MOVW10_COMPACT, SEM_FN_NAME (sh64_compact,movw10_compact) },
-  { SH64_COMPACT_INSN_MOVW11_COMPACT, SEM_FN_NAME (sh64_compact,movw11_compact) },
-  { SH64_COMPACT_INSN_MOVA_COMPACT, SEM_FN_NAME (sh64_compact,mova_compact) },
-  { SH64_COMPACT_INSN_MOVCAL_COMPACT, SEM_FN_NAME (sh64_compact,movcal_compact) },
-  { SH64_COMPACT_INSN_MOVT_COMPACT, SEM_FN_NAME (sh64_compact,movt_compact) },
-  { SH64_COMPACT_INSN_MULL_COMPACT, SEM_FN_NAME (sh64_compact,mull_compact) },
-  { SH64_COMPACT_INSN_MULSW_COMPACT, SEM_FN_NAME (sh64_compact,mulsw_compact) },
-  { SH64_COMPACT_INSN_MULUW_COMPACT, SEM_FN_NAME (sh64_compact,muluw_compact) },
-  { SH64_COMPACT_INSN_NEG_COMPACT, SEM_FN_NAME (sh64_compact,neg_compact) },
-  { SH64_COMPACT_INSN_NEGC_COMPACT, SEM_FN_NAME (sh64_compact,negc_compact) },
-  { SH64_COMPACT_INSN_NOP_COMPACT, SEM_FN_NAME (sh64_compact,nop_compact) },
-  { SH64_COMPACT_INSN_NOT_COMPACT, SEM_FN_NAME (sh64_compact,not_compact) },
-  { SH64_COMPACT_INSN_OCBI_COMPACT, SEM_FN_NAME (sh64_compact,ocbi_compact) },
-  { SH64_COMPACT_INSN_OCBP_COMPACT, SEM_FN_NAME (sh64_compact,ocbp_compact) },
-  { SH64_COMPACT_INSN_OCBWB_COMPACT, SEM_FN_NAME (sh64_compact,ocbwb_compact) },
-  { SH64_COMPACT_INSN_OR_COMPACT, SEM_FN_NAME (sh64_compact,or_compact) },
-  { SH64_COMPACT_INSN_ORI_COMPACT, SEM_FN_NAME (sh64_compact,ori_compact) },
-  { SH64_COMPACT_INSN_ORB_COMPACT, SEM_FN_NAME (sh64_compact,orb_compact) },
-  { SH64_COMPACT_INSN_PREF_COMPACT, SEM_FN_NAME (sh64_compact,pref_compact) },
-  { SH64_COMPACT_INSN_ROTCL_COMPACT, SEM_FN_NAME (sh64_compact,rotcl_compact) },
-  { SH64_COMPACT_INSN_ROTCR_COMPACT, SEM_FN_NAME (sh64_compact,rotcr_compact) },
-  { SH64_COMPACT_INSN_ROTL_COMPACT, SEM_FN_NAME (sh64_compact,rotl_compact) },
-  { SH64_COMPACT_INSN_ROTR_COMPACT, SEM_FN_NAME (sh64_compact,rotr_compact) },
-  { SH64_COMPACT_INSN_RTS_COMPACT, SEM_FN_NAME (sh64_compact,rts_compact) },
-  { SH64_COMPACT_INSN_SETS_COMPACT, SEM_FN_NAME (sh64_compact,sets_compact) },
-  { SH64_COMPACT_INSN_SETT_COMPACT, SEM_FN_NAME (sh64_compact,sett_compact) },
-  { SH64_COMPACT_INSN_SHAD_COMPACT, SEM_FN_NAME (sh64_compact,shad_compact) },
-  { SH64_COMPACT_INSN_SHAL_COMPACT, SEM_FN_NAME (sh64_compact,shal_compact) },
-  { SH64_COMPACT_INSN_SHAR_COMPACT, SEM_FN_NAME (sh64_compact,shar_compact) },
-  { SH64_COMPACT_INSN_SHLD_COMPACT, SEM_FN_NAME (sh64_compact,shld_compact) },
-  { SH64_COMPACT_INSN_SHLL_COMPACT, SEM_FN_NAME (sh64_compact,shll_compact) },
-  { SH64_COMPACT_INSN_SHLL2_COMPACT, SEM_FN_NAME (sh64_compact,shll2_compact) },
-  { SH64_COMPACT_INSN_SHLL8_COMPACT, SEM_FN_NAME (sh64_compact,shll8_compact) },
-  { SH64_COMPACT_INSN_SHLL16_COMPACT, SEM_FN_NAME (sh64_compact,shll16_compact) },
-  { SH64_COMPACT_INSN_SHLR_COMPACT, SEM_FN_NAME (sh64_compact,shlr_compact) },
-  { SH64_COMPACT_INSN_SHLR2_COMPACT, SEM_FN_NAME (sh64_compact,shlr2_compact) },
-  { SH64_COMPACT_INSN_SHLR8_COMPACT, SEM_FN_NAME (sh64_compact,shlr8_compact) },
-  { SH64_COMPACT_INSN_SHLR16_COMPACT, SEM_FN_NAME (sh64_compact,shlr16_compact) },
-  { SH64_COMPACT_INSN_STC_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stc_gbr_compact) },
-  { SH64_COMPACT_INSN_STCL_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stcl_gbr_compact) },
-  { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpscr_compact) },
-  { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) },
-  { SH64_COMPACT_INSN_STS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpul_compact) },
-  { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,stsl_fpul_compact) },
-  { SH64_COMPACT_INSN_STS_MACH_COMPACT, SEM_FN_NAME (sh64_compact,sts_mach_compact) },
-  { SH64_COMPACT_INSN_STSL_MACH_COMPACT, SEM_FN_NAME (sh64_compact,stsl_mach_compact) },
-  { SH64_COMPACT_INSN_STS_MACL_COMPACT, SEM_FN_NAME (sh64_compact,sts_macl_compact) },
-  { SH64_COMPACT_INSN_STSL_MACL_COMPACT, SEM_FN_NAME (sh64_compact,stsl_macl_compact) },
-  { SH64_COMPACT_INSN_STS_PR_COMPACT, SEM_FN_NAME (sh64_compact,sts_pr_compact) },
-  { SH64_COMPACT_INSN_STSL_PR_COMPACT, SEM_FN_NAME (sh64_compact,stsl_pr_compact) },
-  { SH64_COMPACT_INSN_SUB_COMPACT, SEM_FN_NAME (sh64_compact,sub_compact) },
-  { SH64_COMPACT_INSN_SUBC_COMPACT, SEM_FN_NAME (sh64_compact,subc_compact) },
-  { SH64_COMPACT_INSN_SUBV_COMPACT, SEM_FN_NAME (sh64_compact,subv_compact) },
-  { SH64_COMPACT_INSN_SWAPB_COMPACT, SEM_FN_NAME (sh64_compact,swapb_compact) },
-  { SH64_COMPACT_INSN_SWAPW_COMPACT, SEM_FN_NAME (sh64_compact,swapw_compact) },
-  { SH64_COMPACT_INSN_TASB_COMPACT, SEM_FN_NAME (sh64_compact,tasb_compact) },
-  { SH64_COMPACT_INSN_TRAPA_COMPACT, SEM_FN_NAME (sh64_compact,trapa_compact) },
-  { SH64_COMPACT_INSN_TST_COMPACT, SEM_FN_NAME (sh64_compact,tst_compact) },
-  { SH64_COMPACT_INSN_TSTI_COMPACT, SEM_FN_NAME (sh64_compact,tsti_compact) },
-  { SH64_COMPACT_INSN_TSTB_COMPACT, SEM_FN_NAME (sh64_compact,tstb_compact) },
-  { SH64_COMPACT_INSN_XOR_COMPACT, SEM_FN_NAME (sh64_compact,xor_compact) },
-  { SH64_COMPACT_INSN_XORI_COMPACT, SEM_FN_NAME (sh64_compact,xori_compact) },
-  { SH64_COMPACT_INSN_XORB_COMPACT, SEM_FN_NAME (sh64_compact,xorb_compact) },
-  { SH64_COMPACT_INSN_XTRCT_COMPACT, SEM_FN_NAME (sh64_compact,xtrct_compact) },
-  { 0, 0 }
-};
-
-/* Add the semantic fns to IDESC_TABLE.  */
-
-void
-SEM_FN_NAME (sh64_compact,init_idesc_table) (SIM_CPU *current_cpu)
-{
-  IDESC *idesc_table = CPU_IDESC (current_cpu);
-  const struct sem_fn_desc *sf;
-  int mach_num = MACH_NUM (CPU_MACH (current_cpu));
-
-  for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
-    {
-      const CGEN_INSN *insn = idesc_table[sf->index].idata;
-      int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
-		     || CGEN_INSN_MACH_HAS_P (insn, mach_num));
-#if FAST_P
-      if (valid_p)
-	idesc_table[sf->index].sem_fast = sf->fn;
-      else
-	idesc_table[sf->index].sem_fast = SEM_FN_NAME (sh64_compact,x_invalid);
-#else
-      if (valid_p)
-	idesc_table[sf->index].sem_full = sf->fn;
-      else
-	idesc_table[sf->index].sem_full = SEM_FN_NAME (sh64_compact,x_invalid);
-#endif
-    }
-}
-
diff --git a/sim/sh64/sem-media-switch.c b/sim/sh64/sem-media-switch.c
deleted file mode 100644
index 075738ae0ef..00000000000
--- a/sim/sh64/sem-media-switch.c
+++ /dev/null
@@ -1,5558 +0,0 @@
-/* Simulator instruction semantics for sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { SH64_MEDIA_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { SH64_MEDIA_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { SH64_MEDIA_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { SH64_MEDIA_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { SH64_MEDIA_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { SH64_MEDIA_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { SH64_MEDIA_INSN_ADD, && case_sem_INSN_ADD },
-    { SH64_MEDIA_INSN_ADDL, && case_sem_INSN_ADDL },
-    { SH64_MEDIA_INSN_ADDI, && case_sem_INSN_ADDI },
-    { SH64_MEDIA_INSN_ADDIL, && case_sem_INSN_ADDIL },
-    { SH64_MEDIA_INSN_ADDZL, && case_sem_INSN_ADDZL },
-    { SH64_MEDIA_INSN_ALLOCO, && case_sem_INSN_ALLOCO },
-    { SH64_MEDIA_INSN_AND, && case_sem_INSN_AND },
-    { SH64_MEDIA_INSN_ANDC, && case_sem_INSN_ANDC },
-    { SH64_MEDIA_INSN_ANDI, && case_sem_INSN_ANDI },
-    { SH64_MEDIA_INSN_BEQ, && case_sem_INSN_BEQ },
-    { SH64_MEDIA_INSN_BEQI, && case_sem_INSN_BEQI },
-    { SH64_MEDIA_INSN_BGE, && case_sem_INSN_BGE },
-    { SH64_MEDIA_INSN_BGEU, && case_sem_INSN_BGEU },
-    { SH64_MEDIA_INSN_BGT, && case_sem_INSN_BGT },
-    { SH64_MEDIA_INSN_BGTU, && case_sem_INSN_BGTU },
-    { SH64_MEDIA_INSN_BLINK, && case_sem_INSN_BLINK },
-    { SH64_MEDIA_INSN_BNE, && case_sem_INSN_BNE },
-    { SH64_MEDIA_INSN_BNEI, && case_sem_INSN_BNEI },
-    { SH64_MEDIA_INSN_BRK, && case_sem_INSN_BRK },
-    { SH64_MEDIA_INSN_BYTEREV, && case_sem_INSN_BYTEREV },
-    { SH64_MEDIA_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
-    { SH64_MEDIA_INSN_CMPGT, && case_sem_INSN_CMPGT },
-    { SH64_MEDIA_INSN_CMPGTU, && case_sem_INSN_CMPGTU },
-    { SH64_MEDIA_INSN_CMVEQ, && case_sem_INSN_CMVEQ },
-    { SH64_MEDIA_INSN_CMVNE, && case_sem_INSN_CMVNE },
-    { SH64_MEDIA_INSN_FABSD, && case_sem_INSN_FABSD },
-    { SH64_MEDIA_INSN_FABSS, && case_sem_INSN_FABSS },
-    { SH64_MEDIA_INSN_FADDD, && case_sem_INSN_FADDD },
-    { SH64_MEDIA_INSN_FADDS, && case_sem_INSN_FADDS },
-    { SH64_MEDIA_INSN_FCMPEQD, && case_sem_INSN_FCMPEQD },
-    { SH64_MEDIA_INSN_FCMPEQS, && case_sem_INSN_FCMPEQS },
-    { SH64_MEDIA_INSN_FCMPGED, && case_sem_INSN_FCMPGED },
-    { SH64_MEDIA_INSN_FCMPGES, && case_sem_INSN_FCMPGES },
-    { SH64_MEDIA_INSN_FCMPGTD, && case_sem_INSN_FCMPGTD },
-    { SH64_MEDIA_INSN_FCMPGTS, && case_sem_INSN_FCMPGTS },
-    { SH64_MEDIA_INSN_FCMPUND, && case_sem_INSN_FCMPUND },
-    { SH64_MEDIA_INSN_FCMPUNS, && case_sem_INSN_FCMPUNS },
-    { SH64_MEDIA_INSN_FCNVDS, && case_sem_INSN_FCNVDS },
-    { SH64_MEDIA_INSN_FCNVSD, && case_sem_INSN_FCNVSD },
-    { SH64_MEDIA_INSN_FDIVD, && case_sem_INSN_FDIVD },
-    { SH64_MEDIA_INSN_FDIVS, && case_sem_INSN_FDIVS },
-    { SH64_MEDIA_INSN_FGETSCR, && case_sem_INSN_FGETSCR },
-    { SH64_MEDIA_INSN_FIPRS, && case_sem_INSN_FIPRS },
-    { SH64_MEDIA_INSN_FLDD, && case_sem_INSN_FLDD },
-    { SH64_MEDIA_INSN_FLDP, && case_sem_INSN_FLDP },
-    { SH64_MEDIA_INSN_FLDS, && case_sem_INSN_FLDS },
-    { SH64_MEDIA_INSN_FLDXD, && case_sem_INSN_FLDXD },
-    { SH64_MEDIA_INSN_FLDXP, && case_sem_INSN_FLDXP },
-    { SH64_MEDIA_INSN_FLDXS, && case_sem_INSN_FLDXS },
-    { SH64_MEDIA_INSN_FLOATLD, && case_sem_INSN_FLOATLD },
-    { SH64_MEDIA_INSN_FLOATLS, && case_sem_INSN_FLOATLS },
-    { SH64_MEDIA_INSN_FLOATQD, && case_sem_INSN_FLOATQD },
-    { SH64_MEDIA_INSN_FLOATQS, && case_sem_INSN_FLOATQS },
-    { SH64_MEDIA_INSN_FMACS, && case_sem_INSN_FMACS },
-    { SH64_MEDIA_INSN_FMOVD, && case_sem_INSN_FMOVD },
-    { SH64_MEDIA_INSN_FMOVDQ, && case_sem_INSN_FMOVDQ },
-    { SH64_MEDIA_INSN_FMOVLS, && case_sem_INSN_FMOVLS },
-    { SH64_MEDIA_INSN_FMOVQD, && case_sem_INSN_FMOVQD },
-    { SH64_MEDIA_INSN_FMOVS, && case_sem_INSN_FMOVS },
-    { SH64_MEDIA_INSN_FMOVSL, && case_sem_INSN_FMOVSL },
-    { SH64_MEDIA_INSN_FMULD, && case_sem_INSN_FMULD },
-    { SH64_MEDIA_INSN_FMULS, && case_sem_INSN_FMULS },
-    { SH64_MEDIA_INSN_FNEGD, && case_sem_INSN_FNEGD },
-    { SH64_MEDIA_INSN_FNEGS, && case_sem_INSN_FNEGS },
-    { SH64_MEDIA_INSN_FPUTSCR, && case_sem_INSN_FPUTSCR },
-    { SH64_MEDIA_INSN_FSQRTD, && case_sem_INSN_FSQRTD },
-    { SH64_MEDIA_INSN_FSQRTS, && case_sem_INSN_FSQRTS },
-    { SH64_MEDIA_INSN_FSTD, && case_sem_INSN_FSTD },
-    { SH64_MEDIA_INSN_FSTP, && case_sem_INSN_FSTP },
-    { SH64_MEDIA_INSN_FSTS, && case_sem_INSN_FSTS },
-    { SH64_MEDIA_INSN_FSTXD, && case_sem_INSN_FSTXD },
-    { SH64_MEDIA_INSN_FSTXP, && case_sem_INSN_FSTXP },
-    { SH64_MEDIA_INSN_FSTXS, && case_sem_INSN_FSTXS },
-    { SH64_MEDIA_INSN_FSUBD, && case_sem_INSN_FSUBD },
-    { SH64_MEDIA_INSN_FSUBS, && case_sem_INSN_FSUBS },
-    { SH64_MEDIA_INSN_FTRCDL, && case_sem_INSN_FTRCDL },
-    { SH64_MEDIA_INSN_FTRCSL, && case_sem_INSN_FTRCSL },
-    { SH64_MEDIA_INSN_FTRCDQ, && case_sem_INSN_FTRCDQ },
-    { SH64_MEDIA_INSN_FTRCSQ, && case_sem_INSN_FTRCSQ },
-    { SH64_MEDIA_INSN_FTRVS, && case_sem_INSN_FTRVS },
-    { SH64_MEDIA_INSN_GETCFG, && case_sem_INSN_GETCFG },
-    { SH64_MEDIA_INSN_GETCON, && case_sem_INSN_GETCON },
-    { SH64_MEDIA_INSN_GETTR, && case_sem_INSN_GETTR },
-    { SH64_MEDIA_INSN_ICBI, && case_sem_INSN_ICBI },
-    { SH64_MEDIA_INSN_LDB, && case_sem_INSN_LDB },
-    { SH64_MEDIA_INSN_LDL, && case_sem_INSN_LDL },
-    { SH64_MEDIA_INSN_LDQ, && case_sem_INSN_LDQ },
-    { SH64_MEDIA_INSN_LDUB, && case_sem_INSN_LDUB },
-    { SH64_MEDIA_INSN_LDUW, && case_sem_INSN_LDUW },
-    { SH64_MEDIA_INSN_LDW, && case_sem_INSN_LDW },
-    { SH64_MEDIA_INSN_LDHIL, && case_sem_INSN_LDHIL },
-    { SH64_MEDIA_INSN_LDHIQ, && case_sem_INSN_LDHIQ },
-    { SH64_MEDIA_INSN_LDLOL, && case_sem_INSN_LDLOL },
-    { SH64_MEDIA_INSN_LDLOQ, && case_sem_INSN_LDLOQ },
-    { SH64_MEDIA_INSN_LDXB, && case_sem_INSN_LDXB },
-    { SH64_MEDIA_INSN_LDXL, && case_sem_INSN_LDXL },
-    { SH64_MEDIA_INSN_LDXQ, && case_sem_INSN_LDXQ },
-    { SH64_MEDIA_INSN_LDXUB, && case_sem_INSN_LDXUB },
-    { SH64_MEDIA_INSN_LDXUW, && case_sem_INSN_LDXUW },
-    { SH64_MEDIA_INSN_LDXW, && case_sem_INSN_LDXW },
-    { SH64_MEDIA_INSN_MABSL, && case_sem_INSN_MABSL },
-    { SH64_MEDIA_INSN_MABSW, && case_sem_INSN_MABSW },
-    { SH64_MEDIA_INSN_MADDL, && case_sem_INSN_MADDL },
-    { SH64_MEDIA_INSN_MADDW, && case_sem_INSN_MADDW },
-    { SH64_MEDIA_INSN_MADDSL, && case_sem_INSN_MADDSL },
-    { SH64_MEDIA_INSN_MADDSUB, && case_sem_INSN_MADDSUB },
-    { SH64_MEDIA_INSN_MADDSW, && case_sem_INSN_MADDSW },
-    { SH64_MEDIA_INSN_MCMPEQB, && case_sem_INSN_MCMPEQB },
-    { SH64_MEDIA_INSN_MCMPEQL, && case_sem_INSN_MCMPEQL },
-    { SH64_MEDIA_INSN_MCMPEQW, && case_sem_INSN_MCMPEQW },
-    { SH64_MEDIA_INSN_MCMPGTL, && case_sem_INSN_MCMPGTL },
-    { SH64_MEDIA_INSN_MCMPGTUB, && case_sem_INSN_MCMPGTUB },
-    { SH64_MEDIA_INSN_MCMPGTW, && case_sem_INSN_MCMPGTW },
-    { SH64_MEDIA_INSN_MCMV, && case_sem_INSN_MCMV },
-    { SH64_MEDIA_INSN_MCNVSLW, && case_sem_INSN_MCNVSLW },
-    { SH64_MEDIA_INSN_MCNVSWB, && case_sem_INSN_MCNVSWB },
-    { SH64_MEDIA_INSN_MCNVSWUB, && case_sem_INSN_MCNVSWUB },
-    { SH64_MEDIA_INSN_MEXTR1, && case_sem_INSN_MEXTR1 },
-    { SH64_MEDIA_INSN_MEXTR2, && case_sem_INSN_MEXTR2 },
-    { SH64_MEDIA_INSN_MEXTR3, && case_sem_INSN_MEXTR3 },
-    { SH64_MEDIA_INSN_MEXTR4, && case_sem_INSN_MEXTR4 },
-    { SH64_MEDIA_INSN_MEXTR5, && case_sem_INSN_MEXTR5 },
-    { SH64_MEDIA_INSN_MEXTR6, && case_sem_INSN_MEXTR6 },
-    { SH64_MEDIA_INSN_MEXTR7, && case_sem_INSN_MEXTR7 },
-    { SH64_MEDIA_INSN_MMACFXWL, && case_sem_INSN_MMACFXWL },
-    { SH64_MEDIA_INSN_MMACNFX_WL, && case_sem_INSN_MMACNFX_WL },
-    { SH64_MEDIA_INSN_MMULL, && case_sem_INSN_MMULL },
-    { SH64_MEDIA_INSN_MMULW, && case_sem_INSN_MMULW },
-    { SH64_MEDIA_INSN_MMULFXL, && case_sem_INSN_MMULFXL },
-    { SH64_MEDIA_INSN_MMULFXW, && case_sem_INSN_MMULFXW },
-    { SH64_MEDIA_INSN_MMULFXRPW, && case_sem_INSN_MMULFXRPW },
-    { SH64_MEDIA_INSN_MMULHIWL, && case_sem_INSN_MMULHIWL },
-    { SH64_MEDIA_INSN_MMULLOWL, && case_sem_INSN_MMULLOWL },
-    { SH64_MEDIA_INSN_MMULSUMWQ, && case_sem_INSN_MMULSUMWQ },
-    { SH64_MEDIA_INSN_MOVI, && case_sem_INSN_MOVI },
-    { SH64_MEDIA_INSN_MPERMW, && case_sem_INSN_MPERMW },
-    { SH64_MEDIA_INSN_MSADUBQ, && case_sem_INSN_MSADUBQ },
-    { SH64_MEDIA_INSN_MSHALDSL, && case_sem_INSN_MSHALDSL },
-    { SH64_MEDIA_INSN_MSHALDSW, && case_sem_INSN_MSHALDSW },
-    { SH64_MEDIA_INSN_MSHARDL, && case_sem_INSN_MSHARDL },
-    { SH64_MEDIA_INSN_MSHARDW, && case_sem_INSN_MSHARDW },
-    { SH64_MEDIA_INSN_MSHARDSQ, && case_sem_INSN_MSHARDSQ },
-    { SH64_MEDIA_INSN_MSHFHIB, && case_sem_INSN_MSHFHIB },
-    { SH64_MEDIA_INSN_MSHFHIL, && case_sem_INSN_MSHFHIL },
-    { SH64_MEDIA_INSN_MSHFHIW, && case_sem_INSN_MSHFHIW },
-    { SH64_MEDIA_INSN_MSHFLOB, && case_sem_INSN_MSHFLOB },
-    { SH64_MEDIA_INSN_MSHFLOL, && case_sem_INSN_MSHFLOL },
-    { SH64_MEDIA_INSN_MSHFLOW, && case_sem_INSN_MSHFLOW },
-    { SH64_MEDIA_INSN_MSHLLDL, && case_sem_INSN_MSHLLDL },
-    { SH64_MEDIA_INSN_MSHLLDW, && case_sem_INSN_MSHLLDW },
-    { SH64_MEDIA_INSN_MSHLRDL, && case_sem_INSN_MSHLRDL },
-    { SH64_MEDIA_INSN_MSHLRDW, && case_sem_INSN_MSHLRDW },
-    { SH64_MEDIA_INSN_MSUBL, && case_sem_INSN_MSUBL },
-    { SH64_MEDIA_INSN_MSUBW, && case_sem_INSN_MSUBW },
-    { SH64_MEDIA_INSN_MSUBSL, && case_sem_INSN_MSUBSL },
-    { SH64_MEDIA_INSN_MSUBSUB, && case_sem_INSN_MSUBSUB },
-    { SH64_MEDIA_INSN_MSUBSW, && case_sem_INSN_MSUBSW },
-    { SH64_MEDIA_INSN_MULSL, && case_sem_INSN_MULSL },
-    { SH64_MEDIA_INSN_MULUL, && case_sem_INSN_MULUL },
-    { SH64_MEDIA_INSN_NOP, && case_sem_INSN_NOP },
-    { SH64_MEDIA_INSN_NSB, && case_sem_INSN_NSB },
-    { SH64_MEDIA_INSN_OCBI, && case_sem_INSN_OCBI },
-    { SH64_MEDIA_INSN_OCBP, && case_sem_INSN_OCBP },
-    { SH64_MEDIA_INSN_OCBWB, && case_sem_INSN_OCBWB },
-    { SH64_MEDIA_INSN_OR, && case_sem_INSN_OR },
-    { SH64_MEDIA_INSN_ORI, && case_sem_INSN_ORI },
-    { SH64_MEDIA_INSN_PREFI, && case_sem_INSN_PREFI },
-    { SH64_MEDIA_INSN_PTA, && case_sem_INSN_PTA },
-    { SH64_MEDIA_INSN_PTABS, && case_sem_INSN_PTABS },
-    { SH64_MEDIA_INSN_PTB, && case_sem_INSN_PTB },
-    { SH64_MEDIA_INSN_PTREL, && case_sem_INSN_PTREL },
-    { SH64_MEDIA_INSN_PUTCFG, && case_sem_INSN_PUTCFG },
-    { SH64_MEDIA_INSN_PUTCON, && case_sem_INSN_PUTCON },
-    { SH64_MEDIA_INSN_RTE, && case_sem_INSN_RTE },
-    { SH64_MEDIA_INSN_SHARD, && case_sem_INSN_SHARD },
-    { SH64_MEDIA_INSN_SHARDL, && case_sem_INSN_SHARDL },
-    { SH64_MEDIA_INSN_SHARI, && case_sem_INSN_SHARI },
-    { SH64_MEDIA_INSN_SHARIL, && case_sem_INSN_SHARIL },
-    { SH64_MEDIA_INSN_SHLLD, && case_sem_INSN_SHLLD },
-    { SH64_MEDIA_INSN_SHLLDL, && case_sem_INSN_SHLLDL },
-    { SH64_MEDIA_INSN_SHLLI, && case_sem_INSN_SHLLI },
-    { SH64_MEDIA_INSN_SHLLIL, && case_sem_INSN_SHLLIL },
-    { SH64_MEDIA_INSN_SHLRD, && case_sem_INSN_SHLRD },
-    { SH64_MEDIA_INSN_SHLRDL, && case_sem_INSN_SHLRDL },
-    { SH64_MEDIA_INSN_SHLRI, && case_sem_INSN_SHLRI },
-    { SH64_MEDIA_INSN_SHLRIL, && case_sem_INSN_SHLRIL },
-    { SH64_MEDIA_INSN_SHORI, && case_sem_INSN_SHORI },
-    { SH64_MEDIA_INSN_SLEEP, && case_sem_INSN_SLEEP },
-    { SH64_MEDIA_INSN_STB, && case_sem_INSN_STB },
-    { SH64_MEDIA_INSN_STL, && case_sem_INSN_STL },
-    { SH64_MEDIA_INSN_STQ, && case_sem_INSN_STQ },
-    { SH64_MEDIA_INSN_STW, && case_sem_INSN_STW },
-    { SH64_MEDIA_INSN_STHIL, && case_sem_INSN_STHIL },
-    { SH64_MEDIA_INSN_STHIQ, && case_sem_INSN_STHIQ },
-    { SH64_MEDIA_INSN_STLOL, && case_sem_INSN_STLOL },
-    { SH64_MEDIA_INSN_STLOQ, && case_sem_INSN_STLOQ },
-    { SH64_MEDIA_INSN_STXB, && case_sem_INSN_STXB },
-    { SH64_MEDIA_INSN_STXL, && case_sem_INSN_STXL },
-    { SH64_MEDIA_INSN_STXQ, && case_sem_INSN_STXQ },
-    { SH64_MEDIA_INSN_STXW, && case_sem_INSN_STXW },
-    { SH64_MEDIA_INSN_SUB, && case_sem_INSN_SUB },
-    { SH64_MEDIA_INSN_SUBL, && case_sem_INSN_SUBL },
-    { SH64_MEDIA_INSN_SWAPQ, && case_sem_INSN_SWAPQ },
-    { SH64_MEDIA_INSN_SYNCI, && case_sem_INSN_SYNCI },
-    { SH64_MEDIA_INSN_SYNCO, && case_sem_INSN_SYNCO },
-    { SH64_MEDIA_INSN_TRAPA, && case_sem_INSN_TRAPA },
-    { SH64_MEDIA_INSN_XOR, && case_sem_INSN_XOR },
-    { SH64_MEDIA_INSN_XORI, && case_sem_INSN_XORI },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-    {
-#if FAST_P
-      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-    }
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    sh64_media_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    sh64_media_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-#ifdef DEFINE_SWITCH
-    vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    vpc = sh64_media_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = sh64_media_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = sh64_media_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDL) : /* add.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDIL) : /* addi.l $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (ADDSI (EXTSISI (FLD (f_disp10)), SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDZL) : /* addz.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTSIDI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ALLOCO) : /* alloco $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ANDC) : /* andc $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), INVDI (GET_H_GR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ANDI) : /* andi $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQI) : /* beqi$likely $rm, $imm6, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beqi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGE) : /* bge$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEU) : /* bgeu$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGT) : /* bgt$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTU) : /* bgtu$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLINK) : /* blink $trb, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_blink.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    DI opval = ORDI (ADDDI (pc, 4), 1);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-  {
-    UDI opval = CPU (h_tr[FLD (f_trb)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne$likely $rm, $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEI) : /* bnei$likely $rm, $imm6, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beqi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRK) : /* brk */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_break (current_cpu, pc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BYTEREV) : /* byterev $rm, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_source;
-  DI tmp_result;
-  tmp_source = GET_H_GR (FLD (f_left));
-  tmp_result = 0;
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-  {
-    DI opval = tmp_result;
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQ) : /* cmpeq $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPGT) : /* cmpgt $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPGTU) : /* cmpgtu $rm,$rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMVEQ) : /* cmveq $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), 0)) {
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMVNE) : /* cmvne $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FABSD) : /* fabs.d $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FABSS) : /* fabs.s $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fabss (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FADDD) : /* fadd.d $drg, $drh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FADDS) : /* fadd.s $frg, $frh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPEQD) : /* fcmpeq.d $drg, $drh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPEQS) : /* fcmpeq.s $frg, $frh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpeqs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPGED) : /* fcmpge.d $drg, $drh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpged (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPGES) : /* fcmpge.s $frg, $frh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpges (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPGTD) : /* fcmpgt.d $drg, $drh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPGTS) : /* fcmpgt.s $frg, $frh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpgts (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPUND) : /* fcmpun.d $drg, $drh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpund (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCMPUNS) : /* fcmpun.s $frg, $frh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpuns (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCNVDS) : /* fcnv.ds $drgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fcnvds (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FCNVSD) : /* fcnv.sd $frgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FDIVD) : /* fdiv.d $drg, $drh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FDIVS) : /* fdiv.s $frg, $frh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fdivs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FGETSCR) : /* fgetscr $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FIPRS) : /* fipr.s $fvg, $fvh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  UQI tmp_g;
-  UQI tmp_h;
-  SF tmp_temp;
-  tmp_g = FLD (f_left);
-  tmp_h = FLD (f_right);
-  tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
-  {
-    SF opval = tmp_temp;
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDD) : /* fld.d $rm, $disp10x8, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDP) : /* fld.p $rm, $disp10x8, $fpf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
-    CPU (h_fr[tmp_f]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
-    CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDS) : /* fld.s $rm, $disp10x4, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_flds.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDXD) : /* fldx.d $rm, $rn, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDXP) : /* fldx.p $rm, $rn, $fpf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    CPU (h_fr[tmp_f]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
-    CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLDXS) : /* fldx.s $rm, $rn, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLOATLD) : /* float.ld $frgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_floatld (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLOATLS) : /* float.ls $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_floatls (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLOATQD) : /* float.qd $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_floatqd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FLOATQS) : /* float.qs $drgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_floatqs (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMACS) : /* fmac.s $frg, $frh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_dest)]), sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVD) : /* fmov.d $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_left_right));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVDQ) : /* fmov.dq $drgh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SUBWORDDFDI (GET_H_DR (FLD (f_left_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVLS) : /* fmov.ls $rm, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = SUBWORDSISF (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVQD) : /* fmov.qd $rm, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = SUBWORDDIDF (GET_H_GR (FLD (f_left)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVS) : /* fmov.s $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_left_right)]);
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMOVSL) : /* fmov.sl $frgh, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMULD) : /* fmul.d $drg, $drh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FMULS) : /* fmul.s $frg, $frh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FNEGD) : /* fneg.d $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FNEGS) : /* fneg.s $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fnegs (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FPUTSCR) : /* fputscr $frgh */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSQRTD) : /* fsqrt.d $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSQRTS) : /* fsqrt.s $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fsqrts (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTD) : /* fst.d $rm, $disp10x8, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_dest));
-    SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTP) : /* fst.p $rm, $disp10x8, $fpf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = CPU (h_fr[tmp_f]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTS) : /* fst.s $rm, $disp10x4, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_flds.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_dest)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTXD) : /* fstx.d $rm, $rn, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_dest));
-    SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTXP) : /* fstx.p $rm, $rn, $fpf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = CPU (h_fr[tmp_f]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSTXS) : /* fstx.s $rm, $rn, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_dest)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSUBD) : /* fsub.d $drg, $drh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FSUBS) : /* fsub.s $frg, $frh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fsubs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRCDL) : /* ftrc.dl $drgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRCSL) : /* ftrc.sl $frgh, $frf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_ftrcsl (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRCDQ) : /* ftrc.dq $drgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_ftrcdq (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRCSQ) : /* ftrc.sq $frgh, $drf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_ftrcsq (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_FTRVS) : /* ftrv.s $mtrxg, $fvh, $fvf */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_GETCFG) : /* getcfg $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_GETCON) : /* getcon $crk, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_CR (FLD (f_left));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_GETTR) : /* gettr $trb, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_blink.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = CPU (h_tr[FLD (f_trb)]);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ICBI) : /* icbi $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ld.b $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDL) : /* ld.l $rm, $disp10x4, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_flds.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDQ) : /* ld.q $rm, $disp10x8, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ld.ub $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUW) : /* ld.uw $rm, $disp10x2, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDW) : /* ld.w $rm, $disp10x2, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDHIL) : /* ldhi.l $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  SI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -4)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = EXTSIDI (tmp_val);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-  {
-    DI opval = EXTSIDI (SLLSI (tmp_val, SUBSI (32, MULSI (8, tmp_bytecount))));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDHIQ) : /* ldhi.q $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ANDDI (tmp_addr, -8));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8))));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = tmp_val;
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8))));
-}
-  {
-    DI opval = SLLDI (tmp_val, SUBSI (64, MULSI (8, tmp_bytecount)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDLOL) : /* ldlo.l $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  SI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (4, ANDDI (tmp_addr, 3));
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, tmp_addr));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-  {
-    DI opval = EXTSIDI (SLLSI (tmp_val, SUBSI (32, MULSI (8, tmp_bytecount))));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = EXTSIDI (tmp_val);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDLOQ) : /* ldlo.q $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (8, ANDDI (tmp_addr, 7));
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GETMEMDI (current_cpu, pc, tmp_addr);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4))));
-}
-  {
-    DI opval = SLLDI (tmp_val, SUBSI (64, MULSI (8, tmp_bytecount)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4))));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = tmp_val;
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXB) : /* ldx.b $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXL) : /* ldx.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXQ) : /* ldx.q $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXUB) : /* ldx.ub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXUW) : /* ldx.uw $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDXW) : /* ldx.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MABSL) : /* mabs.l $rm, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
-  tmp_result1 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MABSW) : /* mabs.w $rm, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3));
-  tmp_result1 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2));
-  tmp_result2 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1));
-  tmp_result3 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MADDL) : /* madd.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MADDW) : /* madd.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MADDSL) : /* madds.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MADDSUB) : /* madds.ub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MADDSW) : /* madds.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPEQB) : /* mcmpeq.b $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
-  tmp_result1 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
-  tmp_result2 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
-  tmp_result3 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
-  tmp_result4 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
-  tmp_result5 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
-  tmp_result6 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
-  tmp_result7 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPEQL) : /* mcmpeq.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
-  tmp_result1 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPEQW) : /* mcmpeq.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
-  tmp_result1 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
-  tmp_result2 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
-  tmp_result3 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPGTL) : /* mcmpgt.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
-  tmp_result1 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPGTUB) : /* mcmpgt.ub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
-  tmp_result1 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
-  tmp_result2 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
-  tmp_result3 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
-  tmp_result4 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
-  tmp_result5 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
-  tmp_result6 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
-  tmp_result7 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMPGTW) : /* mcmpgt.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
-  tmp_result1 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
-  tmp_result2 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
-  tmp_result3 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCMV) : /* mcmv $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), ANDDI (GET_H_GR (FLD (f_dest)), INVDI (GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCNVSLW) : /* mcnvs.lw $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCNVSWB) : /* mcnvs.wb $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MCNVSWUB) : /* mcnvs.wub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR1) : /* mextr1 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 1);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 1));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR2) : /* mextr2 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 2);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 2));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR3) : /* mextr3 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 3);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 3));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR4) : /* mextr4 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 4);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 4));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR5) : /* mextr5 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 5);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 5));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR6) : /* mextr6 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 6);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 6));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MEXTR7) : /* mextr7 $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 7);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 7));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMACFXWL) : /* mmacfx.wl $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result0 = ((LTDI (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMACNFX_WL) : /* mmacnfx.wl $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result0 = ((LTDI (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULL) : /* mmul.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULW) : /* mmul.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULFXL) : /* mmulfx.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_temp;
-  SI tmp_result0;
-  SI tmp_result1;
-  tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result0 = ((LTDI (SRADI (tmp_temp, 31), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLDI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result1 = ((LTDI (SRADI (tmp_temp, 31), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLDI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULFXW) : /* mmulfx.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  HI tmp_result0;
-  HI tmp_result1;
-  HI tmp_result2;
-  HI tmp_result3;
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result0 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_result1 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result2 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result3 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULFXRPW) : /* mmulfxrp.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  HI tmp_result0;
-  HI tmp_result1;
-  HI tmp_result2;
-  HI tmp_result3;
-  HI tmp_c;
-  tmp_c = SLLSI (1, 14);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result0 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_result1 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result2 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result3 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULHIWL) : /* mmulhi.wl $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULLOWL) : /* mmullo.wl $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MMULSUMWQ) : /* mmulsum.wq $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_acc;
-  tmp_acc = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))));
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MOVI) : /* movi $imm16, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_movi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (FLD (f_imm16));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MPERMW) : /* mperm.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_control;
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_control = ANDQI (GET_H_GR (FLD (f_right)), 255);
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (tmp_control, 3)));
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 2), 3)));
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 4), 3)));
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 6), 3)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSADUBQ) : /* msad.ubq $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_acc;
-  tmp_acc = ABSDI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))));
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHALDSL) : /* mshalds.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHALDSW) : /* mshalds.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHARDL) : /* mshard.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHARDW) : /* mshard.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHARDSQ) : /* mshards.q $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGDI (SLLDI (1, SUBSI (16, 1)))) : (((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), SLLDI (1, SUBSI (16, 1)))) ? (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63))) : (SUBDI (SLLDI (1, SUBSI (16, 1)), 1)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFHIB) : /* mshfhi.b $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3);
-  tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3);
-  tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2);
-  tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2);
-  tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1);
-  tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFHIL) : /* mshfhi.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFHIW) : /* mshfhi.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1);
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFLOB) : /* mshflo.b $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7);
-  tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7);
-  tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6);
-  tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6);
-  tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5);
-  tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5);
-  tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4);
-  tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4);
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFLOL) : /* mshflo.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 1);
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHFLOW) : /* mshflo.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3);
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3);
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2);
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2);
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHLLDL) : /* mshlld.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHLLDW) : /* mshlld.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHLRDL) : /* mshlrd.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSHLRDW) : /* mshlrd.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSUBL) : /* msub.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSUBW) : /* msub.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSUBSL) : /* msubs.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSUBSUB) : /* msubs.ub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSUBSW) : /* msubs.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result4 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result5 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result6 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result7 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULSL) : /* muls.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = MULDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULUL) : /* mulu.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NSB) : /* nsb $rm, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = sh64_nsb (current_cpu, GET_H_GR (FLD (f_left)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBI) : /* ocbi $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBP) : /* ocbp $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OCBWB) : /* ocbwb $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ORI) : /* ori $rm, $imm10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PREFI) : /* prefi $rm, $disp6x32 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PTA) : /* pta$likely $disp16, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_pta.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDSI (FLD (f_disp16), 1);
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PTABS) : /* ptabs$likely $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PTB) : /* ptb$likely $disp16, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_pta.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = FLD (f_disp16);
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PTREL) : /* ptrel$likely $rn, $tra */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PUTCFG) : /* putcfg $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PUTCON) : /* putcon $rm, $crj */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_left));
-    SET_H_CR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHARD) : /* shard $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHARDL) : /* shard.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHARI) : /* shari $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRADI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHARIL) : /* shari.l $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLLD) : /* shlld $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SLLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLLDL) : /* shlld.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLLI) : /* shlli $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SLLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLLIL) : /* shlli.l $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLRD) : /* shlrd $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLRDL) : /* shlrd.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLRI) : /* shlri $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHLRIL) : /* shlri.l $rm, $uimm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shari.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SHORI) : /* shori $uimm16, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_shori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (SLLDI (GET_H_GR (FLD (f_dest)), 16), ZEXTSIDI (FLD (f_uimm16)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLEEP) : /* sleep */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* st.b $rm, $disp10, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    UQI opval = ANDQI (GET_H_GR (FLD (f_dest)), 255);
-    SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STL) : /* st.l $rm, $disp10x4, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_flds.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (GET_H_GR (FLD (f_dest)), 0xffffffff);
-    SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STQ) : /* st.q $rm, $disp10x8, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STW) : /* st.w $rm, $disp10x2, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = ANDHI (GET_H_GR (FLD (f_dest)), 65535);
-    SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STHIL) : /* sthi.l $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    SI opval = GET_H_GR (FLD (f_dest));
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-}
-} else {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STHIQ) : /* sthi.q $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    SI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-}
-} else {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    SI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STLOL) : /* stlo.l $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (4, ANDDI (tmp_addr, 3));
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    USI opval = GET_H_GR (FLD (f_dest));
-    SETMEMUSI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-} else {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STLOQ) : /* stlo.q $rm, $disp6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (8, ANDDI (tmp_addr, 7));
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    UDI opval = GET_H_GR (FLD (f_dest));
-    SETMEMUDI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    USI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMUSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-} else {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    USI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMUSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STXB) : /* stx.b $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    UQI opval = SUBWORDDIQI (GET_H_GR (FLD (f_dest)), 7);
-    SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STXL) : /* stx.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-    SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STXQ) : /* stx.q $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STXW) : /* stx.w $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = SUBWORDDIHI (GET_H_GR (FLD (f_dest)), 3);
-    SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SUBDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBL) : /* sub.l $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SWAPQ) : /* swap.q $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  DI tmp_temp;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-  tmp_temp = GETMEMDI (current_cpu, pc, tmp_addr);
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-  {
-    DI opval = tmp_temp;
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SYNCI) : /* synci */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SYNCO) : /* synco */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAPA) : /* trapa $rm */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_trapa (current_cpu, GET_H_GR (FLD (f_left)), pc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $rm, $rn, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XORI) : /* xori $rm, $imm6, $rd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_xori.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/sh64/sem-media.c b/sim/sh64/sem-media.c
deleted file mode 100644
index aee11ccf174..00000000000
--- a/sim/sh64/sem-media.c
+++ /dev/null
@@ -1,5965 +0,0 @@
-/* Simulator instruction semantics for sh64.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU sh64
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-/* This is used so that we can compile two copies of the semantic code,
-   one with full feature support and one without that runs fast(er).
-   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */
-#if FAST_P
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#else
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
-#endif
-
-/* x-invalid: --invalid-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-after: --after-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    sh64_media_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-before: --before-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    sh64_media_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-cti-chain: --cti-chain-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-#ifdef DEFINE_SWITCH
-    vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-chain: --chain-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-    vpc = sh64_media_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-begin: --begin-- */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_SH64_MEDIA
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = sh64_media_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = sh64_media_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add: add $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addl: add.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,addl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addi: addi $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addil: addi.l $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,addil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (ADDSI (EXTSISI (FLD (f_disp10)), SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addzl: addz.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,addzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTSIDI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* alloco: alloco $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,alloco) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* and: and $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* andc: andc $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,andc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), INVDI (GET_H_GR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* andi: andi $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ANDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* beq: beq$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* beqi: beqi$likely $rm, $imm6, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,beqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beqi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bge: bge$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgeu: bgeu$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgt: bgt$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgtu: bgtu$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* blink: blink $trb, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_blink.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    DI opval = ORDI (ADDDI (pc, 4), 1);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-  {
-    UDI opval = CPU (h_tr[FLD (f_trb)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bne: bne$likely $rm, $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnei: bnei$likely $rm, $imm6, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,bnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beqi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
-  {
-    UDI opval = CPU (h_tr[FLD (f_tra)]);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* brk: brk */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,brk) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_break (current_cpu, pc);
-
-  return vpc;
-#undef FLD
-}
-
-/* byterev: byterev $rm, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,byterev) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_source;
-  DI tmp_result;
-  tmp_source = GET_H_GR (FLD (f_left));
-  tmp_result = 0;
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-{
-  tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
-  tmp_source = SRLDI (tmp_source, 8);
-}
-  {
-    DI opval = tmp_result;
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpeq: cmpeq $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpgt: cmpgt $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,cmpgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpgtu: cmpgtu $rm,$rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,cmpgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmveq: cmveq $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,cmveq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQDI (GET_H_GR (FLD (f_left)), 0)) {
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* cmvne: cmvne $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,cmvne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* fabsd: fabs.d $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fabsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fabss: fabs.s $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fabss (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* faddd: fadd.d $drg, $drh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,faddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fadds: fadd.s $frg, $frh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpeqd: fcmpeq.d $drg, $drh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpeqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpeqs: fcmpeq.s $frg, $frh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpeqs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpeqs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpged: fcmpge.d $drg, $drh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpged) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpged (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpges: fcmpge.s $frg, $frh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpges (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpgtd: fcmpgt.d $drg, $drh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpgts: fcmpgt.s $frg, $frh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpgts (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpund: fcmpun.d $drg, $drh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpund) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpund (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcmpuns: fcmpun.s $frg, $frh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcmpuns) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTBIDI (sh64_fcmpuns (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcnvds: fcnv.ds $drgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcnvds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fcnvds (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fcnvsd: fcnv.sd $frgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fcnvsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fdivd: fdiv.d $drg, $drh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fdivd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fdivs: fdiv.s $frg, $frh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fdivs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fgetscr: fgetscr $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fgetscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* fiprs: fipr.s $fvg, $fvh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fiprs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  UQI tmp_g;
-  UQI tmp_h;
-  SF tmp_temp;
-  tmp_g = FLD (f_left);
-  tmp_h = FLD (f_right);
-  tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
-  tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
-  {
-    SF opval = tmp_temp;
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* fldd: fld.d $rm, $disp10x8, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fldp: fld.p $rm, $disp10x8, $fpf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fldp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
-    CPU (h_fr[tmp_f]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
-    CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* flds: fld.s $rm, $disp10x4, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,flds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_flds.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fldxd: fldx.d $rm, $rn, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fldxd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fldxp: fldx.p $rm, $rn, $fpf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fldxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    CPU (h_fr[tmp_f]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
-    CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* fldxs: fldx.s $rm, $rn, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fldxs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* floatld: float.ld $frgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,floatld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_floatld (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* floatls: float.ls $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,floatls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_floatls (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* floatqd: float.qd $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,floatqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_floatqd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* floatqs: float.qs $drgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,floatqs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_floatqs (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmacs: fmac.s $frg, $frh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmacs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_dest)]), sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovd: fmov.d $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_left_right));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovdq: fmov.dq $drgh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovdq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SUBWORDDFDI (GET_H_DR (FLD (f_left_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovls: fmov.ls $rm, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = SUBWORDSISF (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovqd: fmov.qd $rm, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = SUBWORDDIDF (GET_H_GR (FLD (f_left)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovs: fmov.s $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_left_right)]);
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmovsl: fmov.sl $frgh, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmovsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmuld: fmul.d $drg, $drh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmuld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fmuls: fmul.s $frg, $frh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fnegd: fneg.d $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fnegd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fnegs: fneg.s $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fnegs (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fputscr: fputscr $frgh */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fputscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* fsqrtd: fsqrt.d $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fsqrtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fsqrts: fsqrt.s $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fsqrts (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fstd: fst.d $rm, $disp10x8, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_dest));
-    SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fstp: fst.p $rm, $disp10x8, $fpf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fstp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = CPU (h_fr[tmp_f]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* fsts: fst.s $rm, $disp10x4, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fsts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_flds.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_dest)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fstxd: fstx.d $rm, $rn, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fstxd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = GET_H_DR (FLD (f_dest));
-    SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fstxp: fstx.p $rm, $rn, $fpf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fstxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_f;
-  tmp_f = FLD (f_dest);
-  {
-    SF opval = CPU (h_fr[tmp_f]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-  {
-    SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* fstxs: fstx.s $rm, $rn, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fstxs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = CPU (h_fr[FLD (f_dest)]);
-    SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fsubd: fsub.d $drg, $drh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* fsubs: fsub.s $frg, $frh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,fsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_fsubs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrcdl: ftrc.dl $drgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ftrcdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_left_right)));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrcsl: ftrc.sl $frgh, $frf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ftrcsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SF opval = sh64_ftrcsl (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    CPU (h_fr[FLD (f_dest)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrcdq: ftrc.dq $drgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ftrcdq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_ftrcdq (current_cpu, GET_H_DR (FLD (f_left_right)));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrcsq: ftrc.sq $frgh, $drf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ftrcsq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fabsd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DF opval = sh64_ftrcsq (current_cpu, CPU (h_fr[FLD (f_left_right)]));
-    SET_H_DR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'f', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ftrvs: ftrv.s $mtrxg, $fvh, $fvf */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ftrvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
-
-  return vpc;
-#undef FLD
-}
-
-/* getcfg: getcfg $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,getcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* getcon: getcon $crk, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,getcon) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_CR (FLD (f_left));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* gettr: gettr $trb, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,gettr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_blink.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = CPU (h_tr[FLD (f_trb)]);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* icbi: icbi $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,icbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* ldb: ld.b $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldl: ld.l $rm, $disp10x4, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_flds.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldq: ld.q $rm, $disp10x8, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldub: ld.ub $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lduw: ld.uw $rm, $disp10x2, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,lduw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldw: ld.w $rm, $disp10x2, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldhil: ldhi.l $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  SI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -4)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = EXTSIDI (tmp_val);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-  {
-    DI opval = EXTSIDI (SLLSI (tmp_val, SUBSI (32, MULSI (8, tmp_bytecount))));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* ldhiq: ldhi.q $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldhiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ANDDI (tmp_addr, -8));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8))));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = tmp_val;
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4))));
-}
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8))));
-}
-  {
-    DI opval = SLLDI (tmp_val, SUBSI (64, MULSI (8, tmp_bytecount)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* ldlol: ldlo.l $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  SI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (4, ANDDI (tmp_addr, 3));
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, tmp_addr));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-  {
-    DI opval = EXTSIDI (SLLSI (tmp_val, SUBSI (32, MULSI (8, tmp_bytecount))));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDSI (SLLSI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = EXTSIDI (tmp_val);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* ldloq: ldlo.q $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (8, ANDDI (tmp_addr, 7));
-  tmp_val = 0;
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GETMEMDI (current_cpu, pc, tmp_addr);
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4))));
-}
-  {
-    DI opval = SLLDI (tmp_val, SUBSI (64, MULSI (8, tmp_bytecount)));
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-} else {
-{
-if (ANDQI (tmp_bytecount, 4)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 32), ZEXTSIDI (GETMEMSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4))));
-}
-if (ANDQI (tmp_bytecount, 2)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 16), ZEXTHIDI (GETMEMHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2))));
-}
-if (ANDQI (tmp_bytecount, 1)) {
-  tmp_val = ADDDI (SLLDI (tmp_val, 8), ZEXTQIDI (GETMEMQI (current_cpu, pc, tmp_addr)));
-}
-  {
-    DI opval = tmp_val;
-    SET_H_GR (FLD (f_dest), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* ldxb: ldx.b $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldxl: ldx.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldxq: ldx.q $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldxub: ldx.ub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldxuw: ldx.uw $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxuw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldxw: ldx.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ldxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mabsl: mabs.l $rm, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mabsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
-  tmp_result1 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mabsw: mabs.w $rm, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3));
-  tmp_result1 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2));
-  tmp_result2 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1));
-  tmp_result3 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* maddl: madd.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,maddl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* maddw: madd.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,maddw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* maddsl: madds.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,maddsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* maddsub: madds.ub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,maddsub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), MAKEDI (0, 0))) ? (0) : (((LTDI (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, 8))) ? (ADDDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* maddsw: madds.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,maddsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (16, 1)))) ? (ADDDI (EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), EXTHIDI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpeqb: mcmpeq.b $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpeqb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
-  tmp_result1 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
-  tmp_result2 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
-  tmp_result3 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
-  tmp_result4 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
-  tmp_result5 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
-  tmp_result6 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
-  tmp_result7 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpeql: mcmpeq.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpeql) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
-  tmp_result1 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpeqw: mcmpeq.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpeqw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
-  tmp_result1 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
-  tmp_result2 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
-  tmp_result3 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpgtl: mcmpgt.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpgtl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
-  tmp_result1 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpgtub: mcmpgt.ub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpgtub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
-  tmp_result1 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
-  tmp_result2 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
-  tmp_result3 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
-  tmp_result4 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
-  tmp_result5 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
-  tmp_result6 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
-  tmp_result7 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmpgtw: mcmpgt.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmpgtw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
-  tmp_result1 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
-  tmp_result2 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
-  tmp_result3 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcmv: mcmv $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), ANDDI (GET_H_GR (FLD (f_dest)), INVDI (GET_H_GR (FLD (f_right)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mcnvslw: mcnvs.lw $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcnvslw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcnvswb: mcnvs.wb $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcnvswb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), NEGDI (SLLDI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mcnvswub: mcnvs.wub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mcnvswub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), MAKEDI (0, 0))) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLDI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr1: mextr1 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 1);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 1));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr2: mextr2 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 2);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 2));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr3: mextr3 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 3);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 3));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr4: mextr4 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr4) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 4);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 4));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr5: mextr5 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr5) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 5);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 5));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr6: mextr6 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 6);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 6));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mextr7: mextr7 $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mextr7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_count;
-  DI tmp_mask;
-  DI tmp_rhs;
-  tmp_count = MULQI (8, 7);
-  tmp_mask = SLLDI (INVSI (0), tmp_count);
-  tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
-  tmp_count = MULQI (8, SUBQI (8, 7));
-  tmp_mask = SRLDI (INVSI (0), tmp_count);
-  {
-    DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmacfxwl: mmacfx.wl $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmacfxwl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result0 = ((LTDI (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (ADDDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmacnfx.wl: mmacnfx.wl $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmacnfx_wl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result0 = ((LTDI (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (tmp_result0), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_temp = ((LTDI (SLLDI (tmp_temp, 1), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (tmp_temp, 1), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp)), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (tmp_result1), EXTSIDI (tmp_temp))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmull: mmul.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmull) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulw: mmul.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulfxl: mmulfx.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulfxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_temp;
-  SI tmp_result0;
-  SI tmp_result1;
-  tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result0 = ((LTDI (SRADI (tmp_temp, 31), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLDI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result1 = ((LTDI (SRADI (tmp_temp, 31), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLDI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulfxw: mmulfx.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulfxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  HI tmp_result0;
-  HI tmp_result1;
-  HI tmp_result2;
-  HI tmp_result3;
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result0 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_result1 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result2 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result3 = ((LTSI (SRASI (tmp_temp, 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulfxrpw: mmulfxrp.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulfxrpw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_temp;
-  HI tmp_result0;
-  HI tmp_result1;
-  HI tmp_result2;
-  HI tmp_result3;
-  HI tmp_c;
-  tmp_c = SLLSI (1, 14);
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result0 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  tmp_result1 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result2 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_result3 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLDI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulhiwl: mmulhi.wl $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulhiwl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
-  tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmullowl: mmullo.wl $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmullowl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
-  tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mmulsumwq: mmulsum.wq $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mmulsumwq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_acc;
-  tmp_acc = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))));
-  tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))));
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* movi: movi $imm16, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,movi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_movi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (FLD (f_imm16));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mpermw: mperm.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mpermw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_control;
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_control = ANDQI (GET_H_GR (FLD (f_right)), 255);
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (tmp_control, 3)));
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 2), 3)));
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 4), 3)));
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 6), 3)));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msadubq: msad.ubq $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msadubq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_acc;
-  tmp_acc = ABSDI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))));
-  tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))));
-  {
-    DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshaldsl: mshalds.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshaldsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLDI (1, SUBSI (32, 1)))) ? (SLLDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshaldsw: mshalds.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshaldsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLDI (1, SUBSI (16, 1)))) ? (SLLDI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshardl: mshard.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshardl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshardw: mshard.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshardw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshardsq: mshards.q $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshardsq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGDI (SLLDI (1, SUBSI (16, 1)))) : (((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), SLLDI (1, SUBSI (16, 1)))) ? (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63))) : (SUBDI (SLLDI (1, SUBSI (16, 1)), 1)))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mshfhib: mshfhi.b $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshfhib) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3);
-  tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3);
-  tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2);
-  tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2);
-  tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1);
-  tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshfhil: mshfhi.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshfhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshfhiw: mshfhi.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshfhiw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1);
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0);
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0);
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshflob: mshflo.b $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshflob) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7);
-  tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7);
-  tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6);
-  tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6);
-  tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5);
-  tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5);
-  tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4);
-  tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4);
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshflol: mshflo.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshflol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 1);
-  tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 1);
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshflow: mshflo.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshflow) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3);
-  tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3);
-  tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2);
-  tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2);
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshlldl: mshlld.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshlldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshlldw: mshlld.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshlldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshlrdl: mshlrd.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshlrdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  tmp_result1 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mshlrdw: mshlrd.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mshlrdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result1 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result2 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  tmp_result3 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msubl: msub.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msubl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result1 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msubw: msub.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msubw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  HI tmp_result3;
-  HI tmp_result2;
-  HI tmp_result1;
-  HI tmp_result0;
-  tmp_result0 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
-  tmp_result1 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
-  tmp_result2 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
-  tmp_result3 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
-  {
-    DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msubsl: msubs.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msubsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI tmp_result1;
-  SI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (32, 1)))) ? (SUBDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msubsub: msubs.ub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msubsub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result2 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result3 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result4 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result5 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result6 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  tmp_result7 = ((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), MAKEDI (0, 0))) ? (0) : (((LTDI (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, 8))) ? (SUBDI (ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), ZEXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBQI (SLLQI (1, 8), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* msubsw: msubs.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,msubsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  QI tmp_result7;
-  QI tmp_result6;
-  QI tmp_result5;
-  QI tmp_result4;
-  QI tmp_result3;
-  QI tmp_result2;
-  QI tmp_result1;
-  QI tmp_result0;
-  tmp_result0 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result1 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result2 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result3 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result4 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result5 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result6 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  tmp_result7 = ((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTDI (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))), SLLDI (1, SUBSI (16, 1)))) ? (SUBDI (EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0)), EXTQIDI (SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
-  {
-    DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* mulsl: muls.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mulsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = MULDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulul: mulu.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,mulul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* nop: nop */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* nsb: nsb $rm, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,nsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = sh64_nsb (current_cpu, GET_H_GR (FLD (f_left)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbi: ocbi $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbp: ocbp $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* ocbwb: ocbwb $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ocbwb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* or: or $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ori: ori $rm, $imm10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm10)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* prefi: prefi $rm, $disp6x32 */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,prefi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* pta: pta$likely $disp16, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,pta) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_pta.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDSI (FLD (f_disp16), 1);
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ptabs: ptabs$likely $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ptabs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_right));
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ptb: ptb$likely $disp16, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ptb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_pta.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = FLD (f_disp16);
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ptrel: ptrel$likely $rn, $tra */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
-    CPU (h_tr[FLD (f_tra)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* putcfg: putcfg $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,putcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* putcon: putcon $rm, $crj */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,putcon) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_left));
-    SET_H_CR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* rte: rte */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* shard: shard $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shard) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shardl: shard.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shardl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shari: shari $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shari) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRADI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sharil: shari.l $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,sharil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlld: shlld $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SLLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlldl: shlld.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlli: shlli $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SLLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shllil: shlli.l $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shllil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlrd: shlrd $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlrdl: shlrd.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlrdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlri: shlri $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SRLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shlril: shlri.l $rm, $uimm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shlril) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shari.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* shori: shori $uimm16, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,shori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_shori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = ORDI (SLLDI (GET_H_GR (FLD (f_dest)), 16), ZEXTSIDI (FLD (f_uimm16)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sleep: sleep */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,sleep) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* stb: st.b $rm, $disp10, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    UQI opval = ANDQI (GET_H_GR (FLD (f_dest)), 255);
-    SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stl: st.l $rm, $disp10x4, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_flds.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (GET_H_GR (FLD (f_dest)), 0xffffffff);
-    SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stq: st.q $rm, $disp10x8, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_fldd.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stw: st.w $rm, $disp10x2, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_lduw.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = ANDHI (GET_H_GR (FLD (f_dest)), 65535);
-    SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sthil: sthi.l $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,sthil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    SI opval = GET_H_GR (FLD (f_dest));
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-}
-} else {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* sthiq: sthi.q $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,sthiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    SI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-}
-} else {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    SI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMSI (current_cpu, pc, ANDDI (tmp_addr, -8), opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    HI opval = ANDHI (tmp_val, 65535);
-    SETMEMHI (current_cpu, pc, ANDDI (tmp_addr, -4), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* stlol: stlo.l $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (4, ANDDI (tmp_addr, 3));
-if (ANDQI (tmp_bytecount, 4)) {
-  {
-    USI opval = GET_H_GR (FLD (f_dest));
-    SETMEMUSI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-} else {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* stloq: stlo.q $rm, $disp6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ldhil.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  QI tmp_bytecount;
-  DI tmp_val;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
-  tmp_bytecount = SUBSI (8, ANDDI (tmp_addr, 7));
-if (ANDQI (tmp_bytecount, 8)) {
-  {
-    UDI opval = GET_H_GR (FLD (f_dest));
-    SETMEMUDI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-} else {
-if (GET_H_ENDIAN ()) {
-{
-  tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    USI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMUSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-}
-} else {
-{
-  tmp_val = GET_H_GR (FLD (f_dest));
-if (ANDQI (tmp_bytecount, 1)) {
-{
-  {
-    UQI opval = ANDQI (tmp_val, 255);
-    SETMEMUQI (current_cpu, pc, tmp_addr, opval);
-    written |= (1 << 6);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 8);
-}
-}
-if (ANDQI (tmp_bytecount, 2)) {
-{
-  {
-    UHI opval = ANDHI (tmp_val, 65535);
-    SETMEMUHI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 1), -2), opval);
-    written |= (1 << 5);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 16);
-}
-}
-if (ANDQI (tmp_bytecount, 4)) {
-{
-  {
-    USI opval = ANDSI (tmp_val, 0xffffffff);
-    SETMEMUSI (current_cpu, pc, ANDDI (ADDDI (tmp_addr, 3), -4), opval);
-    written |= (1 << 7);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_val = SRLDI (tmp_val, 32);
-}
-}
-}
-}
-}
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* stxb: stx.b $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stxb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    UQI opval = SUBWORDDIQI (GET_H_GR (FLD (f_dest)), 7);
-    SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stxl: stx.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
-    SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stxq: stx.q $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stxq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stxw: stx.w $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,stxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = SUBWORDDIHI (GET_H_GR (FLD (f_dest)), 3);
-    SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sub: sub $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = SUBDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* subl: sub.l $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,subl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = EXTSIDI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* swapq: swap.q $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,swapq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  DI tmp_addr;
-  DI tmp_temp;
-  tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-  tmp_temp = GETMEMDI (current_cpu, pc, tmp_addr);
-  {
-    DI opval = GET_H_GR (FLD (f_dest));
-    SETMEMDI (current_cpu, pc, tmp_addr, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
-  }
-  {
-    DI opval = tmp_temp;
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* synci: synci */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,synci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* synco: synco */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,synco) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-((void) 0); /*nop*/
-
-  return vpc;
-#undef FLD
-}
-
-/* trapa: trapa $rm */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,trapa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-sh64_trapa (current_cpu, GET_H_GR (FLD (f_left)), pc);
-
-  return vpc;
-#undef FLD
-}
-
-/* xor: xor $rm, $rn, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xori: xori $rm, $imm6, $rd */
-
-static SEM_PC
-SEM_FN_NAME (sh64_media,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_xori.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    DI opval = XORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)));
-    SET_H_GR (FLD (f_dest), opval);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* Table of all semantic fns.  */
-
-static const struct sem_fn_desc sem_fns[] = {
-  { SH64_MEDIA_INSN_X_INVALID, SEM_FN_NAME (sh64_media,x_invalid) },
-  { SH64_MEDIA_INSN_X_AFTER, SEM_FN_NAME (sh64_media,x_after) },
-  { SH64_MEDIA_INSN_X_BEFORE, SEM_FN_NAME (sh64_media,x_before) },
-  { SH64_MEDIA_INSN_X_CTI_CHAIN, SEM_FN_NAME (sh64_media,x_cti_chain) },
-  { SH64_MEDIA_INSN_X_CHAIN, SEM_FN_NAME (sh64_media,x_chain) },
-  { SH64_MEDIA_INSN_X_BEGIN, SEM_FN_NAME (sh64_media,x_begin) },
-  { SH64_MEDIA_INSN_ADD, SEM_FN_NAME (sh64_media,add) },
-  { SH64_MEDIA_INSN_ADDL, SEM_FN_NAME (sh64_media,addl) },
-  { SH64_MEDIA_INSN_ADDI, SEM_FN_NAME (sh64_media,addi) },
-  { SH64_MEDIA_INSN_ADDIL, SEM_FN_NAME (sh64_media,addil) },
-  { SH64_MEDIA_INSN_ADDZL, SEM_FN_NAME (sh64_media,addzl) },
-  { SH64_MEDIA_INSN_ALLOCO, SEM_FN_NAME (sh64_media,alloco) },
-  { SH64_MEDIA_INSN_AND, SEM_FN_NAME (sh64_media,and) },
-  { SH64_MEDIA_INSN_ANDC, SEM_FN_NAME (sh64_media,andc) },
-  { SH64_MEDIA_INSN_ANDI, SEM_FN_NAME (sh64_media,andi) },
-  { SH64_MEDIA_INSN_BEQ, SEM_FN_NAME (sh64_media,beq) },
-  { SH64_MEDIA_INSN_BEQI, SEM_FN_NAME (sh64_media,beqi) },
-  { SH64_MEDIA_INSN_BGE, SEM_FN_NAME (sh64_media,bge) },
-  { SH64_MEDIA_INSN_BGEU, SEM_FN_NAME (sh64_media,bgeu) },
-  { SH64_MEDIA_INSN_BGT, SEM_FN_NAME (sh64_media,bgt) },
-  { SH64_MEDIA_INSN_BGTU, SEM_FN_NAME (sh64_media,bgtu) },
-  { SH64_MEDIA_INSN_BLINK, SEM_FN_NAME (sh64_media,blink) },
-  { SH64_MEDIA_INSN_BNE, SEM_FN_NAME (sh64_media,bne) },
-  { SH64_MEDIA_INSN_BNEI, SEM_FN_NAME (sh64_media,bnei) },
-  { SH64_MEDIA_INSN_BRK, SEM_FN_NAME (sh64_media,brk) },
-  { SH64_MEDIA_INSN_BYTEREV, SEM_FN_NAME (sh64_media,byterev) },
-  { SH64_MEDIA_INSN_CMPEQ, SEM_FN_NAME (sh64_media,cmpeq) },
-  { SH64_MEDIA_INSN_CMPGT, SEM_FN_NAME (sh64_media,cmpgt) },
-  { SH64_MEDIA_INSN_CMPGTU, SEM_FN_NAME (sh64_media,cmpgtu) },
-  { SH64_MEDIA_INSN_CMVEQ, SEM_FN_NAME (sh64_media,cmveq) },
-  { SH64_MEDIA_INSN_CMVNE, SEM_FN_NAME (sh64_media,cmvne) },
-  { SH64_MEDIA_INSN_FABSD, SEM_FN_NAME (sh64_media,fabsd) },
-  { SH64_MEDIA_INSN_FABSS, SEM_FN_NAME (sh64_media,fabss) },
-  { SH64_MEDIA_INSN_FADDD, SEM_FN_NAME (sh64_media,faddd) },
-  { SH64_MEDIA_INSN_FADDS, SEM_FN_NAME (sh64_media,fadds) },
-  { SH64_MEDIA_INSN_FCMPEQD, SEM_FN_NAME (sh64_media,fcmpeqd) },
-  { SH64_MEDIA_INSN_FCMPEQS, SEM_FN_NAME (sh64_media,fcmpeqs) },
-  { SH64_MEDIA_INSN_FCMPGED, SEM_FN_NAME (sh64_media,fcmpged) },
-  { SH64_MEDIA_INSN_FCMPGES, SEM_FN_NAME (sh64_media,fcmpges) },
-  { SH64_MEDIA_INSN_FCMPGTD, SEM_FN_NAME (sh64_media,fcmpgtd) },
-  { SH64_MEDIA_INSN_FCMPGTS, SEM_FN_NAME (sh64_media,fcmpgts) },
-  { SH64_MEDIA_INSN_FCMPUND, SEM_FN_NAME (sh64_media,fcmpund) },
-  { SH64_MEDIA_INSN_FCMPUNS, SEM_FN_NAME (sh64_media,fcmpuns) },
-  { SH64_MEDIA_INSN_FCNVDS, SEM_FN_NAME (sh64_media,fcnvds) },
-  { SH64_MEDIA_INSN_FCNVSD, SEM_FN_NAME (sh64_media,fcnvsd) },
-  { SH64_MEDIA_INSN_FDIVD, SEM_FN_NAME (sh64_media,fdivd) },
-  { SH64_MEDIA_INSN_FDIVS, SEM_FN_NAME (sh64_media,fdivs) },
-  { SH64_MEDIA_INSN_FGETSCR, SEM_FN_NAME (sh64_media,fgetscr) },
-  { SH64_MEDIA_INSN_FIPRS, SEM_FN_NAME (sh64_media,fiprs) },
-  { SH64_MEDIA_INSN_FLDD, SEM_FN_NAME (sh64_media,fldd) },
-  { SH64_MEDIA_INSN_FLDP, SEM_FN_NAME (sh64_media,fldp) },
-  { SH64_MEDIA_INSN_FLDS, SEM_FN_NAME (sh64_media,flds) },
-  { SH64_MEDIA_INSN_FLDXD, SEM_FN_NAME (sh64_media,fldxd) },
-  { SH64_MEDIA_INSN_FLDXP, SEM_FN_NAME (sh64_media,fldxp) },
-  { SH64_MEDIA_INSN_FLDXS, SEM_FN_NAME (sh64_media,fldxs) },
-  { SH64_MEDIA_INSN_FLOATLD, SEM_FN_NAME (sh64_media,floatld) },
-  { SH64_MEDIA_INSN_FLOATLS, SEM_FN_NAME (sh64_media,floatls) },
-  { SH64_MEDIA_INSN_FLOATQD, SEM_FN_NAME (sh64_media,floatqd) },
-  { SH64_MEDIA_INSN_FLOATQS, SEM_FN_NAME (sh64_media,floatqs) },
-  { SH64_MEDIA_INSN_FMACS, SEM_FN_NAME (sh64_media,fmacs) },
-  { SH64_MEDIA_INSN_FMOVD, SEM_FN_NAME (sh64_media,fmovd) },
-  { SH64_MEDIA_INSN_FMOVDQ, SEM_FN_NAME (sh64_media,fmovdq) },
-  { SH64_MEDIA_INSN_FMOVLS, SEM_FN_NAME (sh64_media,fmovls) },
-  { SH64_MEDIA_INSN_FMOVQD, SEM_FN_NAME (sh64_media,fmovqd) },
-  { SH64_MEDIA_INSN_FMOVS, SEM_FN_NAME (sh64_media,fmovs) },
-  { SH64_MEDIA_INSN_FMOVSL, SEM_FN_NAME (sh64_media,fmovsl) },
-  { SH64_MEDIA_INSN_FMULD, SEM_FN_NAME (sh64_media,fmuld) },
-  { SH64_MEDIA_INSN_FMULS, SEM_FN_NAME (sh64_media,fmuls) },
-  { SH64_MEDIA_INSN_FNEGD, SEM_FN_NAME (sh64_media,fnegd) },
-  { SH64_MEDIA_INSN_FNEGS, SEM_FN_NAME (sh64_media,fnegs) },
-  { SH64_MEDIA_INSN_FPUTSCR, SEM_FN_NAME (sh64_media,fputscr) },
-  { SH64_MEDIA_INSN_FSQRTD, SEM_FN_NAME (sh64_media,fsqrtd) },
-  { SH64_MEDIA_INSN_FSQRTS, SEM_FN_NAME (sh64_media,fsqrts) },
-  { SH64_MEDIA_INSN_FSTD, SEM_FN_NAME (sh64_media,fstd) },
-  { SH64_MEDIA_INSN_FSTP, SEM_FN_NAME (sh64_media,fstp) },
-  { SH64_MEDIA_INSN_FSTS, SEM_FN_NAME (sh64_media,fsts) },
-  { SH64_MEDIA_INSN_FSTXD, SEM_FN_NAME (sh64_media,fstxd) },
-  { SH64_MEDIA_INSN_FSTXP, SEM_FN_NAME (sh64_media,fstxp) },
-  { SH64_MEDIA_INSN_FSTXS, SEM_FN_NAME (sh64_media,fstxs) },
-  { SH64_MEDIA_INSN_FSUBD, SEM_FN_NAME (sh64_media,fsubd) },
-  { SH64_MEDIA_INSN_FSUBS, SEM_FN_NAME (sh64_media,fsubs) },
-  { SH64_MEDIA_INSN_FTRCDL, SEM_FN_NAME (sh64_media,ftrcdl) },
-  { SH64_MEDIA_INSN_FTRCSL, SEM_FN_NAME (sh64_media,ftrcsl) },
-  { SH64_MEDIA_INSN_FTRCDQ, SEM_FN_NAME (sh64_media,ftrcdq) },
-  { SH64_MEDIA_INSN_FTRCSQ, SEM_FN_NAME (sh64_media,ftrcsq) },
-  { SH64_MEDIA_INSN_FTRVS, SEM_FN_NAME (sh64_media,ftrvs) },
-  { SH64_MEDIA_INSN_GETCFG, SEM_FN_NAME (sh64_media,getcfg) },
-  { SH64_MEDIA_INSN_GETCON, SEM_FN_NAME (sh64_media,getcon) },
-  { SH64_MEDIA_INSN_GETTR, SEM_FN_NAME (sh64_media,gettr) },
-  { SH64_MEDIA_INSN_ICBI, SEM_FN_NAME (sh64_media,icbi) },
-  { SH64_MEDIA_INSN_LDB, SEM_FN_NAME (sh64_media,ldb) },
-  { SH64_MEDIA_INSN_LDL, SEM_FN_NAME (sh64_media,ldl) },
-  { SH64_MEDIA_INSN_LDQ, SEM_FN_NAME (sh64_media,ldq) },
-  { SH64_MEDIA_INSN_LDUB, SEM_FN_NAME (sh64_media,ldub) },
-  { SH64_MEDIA_INSN_LDUW, SEM_FN_NAME (sh64_media,lduw) },
-  { SH64_MEDIA_INSN_LDW, SEM_FN_NAME (sh64_media,ldw) },
-  { SH64_MEDIA_INSN_LDHIL, SEM_FN_NAME (sh64_media,ldhil) },
-  { SH64_MEDIA_INSN_LDHIQ, SEM_FN_NAME (sh64_media,ldhiq) },
-  { SH64_MEDIA_INSN_LDLOL, SEM_FN_NAME (sh64_media,ldlol) },
-  { SH64_MEDIA_INSN_LDLOQ, SEM_FN_NAME (sh64_media,ldloq) },
-  { SH64_MEDIA_INSN_LDXB, SEM_FN_NAME (sh64_media,ldxb) },
-  { SH64_MEDIA_INSN_LDXL, SEM_FN_NAME (sh64_media,ldxl) },
-  { SH64_MEDIA_INSN_LDXQ, SEM_FN_NAME (sh64_media,ldxq) },
-  { SH64_MEDIA_INSN_LDXUB, SEM_FN_NAME (sh64_media,ldxub) },
-  { SH64_MEDIA_INSN_LDXUW, SEM_FN_NAME (sh64_media,ldxuw) },
-  { SH64_MEDIA_INSN_LDXW, SEM_FN_NAME (sh64_media,ldxw) },
-  { SH64_MEDIA_INSN_MABSL, SEM_FN_NAME (sh64_media,mabsl) },
-  { SH64_MEDIA_INSN_MABSW, SEM_FN_NAME (sh64_media,mabsw) },
-  { SH64_MEDIA_INSN_MADDL, SEM_FN_NAME (sh64_media,maddl) },
-  { SH64_MEDIA_INSN_MADDW, SEM_FN_NAME (sh64_media,maddw) },
-  { SH64_MEDIA_INSN_MADDSL, SEM_FN_NAME (sh64_media,maddsl) },
-  { SH64_MEDIA_INSN_MADDSUB, SEM_FN_NAME (sh64_media,maddsub) },
-  { SH64_MEDIA_INSN_MADDSW, SEM_FN_NAME (sh64_media,maddsw) },
-  { SH64_MEDIA_INSN_MCMPEQB, SEM_FN_NAME (sh64_media,mcmpeqb) },
-  { SH64_MEDIA_INSN_MCMPEQL, SEM_FN_NAME (sh64_media,mcmpeql) },
-  { SH64_MEDIA_INSN_MCMPEQW, SEM_FN_NAME (sh64_media,mcmpeqw) },
-  { SH64_MEDIA_INSN_MCMPGTL, SEM_FN_NAME (sh64_media,mcmpgtl) },
-  { SH64_MEDIA_INSN_MCMPGTUB, SEM_FN_NAME (sh64_media,mcmpgtub) },
-  { SH64_MEDIA_INSN_MCMPGTW, SEM_FN_NAME (sh64_media,mcmpgtw) },
-  { SH64_MEDIA_INSN_MCMV, SEM_FN_NAME (sh64_media,mcmv) },
-  { SH64_MEDIA_INSN_MCNVSLW, SEM_FN_NAME (sh64_media,mcnvslw) },
-  { SH64_MEDIA_INSN_MCNVSWB, SEM_FN_NAME (sh64_media,mcnvswb) },
-  { SH64_MEDIA_INSN_MCNVSWUB, SEM_FN_NAME (sh64_media,mcnvswub) },
-  { SH64_MEDIA_INSN_MEXTR1, SEM_FN_NAME (sh64_media,mextr1) },
-  { SH64_MEDIA_INSN_MEXTR2, SEM_FN_NAME (sh64_media,mextr2) },
-  { SH64_MEDIA_INSN_MEXTR3, SEM_FN_NAME (sh64_media,mextr3) },
-  { SH64_MEDIA_INSN_MEXTR4, SEM_FN_NAME (sh64_media,mextr4) },
-  { SH64_MEDIA_INSN_MEXTR5, SEM_FN_NAME (sh64_media,mextr5) },
-  { SH64_MEDIA_INSN_MEXTR6, SEM_FN_NAME (sh64_media,mextr6) },
-  { SH64_MEDIA_INSN_MEXTR7, SEM_FN_NAME (sh64_media,mextr7) },
-  { SH64_MEDIA_INSN_MMACFXWL, SEM_FN_NAME (sh64_media,mmacfxwl) },
-  { SH64_MEDIA_INSN_MMACNFX_WL, SEM_FN_NAME (sh64_media,mmacnfx_wl) },
-  { SH64_MEDIA_INSN_MMULL, SEM_FN_NAME (sh64_media,mmull) },
-  { SH64_MEDIA_INSN_MMULW, SEM_FN_NAME (sh64_media,mmulw) },
-  { SH64_MEDIA_INSN_MMULFXL, SEM_FN_NAME (sh64_media,mmulfxl) },
-  { SH64_MEDIA_INSN_MMULFXW, SEM_FN_NAME (sh64_media,mmulfxw) },
-  { SH64_MEDIA_INSN_MMULFXRPW, SEM_FN_NAME (sh64_media,mmulfxrpw) },
-  { SH64_MEDIA_INSN_MMULHIWL, SEM_FN_NAME (sh64_media,mmulhiwl) },
-  { SH64_MEDIA_INSN_MMULLOWL, SEM_FN_NAME (sh64_media,mmullowl) },
-  { SH64_MEDIA_INSN_MMULSUMWQ, SEM_FN_NAME (sh64_media,mmulsumwq) },
-  { SH64_MEDIA_INSN_MOVI, SEM_FN_NAME (sh64_media,movi) },
-  { SH64_MEDIA_INSN_MPERMW, SEM_FN_NAME (sh64_media,mpermw) },
-  { SH64_MEDIA_INSN_MSADUBQ, SEM_FN_NAME (sh64_media,msadubq) },
-  { SH64_MEDIA_INSN_MSHALDSL, SEM_FN_NAME (sh64_media,mshaldsl) },
-  { SH64_MEDIA_INSN_MSHALDSW, SEM_FN_NAME (sh64_media,mshaldsw) },
-  { SH64_MEDIA_INSN_MSHARDL, SEM_FN_NAME (sh64_media,mshardl) },
-  { SH64_MEDIA_INSN_MSHARDW, SEM_FN_NAME (sh64_media,mshardw) },
-  { SH64_MEDIA_INSN_MSHARDSQ, SEM_FN_NAME (sh64_media,mshardsq) },
-  { SH64_MEDIA_INSN_MSHFHIB, SEM_FN_NAME (sh64_media,mshfhib) },
-  { SH64_MEDIA_INSN_MSHFHIL, SEM_FN_NAME (sh64_media,mshfhil) },
-  { SH64_MEDIA_INSN_MSHFHIW, SEM_FN_NAME (sh64_media,mshfhiw) },
-  { SH64_MEDIA_INSN_MSHFLOB, SEM_FN_NAME (sh64_media,mshflob) },
-  { SH64_MEDIA_INSN_MSHFLOL, SEM_FN_NAME (sh64_media,mshflol) },
-  { SH64_MEDIA_INSN_MSHFLOW, SEM_FN_NAME (sh64_media,mshflow) },
-  { SH64_MEDIA_INSN_MSHLLDL, SEM_FN_NAME (sh64_media,mshlldl) },
-  { SH64_MEDIA_INSN_MSHLLDW, SEM_FN_NAME (sh64_media,mshlldw) },
-  { SH64_MEDIA_INSN_MSHLRDL, SEM_FN_NAME (sh64_media,mshlrdl) },
-  { SH64_MEDIA_INSN_MSHLRDW, SEM_FN_NAME (sh64_media,mshlrdw) },
-  { SH64_MEDIA_INSN_MSUBL, SEM_FN_NAME (sh64_media,msubl) },
-  { SH64_MEDIA_INSN_MSUBW, SEM_FN_NAME (sh64_media,msubw) },
-  { SH64_MEDIA_INSN_MSUBSL, SEM_FN_NAME (sh64_media,msubsl) },
-  { SH64_MEDIA_INSN_MSUBSUB, SEM_FN_NAME (sh64_media,msubsub) },
-  { SH64_MEDIA_INSN_MSUBSW, SEM_FN_NAME (sh64_media,msubsw) },
-  { SH64_MEDIA_INSN_MULSL, SEM_FN_NAME (sh64_media,mulsl) },
-  { SH64_MEDIA_INSN_MULUL, SEM_FN_NAME (sh64_media,mulul) },
-  { SH64_MEDIA_INSN_NOP, SEM_FN_NAME (sh64_media,nop) },
-  { SH64_MEDIA_INSN_NSB, SEM_FN_NAME (sh64_media,nsb) },
-  { SH64_MEDIA_INSN_OCBI, SEM_FN_NAME (sh64_media,ocbi) },
-  { SH64_MEDIA_INSN_OCBP, SEM_FN_NAME (sh64_media,ocbp) },
-  { SH64_MEDIA_INSN_OCBWB, SEM_FN_NAME (sh64_media,ocbwb) },
-  { SH64_MEDIA_INSN_OR, SEM_FN_NAME (sh64_media,or) },
-  { SH64_MEDIA_INSN_ORI, SEM_FN_NAME (sh64_media,ori) },
-  { SH64_MEDIA_INSN_PREFI, SEM_FN_NAME (sh64_media,prefi) },
-  { SH64_MEDIA_INSN_PTA, SEM_FN_NAME (sh64_media,pta) },
-  { SH64_MEDIA_INSN_PTABS, SEM_FN_NAME (sh64_media,ptabs) },
-  { SH64_MEDIA_INSN_PTB, SEM_FN_NAME (sh64_media,ptb) },
-  { SH64_MEDIA_INSN_PTREL, SEM_FN_NAME (sh64_media,ptrel) },
-  { SH64_MEDIA_INSN_PUTCFG, SEM_FN_NAME (sh64_media,putcfg) },
-  { SH64_MEDIA_INSN_PUTCON, SEM_FN_NAME (sh64_media,putcon) },
-  { SH64_MEDIA_INSN_RTE, SEM_FN_NAME (sh64_media,rte) },
-  { SH64_MEDIA_INSN_SHARD, SEM_FN_NAME (sh64_media,shard) },
-  { SH64_MEDIA_INSN_SHARDL, SEM_FN_NAME (sh64_media,shardl) },
-  { SH64_MEDIA_INSN_SHARI, SEM_FN_NAME (sh64_media,shari) },
-  { SH64_MEDIA_INSN_SHARIL, SEM_FN_NAME (sh64_media,sharil) },
-  { SH64_MEDIA_INSN_SHLLD, SEM_FN_NAME (sh64_media,shlld) },
-  { SH64_MEDIA_INSN_SHLLDL, SEM_FN_NAME (sh64_media,shlldl) },
-  { SH64_MEDIA_INSN_SHLLI, SEM_FN_NAME (sh64_media,shlli) },
-  { SH64_MEDIA_INSN_SHLLIL, SEM_FN_NAME (sh64_media,shllil) },
-  { SH64_MEDIA_INSN_SHLRD, SEM_FN_NAME (sh64_media,shlrd) },
-  { SH64_MEDIA_INSN_SHLRDL, SEM_FN_NAME (sh64_media,shlrdl) },
-  { SH64_MEDIA_INSN_SHLRI, SEM_FN_NAME (sh64_media,shlri) },
-  { SH64_MEDIA_INSN_SHLRIL, SEM_FN_NAME (sh64_media,shlril) },
-  { SH64_MEDIA_INSN_SHORI, SEM_FN_NAME (sh64_media,shori) },
-  { SH64_MEDIA_INSN_SLEEP, SEM_FN_NAME (sh64_media,sleep) },
-  { SH64_MEDIA_INSN_STB, SEM_FN_NAME (sh64_media,stb) },
-  { SH64_MEDIA_INSN_STL, SEM_FN_NAME (sh64_media,stl) },
-  { SH64_MEDIA_INSN_STQ, SEM_FN_NAME (sh64_media,stq) },
-  { SH64_MEDIA_INSN_STW, SEM_FN_NAME (sh64_media,stw) },
-  { SH64_MEDIA_INSN_STHIL, SEM_FN_NAME (sh64_media,sthil) },
-  { SH64_MEDIA_INSN_STHIQ, SEM_FN_NAME (sh64_media,sthiq) },
-  { SH64_MEDIA_INSN_STLOL, SEM_FN_NAME (sh64_media,stlol) },
-  { SH64_MEDIA_INSN_STLOQ, SEM_FN_NAME (sh64_media,stloq) },
-  { SH64_MEDIA_INSN_STXB, SEM_FN_NAME (sh64_media,stxb) },
-  { SH64_MEDIA_INSN_STXL, SEM_FN_NAME (sh64_media,stxl) },
-  { SH64_MEDIA_INSN_STXQ, SEM_FN_NAME (sh64_media,stxq) },
-  { SH64_MEDIA_INSN_STXW, SEM_FN_NAME (sh64_media,stxw) },
-  { SH64_MEDIA_INSN_SUB, SEM_FN_NAME (sh64_media,sub) },
-  { SH64_MEDIA_INSN_SUBL, SEM_FN_NAME (sh64_media,subl) },
-  { SH64_MEDIA_INSN_SWAPQ, SEM_FN_NAME (sh64_media,swapq) },
-  { SH64_MEDIA_INSN_SYNCI, SEM_FN_NAME (sh64_media,synci) },
-  { SH64_MEDIA_INSN_SYNCO, SEM_FN_NAME (sh64_media,synco) },
-  { SH64_MEDIA_INSN_TRAPA, SEM_FN_NAME (sh64_media,trapa) },
-  { SH64_MEDIA_INSN_XOR, SEM_FN_NAME (sh64_media,xor) },
-  { SH64_MEDIA_INSN_XORI, SEM_FN_NAME (sh64_media,xori) },
-  { 0, 0 }
-};
-
-/* Add the semantic fns to IDESC_TABLE.  */
-
-void
-SEM_FN_NAME (sh64_media,init_idesc_table) (SIM_CPU *current_cpu)
-{
-  IDESC *idesc_table = CPU_IDESC (current_cpu);
-  const struct sem_fn_desc *sf;
-  int mach_num = MACH_NUM (CPU_MACH (current_cpu));
-
-  for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
-    {
-      const CGEN_INSN *insn = idesc_table[sf->index].idata;
-      int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
-		     || CGEN_INSN_MACH_HAS_P (insn, mach_num));
-#if FAST_P
-      if (valid_p)
-	idesc_table[sf->index].sem_fast = sf->fn;
-      else
-	idesc_table[sf->index].sem_fast = SEM_FN_NAME (sh64_media,x_invalid);
-#else
-      if (valid_p)
-	idesc_table[sf->index].sem_full = sf->fn;
-      else
-	idesc_table[sf->index].sem_full = SEM_FN_NAME (sh64_media,x_invalid);
-#endif
-    }
-}
-
diff --git a/sim/sh64/sh-desc.c b/sim/sh64/sh-desc.c
deleted file mode 100644
index e95ab8782f5..00000000000
--- a/sim/sh64/sh-desc.c
+++ /dev/null
@@ -1,3287 +0,0 @@
-/* CPU data for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#include "sysdep.h"
-#include <ctype.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "sh-desc.h"
-#include "sh-opc.h"
-#include "opintl.h"
-#include "libiberty.h"
-
-/* Attributes.  */
-
-static const CGEN_ATTR_ENTRY bool_attr[] =
-{
-  { "#f", 0 },
-  { "#t", 1 },
-  { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY MACH_attr[] =
-{
-  { "base", MACH_BASE },
-  { "sh2", MACH_SH2 },
-  { "sh3", MACH_SH3 },
-  { "sh3e", MACH_SH3E },
-  { "sh4", MACH_SH4 },
-  { "sh5", MACH_SH5 },
-  { "max", MACH_MAX },
-  { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY ISA_attr[] =
-{
-  { "compact", ISA_COMPACT },
-  { "media", ISA_MEDIA },
-  { "max", ISA_MAX },
-  { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] =
-{
-  { "MACH", & MACH_attr[0], & MACH_attr[0] },
-  { "ISA", & ISA_attr[0], & ISA_attr[0] },
-  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
-  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
-  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
-  { "RESERVED", &bool_attr[0], &bool_attr[0] },
-  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
-  { "SIGNED", &bool_attr[0], &bool_attr[0] },
-  { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[] =
-{
-  { "MACH", & MACH_attr[0], & MACH_attr[0] },
-  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
-  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
-  { "PC", &bool_attr[0], &bool_attr[0] },
-  { "PROFILE", &bool_attr[0], &bool_attr[0] },
-  { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[] =
-{
-  { "MACH", & MACH_attr[0], & MACH_attr[0] },
-  { "ISA", & ISA_attr[0], & ISA_attr[0] },
-  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
-  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
-  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
-  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
-  { "SIGNED", &bool_attr[0], &bool_attr[0] },
-  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
-  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
-  { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] =
-{
-  { "MACH", & MACH_attr[0], & MACH_attr[0] },
-  { "ISA", & ISA_attr[0], & ISA_attr[0] },
-  { "ALIAS", &bool_attr[0], &bool_attr[0] },
-  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
-  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
-  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
-  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
-  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
-  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
-  { "RELAX", &bool_attr[0], &bool_attr[0] },
-  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
-  { "PBB", &bool_attr[0], &bool_attr[0] },
-  { "ILLSLOT", &bool_attr[0], &bool_attr[0] },
-  { "FP-INSN", &bool_attr[0], &bool_attr[0] },
-  { 0, 0, 0 }
-};
-
-/* Instruction set variants.  */
-
-static const CGEN_ISA sh_cgen_isa_table[] = {
-  { "media", 32, 32, 32, 32 },
-  { "compact", 16, 16, 16, 16 },
-  { 0, 0, 0, 0, 0 }
-};
-
-/* Machine variants.  */
-
-static const CGEN_MACH sh_cgen_mach_table[] = {
-  { "sh2", "sh2", MACH_SH2 },
-  { "sh3", "sh3", MACH_SH3 },
-  { "sh3e", "sh3e", MACH_SH3E },
-  { "sh4", "sh4", MACH_SH4 },
-  { "sh5", "sh5", MACH_SH5 },
-  { 0, 0, 0 }
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_frc_names_entries[] =
-{
-  { "fr0", 0, {0, {0}}, 0, 0 },
-  { "fr1", 1, {0, {0}}, 0, 0 },
-  { "fr2", 2, {0, {0}}, 0, 0 },
-  { "fr3", 3, {0, {0}}, 0, 0 },
-  { "fr4", 4, {0, {0}}, 0, 0 },
-  { "fr5", 5, {0, {0}}, 0, 0 },
-  { "fr6", 6, {0, {0}}, 0, 0 },
-  { "fr7", 7, {0, {0}}, 0, 0 },
-  { "fr8", 8, {0, {0}}, 0, 0 },
-  { "fr9", 9, {0, {0}}, 0, 0 },
-  { "fr10", 10, {0, {0}}, 0, 0 },
-  { "fr11", 11, {0, {0}}, 0, 0 },
-  { "fr12", 12, {0, {0}}, 0, 0 },
-  { "fr13", 13, {0, {0}}, 0, 0 },
-  { "fr14", 14, {0, {0}}, 0, 0 },
-  { "fr15", 15, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_frc_names =
-{
-  & sh_cgen_opval_frc_names_entries[0],
-  16,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_drc_names_entries[] =
-{
-  { "dr0", 0, {0, {0}}, 0, 0 },
-  { "dr2", 2, {0, {0}}, 0, 0 },
-  { "dr4", 4, {0, {0}}, 0, 0 },
-  { "dr6", 6, {0, {0}}, 0, 0 },
-  { "dr8", 8, {0, {0}}, 0, 0 },
-  { "dr10", 10, {0, {0}}, 0, 0 },
-  { "dr12", 12, {0, {0}}, 0, 0 },
-  { "dr14", 14, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_drc_names =
-{
-  & sh_cgen_opval_drc_names_entries[0],
-  8,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_xf_names_entries[] =
-{
-  { "xf0", 0, {0, {0}}, 0, 0 },
-  { "xf1", 1, {0, {0}}, 0, 0 },
-  { "xf2", 2, {0, {0}}, 0, 0 },
-  { "xf3", 3, {0, {0}}, 0, 0 },
-  { "xf4", 4, {0, {0}}, 0, 0 },
-  { "xf5", 5, {0, {0}}, 0, 0 },
-  { "xf6", 6, {0, {0}}, 0, 0 },
-  { "xf7", 7, {0, {0}}, 0, 0 },
-  { "xf8", 8, {0, {0}}, 0, 0 },
-  { "xf9", 9, {0, {0}}, 0, 0 },
-  { "xf10", 10, {0, {0}}, 0, 0 },
-  { "xf11", 11, {0, {0}}, 0, 0 },
-  { "xf12", 12, {0, {0}}, 0, 0 },
-  { "xf13", 13, {0, {0}}, 0, 0 },
-  { "xf14", 14, {0, {0}}, 0, 0 },
-  { "xf15", 15, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_xf_names =
-{
-  & sh_cgen_opval_xf_names_entries[0],
-  16,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_gr_entries[] =
-{
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 },
-  { "r16", 16, {0, {0}}, 0, 0 },
-  { "r17", 17, {0, {0}}, 0, 0 },
-  { "r18", 18, {0, {0}}, 0, 0 },
-  { "r19", 19, {0, {0}}, 0, 0 },
-  { "r20", 20, {0, {0}}, 0, 0 },
-  { "r21", 21, {0, {0}}, 0, 0 },
-  { "r22", 22, {0, {0}}, 0, 0 },
-  { "r23", 23, {0, {0}}, 0, 0 },
-  { "r24", 24, {0, {0}}, 0, 0 },
-  { "r25", 25, {0, {0}}, 0, 0 },
-  { "r26", 26, {0, {0}}, 0, 0 },
-  { "r27", 27, {0, {0}}, 0, 0 },
-  { "r28", 28, {0, {0}}, 0, 0 },
-  { "r29", 29, {0, {0}}, 0, 0 },
-  { "r30", 30, {0, {0}}, 0, 0 },
-  { "r31", 31, {0, {0}}, 0, 0 },
-  { "r32", 32, {0, {0}}, 0, 0 },
-  { "r33", 33, {0, {0}}, 0, 0 },
-  { "r34", 34, {0, {0}}, 0, 0 },
-  { "r35", 35, {0, {0}}, 0, 0 },
-  { "r36", 36, {0, {0}}, 0, 0 },
-  { "r37", 37, {0, {0}}, 0, 0 },
-  { "r38", 38, {0, {0}}, 0, 0 },
-  { "r39", 39, {0, {0}}, 0, 0 },
-  { "r40", 40, {0, {0}}, 0, 0 },
-  { "r41", 41, {0, {0}}, 0, 0 },
-  { "r42", 42, {0, {0}}, 0, 0 },
-  { "r43", 43, {0, {0}}, 0, 0 },
-  { "r44", 44, {0, {0}}, 0, 0 },
-  { "r45", 45, {0, {0}}, 0, 0 },
-  { "r46", 46, {0, {0}}, 0, 0 },
-  { "r47", 47, {0, {0}}, 0, 0 },
-  { "r48", 48, {0, {0}}, 0, 0 },
-  { "r49", 49, {0, {0}}, 0, 0 },
-  { "r50", 50, {0, {0}}, 0, 0 },
-  { "r51", 51, {0, {0}}, 0, 0 },
-  { "r52", 52, {0, {0}}, 0, 0 },
-  { "r53", 53, {0, {0}}, 0, 0 },
-  { "r54", 54, {0, {0}}, 0, 0 },
-  { "r55", 55, {0, {0}}, 0, 0 },
-  { "r56", 56, {0, {0}}, 0, 0 },
-  { "r57", 57, {0, {0}}, 0, 0 },
-  { "r58", 58, {0, {0}}, 0, 0 },
-  { "r59", 59, {0, {0}}, 0, 0 },
-  { "r60", 60, {0, {0}}, 0, 0 },
-  { "r61", 61, {0, {0}}, 0, 0 },
-  { "r62", 62, {0, {0}}, 0, 0 },
-  { "r63", 63, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_gr =
-{
-  & sh_cgen_opval_h_gr_entries[0],
-  64,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_grc_entries[] =
-{
-  { "r0", 0, {0, {0}}, 0, 0 },
-  { "r1", 1, {0, {0}}, 0, 0 },
-  { "r2", 2, {0, {0}}, 0, 0 },
-  { "r3", 3, {0, {0}}, 0, 0 },
-  { "r4", 4, {0, {0}}, 0, 0 },
-  { "r5", 5, {0, {0}}, 0, 0 },
-  { "r6", 6, {0, {0}}, 0, 0 },
-  { "r7", 7, {0, {0}}, 0, 0 },
-  { "r8", 8, {0, {0}}, 0, 0 },
-  { "r9", 9, {0, {0}}, 0, 0 },
-  { "r10", 10, {0, {0}}, 0, 0 },
-  { "r11", 11, {0, {0}}, 0, 0 },
-  { "r12", 12, {0, {0}}, 0, 0 },
-  { "r13", 13, {0, {0}}, 0, 0 },
-  { "r14", 14, {0, {0}}, 0, 0 },
-  { "r15", 15, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_grc =
-{
-  & sh_cgen_opval_h_grc_entries[0],
-  16,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_cr_entries[] =
-{
-  { "cr0", 0, {0, {0}}, 0, 0 },
-  { "cr1", 1, {0, {0}}, 0, 0 },
-  { "cr2", 2, {0, {0}}, 0, 0 },
-  { "cr3", 3, {0, {0}}, 0, 0 },
-  { "cr4", 4, {0, {0}}, 0, 0 },
-  { "cr5", 5, {0, {0}}, 0, 0 },
-  { "cr6", 6, {0, {0}}, 0, 0 },
-  { "cr7", 7, {0, {0}}, 0, 0 },
-  { "cr8", 8, {0, {0}}, 0, 0 },
-  { "cr9", 9, {0, {0}}, 0, 0 },
-  { "cr10", 10, {0, {0}}, 0, 0 },
-  { "cr11", 11, {0, {0}}, 0, 0 },
-  { "cr12", 12, {0, {0}}, 0, 0 },
-  { "cr13", 13, {0, {0}}, 0, 0 },
-  { "cr14", 14, {0, {0}}, 0, 0 },
-  { "cr15", 15, {0, {0}}, 0, 0 },
-  { "cr16", 16, {0, {0}}, 0, 0 },
-  { "cr17", 17, {0, {0}}, 0, 0 },
-  { "cr18", 18, {0, {0}}, 0, 0 },
-  { "cr19", 19, {0, {0}}, 0, 0 },
-  { "cr20", 20, {0, {0}}, 0, 0 },
-  { "cr21", 21, {0, {0}}, 0, 0 },
-  { "cr22", 22, {0, {0}}, 0, 0 },
-  { "cr23", 23, {0, {0}}, 0, 0 },
-  { "cr24", 24, {0, {0}}, 0, 0 },
-  { "cr25", 25, {0, {0}}, 0, 0 },
-  { "cr26", 26, {0, {0}}, 0, 0 },
-  { "cr27", 27, {0, {0}}, 0, 0 },
-  { "cr28", 28, {0, {0}}, 0, 0 },
-  { "cr29", 29, {0, {0}}, 0, 0 },
-  { "cr30", 30, {0, {0}}, 0, 0 },
-  { "cr31", 31, {0, {0}}, 0, 0 },
-  { "cr32", 32, {0, {0}}, 0, 0 },
-  { "cr33", 33, {0, {0}}, 0, 0 },
-  { "cr34", 34, {0, {0}}, 0, 0 },
-  { "cr35", 35, {0, {0}}, 0, 0 },
-  { "cr36", 36, {0, {0}}, 0, 0 },
-  { "cr37", 37, {0, {0}}, 0, 0 },
-  { "cr38", 38, {0, {0}}, 0, 0 },
-  { "cr39", 39, {0, {0}}, 0, 0 },
-  { "cr40", 40, {0, {0}}, 0, 0 },
-  { "cr41", 41, {0, {0}}, 0, 0 },
-  { "cr42", 42, {0, {0}}, 0, 0 },
-  { "cr43", 43, {0, {0}}, 0, 0 },
-  { "cr44", 44, {0, {0}}, 0, 0 },
-  { "cr45", 45, {0, {0}}, 0, 0 },
-  { "cr46", 46, {0, {0}}, 0, 0 },
-  { "cr47", 47, {0, {0}}, 0, 0 },
-  { "cr48", 48, {0, {0}}, 0, 0 },
-  { "cr49", 49, {0, {0}}, 0, 0 },
-  { "cr50", 50, {0, {0}}, 0, 0 },
-  { "cr51", 51, {0, {0}}, 0, 0 },
-  { "cr52", 52, {0, {0}}, 0, 0 },
-  { "cr53", 53, {0, {0}}, 0, 0 },
-  { "cr54", 54, {0, {0}}, 0, 0 },
-  { "cr55", 55, {0, {0}}, 0, 0 },
-  { "cr56", 56, {0, {0}}, 0, 0 },
-  { "cr57", 57, {0, {0}}, 0, 0 },
-  { "cr58", 58, {0, {0}}, 0, 0 },
-  { "cr59", 59, {0, {0}}, 0, 0 },
-  { "cr60", 60, {0, {0}}, 0, 0 },
-  { "cr61", 61, {0, {0}}, 0, 0 },
-  { "cr62", 62, {0, {0}}, 0, 0 },
-  { "cr63", 63, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_cr =
-{
-  & sh_cgen_opval_h_cr_entries[0],
-  64,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fr_entries[] =
-{
-  { "fr0", 0, {0, {0}}, 0, 0 },
-  { "fr1", 1, {0, {0}}, 0, 0 },
-  { "fr2", 2, {0, {0}}, 0, 0 },
-  { "fr3", 3, {0, {0}}, 0, 0 },
-  { "fr4", 4, {0, {0}}, 0, 0 },
-  { "fr5", 5, {0, {0}}, 0, 0 },
-  { "fr6", 6, {0, {0}}, 0, 0 },
-  { "fr7", 7, {0, {0}}, 0, 0 },
-  { "fr8", 8, {0, {0}}, 0, 0 },
-  { "fr9", 9, {0, {0}}, 0, 0 },
-  { "fr10", 10, {0, {0}}, 0, 0 },
-  { "fr11", 11, {0, {0}}, 0, 0 },
-  { "fr12", 12, {0, {0}}, 0, 0 },
-  { "fr13", 13, {0, {0}}, 0, 0 },
-  { "fr14", 14, {0, {0}}, 0, 0 },
-  { "fr15", 15, {0, {0}}, 0, 0 },
-  { "fr16", 16, {0, {0}}, 0, 0 },
-  { "fr17", 17, {0, {0}}, 0, 0 },
-  { "fr18", 18, {0, {0}}, 0, 0 },
-  { "fr19", 19, {0, {0}}, 0, 0 },
-  { "fr20", 20, {0, {0}}, 0, 0 },
-  { "fr21", 21, {0, {0}}, 0, 0 },
-  { "fr22", 22, {0, {0}}, 0, 0 },
-  { "fr23", 23, {0, {0}}, 0, 0 },
-  { "fr24", 24, {0, {0}}, 0, 0 },
-  { "fr25", 25, {0, {0}}, 0, 0 },
-  { "fr26", 26, {0, {0}}, 0, 0 },
-  { "fr27", 27, {0, {0}}, 0, 0 },
-  { "fr28", 28, {0, {0}}, 0, 0 },
-  { "fr29", 29, {0, {0}}, 0, 0 },
-  { "fr30", 30, {0, {0}}, 0, 0 },
-  { "fr31", 31, {0, {0}}, 0, 0 },
-  { "fr32", 32, {0, {0}}, 0, 0 },
-  { "fr33", 33, {0, {0}}, 0, 0 },
-  { "fr34", 34, {0, {0}}, 0, 0 },
-  { "fr35", 35, {0, {0}}, 0, 0 },
-  { "fr36", 36, {0, {0}}, 0, 0 },
-  { "fr37", 37, {0, {0}}, 0, 0 },
-  { "fr38", 38, {0, {0}}, 0, 0 },
-  { "fr39", 39, {0, {0}}, 0, 0 },
-  { "fr40", 40, {0, {0}}, 0, 0 },
-  { "fr41", 41, {0, {0}}, 0, 0 },
-  { "fr42", 42, {0, {0}}, 0, 0 },
-  { "fr43", 43, {0, {0}}, 0, 0 },
-  { "fr44", 44, {0, {0}}, 0, 0 },
-  { "fr45", 45, {0, {0}}, 0, 0 },
-  { "fr46", 46, {0, {0}}, 0, 0 },
-  { "fr47", 47, {0, {0}}, 0, 0 },
-  { "fr48", 48, {0, {0}}, 0, 0 },
-  { "fr49", 49, {0, {0}}, 0, 0 },
-  { "fr50", 50, {0, {0}}, 0, 0 },
-  { "fr51", 51, {0, {0}}, 0, 0 },
-  { "fr52", 52, {0, {0}}, 0, 0 },
-  { "fr53", 53, {0, {0}}, 0, 0 },
-  { "fr54", 54, {0, {0}}, 0, 0 },
-  { "fr55", 55, {0, {0}}, 0, 0 },
-  { "fr56", 56, {0, {0}}, 0, 0 },
-  { "fr57", 57, {0, {0}}, 0, 0 },
-  { "fr58", 58, {0, {0}}, 0, 0 },
-  { "fr59", 59, {0, {0}}, 0, 0 },
-  { "fr60", 60, {0, {0}}, 0, 0 },
-  { "fr61", 61, {0, {0}}, 0, 0 },
-  { "fr62", 62, {0, {0}}, 0, 0 },
-  { "fr63", 63, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_fr =
-{
-  & sh_cgen_opval_h_fr_entries[0],
-  64,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fp_entries[] =
-{
-  { "fp0", 0, {0, {0}}, 0, 0 },
-  { "fp1", 1, {0, {0}}, 0, 0 },
-  { "fp2", 2, {0, {0}}, 0, 0 },
-  { "fp3", 3, {0, {0}}, 0, 0 },
-  { "fp4", 4, {0, {0}}, 0, 0 },
-  { "fp5", 5, {0, {0}}, 0, 0 },
-  { "fp6", 6, {0, {0}}, 0, 0 },
-  { "fp7", 7, {0, {0}}, 0, 0 },
-  { "fp8", 8, {0, {0}}, 0, 0 },
-  { "fp9", 9, {0, {0}}, 0, 0 },
-  { "fp10", 10, {0, {0}}, 0, 0 },
-  { "fp11", 11, {0, {0}}, 0, 0 },
-  { "fp12", 12, {0, {0}}, 0, 0 },
-  { "fp13", 13, {0, {0}}, 0, 0 },
-  { "fp14", 14, {0, {0}}, 0, 0 },
-  { "fp15", 15, {0, {0}}, 0, 0 },
-  { "fp16", 16, {0, {0}}, 0, 0 },
-  { "fp17", 17, {0, {0}}, 0, 0 },
-  { "fp18", 18, {0, {0}}, 0, 0 },
-  { "fp19", 19, {0, {0}}, 0, 0 },
-  { "fp20", 20, {0, {0}}, 0, 0 },
-  { "fp21", 21, {0, {0}}, 0, 0 },
-  { "fp22", 22, {0, {0}}, 0, 0 },
-  { "fp23", 23, {0, {0}}, 0, 0 },
-  { "fp24", 24, {0, {0}}, 0, 0 },
-  { "fp25", 25, {0, {0}}, 0, 0 },
-  { "fp26", 26, {0, {0}}, 0, 0 },
-  { "fp27", 27, {0, {0}}, 0, 0 },
-  { "fp28", 28, {0, {0}}, 0, 0 },
-  { "fp29", 29, {0, {0}}, 0, 0 },
-  { "fp30", 30, {0, {0}}, 0, 0 },
-  { "fp31", 31, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_fp =
-{
-  & sh_cgen_opval_h_fp_entries[0],
-  32,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fv_entries[] =
-{
-  { "fv0", 0, {0, {0}}, 0, 0 },
-  { "fv1", 1, {0, {0}}, 0, 0 },
-  { "fv2", 2, {0, {0}}, 0, 0 },
-  { "fv3", 3, {0, {0}}, 0, 0 },
-  { "fv4", 4, {0, {0}}, 0, 0 },
-  { "fv5", 5, {0, {0}}, 0, 0 },
-  { "fv6", 6, {0, {0}}, 0, 0 },
-  { "fv7", 7, {0, {0}}, 0, 0 },
-  { "fv8", 8, {0, {0}}, 0, 0 },
-  { "fv9", 9, {0, {0}}, 0, 0 },
-  { "fv10", 10, {0, {0}}, 0, 0 },
-  { "fv11", 11, {0, {0}}, 0, 0 },
-  { "fv12", 12, {0, {0}}, 0, 0 },
-  { "fv13", 13, {0, {0}}, 0, 0 },
-  { "fv14", 14, {0, {0}}, 0, 0 },
-  { "fv15", 15, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_fv =
-{
-  & sh_cgen_opval_h_fv_entries[0],
-  16,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmtx_entries[] =
-{
-  { "mtrx0", 0, {0, {0}}, 0, 0 },
-  { "mtrx1", 1, {0, {0}}, 0, 0 },
-  { "mtrx2", 2, {0, {0}}, 0, 0 },
-  { "mtrx3", 3, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_fmtx =
-{
-  & sh_cgen_opval_h_fmtx_entries[0],
-  4,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_dr_entries[] =
-{
-  { "dr0", 0, {0, {0}}, 0, 0 },
-  { "dr1", 1, {0, {0}}, 0, 0 },
-  { "dr2", 2, {0, {0}}, 0, 0 },
-  { "dr3", 3, {0, {0}}, 0, 0 },
-  { "dr4", 4, {0, {0}}, 0, 0 },
-  { "dr5", 5, {0, {0}}, 0, 0 },
-  { "dr6", 6, {0, {0}}, 0, 0 },
-  { "dr7", 7, {0, {0}}, 0, 0 },
-  { "dr8", 8, {0, {0}}, 0, 0 },
-  { "dr9", 9, {0, {0}}, 0, 0 },
-  { "dr10", 10, {0, {0}}, 0, 0 },
-  { "dr11", 11, {0, {0}}, 0, 0 },
-  { "dr12", 12, {0, {0}}, 0, 0 },
-  { "dr13", 13, {0, {0}}, 0, 0 },
-  { "dr14", 14, {0, {0}}, 0, 0 },
-  { "dr15", 15, {0, {0}}, 0, 0 },
-  { "dr16", 16, {0, {0}}, 0, 0 },
-  { "dr17", 17, {0, {0}}, 0, 0 },
-  { "dr18", 18, {0, {0}}, 0, 0 },
-  { "dr19", 19, {0, {0}}, 0, 0 },
-  { "dr20", 20, {0, {0}}, 0, 0 },
-  { "dr21", 21, {0, {0}}, 0, 0 },
-  { "dr22", 22, {0, {0}}, 0, 0 },
-  { "dr23", 23, {0, {0}}, 0, 0 },
-  { "dr24", 24, {0, {0}}, 0, 0 },
-  { "dr25", 25, {0, {0}}, 0, 0 },
-  { "dr26", 26, {0, {0}}, 0, 0 },
-  { "dr27", 27, {0, {0}}, 0, 0 },
-  { "dr28", 28, {0, {0}}, 0, 0 },
-  { "dr29", 29, {0, {0}}, 0, 0 },
-  { "dr30", 30, {0, {0}}, 0, 0 },
-  { "dr31", 31, {0, {0}}, 0, 0 },
-  { "dr32", 32, {0, {0}}, 0, 0 },
-  { "dr33", 33, {0, {0}}, 0, 0 },
-  { "dr34", 34, {0, {0}}, 0, 0 },
-  { "dr35", 35, {0, {0}}, 0, 0 },
-  { "dr36", 36, {0, {0}}, 0, 0 },
-  { "dr37", 37, {0, {0}}, 0, 0 },
-  { "dr38", 38, {0, {0}}, 0, 0 },
-  { "dr39", 39, {0, {0}}, 0, 0 },
-  { "dr40", 40, {0, {0}}, 0, 0 },
-  { "dr41", 41, {0, {0}}, 0, 0 },
-  { "dr42", 42, {0, {0}}, 0, 0 },
-  { "dr43", 43, {0, {0}}, 0, 0 },
-  { "dr44", 44, {0, {0}}, 0, 0 },
-  { "dr45", 45, {0, {0}}, 0, 0 },
-  { "dr46", 46, {0, {0}}, 0, 0 },
-  { "dr47", 47, {0, {0}}, 0, 0 },
-  { "dr48", 48, {0, {0}}, 0, 0 },
-  { "dr49", 49, {0, {0}}, 0, 0 },
-  { "dr50", 50, {0, {0}}, 0, 0 },
-  { "dr51", 51, {0, {0}}, 0, 0 },
-  { "dr52", 52, {0, {0}}, 0, 0 },
-  { "dr53", 53, {0, {0}}, 0, 0 },
-  { "dr54", 54, {0, {0}}, 0, 0 },
-  { "dr55", 55, {0, {0}}, 0, 0 },
-  { "dr56", 56, {0, {0}}, 0, 0 },
-  { "dr57", 57, {0, {0}}, 0, 0 },
-  { "dr58", 58, {0, {0}}, 0, 0 },
-  { "dr59", 59, {0, {0}}, 0, 0 },
-  { "dr60", 60, {0, {0}}, 0, 0 },
-  { "dr61", 61, {0, {0}}, 0, 0 },
-  { "dr62", 62, {0, {0}}, 0, 0 },
-  { "dr63", 63, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_dr =
-{
-  & sh_cgen_opval_h_dr_entries[0],
-  64,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_tr_entries[] =
-{
-  { "tr0", 0, {0, {0}}, 0, 0 },
-  { "tr1", 1, {0, {0}}, 0, 0 },
-  { "tr2", 2, {0, {0}}, 0, 0 },
-  { "tr3", 3, {0, {0}}, 0, 0 },
-  { "tr4", 4, {0, {0}}, 0, 0 },
-  { "tr5", 5, {0, {0}}, 0, 0 },
-  { "tr6", 6, {0, {0}}, 0, 0 },
-  { "tr7", 7, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_tr =
-{
-  & sh_cgen_opval_h_tr_entries[0],
-  8,
-  0, 0, 0, 0
-};
-
-static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fvc_entries[] =
-{
-  { "fv0", 0, {0, {0}}, 0, 0 },
-  { "fv4", 4, {0, {0}}, 0, 0 },
-  { "fv8", 8, {0, {0}}, 0, 0 },
-  { "fv12", 12, {0, {0}}, 0, 0 }
-};
-
-CGEN_KEYWORD sh_cgen_opval_h_fvc =
-{
-  & sh_cgen_opval_h_fvc_entries[0],
-  4,
-  0, 0, 0, 0
-};
-
-
-/* The hardware table.  */
-
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define A(a) (1 << CGEN_HW_##a)
-#else
-#define A(a) (1 << CGEN_HW_/**/a)
-#endif
-
-const CGEN_HW_ENTRY sh_cgen_hw_table[] =
-{
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
-  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0, { (1<<MACH_BASE) } } },
-  { "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { (1<<MACH_BASE) } } },
-  { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0, { (1<<MACH_BASE) } } },
-  { "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0, { (1<<MACH_BASE) } } },
-  { "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0, { (1<<MACH_BASE) } } },
-  { "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-fpccr", HW_H_FPCCR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
-  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
-};
-
-#undef A
-
-
-/* The instruction field table.  */
-
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define A(a) (1 << CGEN_IFLD_##a)
-#else
-#define A(a) (1 << CGEN_IFLD_/**/a)
-#endif
-
-const CGEN_IFLD sh_cgen_ifld_table[] =
-{
-  { SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_OP16, "f-op16", 0, 16, 15, 16, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_SUB4, "f-sub4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_SUB8, "f-sub8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_SUB10, "f-sub10", 0, 16, 9, 10, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_RN, "f-rn", 0, 16, 11, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_RM, "f-rm", 0, 16, 7, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_8_1, "f-8-1", 0, 16, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_DISP8, "f-disp8", 0, 16, 7, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_DISP12, "f-disp12", 0, 16, 11, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM4, "f-imm4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM4X2, "f-imm4x2", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM4X4, "f-imm4x4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM8X2, "f-imm8x2", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_IMM8X4, "f-imm8x4", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_DN, "f-dn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_DM, "f-dm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_VN, "f-vn", 0, 16, 11, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_VM, "f-vm", 0, 16, 9, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_XN, "f-xn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_XM, "f-xm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-  { SH_F_OP, "f-op", 0, 32, 31, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_EXT, "f-ext", 0, 32, 19, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_RSVD, "f-rsvd", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_LEFT, "f-left", 0, 32, 25, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_RIGHT, "f-right", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DEST, "f-dest", 0, 32, 9, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_TRA, "f-tra", 0, 32, 6, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_TRB, "f-trb", 0, 32, 22, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_LIKELY, "f-likely", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_25, "f-25", 0, 32, 25, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_IMM6, "f-imm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_IMM10, "f-imm10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_IMM16, "f-imm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_UIMM6, "f-uimm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_UIMM16, "f-uimm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP6, "f-disp6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP6X32, "f-disp6x32", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP10, "f-disp10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP10X8, "f-disp10x8", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP10X4, "f-disp10x4", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP10X2, "f-disp10x2", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { SH_F_DISP16, "f-disp16", 0, 32, 25, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { 0, 0, 0, 0, 0, 0, {0, {0}} }
-};
-
-#undef A
-
-
-/* The operand table.  */
-
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define A(a) (1 << CGEN_OPERAND_##a)
-#else
-#define A(a) (1 << CGEN_OPERAND_/**/a)
-#endif
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define OPERAND(op) SH_OPERAND_##op
-#else
-#define OPERAND(op) SH_OPERAND_/**/op
-#endif
-
-const CGEN_OPERAND sh_cgen_operand_table[] =
-{
-/* pc: program counter */
-  { "pc", SH_OPERAND_PC, HW_H_PC, 0, 0,
-    { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* endian: Endian mode */
-  { "endian", SH_OPERAND_ENDIAN, HW_H_ENDIAN, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } }  },
-/* ism: Instruction set mode */
-  { "ism", SH_OPERAND_ISM, HW_H_ISM, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } }  },
-/* rm: Left general purpose register */
-  { "rm", SH_OPERAND_RM, HW_H_GRC, 7, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* rn: Right general purpose register */
-  { "rn", SH_OPERAND_RN, HW_H_GRC, 11, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* r0: Register 0 */
-  { "r0", SH_OPERAND_R0, HW_H_GRC, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* frn: Single precision register */
-  { "frn", SH_OPERAND_FRN, HW_H_FRC, 11, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* frm: Single precision register */
-  { "frm", SH_OPERAND_FRM, HW_H_FRC, 7, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fvn: Left floating point vector */
-  { "fvn", SH_OPERAND_FVN, HW_H_FVC, 11, 2,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fvm: Right floating point vector */
-  { "fvm", SH_OPERAND_FVM, HW_H_FVC, 9, 2,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* drn: Left double precision register */
-  { "drn", SH_OPERAND_DRN, HW_H_DRC, 11, 3,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* drm: Right double precision register */
-  { "drm", SH_OPERAND_DRM, HW_H_DRC, 7, 3,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm4: Immediate value (4 bits) */
-  { "imm4", SH_OPERAND_IMM4, HW_H_SINT, 3, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm8: Immediate value (8 bits) */
-  { "imm8", SH_OPERAND_IMM8, HW_H_SINT, 7, 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* uimm8: Immediate value (8 bits unsigned) */
-  { "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 7, 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm4x2: Immediate value (4 bits, 2x scale) */
-  { "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 3, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm4x4: Immediate value (4 bits, 4x scale) */
-  { "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 3, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm8x2: Immediate value (8 bits, 2x scale) */
-  { "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 7, 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* imm8x4: Immediate value (8 bits, 4x scale) */
-  { "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 7, 8,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* disp8: Displacement (8 bits) */
-  { "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 7, 8,
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* disp12: Displacement (12 bits) */
-  { "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 11, 12,
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* rm64: Register m (64 bits) */
-  { "rm64", SH_OPERAND_RM64, HW_H_GR, 7, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* rn64: Register n (64 bits) */
-  { "rn64", SH_OPERAND_RN64, HW_H_GR, 11, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* gbr: Global base register */
-  { "gbr", SH_OPERAND_GBR, HW_H_GBR, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* pr: Procedure link register */
-  { "pr", SH_OPERAND_PR, HW_H_PR, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fpscr: Floating point status/control register */
-  { "fpscr", SH_OPERAND_FPSCR, HW_H_FPCCR, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* tbit: Condition code flag */
-  { "tbit", SH_OPERAND_TBIT, HW_H_TBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* sbit: Multiply-accumulate saturation flag */
-  { "sbit", SH_OPERAND_SBIT, HW_H_SBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* mbit: Divide-step M flag */
-  { "mbit", SH_OPERAND_MBIT, HW_H_MBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* qbit: Divide-step Q flag */
-  { "qbit", SH_OPERAND_QBIT, HW_H_QBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fpul: Floating point ??? */
-  { "fpul", SH_OPERAND_FPUL, HW_H_FR, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* frbit: Floating point register bank bit */
-  { "frbit", SH_OPERAND_FRBIT, HW_H_FRBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* szbit: Floating point transfer size bit */
-  { "szbit", SH_OPERAND_SZBIT, HW_H_SZBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* prbit: Floating point precision bit */
-  { "prbit", SH_OPERAND_PRBIT, HW_H_PRBIT, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* macl: Multiply-accumulate low register */
-  { "macl", SH_OPERAND_MACL, HW_H_MACL, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* mach: Multiply-accumulate high register */
-  { "mach", SH_OPERAND_MACH, HW_H_MACH, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fsdm: bar */
-  { "fsdm", SH_OPERAND_FSDM, HW_H_FRC, 7, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* fsdn: bar */
-  { "fsdn", SH_OPERAND_FSDN, HW_H_FRC, 11, 4,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }  },
-/* rm: Left general purpose reg */
-  { "rm", SH_OPERAND_RM, HW_H_GR, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* rn: Right general purpose reg */
-  { "rn", SH_OPERAND_RN, HW_H_GR, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* rd: Destination general purpose reg */
-  { "rd", SH_OPERAND_RD, HW_H_GR, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* frg: Left single precision register */
-  { "frg", SH_OPERAND_FRG, HW_H_FR, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* frh: Right single precision register */
-  { "frh", SH_OPERAND_FRH, HW_H_FR, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* frf: Destination single precision reg */
-  { "frf", SH_OPERAND_FRF, HW_H_FR, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* frgh: Single precision register pair */
-  { "frgh", SH_OPERAND_FRGH, HW_H_FR, 15, 12,
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* fpf: Pair of single precision registers */
-  { "fpf", SH_OPERAND_FPF, HW_H_FP, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* fvg: Left single precision vector */
-  { "fvg", SH_OPERAND_FVG, HW_H_FV, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* fvh: Right single precision vector */
-  { "fvh", SH_OPERAND_FVH, HW_H_FV, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* fvf: Destination single precision vector */
-  { "fvf", SH_OPERAND_FVF, HW_H_FV, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* mtrxg: Left single precision matrix */
-  { "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* drg: Left double precision register */
-  { "drg", SH_OPERAND_DRG, HW_H_DR, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* drh: Right double precision register */
-  { "drh", SH_OPERAND_DRH, HW_H_DR, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* drf: Destination double precision reg */
-  { "drf", SH_OPERAND_DRF, HW_H_DR, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* drgh: Double precision register pair */
-  { "drgh", SH_OPERAND_DRGH, HW_H_DR, 15, 12,
-    { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* fpscr: Floating point status register */
-  { "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* crj: Control register j */
-  { "crj", SH_OPERAND_CRJ, HW_H_CR, 9, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* crk: Control register k */
-  { "crk", SH_OPERAND_CRK, HW_H_CR, 25, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* tra: Target register a */
-  { "tra", SH_OPERAND_TRA, HW_H_TR, 6, 3,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* trb: Target register b */
-  { "trb", SH_OPERAND_TRB, HW_H_TR, 22, 3,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp6: Displacement (6 bits) */
-  { "disp6", SH_OPERAND_DISP6, HW_H_SINT, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp6x32: Displacement (6 bits, scale 32) */
-  { "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp10: Displacement (10 bits) */
-  { "disp10", SH_OPERAND_DISP10, HW_H_SINT, 19, 10,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp10x2: Displacement (10 bits, scale 2) */
-  { "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 19, 10,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp10x4: Displacement (10 bits, scale 4) */
-  { "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 19, 10,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp10x8: Displacement (10 bits, scale 8) */
-  { "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 19, 10,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* disp16: Displacement (16 bits) */
-  { "disp16", SH_OPERAND_DISP16, HW_H_SINT, 25, 16,
-    { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* imm6: Immediate (6 bits) */
-  { "imm6", SH_OPERAND_IMM6, HW_H_SINT, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* imm10: Immediate (10 bits) */
-  { "imm10", SH_OPERAND_IMM10, HW_H_SINT, 19, 10,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* imm16: Immediate (16 bits) */
-  { "imm16", SH_OPERAND_IMM16, HW_H_SINT, 25, 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* uimm6: Immediate (6 bits) */
-  { "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 15, 6,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* uimm16: Unsigned immediate (16 bits) */
-  { "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 25, 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-/* likely: Likely branch? */
-  { "likely", SH_OPERAND_LIKELY, HW_H_UINT, 9, 1,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }  },
-  { 0, 0, 0, 0, 0, {0, {0}} }
-};
-
-#undef A
-
-
-/* The instruction table.  */
-
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define A(a) (1 << CGEN_INSN_##a)
-#else
-#define A(a) (1 << CGEN_INSN_/**/a)
-#endif
-
-static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] =
-{
-  /* Special null first entry.
-     A `num' value of zero is thus invalid.
-     Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0, 0, {0, {0}} },
-/* add $rm, $rn */
-  {
-    SH_INSN_ADD_COMPACT, "add-compact", "add", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* add #$imm8, $rn */
-  {
-    SH_INSN_ADDI_COMPACT, "addi-compact", "add", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* addc $rm, $rn */
-  {
-    SH_INSN_ADDC_COMPACT, "addc-compact", "addc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* addv $rm, $rn */
-  {
-    SH_INSN_ADDV_COMPACT, "addv-compact", "addv", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* and $rm64, $rn64 */
-  {
-    SH_INSN_AND_COMPACT, "and-compact", "and", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* and #$uimm8, r0 */
-  {
-    SH_INSN_ANDI_COMPACT, "andi-compact", "and", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* and.b #$imm8, @(r0, gbr) */
-  {
-    SH_INSN_ANDB_COMPACT, "andb-compact", "and.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bf $disp8 */
-  {
-    SH_INSN_BF_COMPACT, "bf-compact", "bf", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bf/s $disp8 */
-  {
-    SH_INSN_BFS_COMPACT, "bfs-compact", "bf/s", 16,
-    { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bra $disp12 */
-  {
-    SH_INSN_BRA_COMPACT, "bra-compact", "bra", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* braf $rn */
-  {
-    SH_INSN_BRAF_COMPACT, "braf-compact", "braf", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* brk */
-  {
-    SH_INSN_BRK_COMPACT, "brk-compact", "brk", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bsr $disp12 */
-  {
-    SH_INSN_BSR_COMPACT, "bsr-compact", "bsr", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bsrf $rn */
-  {
-    SH_INSN_BSRF_COMPACT, "bsrf-compact", "bsrf", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bt $disp8 */
-  {
-    SH_INSN_BT_COMPACT, "bt-compact", "bt", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* bt/s $disp8 */
-  {
-    SH_INSN_BTS_COMPACT, "bts-compact", "bt/s", 16,
-    { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* clrmac */
-  {
-    SH_INSN_CLRMAC_COMPACT, "clrmac-compact", "clrmac", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* clrs */
-  {
-    SH_INSN_CLRS_COMPACT, "clrs-compact", "clrs", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* clrt */
-  {
-    SH_INSN_CLRT_COMPACT, "clrt-compact", "clrt", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/eq $rm, $rn */
-  {
-    SH_INSN_CMPEQ_COMPACT, "cmpeq-compact", "cmp/eq", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/eq #$imm8, r0 */
-  {
-    SH_INSN_CMPEQI_COMPACT, "cmpeqi-compact", "cmp/eq", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/ge $rm, $rn */
-  {
-    SH_INSN_CMPGE_COMPACT, "cmpge-compact", "cmp/ge", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/gt $rm, $rn */
-  {
-    SH_INSN_CMPGT_COMPACT, "cmpgt-compact", "cmp/gt", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/hi $rm, $rn */
-  {
-    SH_INSN_CMPHI_COMPACT, "cmphi-compact", "cmp/hi", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/hs $rm, $rn */
-  {
-    SH_INSN_CMPHS_COMPACT, "cmphs-compact", "cmp/hs", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/pl $rn */
-  {
-    SH_INSN_CMPPL_COMPACT, "cmppl-compact", "cmp/pl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/pz $rn */
-  {
-    SH_INSN_CMPPZ_COMPACT, "cmppz-compact", "cmp/pz", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* cmp/str $rm, $rn */
-  {
-    SH_INSN_CMPSTR_COMPACT, "cmpstr-compact", "cmp/str", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* div0s $rm, $rn */
-  {
-    SH_INSN_DIV0S_COMPACT, "div0s-compact", "div0s", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* div0u */
-  {
-    SH_INSN_DIV0U_COMPACT, "div0u-compact", "div0u", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* div1 $rm, $rn */
-  {
-    SH_INSN_DIV1_COMPACT, "div1-compact", "div1", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* dmuls.l $rm, $rn */
-  {
-    SH_INSN_DMULSL_COMPACT, "dmulsl-compact", "dmuls.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* dmulu.l $rm, $rn */
-  {
-    SH_INSN_DMULUL_COMPACT, "dmulul-compact", "dmulu.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* dt $rn */
-  {
-    SH_INSN_DT_COMPACT, "dt-compact", "dt", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* exts.b $rm, $rn */
-  {
-    SH_INSN_EXTSB_COMPACT, "extsb-compact", "exts.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* exts.w $rm, $rn */
-  {
-    SH_INSN_EXTSW_COMPACT, "extsw-compact", "exts.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* extu.b $rm, $rn */
-  {
-    SH_INSN_EXTUB_COMPACT, "extub-compact", "extu.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* extu.w $rm, $rn */
-  {
-    SH_INSN_EXTUW_COMPACT, "extuw-compact", "extu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fabs $fsdn */
-  {
-    SH_INSN_FABS_COMPACT, "fabs-compact", "fabs", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fadd $fsdm, $fsdn */
-  {
-    SH_INSN_FADD_COMPACT, "fadd-compact", "fadd", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fcmp/eq $fsdm, $fsdn */
-  {
-    SH_INSN_FCMPEQ_COMPACT, "fcmpeq-compact", "fcmp/eq", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fcmp/gt $fsdm, $fsdn */
-  {
-    SH_INSN_FCMPGT_COMPACT, "fcmpgt-compact", "fcmp/gt", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fcnvds $drn, fpul */
-  {
-    SH_INSN_FCNVDS_COMPACT, "fcnvds-compact", "fcnvds", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fcnvsd fpul, $drn */
-  {
-    SH_INSN_FCNVSD_COMPACT, "fcnvsd-compact", "fcnvsd", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fdiv $fsdm, $fsdn */
-  {
-    SH_INSN_FDIV_COMPACT, "fdiv-compact", "fdiv", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fipr $fvm, $fvn */
-  {
-    SH_INSN_FIPR_COMPACT, "fipr-compact", "fipr", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* flds $frn */
-  {
-    SH_INSN_FLDS_COMPACT, "flds-compact", "flds", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fldi0 $frn */
-  {
-    SH_INSN_FLDI0_COMPACT, "fldi0-compact", "fldi0", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fldi1 $frn */
-  {
-    SH_INSN_FLDI1_COMPACT, "fldi1-compact", "fldi1", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* float fpul, $fsdn */
-  {
-    SH_INSN_FLOAT_COMPACT, "float-compact", "float", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmac fr0, $frm, $frn */
-  {
-    SH_INSN_FMAC_COMPACT, "fmac-compact", "fmac", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov $frm, $frn */
-  {
-    SH_INSN_FMOV1_COMPACT, "fmov1-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov @$rm, $frn */
-  {
-    SH_INSN_FMOV2_COMPACT, "fmov2-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov @${rm}+, frn */
-  {
-    SH_INSN_FMOV3_COMPACT, "fmov3-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov @(r0, $rm), $frn */
-  {
-    SH_INSN_FMOV4_COMPACT, "fmov4-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov $frm, @$rn */
-  {
-    SH_INSN_FMOV5_COMPACT, "fmov5-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov $frm, @-$rn */
-  {
-    SH_INSN_FMOV6_COMPACT, "fmov6-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmov $frm, @(r0, $rn) */
-  {
-    SH_INSN_FMOV7_COMPACT, "fmov7-compact", "fmov", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fmul $fsdm, $fsdn */
-  {
-    SH_INSN_FMUL_COMPACT, "fmul-compact", "fmul", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fneg $fsdn */
-  {
-    SH_INSN_FNEG_COMPACT, "fneg-compact", "fneg", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* frchg */
-  {
-    SH_INSN_FRCHG_COMPACT, "frchg-compact", "frchg", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fschg */
-  {
-    SH_INSN_FSCHG_COMPACT, "fschg-compact", "fschg", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fsqrt $fsdn */
-  {
-    SH_INSN_FSQRT_COMPACT, "fsqrt-compact", "fsqrt", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fsts fpul, $frn */
-  {
-    SH_INSN_FSTS_COMPACT, "fsts-compact", "fsts", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* fsub $fsdm, $fsdn */
-  {
-    SH_INSN_FSUB_COMPACT, "fsub-compact", "fsub", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ftrc $fsdn, fpul */
-  {
-    SH_INSN_FTRC_COMPACT, "ftrc-compact", "ftrc", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ftrv xmtrx, $fvn */
-  {
-    SH_INSN_FTRV_COMPACT, "ftrv-compact", "ftrv", 16,
-    { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* jmp @$rn */
-  {
-    SH_INSN_JMP_COMPACT, "jmp-compact", "jmp", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* jsr @$rn */
-  {
-    SH_INSN_JSR_COMPACT, "jsr-compact", "jsr", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ldc $rn, gbr */
-  {
-    SH_INSN_LDC_COMPACT, "ldc-compact", "ldc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ldc.l @${rn}+, gbr */
-  {
-    SH_INSN_LDCL_COMPACT, "ldcl-compact", "ldc.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds $rn, fpscr */
-  {
-    SH_INSN_LDS_FPSCR_COMPACT, "lds-fpscr-compact", "lds", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds.l @${rn}+, fpscr */
-  {
-    SH_INSN_LDSL_FPSCR_COMPACT, "ldsl-fpscr-compact", "lds.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds $rn, fpul */
-  {
-    SH_INSN_LDS_FPUL_COMPACT, "lds-fpul-compact", "lds", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds.l @${rn}+, fpul */
-  {
-    SH_INSN_LDSL_FPUL_COMPACT, "ldsl-fpul-compact", "lds.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds $rn, mach */
-  {
-    SH_INSN_LDS_MACH_COMPACT, "lds-mach-compact", "lds", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds.l @${rn}+, mach */
-  {
-    SH_INSN_LDSL_MACH_COMPACT, "ldsl-mach-compact", "lds.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds $rn, macl */
-  {
-    SH_INSN_LDS_MACL_COMPACT, "lds-macl-compact", "lds", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds.l @${rn}+, macl */
-  {
-    SH_INSN_LDSL_MACL_COMPACT, "ldsl-macl-compact", "lds.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds $rn, pr */
-  {
-    SH_INSN_LDS_PR_COMPACT, "lds-pr-compact", "lds", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* lds.l @${rn}+, pr */
-  {
-    SH_INSN_LDSL_PR_COMPACT, "ldsl-pr-compact", "lds.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mac.l @${rm}+, @${rn}+ */
-  {
-    SH_INSN_MACL_COMPACT, "macl-compact", "mac.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mac.w @${rm}+, @${rn}+ */
-  {
-    SH_INSN_MACW_COMPACT, "macw-compact", "mac.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov $rm64, $rn64 */
-  {
-    SH_INSN_MOV_COMPACT, "mov-compact", "mov", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov #$imm8, $rn */
-  {
-    SH_INSN_MOVI_COMPACT, "movi-compact", "mov", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b $rm, @$rn */
-  {
-    SH_INSN_MOVB1_COMPACT, "movb1-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b $rm, @-$rn */
-  {
-    SH_INSN_MOVB2_COMPACT, "movb2-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b $rm, @(r0,$rn) */
-  {
-    SH_INSN_MOVB3_COMPACT, "movb3-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b r0, @($imm8, gbr) */
-  {
-    SH_INSN_MOVB4_COMPACT, "movb4-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b r0, @($imm4, $rm) */
-  {
-    SH_INSN_MOVB5_COMPACT, "movb5-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b @$rm, $rn */
-  {
-    SH_INSN_MOVB6_COMPACT, "movb6-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b @${rm}+, $rn */
-  {
-    SH_INSN_MOVB7_COMPACT, "movb7-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b @(r0, $rm), $rn */
-  {
-    SH_INSN_MOVB8_COMPACT, "movb8-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b @($imm8, gbr), r0 */
-  {
-    SH_INSN_MOVB9_COMPACT, "movb9-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.b @($imm4, $rm), r0 */
-  {
-    SH_INSN_MOVB10_COMPACT, "movb10-compact", "mov.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l $rm, @$rn */
-  {
-    SH_INSN_MOVL1_COMPACT, "movl1-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l $rm, @-$rn */
-  {
-    SH_INSN_MOVL2_COMPACT, "movl2-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l $rm, @(r0, $rn) */
-  {
-    SH_INSN_MOVL3_COMPACT, "movl3-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l r0, @($imm8x4, gbr) */
-  {
-    SH_INSN_MOVL4_COMPACT, "movl4-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l $rm, @($imm4x4, $rn) */
-  {
-    SH_INSN_MOVL5_COMPACT, "movl5-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @$rm, $rn */
-  {
-    SH_INSN_MOVL6_COMPACT, "movl6-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @${rm}+, $rn */
-  {
-    SH_INSN_MOVL7_COMPACT, "movl7-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @(r0, $rm), $rn */
-  {
-    SH_INSN_MOVL8_COMPACT, "movl8-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @($imm8x4, gbr), r0 */
-  {
-    SH_INSN_MOVL9_COMPACT, "movl9-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @($imm8x4, pc), $rn */
-  {
-    SH_INSN_MOVL10_COMPACT, "movl10-compact", "mov.l", 16,
-    { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.l @($imm4x4, $rm), $rn */
-  {
-    SH_INSN_MOVL11_COMPACT, "movl11-compact", "mov.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w $rm, @$rn */
-  {
-    SH_INSN_MOVW1_COMPACT, "movw1-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w $rm, @-$rn */
-  {
-    SH_INSN_MOVW2_COMPACT, "movw2-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w $rm, @(r0, $rn) */
-  {
-    SH_INSN_MOVW3_COMPACT, "movw3-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w r0, @($imm8x2, gbr) */
-  {
-    SH_INSN_MOVW4_COMPACT, "movw4-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w r0, @($imm4x2, $rn) */
-  {
-    SH_INSN_MOVW5_COMPACT, "movw5-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @$rm, $rn */
-  {
-    SH_INSN_MOVW6_COMPACT, "movw6-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @${rm}+, $rn */
-  {
-    SH_INSN_MOVW7_COMPACT, "movw7-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @(r0, $rm), $rn */
-  {
-    SH_INSN_MOVW8_COMPACT, "movw8-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @($imm8x2, gbr), r0 */
-  {
-    SH_INSN_MOVW9_COMPACT, "movw9-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @($imm8x2, pc), $rn */
-  {
-    SH_INSN_MOVW10_COMPACT, "movw10-compact", "mov.w", 16,
-    { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mov.w @($imm4x2, $rm), r0 */
-  {
-    SH_INSN_MOVW11_COMPACT, "movw11-compact", "mov.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mova @($imm8x4, pc), r0 */
-  {
-    SH_INSN_MOVA_COMPACT, "mova-compact", "mova", 16,
-    { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* movca.l r0, @$rn */
-  {
-    SH_INSN_MOVCAL_COMPACT, "movcal-compact", "movca.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* movt $rn */
-  {
-    SH_INSN_MOVT_COMPACT, "movt-compact", "movt", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mul.l $rm, $rn */
-  {
-    SH_INSN_MULL_COMPACT, "mull-compact", "mul.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* muls.w $rm, $rn */
-  {
-    SH_INSN_MULSW_COMPACT, "mulsw-compact", "muls.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* mulu.w $rm, $rn */
-  {
-    SH_INSN_MULUW_COMPACT, "muluw-compact", "mulu.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* neg $rm, $rn */
-  {
-    SH_INSN_NEG_COMPACT, "neg-compact", "neg", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* negc $rm, $rn */
-  {
-    SH_INSN_NEGC_COMPACT, "negc-compact", "negc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* nop */
-  {
-    SH_INSN_NOP_COMPACT, "nop-compact", "nop", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* not $rm64, $rn64 */
-  {
-    SH_INSN_NOT_COMPACT, "not-compact", "not", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ocbi @$rn */
-  {
-    SH_INSN_OCBI_COMPACT, "ocbi-compact", "ocbi", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ocbp @$rn */
-  {
-    SH_INSN_OCBP_COMPACT, "ocbp-compact", "ocbp", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* ocbwb @$rn */
-  {
-    SH_INSN_OCBWB_COMPACT, "ocbwb-compact", "ocbwb", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* or $rm64, $rn64 */
-  {
-    SH_INSN_OR_COMPACT, "or-compact", "or", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* or #$uimm8, r0 */
-  {
-    SH_INSN_ORI_COMPACT, "ori-compact", "or", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* or.b #$imm8, @(r0, gbr) */
-  {
-    SH_INSN_ORB_COMPACT, "orb-compact", "or.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* pref @$rn */
-  {
-    SH_INSN_PREF_COMPACT, "pref-compact", "pref", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* rotcl $rn */
-  {
-    SH_INSN_ROTCL_COMPACT, "rotcl-compact", "rotcl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* rotcr $rn */
-  {
-    SH_INSN_ROTCR_COMPACT, "rotcr-compact", "rotcr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* rotl $rn */
-  {
-    SH_INSN_ROTL_COMPACT, "rotl-compact", "rotl", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* rotr $rn */
-  {
-    SH_INSN_ROTR_COMPACT, "rotr-compact", "rotr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* rts */
-  {
-    SH_INSN_RTS_COMPACT, "rts-compact", "rts", 16,
-    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sets */
-  {
-    SH_INSN_SETS_COMPACT, "sets-compact", "sets", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sett */
-  {
-    SH_INSN_SETT_COMPACT, "sett-compact", "sett", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shad $rm, $rn */
-  {
-    SH_INSN_SHAD_COMPACT, "shad-compact", "shad", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shal $rn */
-  {
-    SH_INSN_SHAL_COMPACT, "shal-compact", "shal", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shar $rn */
-  {
-    SH_INSN_SHAR_COMPACT, "shar-compact", "shar", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shld $rm, $rn */
-  {
-    SH_INSN_SHLD_COMPACT, "shld-compact", "shld", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shll $rn */
-  {
-    SH_INSN_SHLL_COMPACT, "shll-compact", "shll", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shll2 $rn */
-  {
-    SH_INSN_SHLL2_COMPACT, "shll2-compact", "shll2", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shll8 $rn */
-  {
-    SH_INSN_SHLL8_COMPACT, "shll8-compact", "shll8", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shll16 $rn */
-  {
-    SH_INSN_SHLL16_COMPACT, "shll16-compact", "shll16", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shlr $rn */
-  {
-    SH_INSN_SHLR_COMPACT, "shlr-compact", "shlr", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shlr2 $rn */
-  {
-    SH_INSN_SHLR2_COMPACT, "shlr2-compact", "shlr2", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shlr8 $rn */
-  {
-    SH_INSN_SHLR8_COMPACT, "shlr8-compact", "shlr8", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* shlr16 $rn */
-  {
-    SH_INSN_SHLR16_COMPACT, "shlr16-compact", "shlr16", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* stc gbr, $rn */
-  {
-    SH_INSN_STC_GBR_COMPACT, "stc-gbr-compact", "stc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* stc.l gbr, @-$rn */
-  {
-    SH_INSN_STCL_GBR_COMPACT, "stcl-gbr-compact", "stc.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts fpscr, $rn */
-  {
-    SH_INSN_STS_FPSCR_COMPACT, "sts-fpscr-compact", "sts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts.l fpscr, @-$rn */
-  {
-    SH_INSN_STSL_FPSCR_COMPACT, "stsl-fpscr-compact", "sts.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts fpul, $rn */
-  {
-    SH_INSN_STS_FPUL_COMPACT, "sts-fpul-compact", "sts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts.l fpul, @-$rn */
-  {
-    SH_INSN_STSL_FPUL_COMPACT, "stsl-fpul-compact", "sts.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts mach, $rn */
-  {
-    SH_INSN_STS_MACH_COMPACT, "sts-mach-compact", "sts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts.l mach, @-$rn */
-  {
-    SH_INSN_STSL_MACH_COMPACT, "stsl-mach-compact", "sts.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts macl, $rn */
-  {
-    SH_INSN_STS_MACL_COMPACT, "sts-macl-compact", "sts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts.l macl, @-$rn */
-  {
-    SH_INSN_STSL_MACL_COMPACT, "stsl-macl-compact", "sts.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts pr, $rn */
-  {
-    SH_INSN_STS_PR_COMPACT, "sts-pr-compact", "sts", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sts.l pr, @-$rn */
-  {
-    SH_INSN_STSL_PR_COMPACT, "stsl-pr-compact", "sts.l", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* sub $rm, $rn */
-  {
-    SH_INSN_SUB_COMPACT, "sub-compact", "sub", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* subc $rm, $rn */
-  {
-    SH_INSN_SUBC_COMPACT, "subc-compact", "subc", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* subv $rm, $rn */
-  {
-    SH_INSN_SUBV_COMPACT, "subv-compact", "subv", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* swap.b $rm, $rn */
-  {
-    SH_INSN_SWAPB_COMPACT, "swapb-compact", "swap.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* swap.w $rm, $rn */
-  {
-    SH_INSN_SWAPW_COMPACT, "swapw-compact", "swap.w", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* tas.b @$rn */
-  {
-    SH_INSN_TASB_COMPACT, "tasb-compact", "tas.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* trapa #$uimm8 */
-  {
-    SH_INSN_TRAPA_COMPACT, "trapa-compact", "trapa", 16,
-    { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* tst $rm, $rn */
-  {
-    SH_INSN_TST_COMPACT, "tst-compact", "tst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* tst #$uimm8, r0 */
-  {
-    SH_INSN_TSTI_COMPACT, "tsti-compact", "tst", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* tst.b #$imm8, @(r0, gbr) */
-  {
-    SH_INSN_TSTB_COMPACT, "tstb-compact", "tst.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* xor $rm64, $rn64 */
-  {
-    SH_INSN_XOR_COMPACT, "xor-compact", "xor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* xor #$uimm8, r0 */
-  {
-    SH_INSN_XORI_COMPACT, "xori-compact", "xor", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* xor.b #$imm8, @(r0, gbr) */
-  {
-    SH_INSN_XORB_COMPACT, "xorb-compact", "xor.b", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* xtrct $rm, $rn */
-  {
-    SH_INSN_XTRCT_COMPACT, "xtrct-compact", "xtrct", 16,
-    { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
-  },
-/* add $rm, $rn, $rd */
-  {
-    SH_INSN_ADD, "add", "add", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* add.l $rm, $rn, $rd */
-  {
-    SH_INSN_ADDL, "addl", "add.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* addi $rm, $disp10, $rd */
-  {
-    SH_INSN_ADDI, "addi", "addi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* addi.l $rm, $disp10, $rd */
-  {
-    SH_INSN_ADDIL, "addil", "addi.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* addz.l $rm, $rn, $rd */
-  {
-    SH_INSN_ADDZL, "addzl", "addz.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* alloco $rm, $disp6x32 */
-  {
-    SH_INSN_ALLOCO, "alloco", "alloco", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* and $rm, $rn, $rd */
-  {
-    SH_INSN_AND, "and", "and", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* andc $rm, $rn, $rd */
-  {
-    SH_INSN_ANDC, "andc", "andc", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* andi $rm, $disp10, $rd */
-  {
-    SH_INSN_ANDI, "andi", "andi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* beq$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* beqi$likely $rm, $imm6, $tra */
-  {
-    SH_INSN_BEQI, "beqi", "beqi", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bge$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BGE, "bge", "bge", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bgeu$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BGEU, "bgeu", "bgeu", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bgt$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BGT, "bgt", "bgt", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bgtu$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BGTU, "bgtu", "bgtu", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* blink $trb, $rd */
-  {
-    SH_INSN_BLINK, "blink", "blink", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bne$likely $rm, $rn, $tra */
-  {
-    SH_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* bnei$likely $rm, $imm6, $tra */
-  {
-    SH_INSN_BNEI, "bnei", "bnei", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* brk */
-  {
-    SH_INSN_BRK, "brk", "brk", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* byterev $rm, $rd */
-  {
-    SH_INSN_BYTEREV, "byterev", "byterev", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* cmpeq $rm, $rn, $rd */
-  {
-    SH_INSN_CMPEQ, "cmpeq", "cmpeq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* cmpgt $rm, $rn, $rd */
-  {
-    SH_INSN_CMPGT, "cmpgt", "cmpgt", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* cmpgtu $rm,$rn, $rd */
-  {
-    SH_INSN_CMPGTU, "cmpgtu", "cmpgtu", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* cmveq $rm, $rn, $rd */
-  {
-    SH_INSN_CMVEQ, "cmveq", "cmveq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* cmvne $rm, $rn, $rd */
-  {
-    SH_INSN_CMVNE, "cmvne", "cmvne", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fabs.d $drgh, $drf */
-  {
-    SH_INSN_FABSD, "fabsd", "fabs.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fabs.s $frgh, $frf */
-  {
-    SH_INSN_FABSS, "fabss", "fabs.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fadd.d $drg, $drh, $drf */
-  {
-    SH_INSN_FADDD, "faddd", "fadd.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fadd.s $frg, $frh, $frf */
-  {
-    SH_INSN_FADDS, "fadds", "fadd.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpeq.d $drg, $drh, $rd */
-  {
-    SH_INSN_FCMPEQD, "fcmpeqd", "fcmpeq.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpeq.s $frg, $frh, $rd */
-  {
-    SH_INSN_FCMPEQS, "fcmpeqs", "fcmpeq.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpge.d $drg, $drh, $rd */
-  {
-    SH_INSN_FCMPGED, "fcmpged", "fcmpge.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpge.s $frg, $frh, $rd */
-  {
-    SH_INSN_FCMPGES, "fcmpges", "fcmpge.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpgt.d $drg, $drh, $rd */
-  {
-    SH_INSN_FCMPGTD, "fcmpgtd", "fcmpgt.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpgt.s $frg, $frh, $rd */
-  {
-    SH_INSN_FCMPGTS, "fcmpgts", "fcmpgt.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpun.d $drg, $drh, $rd */
-  {
-    SH_INSN_FCMPUND, "fcmpund", "fcmpun.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcmpun.s $frg, $frh, $rd */
-  {
-    SH_INSN_FCMPUNS, "fcmpuns", "fcmpun.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcnv.ds $drgh, $frf */
-  {
-    SH_INSN_FCNVDS, "fcnvds", "fcnv.ds", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fcnv.sd $frgh, $drf */
-  {
-    SH_INSN_FCNVSD, "fcnvsd", "fcnv.sd", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fdiv.d $drg, $drh, $drf */
-  {
-    SH_INSN_FDIVD, "fdivd", "fdiv.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fdiv.s $frg, $frh, $frf */
-  {
-    SH_INSN_FDIVS, "fdivs", "fdiv.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fgetscr $frf */
-  {
-    SH_INSN_FGETSCR, "fgetscr", "fgetscr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fipr.s $fvg, $fvh, $frf */
-  {
-    SH_INSN_FIPRS, "fiprs", "fipr.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fld.d $rm, $disp10x8, $drf */
-  {
-    SH_INSN_FLDD, "fldd", "fld.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fld.p $rm, $disp10x8, $fpf */
-  {
-    SH_INSN_FLDP, "fldp", "fld.p", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fld.s $rm, $disp10x4, $frf */
-  {
-    SH_INSN_FLDS, "flds", "fld.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fldx.d $rm, $rn, $drf */
-  {
-    SH_INSN_FLDXD, "fldxd", "fldx.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fldx.p $rm, $rn, $fpf */
-  {
-    SH_INSN_FLDXP, "fldxp", "fldx.p", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fldx.s $rm, $rn, $frf */
-  {
-    SH_INSN_FLDXS, "fldxs", "fldx.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* float.ld $frgh, $drf */
-  {
-    SH_INSN_FLOATLD, "floatld", "float.ld", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* float.ls $frgh, $frf */
-  {
-    SH_INSN_FLOATLS, "floatls", "float.ls", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* float.qd $drgh, $drf */
-  {
-    SH_INSN_FLOATQD, "floatqd", "float.qd", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* float.qs $drgh, $frf */
-  {
-    SH_INSN_FLOATQS, "floatqs", "float.qs", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmac.s $frg, $frh, $frf */
-  {
-    SH_INSN_FMACS, "fmacs", "fmac.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.d $drgh, $drf */
-  {
-    SH_INSN_FMOVD, "fmovd", "fmov.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.dq $drgh, $rd */
-  {
-    SH_INSN_FMOVDQ, "fmovdq", "fmov.dq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.ls $rm, $frf */
-  {
-    SH_INSN_FMOVLS, "fmovls", "fmov.ls", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.qd $rm, $drf */
-  {
-    SH_INSN_FMOVQD, "fmovqd", "fmov.qd", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.s $frgh, $frf */
-  {
-    SH_INSN_FMOVS, "fmovs", "fmov.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmov.sl $frgh, $rd */
-  {
-    SH_INSN_FMOVSL, "fmovsl", "fmov.sl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmul.d $drg, $drh, $drf */
-  {
-    SH_INSN_FMULD, "fmuld", "fmul.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fmul.s $frg, $frh, $frf */
-  {
-    SH_INSN_FMULS, "fmuls", "fmul.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fneg.d $drgh, $drf */
-  {
-    SH_INSN_FNEGD, "fnegd", "fneg.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fneg.s $frgh, $frf */
-  {
-    SH_INSN_FNEGS, "fnegs", "fneg.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fputscr $frgh */
-  {
-    SH_INSN_FPUTSCR, "fputscr", "fputscr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fsqrt.d $drgh, $drf */
-  {
-    SH_INSN_FSQRTD, "fsqrtd", "fsqrt.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fsqrt.s $frgh, $frf */
-  {
-    SH_INSN_FSQRTS, "fsqrts", "fsqrt.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fst.d $rm, $disp10x8, $drf */
-  {
-    SH_INSN_FSTD, "fstd", "fst.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fst.p $rm, $disp10x8, $fpf */
-  {
-    SH_INSN_FSTP, "fstp", "fst.p", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fst.s $rm, $disp10x4, $frf */
-  {
-    SH_INSN_FSTS, "fsts", "fst.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fstx.d $rm, $rn, $drf */
-  {
-    SH_INSN_FSTXD, "fstxd", "fstx.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fstx.p $rm, $rn, $fpf */
-  {
-    SH_INSN_FSTXP, "fstxp", "fstx.p", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fstx.s $rm, $rn, $frf */
-  {
-    SH_INSN_FSTXS, "fstxs", "fstx.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fsub.d $drg, $drh, $drf */
-  {
-    SH_INSN_FSUBD, "fsubd", "fsub.d", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* fsub.s $frg, $frh, $frf */
-  {
-    SH_INSN_FSUBS, "fsubs", "fsub.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ftrc.dl $drgh, $frf */
-  {
-    SH_INSN_FTRCDL, "ftrcdl", "ftrc.dl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ftrc.sl $frgh, $frf */
-  {
-    SH_INSN_FTRCSL, "ftrcsl", "ftrc.sl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ftrc.dq $drgh, $drf */
-  {
-    SH_INSN_FTRCDQ, "ftrcdq", "ftrc.dq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ftrc.sq $frgh, $drf */
-  {
-    SH_INSN_FTRCSQ, "ftrcsq", "ftrc.sq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ftrv.s $mtrxg, $fvh, $fvf */
-  {
-    SH_INSN_FTRVS, "ftrvs", "ftrv.s", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* getcfg $rm, $disp6, $rd */
-  {
-    SH_INSN_GETCFG, "getcfg", "getcfg", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* getcon $crk, $rd */
-  {
-    SH_INSN_GETCON, "getcon", "getcon", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* gettr $trb, $rd */
-  {
-    SH_INSN_GETTR, "gettr", "gettr", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* icbi $rm, $disp6x32 */
-  {
-    SH_INSN_ICBI, "icbi", "icbi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.b $rm, $disp10, $rd */
-  {
-    SH_INSN_LDB, "ldb", "ld.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.l $rm, $disp10x4, $rd */
-  {
-    SH_INSN_LDL, "ldl", "ld.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.q $rm, $disp10x8, $rd */
-  {
-    SH_INSN_LDQ, "ldq", "ld.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.ub $rm, $disp10, $rd */
-  {
-    SH_INSN_LDUB, "ldub", "ld.ub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.uw $rm, $disp10x2, $rd */
-  {
-    SH_INSN_LDUW, "lduw", "ld.uw", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ld.w $rm, $disp10x2, $rd */
-  {
-    SH_INSN_LDW, "ldw", "ld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldhi.l $rm, $disp6, $rd */
-  {
-    SH_INSN_LDHIL, "ldhil", "ldhi.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldhi.q $rm, $disp6, $rd */
-  {
-    SH_INSN_LDHIQ, "ldhiq", "ldhi.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldlo.l $rm, $disp6, $rd */
-  {
-    SH_INSN_LDLOL, "ldlol", "ldlo.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldlo.q $rm, $disp6, $rd */
-  {
-    SH_INSN_LDLOQ, "ldloq", "ldlo.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.b $rm, $rn, $rd */
-  {
-    SH_INSN_LDXB, "ldxb", "ldx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.l $rm, $rn, $rd */
-  {
-    SH_INSN_LDXL, "ldxl", "ldx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.q $rm, $rn, $rd */
-  {
-    SH_INSN_LDXQ, "ldxq", "ldx.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.ub $rm, $rn, $rd */
-  {
-    SH_INSN_LDXUB, "ldxub", "ldx.ub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.uw $rm, $rn, $rd */
-  {
-    SH_INSN_LDXUW, "ldxuw", "ldx.uw", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ldx.w $rm, $rn, $rd */
-  {
-    SH_INSN_LDXW, "ldxw", "ldx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mabs.l $rm, $rd */
-  {
-    SH_INSN_MABSL, "mabsl", "mabs.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mabs.w $rm, $rd */
-  {
-    SH_INSN_MABSW, "mabsw", "mabs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* madd.l $rm, $rn, $rd */
-  {
-    SH_INSN_MADDL, "maddl", "madd.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* madd.w $rm, $rn, $rd */
-  {
-    SH_INSN_MADDW, "maddw", "madd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* madds.l $rm, $rn, $rd */
-  {
-    SH_INSN_MADDSL, "maddsl", "madds.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* madds.ub $rm, $rn, $rd */
-  {
-    SH_INSN_MADDSUB, "maddsub", "madds.ub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* madds.w $rm, $rn, $rd */
-  {
-    SH_INSN_MADDSW, "maddsw", "madds.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpeq.b $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPEQB, "mcmpeqb", "mcmpeq.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpeq.l $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPEQL, "mcmpeql", "mcmpeq.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpeq.w $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPEQW, "mcmpeqw", "mcmpeq.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpgt.l $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPGTL, "mcmpgtl", "mcmpgt.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpgt.ub $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPGTUB, "mcmpgtub", "mcmpgt.ub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmpgt.w $rm, $rn, $rd */
-  {
-    SH_INSN_MCMPGTW, "mcmpgtw", "mcmpgt.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcmv $rm, $rn, $rd */
-  {
-    SH_INSN_MCMV, "mcmv", "mcmv", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcnvs.lw $rm, $rn, $rd */
-  {
-    SH_INSN_MCNVSLW, "mcnvslw", "mcnvs.lw", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcnvs.wb $rm, $rn, $rd */
-  {
-    SH_INSN_MCNVSWB, "mcnvswb", "mcnvs.wb", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mcnvs.wub $rm, $rn, $rd */
-  {
-    SH_INSN_MCNVSWUB, "mcnvswub", "mcnvs.wub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr1 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR1, "mextr1", "mextr1", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr2 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR2, "mextr2", "mextr2", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr3 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR3, "mextr3", "mextr3", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr4 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR4, "mextr4", "mextr4", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr5 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR5, "mextr5", "mextr5", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr6 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR6, "mextr6", "mextr6", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mextr7 $rm, $rn, $rd */
-  {
-    SH_INSN_MEXTR7, "mextr7", "mextr7", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmacfx.wl $rm, $rn, $rd */
-  {
-    SH_INSN_MMACFXWL, "mmacfxwl", "mmacfx.wl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmacnfx.wl $rm, $rn, $rd */
-  {
-    SH_INSN_MMACNFX_WL, "mmacnfx.wl", "mmacnfx.wl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmul.l $rm, $rn, $rd */
-  {
-    SH_INSN_MMULL, "mmull", "mmul.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmul.w $rm, $rn, $rd */
-  {
-    SH_INSN_MMULW, "mmulw", "mmul.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmulfx.l $rm, $rn, $rd */
-  {
-    SH_INSN_MMULFXL, "mmulfxl", "mmulfx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmulfx.w $rm, $rn, $rd */
-  {
-    SH_INSN_MMULFXW, "mmulfxw", "mmulfx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmulfxrp.w $rm, $rn, $rd */
-  {
-    SH_INSN_MMULFXRPW, "mmulfxrpw", "mmulfxrp.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmulhi.wl $rm, $rn, $rd */
-  {
-    SH_INSN_MMULHIWL, "mmulhiwl", "mmulhi.wl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmullo.wl $rm, $rn, $rd */
-  {
-    SH_INSN_MMULLOWL, "mmullowl", "mmullo.wl", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mmulsum.wq $rm, $rn, $rd */
-  {
-    SH_INSN_MMULSUMWQ, "mmulsumwq", "mmulsum.wq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* movi $imm16, $rd */
-  {
-    SH_INSN_MOVI, "movi", "movi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mperm.w $rm, $rn, $rd */
-  {
-    SH_INSN_MPERMW, "mpermw", "mperm.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msad.ubq $rm, $rn, $rd */
-  {
-    SH_INSN_MSADUBQ, "msadubq", "msad.ubq", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshalds.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHALDSL, "mshaldsl", "mshalds.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshalds.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHALDSW, "mshaldsw", "mshalds.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshard.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHARDL, "mshardl", "mshard.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshard.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHARDW, "mshardw", "mshard.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshards.q $rm, $rn, $rd */
-  {
-    SH_INSN_MSHARDSQ, "mshardsq", "mshards.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshfhi.b $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFHIB, "mshfhib", "mshfhi.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshfhi.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFHIL, "mshfhil", "mshfhi.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshfhi.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFHIW, "mshfhiw", "mshfhi.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshflo.b $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFLOB, "mshflob", "mshflo.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshflo.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFLOL, "mshflol", "mshflo.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshflo.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHFLOW, "mshflow", "mshflo.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshlld.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHLLDL, "mshlldl", "mshlld.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshlld.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHLLDW, "mshlldw", "mshlld.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshlrd.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSHLRDL, "mshlrdl", "mshlrd.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mshlrd.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSHLRDW, "mshlrdw", "mshlrd.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msub.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSUBL, "msubl", "msub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msub.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSUBW, "msubw", "msub.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msubs.l $rm, $rn, $rd */
-  {
-    SH_INSN_MSUBSL, "msubsl", "msubs.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msubs.ub $rm, $rn, $rd */
-  {
-    SH_INSN_MSUBSUB, "msubsub", "msubs.ub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* msubs.w $rm, $rn, $rd */
-  {
-    SH_INSN_MSUBSW, "msubsw", "msubs.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* muls.l $rm, $rn, $rd */
-  {
-    SH_INSN_MULSL, "mulsl", "muls.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* mulu.l $rm, $rn, $rd */
-  {
-    SH_INSN_MULUL, "mulul", "mulu.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* nop */
-  {
-    SH_INSN_NOP, "nop", "nop", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* nsb $rm, $rd */
-  {
-    SH_INSN_NSB, "nsb", "nsb", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ocbi $rm, $disp6x32 */
-  {
-    SH_INSN_OCBI, "ocbi", "ocbi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ocbp $rm, $disp6x32 */
-  {
-    SH_INSN_OCBP, "ocbp", "ocbp", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ocbwb $rm, $disp6x32 */
-  {
-    SH_INSN_OCBWB, "ocbwb", "ocbwb", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* or $rm, $rn, $rd */
-  {
-    SH_INSN_OR, "or", "or", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ori $rm, $imm10, $rd */
-  {
-    SH_INSN_ORI, "ori", "ori", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* prefi $rm, $disp6x32 */
-  {
-    SH_INSN_PREFI, "prefi", "prefi", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* pta$likely $disp16, $tra */
-  {
-    SH_INSN_PTA, "pta", "pta", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ptabs$likely $rn, $tra */
-  {
-    SH_INSN_PTABS, "ptabs", "ptabs", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ptb$likely $disp16, $tra */
-  {
-    SH_INSN_PTB, "ptb", "ptb", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* ptrel$likely $rn, $tra */
-  {
-    SH_INSN_PTREL, "ptrel", "ptrel", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* putcfg $rm, $disp6, $rd */
-  {
-    SH_INSN_PUTCFG, "putcfg", "putcfg", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* putcon $rm, $crj */
-  {
-    SH_INSN_PUTCON, "putcon", "putcon", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* rte */
-  {
-    SH_INSN_RTE, "rte", "rte", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shard $rm, $rn, $rd */
-  {
-    SH_INSN_SHARD, "shard", "shard", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shard.l $rm, $rn, $rd */
-  {
-    SH_INSN_SHARDL, "shardl", "shard.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shari $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHARI, "shari", "shari", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shari.l $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHARIL, "sharil", "shari.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlld $rm, $rn, $rd */
-  {
-    SH_INSN_SHLLD, "shlld", "shlld", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlld.l $rm, $rn, $rd */
-  {
-    SH_INSN_SHLLDL, "shlldl", "shlld.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlli $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHLLI, "shlli", "shlli", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlli.l $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHLLIL, "shllil", "shlli.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlrd $rm, $rn, $rd */
-  {
-    SH_INSN_SHLRD, "shlrd", "shlrd", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlrd.l $rm, $rn, $rd */
-  {
-    SH_INSN_SHLRDL, "shlrdl", "shlrd.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlri $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHLRI, "shlri", "shlri", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shlri.l $rm, $uimm6, $rd */
-  {
-    SH_INSN_SHLRIL, "shlril", "shlri.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* shori $uimm16, $rd */
-  {
-    SH_INSN_SHORI, "shori", "shori", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* sleep */
-  {
-    SH_INSN_SLEEP, "sleep", "sleep", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* st.b $rm, $disp10, $rd */
-  {
-    SH_INSN_STB, "stb", "st.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* st.l $rm, $disp10x4, $rd */
-  {
-    SH_INSN_STL, "stl", "st.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* st.q $rm, $disp10x8, $rd */
-  {
-    SH_INSN_STQ, "stq", "st.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* st.w $rm, $disp10x2, $rd */
-  {
-    SH_INSN_STW, "stw", "st.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* sthi.l $rm, $disp6, $rd */
-  {
-    SH_INSN_STHIL, "sthil", "sthi.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* sthi.q $rm, $disp6, $rd */
-  {
-    SH_INSN_STHIQ, "sthiq", "sthi.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stlo.l $rm, $disp6, $rd */
-  {
-    SH_INSN_STLOL, "stlol", "stlo.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stlo.q $rm, $disp6, $rd */
-  {
-    SH_INSN_STLOQ, "stloq", "stlo.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stx.b $rm, $rn, $rd */
-  {
-    SH_INSN_STXB, "stxb", "stx.b", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stx.l $rm, $rn, $rd */
-  {
-    SH_INSN_STXL, "stxl", "stx.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stx.q $rm, $rn, $rd */
-  {
-    SH_INSN_STXQ, "stxq", "stx.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* stx.w $rm, $rn, $rd */
-  {
-    SH_INSN_STXW, "stxw", "stx.w", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* sub $rm, $rn, $rd */
-  {
-    SH_INSN_SUB, "sub", "sub", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* sub.l $rm, $rn, $rd */
-  {
-    SH_INSN_SUBL, "subl", "sub.l", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* swap.q $rm, $rn, $rd */
-  {
-    SH_INSN_SWAPQ, "swapq", "swap.q", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* synci */
-  {
-    SH_INSN_SYNCI, "synci", "synci", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* synco */
-  {
-    SH_INSN_SYNCO, "synco", "synco", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* trapa $rm */
-  {
-    SH_INSN_TRAPA, "trapa", "trapa", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* xor $rm, $rn, $rd */
-  {
-    SH_INSN_XOR, "xor", "xor", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-/* xori $rm, $imm6, $rd */
-  {
-    SH_INSN_XORI, "xori", "xori", 32,
-    { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
-  },
-};
-
-#undef OP
-#undef A
-
-/* Initialize anything needed to be done once, before any cpu_open call.  */
-
-static void
-init_tables ()
-{
-}
-
-/* Subroutine of sh_cgen_cpu_open to look up a mach via its bfd name.  */
-
-static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
-     const CGEN_MACH *table;
-     const char *name;
-{
-  while (table->name)
-    {
-      if (strcmp (name, table->bfd_name) == 0)
-	return table;
-      ++table;
-    }
-  abort ();
-}
-
-/* Subroutine of sh_cgen_cpu_open to build the hardware table.  */
-
-static void
-build_hw_table (cd)
-     CGEN_CPU_TABLE *cd;
-{
-  int i;
-  int machs = cd->machs;
-  const CGEN_HW_ENTRY *init = & sh_cgen_hw_table[0];
-  /* MAX_HW is only an upper bound on the number of selected entries.
-     However each entry is indexed by it's enum so there can be holes in
-     the table.  */
-  const CGEN_HW_ENTRY **selected =
-    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
-
-  cd->hw_table.init_entries = init;
-  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
-  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
-  /* ??? For now we just use machs to determine which ones we want.  */
-  for (i = 0; init[i].name != NULL; ++i)
-    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
-	& machs)
-      selected[init[i].type] = &init[i];
-  cd->hw_table.entries = selected;
-  cd->hw_table.num_entries = MAX_HW;
-}
-
-/* Subroutine of sh_cgen_cpu_open to build the hardware table.  */
-
-static void
-build_ifield_table (cd)
-     CGEN_CPU_TABLE *cd;
-{
-  cd->ifld_table = & sh_cgen_ifld_table[0];
-}
-
-/* Subroutine of sh_cgen_cpu_open to build the hardware table.  */
-
-static void
-build_operand_table (cd)
-     CGEN_CPU_TABLE *cd;
-{
-  int i;
-  int machs = cd->machs;
-  const CGEN_OPERAND *init = & sh_cgen_operand_table[0];
-  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
-     However each entry is indexed by it's enum so there can be holes in
-     the table.  */
-  const CGEN_OPERAND **selected =
-    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
-
-  cd->operand_table.init_entries = init;
-  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
-  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
-  /* ??? For now we just use mach to determine which ones we want.  */
-  for (i = 0; init[i].name != NULL; ++i)
-    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
-	& machs)
-      selected[init[i].type] = &init[i];
-  cd->operand_table.entries = selected;
-  cd->operand_table.num_entries = MAX_OPERANDS;
-}
-
-/* Subroutine of sh_cgen_cpu_open to build the hardware table.
-   ??? This could leave out insns not supported by the specified mach/isa,
-   but that would cause errors like "foo only supported by bar" to become
-   "unknown insn", so for now we include all insns and require the app to
-   do the checking later.
-   ??? On the other hand, parsing of such insns may require their hardware or
-   operand elements to be in the table [which they mightn't be].  */
-
-static void
-build_insn_table (cd)
-     CGEN_CPU_TABLE *cd;
-{
-  int i;
-  const CGEN_IBASE *ib = & sh_cgen_insn_table[0];
-  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
-
-  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
-  for (i = 0; i < MAX_INSNS; ++i)
-    insns[i].base = &ib[i];
-  cd->insn_table.init_entries = insns;
-  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
-  cd->insn_table.num_init_entries = MAX_INSNS;
-}
-
-/* Subroutine of sh_cgen_cpu_open to rebuild the tables.  */
-
-static void
-sh_cgen_rebuild_tables (cd)
-     CGEN_CPU_TABLE *cd;
-{
-  int i,n_isas;
-  unsigned int isas = cd->isas;
-#if 0
-  unsigned int machs = cd->machs;
-#endif
-
-  cd->int_insn_p = CGEN_INT_INSN_P;
-
-  /* Data derived from the isa spec.  */
-#define UNSET (CGEN_SIZE_UNKNOWN + 1)
-  cd->default_insn_bitsize = UNSET;
-  cd->base_insn_bitsize = UNSET;
-  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
-  cd->max_insn_bitsize = 0;
-  for (i = 0; i < MAX_ISAS; ++i)
-    if (((1 << i) & isas) != 0)
-      {
-	const CGEN_ISA *isa = & sh_cgen_isa_table[i];
-
-	/* Default insn sizes of all selected isas must be equal or we set
-	   the result to 0, meaning "unknown".  */
-	if (cd->default_insn_bitsize == UNSET)
-	  cd->default_insn_bitsize = isa->default_insn_bitsize;
-	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
-	  ; /* this is ok */
-	else
-	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
-	/* Base insn sizes of all selected isas must be equal or we set
-	   the result to 0, meaning "unknown".  */
-	if (cd->base_insn_bitsize == UNSET)
-	  cd->base_insn_bitsize = isa->base_insn_bitsize;
-	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
-	  ; /* this is ok */
-	else
-	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
-	/* Set min,max insn sizes.  */
-	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
-	  cd->min_insn_bitsize = isa->min_insn_bitsize;
-	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
-	  cd->max_insn_bitsize = isa->max_insn_bitsize;
-
-	++n_isas;
-      }
-
-#if 0 /* Does nothing?? */
-  /* Data derived from the mach spec.  */
-  for (i = 0; i < MAX_MACHS; ++i)
-    if (((1 << i) & machs) != 0)
-      {
-	const CGEN_MACH *mach = & sh_cgen_mach_table[i];
-
-	++n_machs;
-      }
-#endif
-
-  /* Determine which hw elements are used by MACH.  */
-  build_hw_table (cd);
-
-  /* Build the ifield table.  */
-  build_ifield_table (cd);
-
-  /* Determine which operands are used by MACH/ISA.  */
-  build_operand_table (cd);
-
-  /* Build the instruction table.  */
-  build_insn_table (cd);
-}
-
-/* Initialize a cpu table and return a descriptor.
-   It's much like opening a file, and must be the first function called.
-   The arguments are a set of (type/value) pairs, terminated with
-   CGEN_CPU_OPEN_END.
-
-   Currently supported values:
-   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
-   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
-   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
-   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
-   CGEN_CPU_OPEN_END:     terminates arguments
-
-   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
-   precluded.
-
-   ??? We only support ISO C stdargs here, not K&R.
-   Laziness, plus experiment to see if anything requires K&R - eventually
-   K&R will no longer be supported - e.g. GDB is currently trying this.  */
-
-CGEN_CPU_DESC
-sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
-{
-  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
-  static int init_p;
-  unsigned int isas = 0;  /* 0 = "unspecified" */
-  unsigned int machs = 0; /* 0 = "unspecified" */
-  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
-  va_list ap;
-
-  if (! init_p)
-    {
-      init_tables ();
-      init_p = 1;
-    }
-
-  memset (cd, 0, sizeof (*cd));
-
-  va_start (ap, arg_type);
-  while (arg_type != CGEN_CPU_OPEN_END)
-    {
-      switch (arg_type)
-	{
-	case CGEN_CPU_OPEN_ISAS :
-	  isas = va_arg (ap, unsigned int);
-	  break;
-	case CGEN_CPU_OPEN_MACHS :
-	  machs = va_arg (ap, unsigned int);
-	  break;
-	case CGEN_CPU_OPEN_BFDMACH :
-	  {
-	    const char *name = va_arg (ap, const char *);
-	    const CGEN_MACH *mach =
-	      lookup_mach_via_bfd_name (sh_cgen_mach_table, name);
-
-	    machs |= mach->num << 1;
-	    break;
-	  }
-	case CGEN_CPU_OPEN_ENDIAN :
-	  endian = va_arg (ap, enum cgen_endian);
-	  break;
-	default :
-	  fprintf (stderr, "sh_cgen_cpu_open: unsupported argument `%d'\n",
-		   arg_type);
-	  abort (); /* ??? return NULL? */
-	}
-      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
-    }
-  va_end (ap);
-
-  /* mach unspecified means "all" */
-  if (machs == 0)
-    machs = (1 << MAX_MACHS) - 1;
-  /* base mach is always selected */
-  machs |= 1;
-  /* isa unspecified means "all" */
-  if (isas == 0)
-    isas = (1 << MAX_ISAS) - 1;
-  if (endian == CGEN_ENDIAN_UNKNOWN)
-    {
-      /* ??? If target has only one, could have a default.  */
-      fprintf (stderr, "sh_cgen_cpu_open: no endianness specified\n");
-      abort ();
-    }
-
-  cd->isas = isas;
-  cd->machs = machs;
-  cd->endian = endian;
-  /* FIXME: for the sparc case we can determine insn-endianness statically.
-     The worry here is where both data and insn endian can be independently
-     chosen, in which case this function will need another argument.
-     Actually, will want to allow for more arguments in the future anyway.  */
-  cd->insn_endian = endian;
-
-  /* Table (re)builder.  */
-  cd->rebuild_tables = sh_cgen_rebuild_tables;
-  sh_cgen_rebuild_tables (cd);
-
-  /* Default to not allowing signed overflow.  */
-  cd->signed_overflow_ok_p = 0;
-  
-  return (CGEN_CPU_DESC) cd;
-}
-
-/* Cover fn to sh_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
-   MACH_NAME is the bfd name of the mach.  */
-
-CGEN_CPU_DESC
-sh_cgen_cpu_open_1 (mach_name, endian)
-     const char *mach_name;
-     enum cgen_endian endian;
-{
-  return sh_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
-			       CGEN_CPU_OPEN_ENDIAN, endian,
-			       CGEN_CPU_OPEN_END);
-}
-
-/* Close a cpu table.
-   ??? This can live in a machine independent file, but there's currently
-   no place to put this file (there's no libcgen).  libopcodes is the wrong
-   place as some simulator ports use this but they don't use libopcodes.  */
-
-void
-sh_cgen_cpu_close (cd)
-     CGEN_CPU_DESC cd;
-{
-  if (cd->insn_table.init_entries)
-    free ((CGEN_INSN *) cd->insn_table.init_entries);
-  if (cd->hw_table.entries)
-    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
-  free (cd);
-}
-
diff --git a/sim/sh64/sh-desc.h b/sim/sh64/sh-desc.h
deleted file mode 100644
index 30402cc53fa..00000000000
--- a/sim/sh64/sh-desc.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/* CPU data header for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH_CPU_H
-#define SH_CPU_H
-
-#define CGEN_ARCH sh
-
-/* Given symbol S, return sh_cgen_<S>.  */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define CGEN_SYM(s) sh##_cgen_##s
-#else
-#define CGEN_SYM(s) sh/**/_cgen_/**/s
-#endif
-
-
-/* Selected cpu families.  */
-#define HAVE_CPU_SH64
-
-#define CGEN_INSN_LSB0_P 1
-
-/* Minimum size of any insn (in bytes).  */
-#define CGEN_MIN_INSN_SIZE 2
-
-/* Maximum size of any insn (in bytes).  */
-#define CGEN_MAX_INSN_SIZE 4
-
-#define CGEN_INT_INSN_P 1
-
-/* Maximum nymber of syntax bytes in an instruction.  */
-#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
-
-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
-   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
-   we can't hash on everything up to the space.  */
-#define CGEN_MNEMONIC_OPERANDS
-
-/* Maximum number of fields in an instruction.  */
-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
-
-/* Enums.  */
-
-/* Enum declaration for .  */
-typedef enum frc_names {
-  H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
- , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
- , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
- , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
-} FRC_NAMES;
-
-/* Enum declaration for .  */
-typedef enum drc_names {
-  H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
- , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
-} DRC_NAMES;
-
-/* Enum declaration for .  */
-typedef enum xf_names {
-  H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
- , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
- , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
- , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
-} XF_NAMES;
-
-/* Attributes.  */
-
-/* Enum declaration for machine type selection.  */
-typedef enum mach_attr {
-  MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
- , MACH_SH4, MACH_SH5, MACH_MAX
-} MACH_ATTR;
-
-/* Enum declaration for instruction set selection.  */
-typedef enum isa_attr {
-  ISA_COMPACT, ISA_MEDIA, ISA_MAX
-} ISA_ATTR;
-
-/* Number of architecture variants.  */
-#define MAX_ISAS  ((int) ISA_MAX)
-#define MAX_MACHS ((int) MACH_MAX)
-
-/* Ifield attribute indices.  */
-
-/* Enum declaration for cgen_ifld attrs.  */
-typedef enum cgen_ifld_attr {
-  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
- , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
- , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
-} CGEN_IFLD_ATTR;
-
-/* Number of non-boolean elements in cgen_ifld_attr.  */
-#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
-
-/* Enum declaration for sh ifield types.  */
-typedef enum ifield_type {
-  SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
- , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
- , SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
- , SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
- , SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
- , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
- , SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
- , SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
- , SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
- , SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
- , SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
- , SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
- , SH_F_DISP16, SH_F_MAX
-} IFIELD_TYPE;
-
-#define MAX_IFLD ((int) SH_F_MAX)
-
-/* Hardware attribute indices.  */
-
-/* Enum declaration for cgen_hw attrs.  */
-typedef enum cgen_hw_attr {
-  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
- , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw_attr.  */
-#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
-
-/* Enum declaration for sh hardware types.  */
-typedef enum cgen_hw_type {
-  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
- , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
- , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
- , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
- , HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
- , HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
- , HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
- , HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
- , HW_MAX
-} CGEN_HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
-/* Operand attribute indices.  */
-
-/* Enum declaration for cgen_operand attrs.  */
-typedef enum cgen_operand_attr {
-  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
- , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
- , CGEN_OPERAND_END_NBOOLS
-} CGEN_OPERAND_ATTR;
-
-/* Number of non-boolean elements in cgen_operand_attr.  */
-#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
-
-/* Enum declaration for sh operand types.  */
-typedef enum cgen_operand_type {
-  SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
- , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
- , SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
- , SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
- , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
- , SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
- , SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
- , SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
- , SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
- , SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
- , SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
- , SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
- , SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
- , SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
- , SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
- , SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
- , SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
- , SH_OPERAND_LIKELY, SH_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Number of operands types.  */
-#define MAX_OPERANDS 72
-
-/* Maximum number of operands referenced by any insn.  */
-#define MAX_OPERAND_INSTANCES 8
-
-/* Insn attribute indices.  */
-
-/* Enum declaration for cgen_insn attrs.  */
-typedef enum cgen_insn_attr {
-  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
- , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
- , CGEN_INSN_END_NBOOLS
-} CGEN_INSN_ATTR;
-
-/* Number of non-boolean elements in cgen_insn_attr.  */
-#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
-
-/* cgen.h uses things we just defined.  */
-#include "opcode/cgen.h"
-
-/* Attributes.  */
-extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
-extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
-extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
-extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
-
-/* Hardware decls.  */
-
-extern CGEN_KEYWORD sh_cgen_opval_h_gr;
-extern CGEN_KEYWORD sh_cgen_opval_h_grc;
-extern CGEN_KEYWORD sh_cgen_opval_h_cr;
-extern CGEN_KEYWORD sh_cgen_opval_h_fr;
-extern CGEN_KEYWORD sh_cgen_opval_h_fp;
-extern CGEN_KEYWORD sh_cgen_opval_h_fv;
-extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
-extern CGEN_KEYWORD sh_cgen_opval_h_dr;
-extern CGEN_KEYWORD sh_cgen_opval_h_tr;
-extern CGEN_KEYWORD sh_cgen_opval_frc_names;
-extern CGEN_KEYWORD sh_cgen_opval_drc_names;
-extern CGEN_KEYWORD sh_cgen_opval_xf_names;
-extern CGEN_KEYWORD sh_cgen_opval_frc_names;
-extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
-
-/* Ifield support.  */
-
-extern const struct cgen_ifld sh_cgen_ifld_table[];
-
-
-
-
-#endif /* SH_CPU_H */
diff --git a/sim/sh64/sh-opc.h b/sim/sh64/sh-opc.h
deleted file mode 100644
index 3e0b8e25ec5..00000000000
--- a/sim/sh64/sh-opc.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* Instruction opcode header for sh.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef SH_OPC_H
-#define SH_OPC_H
-
-/* -- opc.h */
-
-/* Allows reason codes to be output when assembler errors occur.  */
-#define CGEN_VERBOSE_ASSEMBLER_ERRORS
-
-/* Override disassembly hashing - there are variable bits in the top
-   byte of these instructions.  */
-#define CGEN_DIS_HASH_SIZE 8
-#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
-
-/* -- asm.c */
-/* Enum declaration for sh instruction types.  */
-typedef enum cgen_insn_type {
-  SH_INSN_INVALID, SH_INSN_ADD_COMPACT, SH_INSN_ADDI_COMPACT, SH_INSN_ADDC_COMPACT
- , SH_INSN_ADDV_COMPACT, SH_INSN_AND_COMPACT, SH_INSN_ANDI_COMPACT, SH_INSN_ANDB_COMPACT
- , SH_INSN_BF_COMPACT, SH_INSN_BFS_COMPACT, SH_INSN_BRA_COMPACT, SH_INSN_BRAF_COMPACT
- , SH_INSN_BRK_COMPACT, SH_INSN_BSR_COMPACT, SH_INSN_BSRF_COMPACT, SH_INSN_BT_COMPACT
- , SH_INSN_BTS_COMPACT, SH_INSN_CLRMAC_COMPACT, SH_INSN_CLRS_COMPACT, SH_INSN_CLRT_COMPACT
- , SH_INSN_CMPEQ_COMPACT, SH_INSN_CMPEQI_COMPACT, SH_INSN_CMPGE_COMPACT, SH_INSN_CMPGT_COMPACT
- , SH_INSN_CMPHI_COMPACT, SH_INSN_CMPHS_COMPACT, SH_INSN_CMPPL_COMPACT, SH_INSN_CMPPZ_COMPACT
- , SH_INSN_CMPSTR_COMPACT, SH_INSN_DIV0S_COMPACT, SH_INSN_DIV0U_COMPACT, SH_INSN_DIV1_COMPACT
- , SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT
- , SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT
- , SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT
- , SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT
- , SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT
- , SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT
- , SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT, SH_INSN_FMOV7_COMPACT, SH_INSN_FMUL_COMPACT
- , SH_INSN_FNEG_COMPACT, SH_INSN_FRCHG_COMPACT, SH_INSN_FSCHG_COMPACT, SH_INSN_FSQRT_COMPACT
- , SH_INSN_FSTS_COMPACT, SH_INSN_FSUB_COMPACT, SH_INSN_FTRC_COMPACT, SH_INSN_FTRV_COMPACT
- , SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_COMPACT, SH_INSN_LDCL_COMPACT
- , SH_INSN_LDS_FPSCR_COMPACT, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT
- , SH_INSN_LDS_MACH_COMPACT, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT
- , SH_INSN_LDS_PR_COMPACT, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT
- , SH_INSN_MOV_COMPACT, SH_INSN_MOVI_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT
- , SH_INSN_MOVB3_COMPACT, SH_INSN_MOVB4_COMPACT, SH_INSN_MOVB5_COMPACT, SH_INSN_MOVB6_COMPACT
- , SH_INSN_MOVB7_COMPACT, SH_INSN_MOVB8_COMPACT, SH_INSN_MOVB9_COMPACT, SH_INSN_MOVB10_COMPACT
- , SH_INSN_MOVL1_COMPACT, SH_INSN_MOVL2_COMPACT, SH_INSN_MOVL3_COMPACT, SH_INSN_MOVL4_COMPACT
- , SH_INSN_MOVL5_COMPACT, SH_INSN_MOVL6_COMPACT, SH_INSN_MOVL7_COMPACT, SH_INSN_MOVL8_COMPACT
- , SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVW1_COMPACT
- , SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT
- , SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT
- , SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT
- , SH_INSN_MOVT_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT, SH_INSN_MULUW_COMPACT
- , SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT, SH_INSN_NOT_COMPACT
- , SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT, SH_INSN_OR_COMPACT
- , SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT, SH_INSN_ROTCL_COMPACT
- , SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT, SH_INSN_RTS_COMPACT
- , SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT, SH_INSN_SHAL_COMPACT
- , SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT, SH_INSN_SHLL2_COMPACT
- , SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT, SH_INSN_SHLR2_COMPACT
- , SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT, SH_INSN_STCL_GBR_COMPACT
- , SH_INSN_STS_FPSCR_COMPACT, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT
- , SH_INSN_STS_MACH_COMPACT, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT
- , SH_INSN_STS_PR_COMPACT, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT
- , SH_INSN_SUBV_COMPACT, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT
- , SH_INSN_TRAPA_COMPACT, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT
- , SH_INSN_XOR_COMPACT, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT
- , SH_INSN_ADD, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL
- , SH_INSN_ADDZL, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC
- , SH_INSN_ANDI, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE
- , SH_INSN_BGEU, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK
- , SH_INSN_BNE, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV
- , SH_INSN_CMPEQ, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ
- , SH_INSN_CMVNE, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD
- , SH_INSN_FADDS, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED
- , SH_INSN_FCMPGES, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND
- , SH_INSN_FCMPUNS, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD
- , SH_INSN_FDIVS, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD
- , SH_INSN_FLDP, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP
- , SH_INSN_FLDXS, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD
- , SH_INSN_FLOATQS, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ
- , SH_INSN_FMOVLS, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL
- , SH_INSN_FMULD, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS
- , SH_INSN_FPUTSCR, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD
- , SH_INSN_FSTP, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP
- , SH_INSN_FSTXS, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL
- , SH_INSN_FTRCSL, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS
- , SH_INSN_GETCFG, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI
- , SH_INSN_LDB, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB
- , SH_INSN_LDUW, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ
- , SH_INSN_LDLOL, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL
- , SH_INSN_LDXQ, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW
- , SH_INSN_MABSL, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW
- , SH_INSN_MADDSL, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB
- , SH_INSN_MCMPEQL, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB
- , SH_INSN_MCMPGTW, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB
- , SH_INSN_MCNVSWUB, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3
- , SH_INSN_MEXTR4, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7
- , SH_INSN_MMACFXWL, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW
- , SH_INSN_MMULFXL, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL
- , SH_INSN_MMULLOWL, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW
- , SH_INSN_MSADUBQ, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL
- , SH_INSN_MSHARDW, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL
- , SH_INSN_MSHFHIW, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW
- , SH_INSN_MSHLLDL, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW
- , SH_INSN_MSUBL, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB
- , SH_INSN_MSUBSW, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP
- , SH_INSN_NSB, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB
- , SH_INSN_OR, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA
- , SH_INSN_PTABS, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG
- , SH_INSN_PUTCON, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL
- , SH_INSN_SHARI, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL
- , SH_INSN_SHLLI, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL
- , SH_INSN_SHLRI, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP
- , SH_INSN_STB, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW
- , SH_INSN_STHIL, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ
- , SH_INSN_STXB, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW
- , SH_INSN_SUB, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI
- , SH_INSN_SYNCO, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI
- , SH_INSN_MAX
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder.  */
-#define CGEN_INSN_INVALID SH_INSN_INVALID
-
-/* Total number of insns in table.  */
-#define MAX_INSNS ((int) SH_INSN_MAX)
-
-/* This struct records data prior to insertion or after extraction.  */
-struct cgen_fields
-{
-  int length;
-  long f_nil;
-  long f_anyof;
-  long f_op4;
-  long f_op8;
-  long f_op16;
-  long f_sub4;
-  long f_sub8;
-  long f_sub10;
-  long f_rn;
-  long f_rm;
-  long f_8_1;
-  long f_disp8;
-  long f_disp12;
-  long f_imm8;
-  long f_imm4;
-  long f_imm4x2;
-  long f_imm4x4;
-  long f_imm8x2;
-  long f_imm8x4;
-  long f_dn;
-  long f_dm;
-  long f_vn;
-  long f_vm;
-  long f_xn;
-  long f_xm;
-  long f_op;
-  long f_ext;
-  long f_rsvd;
-  long f_left;
-  long f_right;
-  long f_dest;
-  long f_left_right;
-  long f_tra;
-  long f_trb;
-  long f_likely;
-  long f_25;
-  long f_8_2;
-  long f_imm6;
-  long f_imm10;
-  long f_imm16;
-  long f_uimm6;
-  long f_uimm16;
-  long f_disp6;
-  long f_disp6x32;
-  long f_disp10;
-  long f_disp10x8;
-  long f_disp10x4;
-  long f_disp10x2;
-  long f_disp16;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
-#endif /* SH_OPC_H */
diff --git a/sim/sh64/sh64-sim.h b/sim/sh64/sh64-sim.h
deleted file mode 100644
index fc3ed7add09..00000000000
--- a/sim/sh64/sh64-sim.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* collection of junk waiting time to sort out
-   Copyright (C) 2000 Free Software Foundation, Inc.
-   Contributed by Red Hat, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef SH64_SIM_H
-#define SH64_SIM_H
-
-#define GETTWI GETTSI
-#define SETTWI SETTSI
-
-
-enum {
-  ISM_COMPACT, ISM_MEDIA
-};
-
-/* Hardware/device support.  */
-extern device sh5_devices;
-
-/* FIXME: Temporary, until device support ready.  */
-struct _device { int foo; };
-
-extern IDESC * sh64_idesc_media;
-extern IDESC * sh64_idesc_compact;
-
-/* Function prototypes from sh64.c.  */
-
-BI sh64_endian (SIM_CPU *);
-VOID sh64_break (SIM_CPU *, PCADDR);
-VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
-VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
-
-SF sh64_fldi0 (SIM_CPU *);
-SF sh64_fldi1 (SIM_CPU *);
-DF sh64_fcnvsd (SIM_CPU *, SF);
-SF sh64_fcnvds (SIM_CPU *, DF);
-
-DF sh64_fabsd (SIM_CPU *, DF);
-SF sh64_fabss (SIM_CPU *, SF);
-DF sh64_faddd (SIM_CPU *, DF, DF);
-SF sh64_fadds (SIM_CPU *, SF, SF);
-DF sh64_fdivd (SIM_CPU *, DF, DF);
-SF sh64_fdivs (SIM_CPU *, SF, SF);
-DF sh64_floatld (SIM_CPU *, SF);
-SF sh64_floatls (SIM_CPU *, SF);
-DF sh64_floatqd (SIM_CPU *, DF);
-SF sh64_floatqs (SIM_CPU *, DF);
-SF sh64_fmacs(SIM_CPU *, SF, SF, SF);
-DF sh64_fmuld (SIM_CPU *, DF, DF);
-SF sh64_fmuls (SIM_CPU *, SF, SF);
-DF sh64_fnegd (SIM_CPU *, DF);
-SF sh64_fnegs (SIM_CPU *, SF);
-DF sh64_fsqrtd (SIM_CPU *, DF);
-SF sh64_fsqrts (SIM_CPU *, SF);
-DF sh64_fsubd (SIM_CPU *, DF, DF);
-SF sh64_fsubs (SIM_CPU *, SF, SF);
-SF sh64_ftrcdl (SIM_CPU *, DF);
-DF sh64_ftrcdq (SIM_CPU *, DF);
-SF sh64_ftrcsl (SIM_CPU *, SF);
-DF sh64_ftrcsq (SIM_CPU *, SF);
-VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
-
-BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
-BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
-BI sh64_fcmpges (SIM_CPU *, SF, SF);
-BI sh64_fcmpged (SIM_CPU *, DF, DF);
-BI sh64_fcmpgts (SIM_CPU *, SF, SF);
-BI sh64_fcmpgtd (SIM_CPU *, DF, DF);
-BI sh64_fcmpund (SIM_CPU *, DF, DF);
-BI sh64_fcmpuns (SIM_CPU *, SF, SF);
-
-DI sh64_nsb (SIM_CPU *, DI);
-
-#endif /* SH64_SIM_H */
diff --git a/sim/sh64/sh64.c b/sim/sh64/sh64.c
deleted file mode 100644
index 12ce3f69a66..00000000000
--- a/sim/sh64/sh64.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/* SH5 simulator support code
-   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
-   Contributed by Red Hat, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU
-#define WANT_CPU_SH64
-
-#include "sim-main.h"
-#include "sim-fpu.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-#include "gdb/callback.h"
-#include "defs-compact.h"
-
-#include "bfd.h"
-/* From include/gdb/.  */
-#include "gdb/sim-sh.h"
-
-#define SYS_exit        1
-#define	SYS_read	3
-#define SYS_write       4
-#define	SYS_open	5
-#define	SYS_close	6
-#define	SYS_lseek	19
-#define	SYS_time	23
-#define	SYS_argc	172
-#define	SYS_argnlen	173
-#define	SYS_argn	174
-
-IDESC * sh64_idesc_media;
-IDESC * sh64_idesc_compact;
-
-BI
-sh64_endian (SIM_CPU *current_cpu)
-{
-  return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
-}
-
-SF
-sh64_fldi0 (SIM_CPU *current_cpu)
-{
-  SF result;
-  sim_fpu_to32 (&result, &sim_fpu_zero);
-  return result;
-}
-
-SF
-sh64_fldi1 (SIM_CPU *current_cpu)
-{
-  SF result;
-  sim_fpu_to32 (&result, &sim_fpu_one);
-  return result;
-}
-
-DF
-sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
-{
-  DF result;
-  sim_fpu f, fres;
-
-  sim_fpu_64to (&f, drgh);
-  sim_fpu_abs (&fres, &f);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fabss(SIM_CPU *current_cpu, SF frgh)
-{
-  SF result;
-  sim_fpu f, fres;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_abs (&fres, &f);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  DF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  sim_fpu_add (&fres, &f1, &f2);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  SF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  sim_fpu_add (&fres, &f1, &f2);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-BI
-sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  return sim_fpu_is_eq (&f1, &f2);
-}
-
-BI
-sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  return sim_fpu_is_eq (&f1, &f2);
-}
-
-BI
-sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  return sim_fpu_is_ge (&f1, &f2);
-}
-
-BI
-sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  return sim_fpu_is_ge (&f1, &f2);
-}
-
-BI
-sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  return sim_fpu_is_gt (&f1, &f2);
-}
-
-BI
-sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  return sim_fpu_is_gt (&f1, &f2);
-}
-
-BI
-sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
-}
-
-BI
-sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  sim_fpu f1, f2;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh); 
-  return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
-}  
-
-SF
-sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
-{
-  union {
-    unsigned long long ll;
-    double d;
-  } f1;
-
-  union {
-    unsigned long l;
-    float f;
-  } f2;
-
-  f1.ll = drgh;
-  f2.f = (float) f1.d;
-  
-  return (SF) f2.l;
-}
-
-DF
-sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
-{
-  DF result;
-  sim_fpu f;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_to64 (&result, &f);
-  return result;
-}
-
-DF
-sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  DF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  sim_fpu_div (&fres, &f1, &f2);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  SF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  sim_fpu_div (&fres, &f1, &f2);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_floatld(SIM_CPU *current_cpu, SF frgh)
-{
-  DF result;
-  sim_fpu f;
-
-  sim_fpu_i32to (&f, frgh, sim_fpu_round_default); 
-  sim_fpu_to64 (&result, &f);
-  return result;
-}
-
-SF
-sh64_floatls(SIM_CPU *current_cpu, SF frgh)
-{
-  SF result;
-  sim_fpu f;
-
-  sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
-  sim_fpu_to32 (&result, &f);
-  return result;
-}
-
-DF
-sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
-{
-  DF result;
-  sim_fpu f;
-
-  sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
-  sim_fpu_to64 (&result, &f);
-  return result;
-}
-
-SF
-sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
-{
-  SF result;
-  sim_fpu f;
-
-  sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
-  sim_fpu_to32 (&result, &f);
-  return result;
-}
-
-SF
-sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
-{
-  SF result;
-  sim_fpu m1, m2, a1, fres;
-
-  sim_fpu_32to (&m1, fr0);
-  sim_fpu_32to (&m2, frm);
-  sim_fpu_32to (&a1, frn);
-
-  sim_fpu_mul (&fres, &m1, &m2);
-  sim_fpu_add (&fres, &fres, &a1);
-  
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  DF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  sim_fpu_mul (&fres, &f1, &f2);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  SF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  sim_fpu_mul (&fres, &f1, &f2);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
-{
-  DF result;
-  sim_fpu f1, f2;
-
-  sim_fpu_64to (&f1, drgh);
-  sim_fpu_neg (&f2, &f1);
-  sim_fpu_to64 (&result, &f2);
-  return result;
-}
-
-SF
-sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
-{
-  SF result;
-  sim_fpu f, fres;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_neg (&fres, &f);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
-{
-  DF result;
-  sim_fpu f, fres;
-
-  sim_fpu_64to (&f, drgh);
-  sim_fpu_sqrt (&fres, &f);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
-{
-  SF result;
-  sim_fpu f, fres;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_sqrt (&fres, &f);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-DF
-sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
-{
-  DF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_64to (&f1, drg);
-  sim_fpu_64to (&f2, drh);
-  sim_fpu_sub (&fres, &f1, &f2);
-  sim_fpu_to64 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
-{
-  SF result;
-  sim_fpu f1, f2, fres;
-
-  sim_fpu_32to (&f1, frg);
-  sim_fpu_32to (&f2, frh);
-  sim_fpu_sub (&fres, &f1, &f2);
-  sim_fpu_to32 (&result, &fres);
-  return result;
-}
-
-SF
-sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
-{
-  SI result;
-  sim_fpu f;
-
-  sim_fpu_64to (&f, drgh);
-  sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
-  return (SF) result;
-}
-
-SF
-sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
-{
-  SI result;
-  sim_fpu f;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
-  return (SF) result;
-}
-
-DF
-sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
-{
-  DI result;
-  sim_fpu f;
-
-  sim_fpu_64to (&f, drgh);
-  sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
-  return (DF) result;
-}
-
-DF
-sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
-{
-  DI result;
-  sim_fpu f;
-
-  sim_fpu_32to (&f, frgh);
-  sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
-  return (DF) result;
-}
-
-void
-sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
-{
-  int i, j;
-
-  for (i = 0; i < 4; i++)
-    {
-      SF result;
-      sim_fpu sum;
-      sim_fpu_32to (&sum, 0);
-
-      for (j = 0; j < 4; j++)
-	{
-	  sim_fpu f1, f2, temp;
-	  sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
-	  sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
-	  sim_fpu_mul (&temp, &f1, &f2);
-	  sim_fpu_add (&sum, &sum, &temp);
-	}
-      sim_fpu_to32 (&result, &sum);
-      sh64_h_fr_set (cpu, f + i, result);
-    }
-}
-
-/* Count the number of arguments.  */
-static int
-count_argc (cpu)
-     SIM_CPU *cpu;
-{
-  int i = 0;
-
-  if (! STATE_PROG_ARGV (CPU_STATE (cpu)))
-    return -1;
-  
-  while (STATE_PROG_ARGV (CPU_STATE (cpu)) [i] != NULL)
-    ++i;
-
-  return i;
-}
-
-/* Read a null terminated string from memory, return in a buffer */
-static char *
-fetch_str (current_cpu, pc, addr)
-     SIM_CPU *current_cpu;
-     PCADDR pc;
-     DI addr;
-{
-  char *buf;
-  int nr = 0;
-  while (sim_core_read_1 (current_cpu,
-			  pc, read_map, addr + nr) != 0)
-    nr++;
-  buf = NZALLOC (char, nr + 1);
-  sim_read (CPU_STATE (current_cpu), addr, buf, nr);
-  return buf;
-}
-
-static void
-trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
-{
-  char ch;
-  switch (trapnum)
-    {
-    case 1:
-      ch = GET_H_GRC (0);
-      sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
-      fflush (stdout);
-      break;
-    case 2:
-      sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
-      break;
-    case 34:
-      {
-	int i;
-	int ret_reg = (shmedia_abi_p) ? 2 : 0;
-	char *buf;
-	DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
-	DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
-	DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
-	
-	switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
-	  {
-	  case SYS_write:
-	    buf = zalloc (PARM3);
-	    sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
-	    SET_H_GR (ret_reg,
-		      sim_io_write (CPU_STATE (current_cpu),
-				    PARM1, buf, PARM3));
-	    zfree (buf);
-	    break;
-
-	  case SYS_lseek:
-	    SET_H_GR (ret_reg,
-		      sim_io_lseek (CPU_STATE (current_cpu),
-				    PARM1, PARM2, PARM3));
-	    break;
-	    
-	  case SYS_exit:
-	    sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
-			     NULL, pc, sim_exited, PARM1);
-	    break;
-
-	  case SYS_read:
-	    buf = zalloc (PARM3);
-	    SET_H_GR (ret_reg,
-		      sim_io_read (CPU_STATE (current_cpu),
-				   PARM1, buf, PARM3));
-	    sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
-	    zfree (buf);
-	    break;
-	    
-	  case SYS_open:
-	    buf = fetch_str (current_cpu, pc, PARM1);
-	    SET_H_GR (ret_reg,
-		      sim_io_open (CPU_STATE (current_cpu),
-				   buf, PARM2));
-	    zfree (buf);
-	    break;
-
-	  case SYS_close:
-	    SET_H_GR (ret_reg,
-		      sim_io_close (CPU_STATE (current_cpu), PARM1));
-	    break;
-
-	  case SYS_time:
-	    SET_H_GR (ret_reg, time (0));
-	    break;
-
-	  case SYS_argc:
-	    SET_H_GR (ret_reg, count_argc (current_cpu));
-	    break;
-
-	  case SYS_argnlen:
-	    if (PARM1 < count_argc (current_cpu))
-	      SET_H_GR (ret_reg,
-			strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
-	    else
-	      SET_H_GR (ret_reg, -1);
-	    break;
-
-	  case SYS_argn:
-	    if (PARM1 < count_argc (current_cpu))
-	      {
-		/* Include the NULL byte.  */
-		i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
-		sim_write (CPU_STATE (current_cpu),
-			   PARM2,
-			   STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
-			   i);
-
-		/* Just for good measure.  */
-		SET_H_GR (ret_reg, i);
-		break;
-	      }
-	    else
-	      SET_H_GR (ret_reg, -1);
-	    break;
-
-	  default:
-	    SET_H_GR (ret_reg, -1);
-	  }
-      }
-      break;
-    case 253:
-      puts ("pass");
-      exit (0);
-    case 254:
-      puts ("fail");
-      exit (1);
-    case 0xc3:
-      /* fall through.  */
-    case 255:
-      sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
-      break;
-    }
-}
-
-void
-sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
-{
-  trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
-}
-
-void
-sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
-{
-  int mach_sh5_p;
-
-  /* If this is an SH5 executable, this is SHcompact code running in
-     the SHmedia ABI.  */
-
-  mach_sh5_p =
-    (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
-
-  trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
-}
-
-DI
-sh64_nsb (SIM_CPU *current_cpu, DI rm)
-{
-  int result = 0, count;
-  UDI source = (UDI) rm;
-
-  if ((source >> 63))
-    source = ~source;
-  source <<= 1;
-
-  for (count = 32; count; count >>= 1)
-    {
-      UDI newval = source << count;
-
-      if ((newval >> count) == source)
-	{
-	  result |= count;
-	  source = newval;
-	}
-    }
-  
-  return result;
-}
-
-void
-sh64_break (SIM_CPU *current_cpu, PCADDR pc)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-  sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
-}
-
-void
-set_isa (SIM_CPU *current_cpu, int mode)
-{
-  /* Do nothing.  */
-}
-
-/* The semantic code invokes this for invalid (unrecognized) instructions.  */
-
-SEM_PC
-sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-  sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
-
-  return vpc;
-}
-
-
-/* Process an address exception.  */
-
-void
-sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
-                  unsigned int map, int nr_bytes, address_word addr,
-                  transfer_type transfer, sim_core_signals sig)
-{
-  sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
-		   transfer, sig);
-}
-
-
-/* Initialize cycle counting for an insn.
-   FIRST_P is non-zero if this is the first insn in a set of parallel
-   insns.  */
-
-void
-sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
-{
-  /* Do nothing.  */
-}
-
-void
-sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
-{
-  /* Do nothing.  */
-}
-
-/* Record the cycles computed for an insn.
-   LAST_P is non-zero if this is the last insn in a set of parallel insns,
-   and we update the total cycle count.
-   CYCLES is the cycle count of the insn.  */
-
-void
-sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
-{
-  /* Do nothing.  */
-}
-
-void
-sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
-{
-  /* Do nothing.  */
-}
-
-int
-sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
-{
-  /* Fetch general purpose registers. */
-  if (nr >= SIM_SH64_R0_REGNUM
-      && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
-      && len == 8)
-    {
-      *((unsigned64*) buf) =
-	H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
-      return len;
-    }
-
-  /* Fetch PC.  */
-  if (nr == SIM_SH64_PC_REGNUM && len == 8)
-    {
-      *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
-      return len;
-    }
-
-  /* Fetch status register (SR).  */
-  if (nr == SIM_SH64_SR_REGNUM && len == 8)
-    {
-      *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
-      return len;
-    }
-      
-  /* Fetch saved status register (SSR) and PC (SPC).  */
-  if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
-      && len == 8)
-    {
-      *((unsigned64*) buf) = 0;
-      return len;
-    }
-
-  /* Fetch target registers.  */
-  if (nr >= SIM_SH64_TR0_REGNUM
-      && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
-      && len == 8)
-    {
-      *((unsigned64*) buf) =
-	H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
-      return len;
-    }
-
-  /* Fetch floating point registers.  */
-  if (nr >= SIM_SH64_FR0_REGNUM
-      && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
-      && len == 4)
-    {
-      *((unsigned32*) buf) =
-	H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
-      return len;
-    }
-
-  /* We should never get here.  */
-  return 0;
-}
-
-int
-sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
-{
-  /* Store general purpose registers. */
-  if (nr >= SIM_SH64_R0_REGNUM
-      && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
-      && len == 8)
-    {
-      sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
-      return len;
-    }
-
-  /* Store PC.  */
-  if (nr == SIM_SH64_PC_REGNUM && len == 8)
-    {
-      unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
-      sh64_h_pc_set (cpu, new_pc);
-      return len;
-    }
-
-  /* Store status register (SR).  */
-  if (nr == SIM_SH64_SR_REGNUM && len == 8)
-    {
-      sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
-      return len;
-    }
-
-  /* Store saved status register (SSR) and PC (SPC).  */
-  if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
-    {
-      /* Do nothing.  */
-      return len;
-    }
-
-  /* Store target registers.  */
-  if (nr >= SIM_SH64_TR0_REGNUM
-      && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
-      && len == 8)
-    {
-      sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
-      return len;
-    }
-
-  /* Store floating point registers.  */
-  if (nr >= SIM_SH64_FR0_REGNUM
-      && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
-      && len == 4)
-    {
-      sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
-      return len;
-    }
-
-  /* We should never get here.  */
-  return 0;
-}
-
-void
-sh64_engine_run_full(SIM_CPU *cpu)
-{
-  if (sh64_h_ism_get (cpu) == ISM_MEDIA)
-    {
-      if (!sh64_idesc_media)
-	{
-	  sh64_media_init_idesc_table (cpu);
-	  sh64_idesc_media = CPU_IDESC (cpu);
-	}
-      else
-	CPU_IDESC (cpu) = sh64_idesc_media;
-      sh64_media_engine_run_full (cpu);
-    }
-  else
-    {
-      if (!sh64_idesc_compact)
-	{
-	  sh64_compact_init_idesc_table (cpu);
-	  sh64_idesc_compact = CPU_IDESC (cpu);
-	}
-      else
-	CPU_IDESC (cpu) = sh64_idesc_compact;
-      sh64_compact_engine_run_full (cpu);
-    }
-}
-
-void
-sh64_engine_run_fast (SIM_CPU *cpu)
-{
-  if (sh64_h_ism_get (cpu) == ISM_MEDIA)
-    {
-      if (!sh64_idesc_media)
-	{
-	  sh64_media_init_idesc_table (cpu);
-	  sh64_idesc_media = CPU_IDESC (cpu);
-	}
-      else
-	CPU_IDESC (cpu) = sh64_idesc_media;
-      sh64_media_engine_run_fast (cpu);
-    }
-  else
-    {
-      if (!sh64_idesc_compact)
-	{
-	  sh64_compact_init_idesc_table (cpu);
-	  sh64_idesc_compact = CPU_IDESC (cpu);
-	}
-      else
-	CPU_IDESC (cpu) = sh64_idesc_compact;
-      sh64_compact_engine_run_fast (cpu);
-    }
-}
-
-static void
-sh64_prepare_run (SIM_CPU *cpu)
-{
-  /* Nothing.  */
-}
-
-static const CGEN_INSN *
-sh64_get_idata (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].idata;
-}
-
-static void
-sh64_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = sh64_fetch_register;
-  CPU_REG_STORE (cpu) = sh64_store_register;
-  CPU_PC_FETCH (cpu) = sh64_h_pc_get;
-  CPU_PC_STORE (cpu) = sh64_h_pc_set;
-  CPU_GET_IDATA (cpu) = sh64_get_idata;
-  /* Only used by profiling.  0 disables it. */
-  CPU_MAX_INSNS (cpu) = 0;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
-#endif
-}
-
-static void
-shmedia_init_cpu (SIM_CPU *cpu)
-{
-  sh64_init_cpu (cpu);
-}
-
-static void
-shcompact_init_cpu (SIM_CPU *cpu)
-{ 
-  sh64_init_cpu (cpu);
-}
-
-static void
-sh64_model_init()
-{
-  /* Do nothing.  */
-}
-
-static const MODEL sh_models [] =
-{
-  { "sh2",  & sh2_mach,  MODEL_SH5, NULL, sh64_model_init },
-  { "sh3",  & sh3_mach,  MODEL_SH5, NULL, sh64_model_init },
-  { "sh3e", & sh3_mach,  MODEL_SH5, NULL, sh64_model_init },
-  { "sh4",  & sh4_mach,  MODEL_SH5, NULL, sh64_model_init },
-  { "sh5",  & sh5_mach,  MODEL_SH5, NULL, sh64_model_init },
-  { 0 }
-};
-
-static const MACH_IMP_PROPERTIES sh5_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-const MACH sh2_mach =
-{
-  "sh2", "sh2", MACH_SH5,
-  16, 16, &sh_models[0], &sh5_imp_properties,
-  shcompact_init_cpu,
-  sh64_prepare_run
-};
-
-const MACH sh3_mach =
-{
-  "sh3", "sh3", MACH_SH5,
-  16, 16, &sh_models[1], &sh5_imp_properties,
-  shcompact_init_cpu,
-  sh64_prepare_run
-};
-
-const MACH sh3e_mach =
-{
-  "sh3e", "sh3e", MACH_SH5,
-  16, 16, &sh_models[2], &sh5_imp_properties,
-  shcompact_init_cpu,
-  sh64_prepare_run
-};
-
-const MACH sh4_mach =
-{
-  "sh4", "sh4", MACH_SH5,
-  16, 16, &sh_models[3], &sh5_imp_properties,
-  shcompact_init_cpu,
-  sh64_prepare_run
-};
-
-const MACH sh5_mach =
-{
-  "sh5", "sh5", MACH_SH5,
-  32, 32, &sh_models[4], &sh5_imp_properties,
-  shmedia_init_cpu,
-  sh64_prepare_run
-};
diff --git a/sim/sh64/sim-if.c b/sim/sh64/sim-if.c
deleted file mode 100644
index f34ff29065e..00000000000
--- a/sim/sh64/sim-if.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Main simulator entry points specific to the SH5.
-   Copyright (C) 2000 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "libiberty.h"
-#include "bfd.h"
-#include "sim-main.h"
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#include "sim-options.h"
-#include "dis-asm.h"
-
-static void free_state (SIM_DESC);
-
-/* Since we don't build the cgen-opcode table, we use a wrapper around
-   the existing disassembler from libopcodes. */
-static CGEN_DISASSEMBLER sh64_disassemble_insn;
-
-/* Records simulator descriptor so utilities like sh5_dump_regs can be
-   called from gdb.  */
-SIM_DESC current_state;
-
-/* Cover function of sim_state_free to free the cpu buffers as well.  */
-
-static void
-free_state (SIM_DESC sd)
-{
-  if (STATE_MODULES (sd) != NULL)
-    sim_module_uninstall (sd);
-  sim_cpu_free_all (sd);
-  sim_state_free (sd);
-}
-
-/* Create an instance of the simulator.  */
-
-SIM_DESC
-sim_open (kind, callback, abfd, argv)
-     SIM_OPEN_KIND kind;
-     host_callback *callback;
-     struct bfd *abfd;
-     char **argv;
-{
-  char c;
-  int i;
-  SIM_DESC sd = sim_state_alloc (kind, callback);
-
-  /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#if 0 /* FIXME: pc is in mach-specific struct */
-  /* FIXME: watchpoints code shouldn't need this */
-  {
-    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-    STATE_WATCHPOINTS (sd)->pc = &(PC);
-    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
-  }
-#endif
-
-  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#if 0 /* FIXME: 'twould be nice if we could do this */
-  /* These options override any module options.
-     Obviously ambiguity should be avoided, however the caller may wish to
-     augment the meaning of an option.  */
-  if (extra_options != NULL)
-    sim_add_option_table (sd, extra_options);
-#endif
-
-  /* getopt will print the error message so we just have to exit if this fails.
-     FIXME: Hmmm...  in the case of gdb we need getopt to call
-     print_filtered.  */
-  if (sim_parse_args (sd, argv) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Allocate core managed memory if none specified by user.
-     Use address 4 here in case the user wanted address 0 unmapped.  */
-  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
-    sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE);
-
-  /* Add a small memory region way up in the address space to handle
-     writes to invalidate an instruction cache line.  This is used for
-     trampolines.  Since we don't simulate the cache, this memory just
-     avoids bus errors.  64K ought to do. */
-  sim_do_command (sd," memory region 0xf0000000,0x10000");
-
-  /* check for/establish the reference program image */
-  if (sim_analyze_program (sd,
-			   (STATE_PROG_ARGV (sd) != NULL
-			    ? *STATE_PROG_ARGV (sd)
-			    : NULL),
-			   abfd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Establish any remaining configuration options.  */
-  if (sim_config (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  if (sim_post_argv_init (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Open a copy of the cpu descriptor table.  */
-  {
-    CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
-					      CGEN_ENDIAN_BIG);
-
-    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
-      {
-	SIM_CPU *cpu = STATE_CPU (sd, i);
-	CPU_CPU_DESC (cpu) = cd;
-	CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn;
-      }
-  }
-
-  /* Clear idesc table pointers for good measure. */
-  sh64_idesc_media = sh64_idesc_compact = NULL;
-
-  /* Initialize various cgen things not done by common framework.
-     Must be done after sh_cgen_cpu_open.  */
-  cgen_init (sd);
-
-  /* Store in a global so things like sparc32_dump_regs can be invoked
-     from the gdb command line.  */
-  current_state = sd;
-
-  return sd;
-}
-
-void
-sim_close (sd, quitting)
-     SIM_DESC sd;
-     int quitting;
-{
-  sh_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
-  sim_module_uninstall (sd);
-}
-
-SIM_RC
-sim_create_inferior (sd, abfd, argv, envp)
-     SIM_DESC sd;
-     struct bfd *abfd;
-     char **argv;
-     char **envp;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-  SIM_ADDR addr;
-
-  if (abfd != NULL)
-    addr = bfd_get_start_address (abfd);
-  else
-    addr = 0;
-  sim_pc_set (current_cpu, addr);
-
-#if 0
-  STATE_ARGV (sd) = sim_copy_argv (argv);
-  STATE_ENVP (sd) = sim_copy_argv (envp);
-#endif
-
-  return SIM_RC_OK;
-}
-
-void
-sim_do_command (sd, cmd)
-     SIM_DESC sd;
-     char *cmd;
-{ 
-  if (sim_args_command (sd, cmd) != SIM_RC_OK)
-    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
-}
-
-
-/* Disassemble an instruction.  */
-
-static void
-sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
-                       const ARGBUF *abuf, IADDR pc, char *buf)
-{
-  struct disassemble_info disasm_info;
-  SFILE sfile;
-  SIM_DESC sd = CPU_STATE (cpu);
-
-  sfile.buffer = sfile.current = buf;
-  INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
-                         (fprintf_ftype) sim_disasm_sprintf);
-
-  disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd));
-  disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd));
-  disasm_info.endian =
-    (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
-     : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
-     : BFD_ENDIAN_UNKNOWN);
-  disasm_info.read_memory_func = sim_disasm_read_memory;
-  disasm_info.memory_error_func = sim_disasm_perror_memory;
-  disasm_info.application_data = (PTR) cpu;
-
-  if (sh64_h_ism_get (cpu) == ISM_MEDIA)
-    print_insn_sh64x_media (pc, &disasm_info);
-  else
-    print_insn_sh (pc, &disasm_info);
-}
diff --git a/sim/sh64/sim-main.h b/sim/sh64/sim-main.h
deleted file mode 100644
index e7cbe99217a..00000000000
--- a/sim/sh64/sim-main.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Main header for the Hitachi SH64 architecture.  */
-
-#ifndef SIM_MAIN_H
-#define SIM_MAIN_H
-
-#define USING_SIM_BASE_H /* FIXME: quick hack */
-
-struct _sim_cpu; /* FIXME: should be in sim-basics.h */
-typedef struct _sim_cpu SIM_CPU;
-
-/* sim-basics.h includes config.h but cgen-types.h must be included before
-   sim-basics.h and cgen-types.h needs config.h.  */
-#include "config.h"
-
-#include "symcat.h"
-#include "sim-basics.h"
-#include "cgen-types.h"
-#include "sh-desc.h"
-#include "sh-opc.h"
-#include "arch.h"
-
-/* These must be defined before sim-base.h.  */
-typedef UDI sim_cia;
-
-#define CIA_GET(cpu)     CPU_PC_GET (cpu)
-#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val) | (sh64_h_ism_get (cpu)))
-
-#include "sim-base.h"
-#include "cgen-sim.h"
-#include "sh64-sim.h"
-
-/* The _sim_cpu struct.  */
-
-struct _sim_cpu {
-  /* sim/common cpu base.  */
-  sim_cpu_base base;
-
-  /* Static parts of cgen.  */
-  CGEN_CPU cgen_cpu;
-
-  /* CPU specific parts go here.
-     Note that in files that don't need to access these pieces WANT_CPU_FOO
-     won't be defined and thus these parts won't appear.  This is ok in the
-     sense that things work.  It is a source of bugs though.
-     One has to of course be careful to not take the size of this
-     struct and no structure members accessed in non-cpu specific files can
-     go after here.  Oh for a better language.  */
-#if defined (WANT_CPU_SH64)
-  SH64_CPU_DATA cpu_data;
-#endif
-};
-
-/* The sim_state struct.  */
-
-struct sim_state {
-  sim_cpu *cpu;
-#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
-
-  CGEN_STATE cgen_state;
-
-  sim_state_base base;
-};
-
-/* Misc.  */
-
-/* Catch address exceptions.  */
-extern SIM_CORE_SIGNAL_FN sh64_core_signal;
-#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
-sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
-		  (TRANSFER), (ERROR))
-
-/* Default memory size.  */
-#define SH64_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-
-#endif /* SIM_MAIN_H */
diff --git a/sim/sh64/tconfig.in b/sim/sh64/tconfig.in
deleted file mode 100644
index bab3f1ce7ed..00000000000
--- a/sim/sh64/tconfig.in
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SH64 target configuration file.  -*- C -*- */
-
-/* Define this if the simulator can vary the size of memory.
-   See the xxx simulator for an example.
-   This enables the `-m size' option.
-   The memory size is stored in STATE_MEM_SIZE.  */
-/* Not used for SH64 since we use the memory module. TODO -- check this  */
-/* #define SIM_HAVE_MEM_SIZE */
-
-/* See sim-hload.c.  We properly handle LMA. -- TODO: check this */
-#define SIM_HANDLES_LMA 1
-
-/* For MSPR support.  FIXME: revisit.  */
-#define WITH_DEVICES 0
-
-/* FIXME: Revisit.  */
-#ifdef HAVE_DV_SOCKSER
-MODULE_INSTALL_FN dv_sockser_install;
-#define MODULE_LIST dv_sockser_install,
-#endif
-
-#if 0
-/* Enable watchpoints.  */
-#define WITH_WATCHPOINTS 1
-#endif
-
-/* ??? Temporary hack until model support unified.  */
-#define SIM_HAVE_MODEL
-
-/* Define this to enable the intrinsic breakpoint mechanism. */
-/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
-   duplicates ifdef SIM_BREAKPOINT (right?) */
-#if 1
-#define SIM_HAVE_BREAKPOINTS
-#define SIM_BREAKPOINT { 0, 0, 0, 0xD }
-#define SIM_BREAKPOINT_SIZE 4
-#endif
-
-/* This is a global setting.  Different cpu families can't mix-n-match -scache
-   and -pbb.  However some cpu families may use -simple while others use
-   one of -scache/-pbb. ???? */
-#define WITH_SCACHE_PBB 1
-
-/* Define this if the target cpu is bi-endian and the simulator supports it.  */
-#define SIM_HAVE_BIENDIAN
diff --git a/sim/testsuite/sim/sh64/ChangeLog b/sim/testsuite/sim/sh64/ChangeLog
deleted file mode 100644
index 8bb2f764ae6..00000000000
--- a/sim/testsuite/sim/sh64/ChangeLog
+++ /dev/null
@@ -1,21 +0,0 @@
-2001-01-06  Ben Elliston  <bje@redhat.com>
-
-	* misc/fr-dr.s: New test.
-
-2001-01-03  Ben Elliston  <bje@redhat.com>
-
-	* interwork.exp: Match .s files only.
-
-2000-12-06  Ben Elliston  <bje@redhat.com>
-
-	* interwork.exp: New test case.
-
-2000-11-16  Ben Elliston  <bje@redhat.com>
-
-	* allinsn.exp: Rename from this ..
-	* compact.exp: .. to this.
-	* media.exp: New test case.
-
-2000-11-13  Ben Elliston  <bje@redhat.com>
-
-	* allinsn.exp: New test case.
diff --git a/sim/testsuite/sim/sh64/compact.exp b/sim/testsuite/sim/sh64/compact.exp
deleted file mode 100644
index d3d482acf0f..00000000000
--- a/sim/testsuite/sim/sh64/compact.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# SHcompact testsuite.
-
-if [istarget sh64-*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "sh5"
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] {
-       # If we're only testing specific files and this isn't one of them,
-       # skip it.
-       if ![runtest_file_p $runtests $src] {
-  	  continue
-	}
-    run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/sh64/compact/ChangeLog b/sim/testsuite/sim/sh64/compact/ChangeLog
deleted file mode 100644
index 99aaec1ff02..00000000000
--- a/sim/testsuite/sim/sh64/compact/ChangeLog
+++ /dev/null
@@ -1,26 +0,0 @@
-2002-01-09  Ben Elliston  <bje@redhat.com>
-
-	* macl.cgs: For good measure, clear the S bit at startup.
-
-2001-01-11  Ben Elliston  <bje@redhat.com>
-
-	* fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that
-	the source register was correctly post-incremented.
-
-2000-12-01  Ben Elliston  <bje@redhat.com>
-
-	* *.cgs (ld): Link tests with -m shelf32.
-
-2000-11-24  Ben Elliston  <bje@redhat.com>
-
-	* fmov.cgs: New test case.
-	* ftrv.cgs: Populate the matrix with meaningful values.
-
-2000-11-22  Ben Elliston  <bje@redhat.com>
-
-	* *.cgs (as): Assemble tests with -isa=shcompact.
-
-2000-11-16  Ben Elliston  <bje@redhat.com>
-
-	* *.cgs: New test cases.
-
diff --git a/sim/testsuite/sim/sh64/compact/add.cgs b/sim/testsuite/sim/sh64/compact/add.cgs
deleted file mode 100644
index 105e4849069..00000000000
--- a/sim/testsuite/sim/sh64/compact/add.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for add $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-init:
-	# Initialise some registers with values which help us to verify
-	# that the correct source registers are used by the ADD instruction.
-	mov #0, r0
-	mov #1, r1
-	mov #2, r2
-	mov #3, r3
-	mov #5, r5
-	mov #15, r15
-
-add:	
-	# 0 + 0 = 0.
-	add r0, r0
-	assert r0, #0
-
-	# 0 + 1 = 1.
-	add r0, r1
-	assert r1, #1
-
-	# 1 + 2 = 3.
-	add r1, r2
-	assert r2, #3
-
-	# 3 + 5 = 8.
-	add r3, r5
-	assert r5, #8
-	
-	# 8 + 8 = 16.
-	add r5, r5
-	assert r5, #16
-
-	# 15 + 1 = 16.
-	add r15, r1
-	assert r1, #16
-
-neg:
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	add r0, r1
-	assert r1, #1
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/addc.cgs b/sim/testsuite/sim/sh64/compact/addc.cgs
deleted file mode 100644
index f6e46e1a969..00000000000
--- a/sim/testsuite/sim/sh64/compact/addc.cgs
+++ /dev/null
@@ -1,90 +0,0 @@
-# sh testcase for addc $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	# Initialise some registers with values which help us to verify
-	# that the correct source registers are used by the ADDC instruction.
-
-	.macro init
-	mov #0, r0
-	mov #1, r1
-	mov #2, r2
-	mov #3, r3
-	mov #5, r5
-	mov #15, r15
-	.endm
-	
-	start
-
-	init
-add:
-	clrt
-	addc r0, r0
-	assert r0, #0
-	clrt
-	addc r0, r1
-	assert r1, #1
-	clrt
-	addc r1, r2
-	assert r2, #3
-	clrt
-	addc r3, r5
-	assert r5, #8
-	clrt
-	addc r5, r5
-	assert r5, #16
-	clrt
-	addc r15, r1
-	assert r1, #16
-
-	init
-addt:
-	sett
-	addc r0, r0
-	assert r0, #1
-	sett
-	addc r0, r1
-	assert r1, #3
-	sett
-	addc r1, r2
-	assert r2, #6
-	sett
-	addc r3, r5
-	assert r5, #9
-	sett
-	addc r5, r5
-	assert r5, #19
-	sett
-	addc r15, r1
-	assert r1, #19
-
-	bra next
-	nop
-
-wrong:
-	fail
-
-next:
-	init
-large:
-	clrt
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	addc r0, r1
-	assert r1, #1
-
-	init
-larget:
-	sett
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	addc r0, r1
-	assert r1, #2
-
-okay:	
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/addi.cgs b/sim/testsuite/sim/sh64/compact/addi.cgs
deleted file mode 100644
index 7c96ddf76d5..00000000000
--- a/sim/testsuite/sim/sh64/compact/addi.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for add #$imm8, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-init:
-	# Initialise some registers with values which help us to verify
-	# that the correct source registers are used by the ADD instruction.
-	mov #0, r0
-	mov #1, r1
-	mov #2, r2
-	mov #3, r3
-	mov #5, r5
-	mov #15, r15
-
-addi:
-	# 0 + 0 = 0.
-	add #0, r0
-	assert r0, #0
-
-	# 0 + 1 = 1.
-	add #0, r1
-	assert r1, #1
-
-	# 2 + 2 = 4.
-	add #2, r2
-	assert r2, #4
-
-	# 120 + 5 = 125.
-	add #120, r5
-	assert r5, #125
-
-large:
-	mov #1, r0
-	neg r0, r0
-	add #2, r0
-	assert r0, #1
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/addv.cgs b/sim/testsuite/sim/sh64/compact/addv.cgs
deleted file mode 100644
index 0267e5dfa00..00000000000
--- a/sim/testsuite/sim/sh64/compact/addv.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for addv $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-zero:
-	mov #0, r0
-	mov #0, r1
-	addv r0, r1
-	# Assert !T and #0.
-	bt wrong
-	assert r1, #0
-
-one:
-	mov #0, r0
-	mov #1, r1
-	addv r0, r1
-	# Assert !T and #1.
-	bt wrong
-	assert r1, #1
-
-large:
-	# Produce MAXINT in R0.
-	mov #0, r0
-	not r0, r0
-	shlr r0
-
-	# Put #3 into R1.
-	mov #3, r1
-
-	# Add them and overflow.
-	addv r0, r1
-
-	# Assert T and overflowed value.
-	bf wrong
-	mov #1, r7
-	rotr r7
-	add #2, r7
-	cmp/eq r1, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/and.cgs b/sim/testsuite/sim/sh64/compact/and.cgs
deleted file mode 100644
index e1452752ae0..00000000000
--- a/sim/testsuite/sim/sh64/compact/and.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# sh testcase for and $rm64, $rn64 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global and
-and:
-	mov #1, r1
-	mov #7, r2
-	rotr r2
-	rotr r2
-	and r1, r2
-
-	# R1 & R2 = 1.
-	assert r2, #1
-
-another:
-	mov #192, r1
-	mov #0, r2
-	and r1, r2
-
-	# R1 & R2 = 0.
-	assert r2, #0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/andb.cgs b/sim/testsuite/sim/sh64/compact/andb.cgs
deleted file mode 100644
index 77e628598b1..00000000000
--- a/sim/testsuite/sim/sh64/compact/andb.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global orb
-init:
-	# Init GBR and R0.
-	mov #30, r0
-	ldc r0, gbr	
-	mov #40, r0
-
-orb:
-	and.b #255, @(r0, gbr)
-	and.b #170, @(r0, gbr)
-	and.b #255, @(r0, gbr)
-	and.b #0, @(r0, gbr)
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/andi.cgs b/sim/testsuite/sim/sh64/compact/andi.cgs
deleted file mode 100644
index 32d71c5b477..00000000000
--- a/sim/testsuite/sim/sh64/compact/andi.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for and #$imm8, r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global andi
-andi:
-	mov #0, r0
-	or #255, r0
-	and #0, r0
-	assert r0, #0
-
-large:
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-
-mask:
-	and #255, r0
-	mov r0, r1
-	mov #0, r0
-	or #255, r0
-	cmp/eq r0, r1
-	bf wrong
-
-mask0:
-	and #0, r0
-	assert r0, #0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bf.cgs b/sim/testsuite/sim/sh64/compact/bf.cgs
deleted file mode 100644
index 5c361f94b89..00000000000
--- a/sim/testsuite/sim/sh64/compact/bf.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for bf $disp8 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global taken
-taken:
-	clrt
-	bf ntaken
-	fail
-	.global ntaken
-ntaken:
-	sett
-	bf bad
-	pass
-bad:
-	fail
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bfs.cgs b/sim/testsuite/sim/sh64/compact/bfs.cgs
deleted file mode 100644
index 3cad5f6fc73..00000000000
--- a/sim/testsuite/sim/sh64/compact/bfs.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for bf/s $disp8 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global taken
-taken:
-	clrt
-	bf/s ntaken
-slot1:
-	nop
-	fail
-	.global ntaken
-ntaken:
-	sett
-	bf/s bad
-slot2:
-	nop
-	pass
-bad:
-	fail
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bra.cgs b/sim/testsuite/sim/sh64/compact/bra.cgs
deleted file mode 100644
index 77c6da9bdde..00000000000
--- a/sim/testsuite/sim/sh64/compact/bra.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for bra $disp12 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global bra
-bra:
-	bra okay
-slot:
-	nop
-bad:
-	fail
-	fail
-	fail
-	.global okay
-okay:
-	pass
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/braf.cgs b/sim/testsuite/sim/sh64/compact/braf.cgs
deleted file mode 100644
index e761f6d0a6d..00000000000
--- a/sim/testsuite/sim/sh64/compact/braf.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for braf $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global braf
-braf:
-	mov #4, r0
-	braf r0
-slot:
-	nop
-bad:
-	fail
-	fail
-okay:
-	pass
-alsobad:
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/brk.cgs b/sim/testsuite/sim/sh64/compact/brk.cgs
deleted file mode 100644
index 99080724565..00000000000
--- a/sim/testsuite/sim/sh64/compact/brk.cgs
+++ /dev/null
@@ -1,18 +0,0 @@
-# sh testcase for brk -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	.global brk
-brk:
-	# If we hit the breakpoint, the sim will stop.
-	pass
-
-	# FIXME: breakpoint instruction.
-	# The SH4 assembler doesn't know about "brk".
-	.word 0x003b
-bad:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bsr.cgs b/sim/testsuite/sim/sh64/compact/bsr.cgs
deleted file mode 100644
index 75a1a2b275e..00000000000
--- a/sim/testsuite/sim/sh64/compact/bsr.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for bsr $disp12 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global bsr
-bsr:
-	bsr okay
-slot:
-	nop
-bad:
-	fail
-	fail
-okay:
-	pass
-alsobad:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bsrf.cgs b/sim/testsuite/sim/sh64/compact/bsrf.cgs
deleted file mode 100644
index 9360eaa88b0..00000000000
--- a/sim/testsuite/sim/sh64/compact/bsrf.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for bsrf $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-bsrf:
-	mov #4, r0
-	bsrf r0
-slot:
-	nop
-bad:
-	fail
-	fail
-okay:
-	pass
-alsobad:
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bt.cgs b/sim/testsuite/sim/sh64/compact/bt.cgs
deleted file mode 100644
index 65b9d61b885..00000000000
--- a/sim/testsuite/sim/sh64/compact/bt.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for bt $disp8
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global taken
-taken:
-	sett
-	bt ntaken
-	fail
-	.global ntaken
-ntaken:
-	clrt
-	bt bad
-	pass
-bad:
-	fail
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/bts.cgs b/sim/testsuite/sim/sh64/compact/bts.cgs
deleted file mode 100644
index 3d62e4d822c..00000000000
--- a/sim/testsuite/sim/sh64/compact/bts.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for bt/s $disp8 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global taken
-taken:
-	sett
-	bt/s ntaken
-slot1:
-	nop
-	fail
-	.global ntaken
-ntaken:
-	clrt
-	bt/s bad
-slot2:
-	nop
-	pass
-bad:
-	fail
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/clrmac.cgs b/sim/testsuite/sim/sh64/compact/clrmac.cgs
deleted file mode 100644
index 482dc804d62..00000000000
--- a/sim/testsuite/sim/sh64/compact/clrmac.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for clrmac -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global clrmac
-clrmac:
-	clrmac
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/clrs.cgs b/sim/testsuite/sim/sh64/compact/clrs.cgs
deleted file mode 100644
index bed5fd5178e..00000000000
--- a/sim/testsuite/sim/sh64/compact/clrs.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for clrs -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global clrs
-clrs:
-	clrs
-	# Somehow ensure that S is set.
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/clrt.cgs b/sim/testsuite/sim/sh64/compact/clrt.cgs
deleted file mode 100644
index 281c2f4243d..00000000000
--- a/sim/testsuite/sim/sh64/compact/clrt.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# sh testcase for clrt -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global clrt
-clrt:
-	clrt
-	bt wrong
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmpeq.cgs b/sim/testsuite/sim/sh64/compact/cmpeq.cgs
deleted file mode 100644
index 3cc744cf7f7..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmpeq.cgs
+++ /dev/null
@@ -1,52 +0,0 @@
-# sh testcase for cmp/eq $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zeroes:
-	mov #0, r1
-	mov #0, r2
-	cmp/eq r1, r2
-	bf wrong
-
-zero1:
-	mov #0, r1
-	mov #1, r2
-	cmp/eq r1, r2
-	bt wrong
-	
-zero2:
-	mov #0, r2
-	mov #1, r1
-	cmp/eq r2, r1
-	bt wrong
-	
-equal:
-	mov #192, r1
-	mov #192, r2
-	cmp/eq r1, r2
-	bf wrong
-	
-noteq:
-	mov #192, r1
-	mov #193, r2
-	cmp/eq r1, r2
-	bt wrong
-	
-large:
-	mov #1, r1
-	rotr r1
-	mov #1, r2
-	rotr r2
-	cmp/eq r1, r2
-	bf wrong
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs
deleted file mode 100644
index 79900a0cecc..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zeroes:
-	mov #0, r0
-	cmp/eq #0, r0
-	bf wrong
-	
-zero1:
-	mov #0, r0
-	cmp/eq #1, r0
-	bt wrong
-	
-zero2:
-	mov #1, r0
-	cmp/eq #0, r0
-	bt wrong
-	
-equal:
-	mov #192, r0
-	cmp/eq #192, r0
-	bf wrong
-	
-sign:
-	mov #255, r0
-	cmp/eq #255, r0
-	bf wrong
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmpge.cgs b/sim/testsuite/sim/sh64/compact/cmpge.cgs
deleted file mode 100644
index 9d4327e35cc..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmpge.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# sh testcase for cmp/ge $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	mov #0, r1
-	cmp/ge r0, r1
-	bf wrong
-
-onezero:
-	mov #1, r0
-	mov #0, r1
-	cmp/ge r0, r1
-	bt wrong
-
-zeroone:
-	mov #0, r0
-	mov #1, r1
-	cmp/ge r0, r1
-	bf wrong
-
-equal:
-	mov #192, r0
-	mov #192, r1
-	cmp/ge r0, r1
-	bf wrong
-
-eqlarge:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	mov #1, r1
-	rotr r1
-	add #85, r1
-	cmp/ge r0, r1
-	bf wrong
-
-large2:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	mov #1, r1
-	rotr r1
-	add #84, r1
-	cmp/ge r0, r1
-	bt wrong
-
-large3:
-	mov #1, r0
-	rotr r0
-	add #84, r0
-	mov #1, r1
-	rotr r1
-	add #85, r1
-	cmp/ge r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/cmpgt.cgs b/sim/testsuite/sim/sh64/compact/cmpgt.cgs
deleted file mode 100644
index 460ca65ae68..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmpgt.cgs
+++ /dev/null
@@ -1,69 +0,0 @@
-# sh testcase for cmp/gt $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	mov #0, r1
-	cmp/gt r0, r1
-	bt wrong
-
-onezero:
-	mov #1, r0
-	mov #0, r1
-	cmp/gt r0, r1
-	bt wrong
-
-zeroone:
-	mov #0, r0
-	mov #1, r1
-	cmp/gt r0, r1
-	bf wrong
-	
-equal:
-	mov #192, r0
-	mov #192, r1
-	cmp/gt r0, r1
-	bt wrong
-
-eqlarge:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	mov #1, r1
-	rotr r1
-	add #85, r1
-	cmp/gt r0, r1
-	bt wrong
-	
-large2:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	mov #1, r1
-	rotr r1
-	add #84, r1
-	cmp/gt r0, r1
-	bt wrong
-
-large3:
-	mov #1, r0
-	rotr r0
-	add #84, r0
-	mov #1, r1
-	rotr r1
-	add #85, r1
-	cmp/gt r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/cmphi.cgs b/sim/testsuite/sim/sh64/compact/cmphi.cgs
deleted file mode 100644
index efbcaa328cd..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmphi.cgs
+++ /dev/null
@@ -1,68 +0,0 @@
-# sh testcase for cmp/hi $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	mov #0, r0
-	cmp/hi r0, r1
-	bt wrong
-
-equal:
-	mov #1, r0
-	rotr r0
-	add #3, r0
-
-	mov #1, r1
-	rotr r1
-	add #3, r1
-
-	cmp/hi r0, r1
-	bt wrong
-
-gt:
-	mov #10, r0
-	mov #12, r1
-	cmp/hi r0, r1
-	bf wrong
-
-lt:
-	mov #12, r0
-	mov #10, r1
-	cmp/hi r0, r1
-	bt wrong
-
-gtneg:
-	mov #1, r0
-	rotr r0
-	add #1, r0
-
-	mov #1, r1
-	rotr r1
-	add #3, r1
-
-	cmp/hi r0, r1
-	bf wrong
-
-ltneg:
-	mov #1, r0
-	rotr r0
-	add #3, r0
-	
-	mov #1, r1
-	rotr r1
-	add #1, r1
-
-	cmp/hi r0, r1
-	bt wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmphs.cgs b/sim/testsuite/sim/sh64/compact/cmphs.cgs
deleted file mode 100644
index 957f80c0245..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmphs.cgs
+++ /dev/null
@@ -1,59 +0,0 @@
-# sh testcase for cmp/hs $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	mov #0, r0
-	cmp/hs r0, r1
-
-equal:
-	mov #1, r0
-	rotr r0
-	add #3, r0
-
-	mov #1, r1
-	rotr r1
-	add #3, r1
-
-	cmp/hs r0, r1
-
-gt:
-	mov #10, r0
-	mov #12, r1
-	cmp/hs r0, r1
-
-lt:
-	mov #12, r0
-	mov #10, r1
-	cmp/hs r0, r1
-
-gtneg:
-	mov #1, r0
-	rotr r0
-	add #1, r0
-
-	mov #1, r1
-	rotr r1
-	add #3, r1
-
-	cmp/hs r0, r1
-
-ltneg:
-	mov #1, r0
-	rotr r0
-	add #3, r0
-	
-	mov #1, r1
-	rotr r1
-	add #1, r1
-
-	cmp/hs r0, r1
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/cmppl.cgs b/sim/testsuite/sim/sh64/compact/cmppl.cgs
deleted file mode 100644
index 1c11377f34b..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmppl.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for cmp/pl $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	cmp/pl r0
-	bt wrong
-
-plus:
-	mov #10, r0
-	cmp/pl r0
-	bf wrong
-
-minus:
-	mov #10, r0
-	neg r0, r0
-	cmp/pl r0
-	bt wrong
-
-large:
-	mov #10, r0
-	shll8 r0
-	add #123, r0
-	cmp/pl r0
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmppz.cgs b/sim/testsuite/sim/sh64/compact/cmppz.cgs
deleted file mode 100644
index 2e0bf48e827..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmppz.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for cmp/pz $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-zero:
-	mov #0, r0
-	cmp/pz r0
-	bf wrong
-
-plus:
-	mov #10, r0
-	cmp/pz r0
-	bf wrong
-
-minus:
-	mov #10, r0
-	neg r0, r0
-	cmp/pz r0
-	bt wrong
-
-large:
-	mov #10, r0
-	shll8 r0
-	add #123, r0
-	cmp/pz r0
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/cmpstr.cgs b/sim/testsuite/sim/sh64/compact/cmpstr.cgs
deleted file mode 100644
index 70d90d33c20..00000000000
--- a/sim/testsuite/sim/sh64/compact/cmpstr.cgs
+++ /dev/null
@@ -1,148 +0,0 @@
-# sh testcase for cmp/str $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-.macro rot8
-	rotr r0
-	rotr r0
-	rotr r0
-	rotr r0
-	rotr r0
-	rotr r0
-	rotr r0
-	rotr r0
-.endm
-
-	start
-
-# Use multiple "wrong" labels because this program is quite long. It's
-# likely that some instructions will be too far away from the branch
-# target to use PC-relative branches.
-	
-match0:
-	# No bytes matching.
-	mov #1, r0
-	neg r0, r0
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	mov r0, r1
-	mov #1, r0
-	neg r0, r0
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	cmp/str r0, r1
-	bt wrong0
-
-	bra match1
-	nop
-wrong0:
-	fail
-
-match1:
-	# One byte matching.
-	mov #1, r0
-	neg r0, r0
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	mov r0, r1
-	mov #1, r0
-	neg r0, r0
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	cmp/str r0, r1
-	bf wrong1
-
-	bra match2
-	nop
-wrong1:
-	fail
-
-match2:
-	# Two bytes matching.
-	mov #1, r0
-	neg r0, r0
-	xor #170, r0
-	rot8
-	xor #170, r0
-	rot8
-	mov r0, r1
-	mov #1, r0
-	neg r0, r0
-	xor #85, r0
-	rot8
-	xor #85, r0
-	rot8
-	cmp/str r0, r1
-	bf wrong2
-
-	bra match3
-	nop
-wrong2:
-	fail
-	
-byte0:
-match3:
-	# One byte matching.
-	# This is also the test for byte 0.
-	mov #85, r0
-	mov #85, r1
-	cmp/str r0, r1
-	bf wrong3
-
-byte1:
-	# Match in byte position 1.
-	mov #85, r0
-	shll8 r0
-	mov #85, r1
-	shll8 r1
-	cmp/str r0, r1
-	bf wrong3
-
-byte2:
-	# Match in byte position 2.
-	mov #85, r0
-	shll16 r0
-	mov #85, r1
-	shll16 r1
-	cmp/str r0, r1
-	bf wrong3
-
-byte3:
-	# Match in byte position 3.
-	mov #85, r0
-	shll16 r0
-	shll8 r0
-	mov #85, r1
-	shll16 r1
-	shll8 r1
-	cmp/str r0, r1
-	bf wrong3
-
-okay:
-	pass
-wrong3:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/div0s.cgs b/sim/testsuite/sim/sh64/compact/div0s.cgs
deleted file mode 100644
index 8cd6422bea8..00000000000
--- a/sim/testsuite/sim/sh64/compact/div0s.cgs
+++ /dev/null
@@ -1,52 +0,0 @@
-# sh testcase for div0s $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-init:
-	mov #0, r0
-	mov #3, r1
-	mov #4, r2
-	neg r1, r3
-	neg r2, r4
-
-perm1:
-	div0s r0, r0
-	bt wrong
-	div0s r0, r1
-	bt wrong
-	div0s r1, r0
-	bt wrong
-
-perm2:
-	div0s r0, r4
-	bf wrong
-	div0s r4, r0
-	bf wrong
-
-perm3:
-	div0s r1, r2
-	bt wrong
-	div0s r2, r1
-	bt wrong
-
-perm4:
-	div0s r3, r4
-	bt wrong
-	div0s r4, r3
-	bt wrong
-
-perm5:
-	div0s r1, r1
-	bt wrong
-	div0s r3, r3
-	bt wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/div0u.cgs b/sim/testsuite/sim/sh64/compact/div0u.cgs
deleted file mode 100644
index 02f8534d4c4..00000000000
--- a/sim/testsuite/sim/sh64/compact/div0u.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for div0u -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global div0u
-div0u:
-	div0u
-	# Can't easily test Q and M (other than visually inspecting
-	# the simulator's trace output).
-	bt wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/div1.cgs b/sim/testsuite/sim/sh64/compact/div1.cgs
deleted file mode 100644
index 63a0e81cb12..00000000000
--- a/sim/testsuite/sim/sh64/compact/div1.cgs
+++ /dev/null
@@ -1,52 +0,0 @@
-# sh testcase for div1 $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #10, r0
-	mov #2, r1
-	div0s r0,r1
-
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-	div1 r0, r1
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/dmulsl.cgs b/sim/testsuite/sim/sh64/compact/dmulsl.cgs
deleted file mode 100644
index 081ce169955..00000000000
--- a/sim/testsuite/sim/sh64/compact/dmulsl.cgs
+++ /dev/null
@@ -1,115 +0,0 @@
-# sh testcase for dmuls.l $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #0, r0
-	mov #0, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #0
-
-test2:	
-	mov #0, r0
-	mov #5, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #0
-
-test3:	
-	mov #5, r0
-	mov #0, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #0
-
-test4:	
-	mov #1, r0
-	mov #5, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #5
-
-test5:	
-	mov #5, r0
-	mov #1, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #5
-
-	bra test6
-	nop
-
-wrong:
-	fail
-
-test6:	
-	mov #2, r0
-	mov #2, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #4
-
-test7:	
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-
-	mov #0, r8
-	not r8, r9
-	not r8, r10
-	shll r10
-	cmp/eq r3, r9
-	bf wrong
-	cmp/eq r4, r10
-	bf wrong
-
-test8:	
-	mov #1, r0
-	neg r0, r0
-	mov #1, r1
-	neg r1, r1
-	dmuls.l r0, r1
-	# check result
-	sts mach, r3
-	sts macl, r4
-	assert r3, #0
-	assert r4, #1
-
-test9:	
-	mov #1, r0
-	neg r0, r0
-	shlr r0
-	mov #1, r1
-	neg r1, r1
-	shlr r1
-	dmuls.l r0, r1
-	
-okay:	
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/dmulul.cgs b/sim/testsuite/sim/sh64/compact/dmulul.cgs
deleted file mode 100644
index b34b870269d..00000000000
--- a/sim/testsuite/sim/sh64/compact/dmulul.cgs
+++ /dev/null
@@ -1,53 +0,0 @@
-# sh testcase for dmulu.l $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #0, r0
-	mov #0, r1
-	dmulu.l r0, r1
-
-	mov #0, r0
-	mov #5, r1
-	dmulu.l r0, r1
-
-	mov #5, r0
-	mov #0, r1
-	dmulu.l r0, r1
-
-	mov #1, r0
-	mov #5, r1
-	dmulu.l r0, r1
-
-	mov #5, r0
-	mov #1, r1
-	dmulu.l r0, r1
-
-	mov #2, r0
-	mov #2, r1
-	dmulu.l r0, r1
-
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	dmulu.l r0, r1
-
-	mov #1, r0
-	neg r0, r0
-	mov #1, r1
-	neg r1, r1
-	dmulu.l r0, r1
-
-	mov #1, r0
-	neg r0, r0
-	shlr r0
-	mov #1, r1
-	neg r1, r1
-	shlr r1
-	dmulu.l r0, r1
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/dt.cgs b/sim/testsuite/sim/sh64/compact/dt.cgs
deleted file mode 100644
index 38e91638bd9..00000000000
--- a/sim/testsuite/sim/sh64/compact/dt.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for dt $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global dt
-dt:
-	mov #3, r0
-	dt r0
-	bt wrong
-	assert r0, #2
-
-	mov #1, r0
-	dt r0
-	bf wrong
-	assert r0, #0
-
-	mov #0, r0
-	dt r0
-	bt wrong
-	mov #0, r7
-	not r7, r7
-	cmp/eq r7, r0
-	bf wrong
-
-	mov #1, r0
-	neg r0, r0
-	dt r0
-	mov #1, r7
-	not r7, r7
-	cmp/eq r7, r0
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/extsb.cgs b/sim/testsuite/sim/sh64/compact/extsb.cgs
deleted file mode 100644
index 90878020a28..00000000000
--- a/sim/testsuite/sim/sh64/compact/extsb.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for exts.b $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global extsb
-extsb:
-	mov #42, r1
-	exts.b r1, r2
-	assert r2, #42
-signed:
-	mov #0, r0
-	or #255, r0
-	exts.b r0, r1
-	mov #0, r7
-	not r7, r7
-	cmp/eq r1, r7
-	bf wrong
-	
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/extsw.cgs b/sim/testsuite/sim/sh64/compact/extsw.cgs
deleted file mode 100644
index d6257747df7..00000000000
--- a/sim/testsuite/sim/sh64/compact/extsw.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for exts.w $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global extsw
-extsw:
-	mov #42, r1
-	exts.w r1, r2
-	assert r2, #42
-	
-another:
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	exts.w r0, r1
-
-	mov #-1, r7
-	shll8 r7
-	cmp/eq r1, r7
-	bf wrong
-	
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/extub.cgs b/sim/testsuite/sim/sh64/compact/extub.cgs
deleted file mode 100644
index 51c14ac4359..00000000000
--- a/sim/testsuite/sim/sh64/compact/extub.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for extu.b $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global extub
-extub:
-	mov #42, r1
-	extu.b r1, r2
-	assert r2, #42
-
-another:
-	mov #0, r0
-	or #255, r0
-	extu.b r0, r1
-
-	mov #0, r0
-	or #255, r0
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/extuw.cgs b/sim/testsuite/sim/sh64/compact/extuw.cgs
deleted file mode 100644
index 057afe7d949..00000000000
--- a/sim/testsuite/sim/sh64/compact/extuw.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for extu.w $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global extuw
-extuw:
-	mov #42, r1
-	extu.w r1, r2
-	assert r2, #42
-	
-another:
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	extu.w r0, r1
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fabs.cgs b/sim/testsuite/sim/sh64/compact/fabs.cgs
deleted file mode 100644
index 6955fa2aa16..00000000000
--- a/sim/testsuite/sim/sh64/compact/fabs.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# sh testcase for fabs -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	_clrpr
-	# fabs(0.0) = 0.0.
-	fldi0 fr0
-	fabs fr0
-	fldi0 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# fabs(1.0) = 1.0.
-	fldi1 fr0
-	fabs fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# fabs(-1.0) = 1.0.
-	fldi1 fr0
-	fneg fr0
-	fabs fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-
-double:
-	# double precision tests.
-	# fabs(0.0) = 0.0.
-	fldi0 fr0
-	_s2d fr0, dr0
-	_setpr
-	fabs dr0
-	_clrpr
-	# check.
-	fldi0 fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bf wrong
-	_clrpr
-
-one:
-	# fabs(1.0) = 1.0.
-	fldi1 fr0
-	_s2d fr0, dr0
-	_setpr
-	fabs dr0
-	_clrpr
-	# check.
-	fldi1 fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bf wrong2
-	_clrpr
-
-minusone:
-	# fabs(-1.0) = 1.0.
-	fldi1 fr0
-	fneg fr0
-	_s2d fr0, dr0
-	_setpr
-	fabs dr0
-	_clrpr
-	# check.
-	fldi1 fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bf wrong2
-	_clrpr
-
-okay:
-	pass
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fadd.cgs b/sim/testsuite/sim/sh64/compact/fadd.cgs
deleted file mode 100644
index b00035308f8..00000000000
--- a/sim/testsuite/sim/sh64/compact/fadd.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for fadd
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	_clrpr
-
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-
-	fldi0 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-
-	fldi1 fr0
-	fldi0 fr1
-	fadd fr0, fr1
-
-	_setpr
-double:
-	fldi1 fr0
-	fldi1 fr1
-	_s2d fr0, dr4
-	_s2d fr1, dr6
-	fadd dr4, dr6
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs
deleted file mode 100644
index 151d5e5647a..00000000000
--- a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs
+++ /dev/null
@@ -1,88 +0,0 @@
-# sh testcase for fcmpeq -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# 1.0 == 1.0.	
-	fldi1 fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# 0.0 != 1.0.
-	fldi0 fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bt wrong
-
-	# 1.0 != 0.0.
-	fldi1 fr0
-	fldi0 fr1
-	fcmp/eq fr0, fr1
-	bt wrong
-
-	# 2.0 != 1.0
-	fldi1 fr0
-	fadd fr0, fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bt wrong
-
-	bra double
-	# delay slot
-	nop
-
-wrong:
-	fail
-	
-double:
-	# 1.0 == 1.0
-	fldi1 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bf wrong
-	_clrpr
-
-	# 0.0 != 1.0
-	fldi0 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bt wrong
-	_clrpr
-
-	# 1.0 != 0.0
-	fldi1 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bt wrong2
-	_clrpr
-
-	# 2.0 != 1.0
-	fldi1 fr0
-	fadd fr0, fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bt wrong2
-	_clrpr
-
-okay:
-	pass
-
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs
deleted file mode 100644
index 931ae3e2e6c..00000000000
--- a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs
+++ /dev/null
@@ -1,95 +0,0 @@
-# sh testcase for fcmpgt -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# 1.0 !> 1.0.
-	fldi1 fr0
-	fldi1 fr1
-	fcmp/gt fr0, fr1
-	bt wrong
-
-	# 0.0 !> 1.0.
-	fldi0 fr0
-	fldi1 fr1
-	fcmp/gt fr0, fr1
-	bf wrong
-
-	# 1.0 > 0.0.
-	fldi1 fr0
-	fldi0 fr1
-	fcmp/gt fr0, fr1
-	bt wrong
-
-	# 2.0 > 1.0
-	fldi1 fr0
-	fadd fr0, fr0
-	fldi1 fr1
-	fcmp/gt fr0, fr1
-	bt wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-
-double:
-	# double precision tests.
-	# 1.0 !> 1.0.
-	fldi1 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/gt dr0, dr2
-	bt wrong2
-	_clrpr
-
-	# 0.0 !> 1.0.
-	fldi0 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/gt dr0, dr2
-	bf wrong2
-	_clrpr
-
-	bra next
-	nop
-
-wrong2:
-	fail
-
-next:
-	# 1.0 > 0.0.
-	fldi1 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/gt dr0, dr2
-	bt wrong2
-	_clrpr
-
-	# 2.0 > 1.0.
-	fldi1 fr0
-	fadd fr0, fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fcmp/gt dr0, dr2
-	bt wrong2
-	_clrpr
-
-okay:
-	pass
-
-wrong3:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fcnvds.cgs b/sim/testsuite/sim/sh64/compact/fcnvds.cgs
deleted file mode 100644
index abf9e704ffb..00000000000
--- a/sim/testsuite/sim/sh64/compact/fcnvds.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for fcnvds -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	_setpr
-	fcnvds dr0, fpul
-	_clrpr
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs
deleted file mode 100644
index 699bde55c6e..00000000000
--- a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for fcnvsd -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	fldi1 fr0
-	flds fr0, fpul
-	_setpr
-	fcnvsd fpul, dr2
-	_clrpr
-
-	# Convert back.
-	_setpr
-	fcnvds dr2, fpul
-	_clrpr
-	fsts fpul, fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fdiv.cgs b/sim/testsuite/sim/sh64/compact/fdiv.cgs
deleted file mode 100644
index 06d1e93a014..00000000000
--- a/sim/testsuite/sim/sh64/compact/fdiv.cgs
+++ /dev/null
@@ -1,83 +0,0 @@
-# sh testcase for fdiv -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	_clrpr
-	
-	# 1.0 / 0.0 should be INF
-	# (and not crash the sim).
-	fldi0 fr0
-	fldi1 fr1
-	fdiv fr0, fr1
-
-	# 0.0 / 1.0 == 0.0.
-	fldi0 fr0
-	fldi1 fr1
-	fdiv fr1, fr0
-	fldi0 fr2
-	fcmp/eq fr0, fr2
-	bf wrong
-
-	# 2.0 / 1.0 == 2.0.
-	fldi1 fr1
-	fldi1 fr2
-	fadd fr2, fr2
-	fdiv fr1, fr2
-	# Load 2.0 into fr3.
-	fldi1 fr3
-	fadd fr3, fr3
-	fcmp/eq fr2, fr3
-	bf wrong
-
-	# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
-	fldi1 fr1
-	fldi1 fr2
-	fadd fr2, fr2
-	fdiv fr2, fr1
-	# fr1 should contain 0.5.
-	fadd fr1, fr1
-	# Load 1.0 into fr3.
-	fldi1 fr3
-	# Compare fr1 with fr3.
-	fcmp/eq fr1, fr3
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-	
-double:	
-	# double test
-	# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
-	fldi1 fr1
-	_s2d fr1, dr6
-	fldi1 fr2
-	fadd fr2, fr2
-	_s2d fr2, dr8
-	_setpr
-	fdiv dr8, dr6
-	# dr0 should contain 0.5.
-	# double it, expect 1.0.
-	fadd dr6, dr6
-	_clrpr
-foo:	
-	# Load 1.0 into dr4.
-	fldi1 fr1
-	_s2d fr1, dr10
-	# Compare dr0 with dr10.
-	_setpr
-	fcmp/eq dr6, dr10
-	bf wrong2
-	_clrpr
-	
-okay:
-	pass
-
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fipr.cgs b/sim/testsuite/sim/sh64/compact/fipr.cgs
deleted file mode 100644
index 092f0f6c066..00000000000
--- a/sim/testsuite/sim/sh64/compact/fipr.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# sh testcase for fipr $fvm, $fvn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-initv1:
-	fldi1 fr0
-	# Load 2 into fr2.
-	fldi1 fr1
-	fadd fr1, fr1
-	# Load 4 into fr2.
-	fldi1 fr2
-	fadd fr2, fr2
-	fadd fr2, fr2
-	fldi0 fr3
-
-initv2:
-	fldi1 fr8
-	fldi0 fr9
-	fldi1 fr10
-	fldi0 fr11
-
-	fipr fv0, fv8
-
-	# Result will be in fr11.
-	fldi1 fr0
-	fldi1 fr1
-	# Two.
-	fadd fr1, fr0
-	# Four.
-	fadd fr0, fr0
-	# Five.
-	fadd fr1, fr0
-	fcmp/eq fr0, fr11
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fldi0.cgs b/sim/testsuite/sim/sh64/compact/fldi0.cgs
deleted file mode 100644
index b0d35e4fb09..00000000000
--- a/sim/testsuite/sim/sh64/compact/fldi0.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# sh testcase for fldi0 $frn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	fldi0 fr0
-	fldi0 fr2
-	fldi0 fr4
-	fldi0 fr6
-	fldi0 fr8
-	fldi0 fr10
-	fldi0 fr12
-	fldi0 fr14
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fldi1.cgs b/sim/testsuite/sim/sh64/compact/fldi1.cgs
deleted file mode 100644
index 8bd5c521be2..00000000000
--- a/sim/testsuite/sim/sh64/compact/fldi1.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# sh testcase for fldi1 $frn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	fldi1 fr1
-	fldi1 fr3
-	fldi1 fr5
-	fldi1 fr7
-	fldi1 fr9
-	fldi1 fr11
-	fldi1 fr13
-	fldi1 fr15
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/flds.cgs b/sim/testsuite/sim/sh64/compact/flds.cgs
deleted file mode 100644
index 797e7cba9ab..00000000000
--- a/sim/testsuite/sim/sh64/compact/flds.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for flds -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	fldi0 fr0
-	flds fr0, fpul
-	fsts fpul, fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-	
-	fldi1 fr0
-	flds fr0, fpul
-	fsts fpul, fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/float.cgs b/sim/testsuite/sim/sh64/compact/float.cgs
deleted file mode 100644
index 8532d7fd651..00000000000
--- a/sim/testsuite/sim/sh64/compact/float.cgs
+++ /dev/null
@@ -1,80 +0,0 @@
-# sh testcase for float -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-pos:	
-	mov #3, r0
-	lds r0, fpul
-	float fpul, fr7
-
-	# Check the result.
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	fadd fr0, fr1
-	fcmp/eq fr1, fr7
-	bf wrong
-
-neg:	
-	mov #3, r0
-	neg r0, r0
-	lds r0, fpul
-	float fpul, fr7
-
-	# Check the result.
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	fadd fr0, fr1
-	fneg fr1
-	fcmp/eq fr1, fr7
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-	
-double:
-	mov #3, r0
-	lds r0, fpul
-	_setpr
-	float fpul, dr8
-	_clrpr
-	# check the result.
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	fadd fr0, fr1
-	_s2d fr1, dr2
-	fcmp/eq dr2, dr8
-	bf wrong
-
-dneg:
-	mov #3, r0
-	neg r0, r0
-	lds r0, fpul
-	_setpr
-	float fpul, dr8
-	_clrpr
-	# check the result.
-	fldi1 fr0
-	fldi1 fr1
-	fadd fr0, fr1
-	fadd fr0, fr1
-	fneg fr1
-	_s2d fr1, dr2
-	fcmp/eq dr2, dr8
-	bf wrong	
-
-okay:
-	pass
-
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fmac.cgs b/sim/testsuite/sim/sh64/compact/fmac.cgs
deleted file mode 100644
index dbf36ab78c8..00000000000
--- a/sim/testsuite/sim/sh64/compact/fmac.cgs
+++ /dev/null
@@ -1,78 +0,0 @@
-# sh testcase for fmac -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# 0.0 * x + y = y.
-
-	fldi0 fr0
-	fldi1 fr1
-	fldi1 fr2
-	fmac fr0, fr1, fr2
-	# check result.
-	fldi1 fr0
-	fcmp/eq fr0, fr2
-	bf wrong
-
-	# x * y + 0.0 = x * y.
-
-	fldi1 fr0
-	fldi1 fr1
-	fldi0 fr2
-	# double it.
-	fadd fr1, fr2
-	fmac fr0, fr1, fr2
-	# check result.
-	fldi1 fr0
-	fadd fr0, fr0
-	fcmp/eq fr0, fr2
-	bf wrong
-	
-	# x * 0.0 + y = y.
-
-	fldi1 fr0
-	fldi0 fr1
-	fldi1 fr2
-	fadd fr2, fr2
-	fmac fr0, fr1, fr2
-	# check result.
-	fldi1 fr0
-	# double fr0.
-	fadd fr0, fr0
-	fcmp/eq fr0, fr2
-	bf wrong
-
-	# x * 0.0 + 0.0 = 0.0
-
-	fldi1 fr0
-	fadd fr0, fr0
-	fldi0 fr1
-	fldi0 fr2
-	fmac fr0, fr1, fr2
-	# check result.
-	fldi0 fr0
-	fcmp/eq fr0, fr2
-	bf wrong
-
-	# 0.0 * x + 0.0 = 0.0.
-
-	fldi0 fr0
-	fldi1 fr1
-	# double it.
-	fadd fr1, fr1
-	fldi0 fr2
-	fmac fr0, fr1, fr2
-	# check result.
-	fldi0 fr0
-	fcmp/eq fr0, fr2
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fmov.cgs b/sim/testsuite/sim/sh64/compact/fmov.cgs
deleted file mode 100644
index f4e1fde3c11..00000000000
--- a/sim/testsuite/sim/sh64/compact/fmov.cgs
+++ /dev/null
@@ -1,273 +0,0 @@
-# sh testcase for all fmov instructions
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	.macro init
-	fldi0 fr0
-	fldi1 fr2
-	.endm
-
-	# Set the SZ (SiZe) bit in the fpscr.
-	.macro _setsz
-	sts fpscr, r7
-	mov #16, r8
-	shll16 r8
-	or r8, r7
-	lds r7, fpscr
-	.endm
-
-	# Clear the SZ bit.
-	.macro _clrsz
-	sts fpscr, r7
-	mov #16, r8
-	shll16 r8
-	not r8, r8
-	and r8, r7
-	lds r7, fpscr
-	.endm
-	start
-
-fmov1:  # Test fr -> fr.
-	init
-	_clrpr
-	_clrsz
-	fmov fr0, fr10
-	# Ensure fr0 and fr10 are now equal.
-	fcmp/eq fr0, fr10
-	bt fmov2
-	fail
-
-fmov2:  # Test dr -> dr.
-	init
-	_setpr
-	_setsz
-	fmov dr0, dr2
-	# Ensure dr0 and dr2 are now equal.
-	fcmp/eq dr0, dr2
-	bt fmov3
-	fail
-
-fmov3:  # Test dr -> xd and xd -> dr.
-	init
-	_setsz
-	fmov dr0, xd0
-	# Ensure dr0 and xd0 are now equal.
-	fmov xd0, dr2
-	fcmp/eq dr0, dr2
-	bt fmov4
-	fail
-
-fmov4:  # Test xd -> xd.
-	init
-	_setsz
-	_setpr
-	fmov dr0, xd0
-	fmov xd0, xd2
-	fmov xd2, dr2
-	# Ensure dr0 and dr2 are now equal.
-	fcmp/eq dr0, dr2
-	bt fmov5
-	fail
-
-fmov5:  # Test fr -> @rn and @rn -> fr.
-	init
-	_clrsz
-	_clrpr
-	mov #40, r0
-	shll8 r0
-	fmov fr0, @r0
-	fmov @r0, fr1
-	fcmp/eq fr0, fr1
-	bt fmov6
-	fail
-
-fmov6:  # Test dr -> @rn and @rn -> dr.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	fmov dr0, @r0
-	fmov @r0, dr2
-	fcmp/eq dr0, dr2
-	bt fmov7
-	fail
-
-fmov7:	# Test xd -> @rn and @rn -> xd.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	fmov dr0, xd0
-	fmov xd0, @r0
-	fmov @r0, xd2
-	fmov xd2, dr2
-	fcmp/eq dr0, dr2
-	bt fmov8
-	fail
-
-fmov8:	# Test fr -> @-rn.
-	init
-	_clrsz
-	_clrpr
-	mov #40, r0
-	shll8 r0
-	# Preserve.
-	mov r0, r1
-	fmov fr0, @-r0
-	fmov @r0, fr2
-	fcmp/eq fr0, fr2
-	bt f8b
-	fail
-f8b:	# check pre-dec.
-	add #4, r0
-	cmp/eq r0, r1
-	bt fmov9
-	fail
-
-fmov9:	# Test dr -> @-rn.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r1
-	fmov dr0, @-r0
-	fmov @r0, dr2
-	fcmp/eq dr0, dr2
-	bt f9b
-	fail
-f9b:	# check pre-dec.
-	add #8, r0
-	cmp/eq r0, r1
-	bt fmov10
-	fail
-
-fmov10:	# Test xd -> @-rn.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r1
-	fmov dr0, xd0
-	fmov xd0, @-r0
-	fmov @r0, xd2
-	fmov xd2, dr2
-	fcmp/eq dr0, dr2
-	bt f10b
-	fail
-f10b:   # check pre-dec.
-	add #8, r0
-	cmp/eq r0, r1
-	bt fmov11
-	fail
-
-fmov11:	# Test @rn+ -> fr.
-	init
-	_clrsz
-	_clrpr
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r1
-	fmov fr0, @r0
-	fmov @r0+, fr2
-	fcmp/eq fr0, fr2
-	bt f11b
-	fail
-f11b:   # check post-inc.
-	add #4, r1
-	cmp/eq r0, r1
-	bt fmov12
-	fail
-
-fmov12:	# Test @rn+ -> dr.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	# preserve r0.
-	mov r0, r1
-	fmov dr0, @r0
-	fmov @r0+, dr2
-	fcmp/eq dr0, dr2
-	bt f12b
-	fail
-f12b:   # check post-inc.
-	add #8, r1
-	cmp/eq r0, r1
-	bt fmov13
-	fail
-
-fmov13:	# Test @rn -> xd.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r1
-	fmov dr0, xd0
-	fmov xd0, @r0
-	fmov @r0+, xd2
-	fmov xd2, dr2
-	fcmp/eq dr0, dr2
-	bt f13b
-	fail
-f13b:
-	add #8, r1
-	cmp/eq r0, r1
-	bt fmov14
-	fail
-
-fmov14:	# Test fr -> @(r0,rn), @(r0, rn) -> fr.
-	init
-	_clrsz
-	_clrpr
-	mov #40, r0
-	shll8 r0
-	mov #0, r1
-	fmov fr0, @(r0, r1)
-	fmov @(r0, r1), fr1
-	fcmp/eq fr0, fr1
-	bt fmov15
-	fail
-
-fmov15:	# Test dr -> @(r0, rn), @(r0, rn) -> dr.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	mov #0, r1
-	fmov dr0, @(r0, r1)
-	fmov @(r0, r1), dr2
-	fcmp/eq dr0, dr2
-	bt fmov16
-	fail
-
-fmov16:	# Test xd -> @(r0, rn), @(r0, rn) -> xd.
-	init
-	_setsz
-	_setpr
-	mov #40, r0
-	shll8 r0
-	mov #0, r1
-	fmov dr0, xd0
-	fmov xd0, @(r0, r1)
-	fmov @(r0, r1), xd2
-	fmov xd2, dr2
-	fcmp/eq dr0, dr2
-	bt okay
-	fail
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fmul.cgs b/sim/testsuite/sim/sh64/compact/fmul.cgs
deleted file mode 100644
index a1325d6395b..00000000000
--- a/sim/testsuite/sim/sh64/compact/fmul.cgs
+++ /dev/null
@@ -1,121 +0,0 @@
-# sh testcase for fmul -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	.macro init
-	fldi0 fr0
-	fldi1 fr1
-	fldi1 fr2
-	fadd fr2, fr2
-	fldi0 fr7
-	fldi1 fr8
-	.endm
-
-	start
-
-	# 0.0 * 0.0 = 0.0.
-	init
-	fmul fr0, fr0
-	fcmp/eq fr7, fr0
-	bf wrong
-
-	# 0.0 * 1.0 = 0.0.
-	init
-	fmul fr1, fr0
-	fcmp/eq fr7, fr0
-	bf wrong
-
-	# 1.0 * 0.0 = 0.0.
-	init
-	fmul fr0, fr1
-	fcmp/eq fr7, fr1
-	bf wrong
-
-	# 1.0 * 1.0 = 1.0.
-	init
-	fmul fr1, fr1
-	fcmp/eq fr8, fr1
-	bf wrong
-
-	# 2.0 * 1.0 = 2.0.
-	init
-	fmul fr2, fr1
-	fcmp/eq fr2, fr1
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-	
-	.macro dinit
-	fldi0 fr0
-	fldi1 fr2
-	fldi1 fr4
-	fadd fr4, fr4
-	fldi0 fr8
-	fldi1 fr10
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_s2d fr4, dr4
-	_s2d fr8, dr8
-	_s2d fr10, dr10
-	.endm
-	
-double:
-	# 0.0 * 0.0 = 0.0.
-	dinit
-	_setpr
-	fmul dr0, dr0
-	fcmp/eq dr8, dr0
-	bf wrong
-	_clrpr
-
-	# 0.0 * 1.0 = 0.0.
-	dinit
-	_setpr
-	fmul dr2, dr0
-	fcmp/eq dr8, dr0
-	bf wrong2
-	_clrpr
-
-	# 1.0 * 0.0 = 0.0.
-	dinit
-	_setpr
-	fmul dr0, dr2
-	fcmp/eq dr8, dr2
-	bf wrong2
-	_clrpr
-
-	bra next
-	nop
-
-wrong2:
-	fail
-
-next:
-	# 1.0 * 1.0 = 1.0.
-	dinit
-	_setpr
-	fmul dr2, dr2
-	fcmp/eq dr10, dr2
-	bf wrong3
-	_clrpr
-
-	# 2.0 * 1.0 = 2.0.
-	dinit
-	_setpr
-	fmul dr4, dr2
-	fcmp/eq dr4, dr2
-	bf wrong3
-	_clrpr
-
-okay:
-	pass
-
-wrong3:	
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fneg.cgs b/sim/testsuite/sim/sh64/compact/fneg.cgs
deleted file mode 100644
index 71fc901fb6d..00000000000
--- a/sim/testsuite/sim/sh64/compact/fneg.cgs
+++ /dev/null
@@ -1,83 +0,0 @@
-# sh testcase for fneg -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# neg(0.0) = 0.0.
-	fldi0 fr0
-	fldi0 fr1
-	fneg fr0
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# neg(1.0) = fsub(0,1)
-	fldi1 fr0
-	fneg fr0
-	fldi0 fr1
-	fldi1 fr2
-	fsub fr2, fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-	
-	# neg(neg(1.0)) = 1.0.
-	fldi1 fr0
-	fldi1 fr1
-	fneg fr0
-	fneg fr0
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-
-double:
-	# neg(0.0) = 0.0.
-	fldi0 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fneg dr0
-	fcmp/eq dr0, dr2
-	bf wrong2
-	_clrpr
-
-	# neg(1.0) = fsub(0,1)
-	fldi1 fr0
-	_s2d fr0, dr0
-	_setpr
-	fneg dr0
-	_clrpr
-	fldi0 fr2
-	fldi1 fr3
-	fsub fr3, fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq fr0, fr2
-	bf wrong2
-	_clrpr
-	
-	# neg(neg(1.0)) = 1.0.
-	fldi1 fr0
-	_s2d fr0, dr0
-	fldi1 fr2
-	_s2d fr2, dr2
-	_setpr
-	fneg dr0
-	fneg dr2
-	fcmp/eq dr0, dr2
-	bf wrong2
-	_clrpr
-		
-okay:
-	pass
-
-wrong2:	
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/frchg.cgs b/sim/testsuite/sim/sh64/compact/frchg.cgs
deleted file mode 100644
index 6f2e743fc37..00000000000
--- a/sim/testsuite/sim/sh64/compact/frchg.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for frchg
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	frchg
-	frchg
-	frchg
-	frchg
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fschg.cgs b/sim/testsuite/sim/sh64/compact/fschg.cgs
deleted file mode 100644
index 54a1491962b..00000000000
--- a/sim/testsuite/sim/sh64/compact/fschg.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for fschg
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	fschg
-	fschg
-	fschg
-	fschg
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fsqrt.cgs b/sim/testsuite/sim/sh64/compact/fsqrt.cgs
deleted file mode 100644
index 933e112c903..00000000000
--- a/sim/testsuite/sim/sh64/compact/fsqrt.cgs
+++ /dev/null
@@ -1,93 +0,0 @@
-# sh testcase for fsqrt -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# sqrt(0.0) = 0.0.
-	fldi0 fr0
-	fsqrt fr0
-	fldi0 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# sqrt(1.0) = 1.0.
-	fldi1 fr0
-	fsqrt fr0
-	fldi1 fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	# sqrt(4.0) = 2.0
-	fldi1 fr0
-	# Double it.
-	fadd fr0, fr0
-	# Double it again.
-	fadd fr0, fr0
-	fsqrt fr0
-	fldi1 fr1
-	# Double it.
-	fadd fr1, fr1
-	fcmp/eq fr0, fr1
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-
-double:
-	# sqrt(0.0) = 0.0.
-	fldi0 fr0
-	_s2d fr0, dr0
-	_setpr
-	fsqrt dr0
-	_clrpr
-	fldi0 fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq dr0, dr2
-	bf wrong2
-	_clrpr
-
-	# sqrt(1.0) = 1.0.
-	fldi1 fr0
-	_s2d fr0, dr0
-	_setpr
-	fsqrt dr0
-	_clrpr
-	fldi1 fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq fr0, fr2
-	bf wrong2
-	_clrpr
-
-	# sqrt(4.0) = 2.0.
-	fldi1 fr0
-	# Double it.
-	fadd fr0, fr0
-	# Double it again.
-	fadd fr0, fr0
-	_s2d fr0, dr0
-	_setpr
-	fsqrt dr0
-	_clrpr
-	fldi1 fr2
-	# Double it.
-	fadd fr2, fr2
-	_s2d fr2, dr2
-	_setpr
-	fcmp/eq fr0, fr2
-	bf wrong2
-	_clrpr
-
-okay:
-	pass
-
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/fsts.cgs b/sim/testsuite/sim/sh64/compact/fsts.cgs
deleted file mode 100644
index 518533db094..00000000000
--- a/sim/testsuite/sim/sh64/compact/fsts.cgs
+++ /dev/null
@@ -1,11 +0,0 @@
-# sh testcase for fsts fpul, $frn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	fsts fpul, fr0
-	fsts fpul, fr1
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/fsub.cgs b/sim/testsuite/sim/sh64/compact/fsub.cgs
deleted file mode 100644
index 346d01ffcaa..00000000000
--- a/sim/testsuite/sim/sh64/compact/fsub.cgs
+++ /dev/null
@@ -1,120 +0,0 @@
-# sh testcase for fmul -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	# 0.0 - 0.0 = 0.0.
-	fldi0 fr0
-	fldi0 fr1
-	fsub fr0, fr1
-	fldi0 fr2
-	fcmp/eq fr1, fr2
-	bf wrong
-
-	# 1.0 - 0.0 = 1.0.
-	fldi0 fr0
-	fldi1 fr1
-	fsub fr0, fr1
-	fldi1 fr2
-	fcmp/eq fr1, fr2
-	bf wrong
-
-	# 1.0 - 1.0 = 0.0.
-	fldi1 fr0
-	fldi1 fr1
-	fsub fr0, fr1
-	fldi0 fr2
-	fcmp/eq fr1, fr2
-	bf wrong
-
-	# 0.0 - 1.0 = -1.0.
-	fldi1 fr0
-	fldi0 fr1
-	fsub fr0, fr1
-	fldi1 fr2
-	fneg fr2
-	fcmp/eq fr1, fr2
-	bf wrong
-
-	bra double	
-	nop
-
-wrong:
-	fail
-
-double:
-	# 0.0 - 0.0 = 0.0.
-	fldi0 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fsub dr0, dr2
-	_clrpr
-	fldi0 fr4
-	_s2d fr4, dr4
-	_setpr
-	fcmp/eq dr2, dr4
-	bf wrong
-	_clrpr
-
-onezero:	
-	# 1.0 - 0.0 = 1.0.
-	fldi0 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fsub dr0, dr2
-	_clrpr
-	fldi1 fr4
-	_s2d fr4, dr4
-	_setpr
-	fcmp/eq dr2, dr4
-	bf wrong2
-	_clrpr
-
-oneone:	
-	# 1.0 - 1.0 = 0.0.
-	fldi1 fr0
-	fldi1 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fsub dr0, dr2
-	_clrpr
-	fldi0 fr4
-	_s2d fr4, dr4
-	_setpr
-	fcmp/eq dr2, dr4
-	bf wrong2
-	_clrpr
-
-	bra zeroone
-	nop
-
-wrong2:
-	fail
-
-zeroone:	
-	# 0.0 - 1.0 = -1.0.
-	fldi1 fr0
-	fldi0 fr2
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_setpr
-	fsub dr0, dr2
-	_clrpr
-	fldi1 fr4
-	fneg fr4
-	_s2d fr4, dr4
-	_setpr
-	fcmp/eq dr2, dr4
-	bf wrong2
-	_clrpr
-		
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/ftrc.cgs b/sim/testsuite/sim/sh64/compact/ftrc.cgs
deleted file mode 100644
index 6a89744b33e..00000000000
--- a/sim/testsuite/sim/sh64/compact/ftrc.cgs
+++ /dev/null
@@ -1,132 +0,0 @@
-# sh testcase for ftrc -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# ftrc(0.0) = 0.
-	fldi0 fr0
-	ftrc fr0, fpul
-	# check results.
-	mov #0, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-	bf wrong
-	
-	# ftrc(1.5) = 1.
-	fldi1 fr0
-	fldi1 fr1
-	fldi1 fr2
-	# double it.
-	fadd fr2, fr2
-	# form the fraction.
-	fdiv fr2, fr1
-	fadd fr1, fr0
-	# now we've got 1.5 in fr0.
-	ftrc fr0, fpul
-	# check results.
-	mov #1, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-	bf wrong
-
-	# ftrc(-1.5) = -1.
-	fldi1 fr0
-	fneg fr0
-	fldi1 fr1
-	fldi1 fr2
-	# double it.
-	fadd fr2, fr2
-	# form the fraction.
-	fdiv fr2, fr1
-	fneg fr1
-	# -1 + -0.5 = -1.5.
-	fadd fr1, fr0
-	# now we've got 1.5 in fr0.
-	ftrc fr0, fpul
-	# check results.
-	mov #1, r0
-	neg r0, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-	bf wrong
-
-	bra double
-	nop
-
-wrong:
-	fail
-
-double:
-	# ftrc(0.0) = 0.
-	fldi0 fr0
-	_s2d fr0, dr0
-	_setpr
-	ftrc dr0, fpul
-	_clrpr
-	# check results.
-	mov #0, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-foo:	
-	bf wrong2
-
-	# ftrc(1.5) = 1.
-	fldi1 fr0
-	fldi1 fr2
-	fldi1 fr4
-	# double it.
-	fadd fr4, fr4
-	# form 0.5.
-	fdiv fr4, fr2
-	fadd fr2, fr0
-	# now we've got 1.5 in fr0, so do some single->double
-	# conversions and perform the ftrc.
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_s2d fr4, dr4
-	_setpr
-	ftrc dr0, fpul
-	_clrpr
-	
-	# check results.
-	mov #1, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-	bf wrong2
-
-	# ftrc(-1.5) = -1.
-	fldi1 fr0
-	fneg fr0
-	fldi1 fr2
-	fldi1 fr4
-	# double it.
-	fadd fr4, fr4
-	# form the fraction.
-	fdiv fr4, fr2
-	fneg fr2
-	# -1 + -0.5 = -1.5.
-	fadd fr2, fr0
-	# now we've got 1.5 in fr0, so do some single->double
-	# conversions and perform the ftrc.
-	_s2d fr0, dr0
-	_s2d fr2, dr2
-	_s2d fr4, dr4
-	_setpr
-	ftrc dr0, fpul
-	_clrpr
-	
-	# check results.
-	mov #1, r0
-	neg r0, r0
-	sts fpul, r1
-	cmp/eq r0, r1
-	bf wrong2
-
-okay:
-	pass
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ftrv.cgs b/sim/testsuite/sim/sh64/compact/ftrv.cgs
deleted file mode 100644
index 9bdf806ba13..00000000000
--- a/sim/testsuite/sim/sh64/compact/ftrv.cgs
+++ /dev/null
@@ -1,74 +0,0 @@
-# sh testcase for ftrv xmtrx, $fvn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	# set the fr bit in the fpscr
-	.macro _setfr
-	sts fpscr, r7
-	mov #32, r8
-	shll16 r8
-	or r8, r7
-	lds r7, fpscr
-	.endm
-
-	# clear the fr bit
-	.macro _clrfr
-	sts fpscr, r7
-	mov #32, r8
-	shll16 r8
-	not r8, r8
-	and r8, r7
-	lds r7, fpscr
-	.endm
-
-	.macro incr old new
-	fldi1 \new
-	fadd \old, \new
-	.endm
-
-	start
-	_setfr
-popmtrx:
-	# 1.0.
-	fldi1 fr0
-	# 2.0.
-	fldi1 fr1
-	fadd fr1, fr1
-
-	incr fr1, fr2
-	incr fr2, fr3
-	incr fr3, fr4
-	incr fr4, fr5
-	incr fr5, fr6
-	incr fr6, fr7
-	incr fr7, fr8
-	incr fr8, fr9
-	incr fr9, fr10
-	incr fr10, fr11
-	incr fr11, fr12
-	incr fr12, fr13
-	incr fr13, fr14
-	incr fr14, fr15
-
-popvect:
-	# Swtich fp banks.
-	_clrfr
-	fldi1 fr4
-	fldi1 fr5
-	fadd fr5, fr5
-	fldi1 fr6
-	fadd fr5, fr6
-	fldi1 fr7
-	fadd fr6, fr7
-
-ftrv:
-	# fr[4,7] should contain the results:
-	# { 30, 70, 110, 150 }.
-	ftrv xmtrx, fv4
-
-okay:
-	pass
-
diff --git a/sim/testsuite/sim/sh64/compact/jmp.cgs b/sim/testsuite/sim/sh64/compact/jmp.cgs
deleted file mode 100644
index e9e99401545..00000000000
--- a/sim/testsuite/sim/sh64/compact/jmp.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for jmp @$rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global jmp
-jmp:
-	# Load 0x1010 into r0.
-	mov #1, r0
-	shll8 r0
-	shll2 r0
-	shll2 r0
-	add #16, r0
-	jmp @r0
-slot:
-	nop
-bad:
-	fail
-okay:
-	pass
-alsobad:
-	fail
-	fail
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/jsr.cgs b/sim/testsuite/sim/sh64/compact/jsr.cgs
deleted file mode 100644
index 5ad7aefc931..00000000000
--- a/sim/testsuite/sim/sh64/compact/jsr.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for jsr @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global jsr
-jsr:
-	# Load 0x1010 into r0.
-	mov #1, r0
-	shll8 r0
-	shll2 r0
-	shll2 r0
-	add #16, r0
-	jsr @r0
-slot:	
-	nop
-bad:
-	fail
-okay:
-	pass
-alsobad:
-	fail
-	fail
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
deleted file mode 100644
index b19a3c194fe..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for ldc $rn, gbr -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldc
-ldc:
-	mov #40, r0
-	shll8 r0
-	ldc r0, gbr
-	stc gbr, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs
deleted file mode 100644
index 613e58e722c..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for ldc.l @${rn}+, gbr -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldcl
-ldcl:
-	mov #40, r0
-	shll8 r0
-	# Preserve address.
-	mov r0, r1
-	ldc.l @r0+, gbr
-
-	# Add 4 to saved address (r1).
-	# Then compare with r0.
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
deleted file mode 100644
index 2dce253375d..00000000000
--- a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for lds $rn, fpscr -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global lds_fpscr
-lds_fpscr:
-	mov #0, r0
-	lds r0, fpscr
-readback:
-	sts fpscr, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs
deleted file mode 100644
index 1a80a7032ea..00000000000
--- a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# sh testcase for lds $rn, fpul -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global lds_fpul
-lds_fpul:
-	mov #63, r0
-	shll8 r0
-	add #128, r0
-	shll16 r0
-	lds r0, fpul
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/lds-mach.cgs b/sim/testsuite/sim/sh64/compact/lds-mach.cgs
deleted file mode 100644
index 1ffd6566c9a..00000000000
--- a/sim/testsuite/sim/sh64/compact/lds-mach.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for lds $rn, mach
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global lds_mach
-lds_mach:
-	mov #41, r0
-	shll8 r0
-	lds r0, mach
-readback:
-	sts mach, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/lds-macl.cgs b/sim/testsuite/sim/sh64/compact/lds-macl.cgs
deleted file mode 100644
index f09315abbb6..00000000000
--- a/sim/testsuite/sim/sh64/compact/lds-macl.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for lds $rn, macl
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global lds_macl
-lds_macl:
-	mov #42, r0
-	shll8 r0
-	lds r0, macl
-readback:
-	sts macl, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/lds-pr.cgs b/sim/testsuite/sim/sh64/compact/lds-pr.cgs
deleted file mode 100644
index 97e3a650767..00000000000
--- a/sim/testsuite/sim/sh64/compact/lds-pr.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for lds $rn, pr
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global lds_pr
-lds_pr:
-	mov #40, r0
-	shll8 r0
-	lds r0, pr
-readback:
-	sts pr, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
deleted file mode 100644
index 642f15dc527..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for lds.l @${rn}+, fpscr -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #40, r0
-	shll8 r0
-	# save address for later examination.
-	mov r0, r1
-
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-	# Store it in memory.
-	mov.l r2, @r0
-
-	lds.l @r0+, fpscr
-
-check:
-	# Read it back.
-	sts fpscr, r3
-	cmp/eq r2, r3
-	bf wrong
-
-inc:
-	# Test for proper post-increment.
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail	
diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
deleted file mode 100644
index 428a5b71816..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for lds.l @${rn}+, fpul -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldsl_fpul
-ldsl_fpul:
-	mov #40, r0
-	shll8 r0
-	# remember the address.
-	mov r0, r1
-	lds.l @r0+, fpul
-
-	# ensure post increment occurred.
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
deleted file mode 100644
index f5ffdec8dce..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for lds.l @${rn}+, mach -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldsl_mach
-ldsl_mach:
-	mov #40, r0
-	shll8 r0
-	# save address for later examination.
-	mov r0, r1
-
-	lds.l @r0+, mach
-
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
deleted file mode 100644
index 4e21bf1942f..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for lds.l @${rn}+, macl -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldsl_macl
-ldsl_macl:
-	mov #40, r0
-	shll8 r0
-	# save address for later examination.
-	mov r0, r1
-
-	lds.l @r0+, macl
-
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs
deleted file mode 100644
index eb8ee531bd3..00000000000
--- a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for lds.l @${rn}+, pr -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ldsl_pr
-ldsl_pr:
-	mov #40, r0
-	shll8 r0
-	# Preserve address.
-	mov r0, r1
-	lds.l @r0+, pr
-
-	# Add 4 to saved address (r1).
-	# Then compare with r0.
-	add #4, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/macl.cgs b/sim/testsuite/sim/sh64/compact/macl.cgs
deleted file mode 100644
index ef2dfa6e929..00000000000
--- a/sim/testsuite/sim/sh64/compact/macl.cgs
+++ /dev/null
@@ -1,76 +0,0 @@
-# sh testcase for mac.l @${rm}+, @${rn}+
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	# force S-bit clear
-	clrs
-
-	# Store some magic numbers in memory.
-	mov #40, r1
-	shll8 r1
-	mov #85, r0
-	mov.l r0, @r1
-	# Keep for later.
-	mov r1, r10
-store2:
-	mov #40, r1
-	shll8 r1
-	add #12, r1
-	mov #17, r0
-	mov.l r0, @r1
-	# Keep for later.
-	mov r1, r11
-
-init:
-	# Set up addresses.
-	mov #40, r1
-	shll8 r1
-	mov #40, r2
-	shll8 r2
-	add #12, r2
-
-	# Prime {MACL, MACH} to #1.
-	mov #1, r3
-	dmulu.l r3, r3
-
-test:
-	mac.l @r1+, @r2+
-
-check:
-	# Check result.
-	sts mach, r5
-	assert r5, #0
-
-	mov #5, r0
-	shll8 r0
-	or #166, r0
-	sts macl, r6
-	cmp/eq r6, r0
-	bf wrong
-
-	# Ensure post-increment occurred.
-	add #4, r10
-	cmp/eq r10, r1
-	bf wrong
-
-	add #4, r11
-	cmp/eq r11, r2
-	bf wrong
-
-doubleinc:
-	mov #40, r0
-	shll8 r0
-	mov r0, r1
-	mac.l @r0+, @r0+
-	add #16, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/macw.cgs b/sim/testsuite/sim/sh64/compact/macw.cgs
deleted file mode 100644
index f5935f7054d..00000000000
--- a/sim/testsuite/sim/sh64/compact/macw.cgs
+++ /dev/null
@@ -1,70 +0,0 @@
-# sh testcase for mac.w @${rm}+, @${rn}+
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# Store some magic numbers in memory.
-	mov #40, r1
-	shll8 r1
-	mov #85, r0
-	mov.l r0, @r1
-	# Keep for later.
-	mov r1, r10
-store2:
-	mov #40, r1
-	shll8 r1
-	add #12, r1
-	mov #17, r0
-	mov.l r0, @r1
-	# Keep for later.
-	mov r1, r11
-
-init:
-	# Set up addresses.
-	mov #40, r1
-	shll8 r1
-	mov #40, r2
-	shll8 r2
-	add #12, r2
-
-	# Prime {MACL, MACH} to #1.
-	mov #1, r3
-	dmulu.l r3, r3
-
-test:
-	mac.w @r1+, @r2+
-
-check:
-	# Check result.
-	sts mach, r5
-	assert r5, #0
-
-	sts macl, r6
-	assert r6, #1
-
-	# Ensure post-increment occurred.
-	add #2, r10
-	cmp/eq r10, r1
-	bf wrong
-
-	add #2, r11
-	cmp/eq r11, r2
-	bf wrong
-
-doubleinc:
-	mov #40, r0
-	shll8 r0
-	mov r0, r1
-	mac.w @r0+, @r0+
-	add #8, r1
-	cmp/eq r0, r1
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/mov.cgs b/sim/testsuite/sim/sh64/compact/mov.cgs
deleted file mode 100644
index 9442388384e..00000000000
--- a/sim/testsuite/sim/sh64/compact/mov.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for mov $rm64, $rn64
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global mov
-mov:
-	mov #1, r0
-	rotr r0
-	mov #0, r15
-	mov #10, r0
-
-	mov r0, r1
-	mov r1, r2
-	mov r2, r3
-	mov r3, r4
-	mov r4, r5
-	mov r5, r6
-	mov r6, r7
-	mov r7, r8
-	mov r8, r9
-	mov r9, r10
-	mov r10, r11
-	mov r11, r12
-	mov r12, r13
-	mov r13, r14
-	mov r14, r15
-
-	cmp/eq r0, r15
-	bf wrong
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/mova.cgs b/sim/testsuite/sim/sh64/compact/mova.cgs
deleted file mode 100644
index f555d66e093..00000000000
--- a/sim/testsuite/sim/sh64/compact/mova.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for mova @($imm8x4, pc), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global mova
-mova:
-	mova @(40, pc), r0
-	mov #16, r1
-	shll8 r1
-	add #40, r1
-	cmp/eq r0, r1
-	bf wrong
-	mova @(12, pc), r0
-	mov #16, r1
-	shll8 r1
-	add #24, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb1.cgs b/sim/testsuite/sim/sh64/compact/movb1.cgs
deleted file mode 100644
index 8278e1bbeaa..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb1.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for mov.b $rm, @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #55, r1
-	mov #40, r2
-	shll8 r2
-	mov.b r1, @r2
-
-	# Load it back into r3.
-	mov #40, r2
-	shll8 r2
-	mov.b @r2, r3
-
-	# Make sure r1 and r3 match.
-	cmp/eq r1, r3
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb10.cgs b/sim/testsuite/sim/sh64/compact/movb10.cgs
deleted file mode 100644
index 0ddb736f868..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb10.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# sh testcase for mov.b @($imm4, $rm), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-	# Store something there first.
-	mov #0, r0
-	or #170, r0
-	mov r0, r7
-	mov.b r0, @(3, r1)
-	# Load it back.
-	mov.b @(3, r1), r0
-	and #255, r0
-	cmp/eq r0, r7
-	bf wrong
-
-okay:
-	pass
-wrong:	
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb2.cgs b/sim/testsuite/sim/sh64/compact/movb2.cgs
deleted file mode 100644
index 692c34fb648..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb2.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for mov.b $rm, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #40, r1
-	shll8 r1
-	mov #55, r2
-	
-	# Save ADDR, DATA.
-	mov r1, r7
-	mov r2, r8
-
-	# Do the move.
-	mov.b r2, @-r1
-	
-	# Load the value back into r3.
-	mov.b @r1, r3
-	cmp/eq r2, r3
-	bf wrong
-
-	# Ensure that r1 has been decremented.
-	mov #1, r0
-	sub r0, r7
-	cmp/eq r7, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb3.cgs b/sim/testsuite/sim/sh64/compact/movb3.cgs
deleted file mode 100644
index 6143562b8c1..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb3.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for mov.b $rm, @(r0,$rn) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #40, r2
-	shll8 r2
-	mov #3, r1
-	mov #0, r0
-	or #170, r0
-	mov r0, r3
-	mov r2, r0
-	mov.b r3, @(r0, r1)
-
-	# Load the value back into a different register.
-	mov.b @(r0, r1), r4
-	# Check the lowest order byte matches the stored value.
-	mov r4, r0
-	and #255, r0
-	cmp/eq r0, r3
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb4.cgs b/sim/testsuite/sim/sh64/compact/movb4.cgs
deleted file mode 100644
index d30a7a8641f..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb4.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for mov.b r0, @($imm8, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #0, r0
-	or #170, r0
-	mov r0, r3
-	mov #30, r2
-	ldc r2, gbr
-	mov.b r0, @(40, gbr)
-
-	# Load the value back into a different register.
-	mov.b @(40, gbr), r0
-	# Check the lowest order byte matches the stored value.
-	and #255, r0
-	cmp/eq r0, r3
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movb5.cgs b/sim/testsuite/sim/sh64/compact/movb5.cgs
deleted file mode 100644
index 4f6795a8860..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb5.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# sh testcase for mov.b r0, @($imm4, rm) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #0, r0
-	or #170, r0
-	mov r0, r3
-	mov #30, r2
-	mov.b r0, @(3, r2)
-
-	# Load the value back into a different register.
-	mov.b @(3, r2), r0
-	and #255, r0
-	cmp/eq r3, r0
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movb6.cgs b/sim/testsuite/sim/sh64/compact/movb6.cgs
deleted file mode 100644
index 9ddebde5ce4..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb6.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for mov.b @$rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r2
-	shll8 r2
-	# Store something first.
-	mov #0, r0
-	or #170, r0
-	mov r0, r7
-	mov.b r7, @r2
-	# Load it back.
-	mov.b @r2, r1
-	mov r1, r0
-	and #255, r0
-	cmp/eq r7, r0
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb7.cgs b/sim/testsuite/sim/sh64/compact/movb7.cgs
deleted file mode 100644
index f55a223436b..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb7.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for mov.b @${rm}+, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-	# Store addr.
-	mov r1, r8
-
-	# Store something there first.
-	mov #0, r0
-	or #170, r0
-	mov r0, r7
-	mov.b r7, @r1
-	# Load it back.
-	mov.b @r1+, r2
-	mov r2, r0
-	and #255, r0
-	cmp/eq r7, r0
-	bf wrong
-
-	# Test address for post-incrementing.
-	add #1, r8
-	cmp/eq r8, r1
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movb8.cgs b/sim/testsuite/sim/sh64/compact/movb8.cgs
deleted file mode 100644
index 883e4b357ed..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb8.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for mov.b @(r0, $rm), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	mov #14, r1
-	# Store something there first.
-	mov #0, r0
-	or #170, r0
-	mov r0, r7
-	mov.b r7, @(r0, r1)
-	# Load it back.
-	mov.b @(r0, r1), r2
-	mov r2, r0
-	and #255, r0
-	cmp/eq r0, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movb9.cgs b/sim/testsuite/sim/sh64/compact/movb9.cgs
deleted file mode 100644
index 3ad1b46f2c0..00000000000
--- a/sim/testsuite/sim/sh64/compact/movb9.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	ldc r0, gbr
-	# Store something there first.
-	mov #0, r0
-	or #170, r0
-	mov r0, r7
-	mov.b r0, @(3, gbr)
-	# Load it back.
-	mov.b @(3, gbr), r0
-	and #255, r0
-	cmp/eq r7, r0
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movcal.cgs b/sim/testsuite/sim/sh64/compact/movcal.cgs
deleted file mode 100644
index 7aac57e7f43..00000000000
--- a/sim/testsuite/sim/sh64/compact/movcal.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for movca.l r0, @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global movcal
-movcal:
-	mov #1, r0
-	rotr r0
-	add #128, r0
-	mov #40, r1
-	shll8 r1
-	movca.l r0, @r1
-
-	# Load the word back in.
-	mov.l @r1, r3
-	cmp/eq r0, r3
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movi.cgs b/sim/testsuite/sim/sh64/compact/movi.cgs
deleted file mode 100644
index bc72c1b8e63..00000000000
--- a/sim/testsuite/sim/sh64/compact/movi.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for mov #$imm8, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global movi
-movi:
-	mov #0, r0
-	cmp/eq #0, r0
-	bf wrong
-	
-	mov #1, r0
-	cmp/eq #1, r0
-	bf wrong
-	
-	mov #255, r0
-	cmp/eq #255, r0
-	bf wrong
-
-	mov #1, r15
-	mov #1, r0
-	cmp/eq r0, r15
-	bf wrong
-
-	mov #255, r15
-	mov r15, r0
-	cmp/eq r0, r15
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movl1.cgs b/sim/testsuite/sim/sh64/compact/movl1.cgs
deleted file mode 100644
index 7d85c380f3e..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl1.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for mov.l $rm, @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-
-	mov.l r2, @r1
-
-	# Load it back.
-	mov.l @r1, r3
-	cmp/eq r2, r3
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl10.cgs b/sim/testsuite/sim/sh64/compact/movl10.cgs
deleted file mode 100644
index 5e9cf2d2fbd..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl10.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for mov.l @($imm8x4, pc), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-
-	# Store to memory.
-	mov #16, r1
-	shll8 r1
-	add #32, r1
-	mov.l r2, @r1
-check:
-	# Read it back.
-	mov.l @(12, pc), r0
-	cmp/eq r2, r0
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl11.cgs b/sim/testsuite/sim/sh64/compact/movl11.cgs
deleted file mode 100644
index 32c763d8a2e..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl11.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for mov.l @($imm4x4, $rm), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-	# Store something first.
-	mov.l r2, @(12, r0)
-
-check:
-	# Read it back.
-	mov.l @(12, r0), r1
-	cmp/eq r2, r1
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movl2.cgs b/sim/testsuite/sim/sh64/compact/movl2.cgs
deleted file mode 100644
index bb550612cce..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl2.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for mov.l $rm, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r1
-	shll8 r1
-	# Save address.
-	mov r1, r7
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-	mov.l r2, @-r1
-
-check:
-	# Compare the value loaded into another reg.
-	mov.l @r1, r3
-	cmp/eq r2, r3
-	bf wrong
-	
-dec:
-	# Ensure address is decremented.
-	mov #4, r6
-	sub r6, r7
-	cmp/eq r1, r7
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl3.cgs b/sim/testsuite/sim/sh64/compact/movl3.cgs
deleted file mode 100644
index 6205de7558d..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl3.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for mov.l $rm, @(r0, $rn)
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-setaddr:
-	mov #0, r0
-	mov #30, r1
-	shll8 r1
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	shll8 r2
-	add #85, r2
-	shll8 r2
-	add #170, r2
-
-	mov.l r2, @(r0, r1)
-
-check:
-	# Load it back.
-	mov.l @(r0, r1), r3
-	cmp/eq r2, r3
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl4.cgs b/sim/testsuite/sim/sh64/compact/movl4.cgs
deleted file mode 100644
index 44440946365..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl4.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# sh testcase for mov.l r0, @($imm8x4, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-setaddr:
-	mov #30, r1
-	shll8 r1
-	ldc r1, gbr
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #170, r0
-	# Preserve.
-	mov r0, r7
-
-	mov.l r0, @(4, gbr)
-check:
-	# Load it back.
-	mov.l @(4, gbr), r0
-	cmp/eq r0, r7
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/movl5.cgs b/sim/testsuite/sim/sh64/compact/movl5.cgs
deleted file mode 100644
index 897ebef2367..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl5.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for mov.l $rm, @($imm4x4, $rn) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-setaddr:
-	mov #30, r1
-	shll8 r1
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #170, r0
-	# Preserve.
-	mov r0, r7
-
-	mov.l r0, @(4, r1)
-check:
-	# Load it back.
-	mov.l @(4, r1), r0
-	cmp/eq r7, r0
-	bf wrong
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl6.cgs b/sim/testsuite/sim/sh64/compact/movl6.cgs
deleted file mode 100644
index 42f63b2a9ac..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl6.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# sh testcase for mov.l @$rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r0
-	shll8 r0
-	# Store something there first.
-	mov #170, r1
-	mov.l r1, @r0
-check:	
-	# Load it back.
-	mov.l @r0, r3
-	cmp/eq r1, r3
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movl7.cgs b/sim/testsuite/sim/sh64/compact/movl7.cgs
deleted file mode 100644
index b6c12fc5515..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl7.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for mov.l @$rm+, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r0
-	shll8 r0
-	# Preserve address.
-	mov r0, r7
-	# Store something first.
-	mov #170, r3
-	mov.l r3, @r0
-	
-	mov.l @r0+, r1
-check:
-	cmp/eq r1, r3
-	bf wrong
-
-	# Ensure address is post-incremented.
-	add #4, r7
-	cmp/eq r7, r0
-	bf wrong
-
-equal:	
-	# Test rm = rn.
-	mov #30, r0
-	shll8 r0
-	mov.l @r0+, r0
-
-okay:	
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl8.cgs b/sim/testsuite/sim/sh64/compact/movl8.cgs
deleted file mode 100644
index a6cd932d0a2..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl8.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for mov.l @(r0, $rm), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #0, r0
-	mov #30, r1
-	shll8 r1
-	# Store something there first.
-	mov #170, r3
-	mov.l r3, @(r0, r1)
-check:	
-	# Load it back.
-	mov.l @(r0, r1), r2
-	cmp/eq r2, r3
-	bf wrong
-
-okay:	
-	pass
-wrong:	
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movl9.cgs b/sim/testsuite/sim/sh64/compact/movl9.cgs
deleted file mode 100644
index 4fa07b069d8..00000000000
--- a/sim/testsuite/sim/sh64/compact/movl9.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for mov.l @($imm8x4, gbr), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-	ldc r1, gbr
-	# Store something there first.
-	mov #170, r0
-	mov r0, r7
-	mov.l r0, @(12, gbr)
-check:	
-	# Load it back.
-	mov.l @(12, gbr), r0
-	cmp/eq r0, r7
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movt.cgs b/sim/testsuite/sim/sh64/compact/movt.cgs
deleted file mode 100644
index 45539810beb..00000000000
--- a/sim/testsuite/sim/sh64/compact/movt.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for movt $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global movt
-init:
-	sett
-	movt r1
-	assert r1, #1
-clear:
-	clrt
-	movt r1
-	assert r1, #0
-set:
-	sett
-	movt r1
-	assert r1, #1
-
-okay:
-	pass
-wrong:
-	fail
-	 
diff --git a/sim/testsuite/sim/sh64/compact/movw1.cgs b/sim/testsuite/sim/sh64/compact/movw1.cgs
deleted file mode 100644
index 5d55a581ffd..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw1.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for mov.w $rm, @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r1
-	shll8 r1
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	mov.w r2, @r1
-check:
-	# Read it back.
-	mov.w @r1, r3
-	shll16 r2
-	shll16 r3
-	cmp/eq r2, r3
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movw10.cgs b/sim/testsuite/sim/sh64/compact/movw10.cgs
deleted file mode 100644
index 5bab9117e9e..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw10.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for mov.w @($imm8x2, pc), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-
-	# Store to memory.
-	mov #16, r1
-	shll8 r1
-	add #32, r1
-	mov.w r2, @r1
-
-check:
-	# Read it back.
-	mov.w @(18, pc), r0
-	shll16 r0
-	shll16 r2
-	cmp/eq r0, r2
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movw11.cgs b/sim/testsuite/sim/sh64/compact/movw11.cgs
deleted file mode 100644
index df739fa783d..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw11.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for mov.w @($imm4x2, $rm), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-
-	# Preserve r0.
-	mov r0, r3
-
-	# Store something first.
-	mov.w r0, @(12, r1)
-
-check:
-	# Read it back.
-	mov.w @(12, r1), r0
-	shll16 r0
-	shll16 r3
-	cmp/eq r0, r3
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw2.cgs b/sim/testsuite/sim/sh64/compact/movw2.cgs
deleted file mode 100644
index 27c29dc0292..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw2.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for mov.w $rm, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r1
-	shll8 r1
-	# Preserve.
-	mov r1, r7
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-store:	
-	mov.w r2, @-r1
-check:
-	# Read it back.
-	mov.w @r1, r3
-	shll16 r2
-	shll16 r3
-	cmp/eq r2, r3
-	bf wrong
-dec:
-	add #2, r1
-	cmp/eq r7, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movw3.cgs b/sim/testsuite/sim/sh64/compact/movw3.cgs
deleted file mode 100644
index d7b39c81506..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw3.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #0, r0
-	mov #30, r1
-	shll8 r1
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	mov.w r2, @(r0, r1)
-check:
-	# Read it back.
-	mov.w @(r0, r1), r3
-	shll16 r2
-	shll16 r3
-	cmp/eq r2, r3
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw4.cgs b/sim/testsuite/sim/sh64/compact/movw4.cgs
deleted file mode 100644
index 4853b5019bc..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw4.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for mov.w r0, @($imm8x2, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	mov #30, r0
-	shll8 r0
-	ldc r0, gbr
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	# Preserve r0.
-	mov r0, r7
-	mov.w r0, @(12, gbr)
-check:
-	mov.w @(12, gbr), r0
-	cmp/eq r0, r7
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw5.cgs b/sim/testsuite/sim/sh64/compact/movw5.cgs
deleted file mode 100644
index 9b4f84f6516..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw5.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for mov.w r0, @($imm4x2, $rn) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r1
-	shll8 r1
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	# Preserve.
-	mov r0, r7
-move:
-	mov.w r0, @(12, r1)
-check:
-	mov.w @(12, r1), r0
-	shll16 r0
-	shll16 r7
-	cmp/eq r0, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw6.cgs b/sim/testsuite/sim/sh64/compact/movw6.cgs
deleted file mode 100644
index 758497c13e7..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw6.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for mov.w @$rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	
-	mov #30, r0
-	shll8 r0
-
-	# Store something first.
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	mov.w r2, @r0
-
-check:
-	# Read it back.
-	mov.w @r0, r1
-	cmp/eq r1, r2
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw7.cgs b/sim/testsuite/sim/sh64/compact/movw7.cgs
deleted file mode 100644
index 45f5c098e4e..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw7.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for mov.w @${rm}+, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	# Preserve address.
-	mov r0, r7
-
-	# Store something first.
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	mov.w r2, @r0
-check:
-	# Read it back.
-	mov.w @r0+, r3
-	cmp/eq r2, r3
-	bf wrong
-
-inc:	
-	# Ensure address is post-incremented.
-	add #2, r7
-	cmp/eq r0, r7
-	bf wrong
-	
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/movw8.cgs b/sim/testsuite/sim/sh64/compact/movw8.cgs
deleted file mode 100644
index 0a7ce3f346c..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw8.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for mov.w @(r0, $rm), $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	mov #10, r1
-
-	# Store something first.
-	# Build up a distinctive bit pattern.
-	mov #1, r2
-	shll8 r2
-	add #12, r2
-	
-	mov.w r2, @(r0, r1)
-check:
-	# Read it back.
-	mov.w @(r0, r1), r3
-	shll16 r2
-	shll16 r3
-	cmp/eq r2, r3
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/movw9.cgs b/sim/testsuite/sim/sh64/compact/movw9.cgs
deleted file mode 100644
index 1872f06afb6..00000000000
--- a/sim/testsuite/sim/sh64/compact/movw9.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# sh testcase for mov.w @($imm8x2, gbr), r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	mov #30, r0
-	shll8 r0
-	ldc r0, gbr
-
-	# Store something first.
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	# Preserve r0.
-	mov r0, r7
-	mov.w r0, @(12, gbr)
-
-check:	
-	# Load it back.
-	mov.w @(12, gbr), r0
-	shll16 r0
-	shll16 r7
-	cmp/eq r0, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/mull.cgs b/sim/testsuite/sim/sh64/compact/mull.cgs
deleted file mode 100644
index 921141aafd6..00000000000
--- a/sim/testsuite/sim/sh64/compact/mull.cgs
+++ /dev/null
@@ -1,64 +0,0 @@
-# sh testcase for mul.l $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global mull
-mull:
-	mov #3, r0
-	mov #5, r1
-	mul.l r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #15, r4
-	cmp/eq r3, r4
-	bf wrong
-
-lxs:
-	# Large * small.
-	mov #255, r0
-	mov #0, r1
-	mul.l r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #0, r4
-	cmp/eq r3, r4
-	bf wrong
-
-sxl:
-	# Small * large.
-	mov #0, r0
-	mov #255, r1
-	mul.l r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #0, r4
-	cmp/eq r3, r4
-	bf wrong
-
-lxl:
-	# Large * large.
-	mov #1, r0
-	neg r0, r0
-	mov #2, r1
-	mul.l r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #2, r4
-	neg r4, r4
-	cmp/eq r3, r4
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/mulsw.cgs b/sim/testsuite/sim/sh64/compact/mulsw.cgs
deleted file mode 100644
index 05c8a3d384c..00000000000
--- a/sim/testsuite/sim/sh64/compact/mulsw.cgs
+++ /dev/null
@@ -1,91 +0,0 @@
-# sh testcase for muls.w $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	sts mach, r7
-	
-	.global mulsw
-zero:
-	mov #0, r0
-	mov #1, r1
-	muls.w r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #0, r4
-	cmp/eq r3, r4
-	bf wrong
-
-sxs:
-	# Small * small.
-	mov #1, r0
-	mov #2, r1
-	muls.w r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #2, r4
-	cmp/eq r3, r4
-	bf wrong
-
-sxl:
-	# Small * large.
-	mov #1, r0
-	mov #255, r1
-	shll8 r1
-	muls.w r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #0, r4
-	not r4, r4
-	shll8 r4
-	cmp/eq r3, r4
-	bf wrong
-
-lxs:
-	# Large * small.
-	mov #255, r0
-	shll8 r0
-	mov #1, r1
-	muls.w r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #0, r4
-	not r4, r4
-	shll8 r4
-	cmp/eq r3, r4
-	bf wrong
-	
-lxl:
-	# Large * large.
-	mov #255, r0
-	shll8 r0
-	mov #255, r1
-	shll8 r1
-	muls.w r0, r1
-
-	# Check the result.
-	sts macl, r3
-	mov #1, r4
-	shll16 r4
-	cmp/eq r3, r4
-	bf wrong
-	
-invariant:	
-	# Ensure MACH is invariant.
-	sts mach, r8
-	cmp/eq r7, r8
-	bf wrong
-	 
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/muluw.cgs b/sim/testsuite/sim/sh64/compact/muluw.cgs
deleted file mode 100644
index fa0a3343332..00000000000
--- a/sim/testsuite/sim/sh64/compact/muluw.cgs
+++ /dev/null
@@ -1,96 +0,0 @@
-# sh testcase for mulu.w $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	sts mach, r7
-
-	.global mulsw
-zero:
-	mov #0, r0
-	mov #1, r1
-	mulu.w r0, r1
-
-	# Check the result.
-	sts macl, r1
-	mov #0, r0
-	cmp/eq r0, r1
-	bf wrong
-
-sxs:
-	# Small * small.
-	mov #1, r0
-	mov #2, r1
-	mulu.w r0, r1
-
-	# Check the result.
-	sts macl, r1
-	mov #2, r0
-	cmp/eq r0, r1
-	bf wrong
-
-sxl:
-	# Small * large.
-	mov #1, r1
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	mulu.w r1, r0
-
-	# Check the result.
-	sts macl, r1
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	cmp/eq r0, r1
-	bf wrong
-
-lxs:
-	# Large * small.
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	mov #1, r1
-	mulu.w r0, r1
-
-	# Check the result.
-	sts macl, r1
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	cmp/eq r0, r1
-	bf wrong
-
-lxl:
-	# Large * large.
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	mov r0, r1
-	mulu.w r0, r1
-
-	# Check the result.
-	sts macl, r1
-	mov #0, r0
-	or #254, r0
-	shll8 r0
-	or #1, r0
-	shll16 r0
-	cmp/eq r0, r1
-	bf wrong
-
-invariant:
-	# Ensure MACH is invariant.
-	sts mach, r8
-	cmp/eq r7, r8
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/neg.cgs b/sim/testsuite/sim/sh64/compact/neg.cgs
deleted file mode 100644
index b6f98d74060..00000000000
--- a/sim/testsuite/sim/sh64/compact/neg.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for neg $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	.macro signbit sign
-	shlr16 r1
-	shlr8 r1
-	shlr r1
-	shlr r1
-	shlr r1
-	shlr r1
-	shlr r1
-	shlr r1
-	shlr r1
-	assert r1, \sign
-	.endm
-	start
-
-	.global neg
-neg:
-	mov #0, r0
-	neg r0, r1
-	signbit #0
-
-	mov #42, r0
-	neg r0, r1
-	signbit #1
-
-	mov #0, r0
-	or #25, r0
-	neg r0, r1
-	signbit #1
-
-	# neg(0) is 0.
-	mov #0, r0
-	neg r0, r1
-	signbit #0
-
-	# neg(neg(x)) = x.
-	mov #42, r0
-	neg r0, r1
-	signbit #1
-	mov #42, r0
-	neg r0, r2
-	neg r2, r1
-	signbit #0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/negc.cgs b/sim/testsuite/sim/sh64/compact/negc.cgs
deleted file mode 100644
index 1f5547d9bab..00000000000
--- a/sim/testsuite/sim/sh64/compact/negc.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# sh testcase for negc $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	.macro signbit sign
-	mov r1, r2
-	shlr16 r2
-	shlr8 r2
-	shlr r2
-	shlr r2
-	shlr r2
-	shlr r2
-	shlr r2
-	shlr r2
-	shlr r2
-	assert r2, \sign
-	.endm
-	start
-
-	.global negc
-negc:
-	clrt
-	mov #1, r0
-	negc r0, r1
-	signbit #1
-
-negc2:
-	sett
-	mov #1, r0
-	negc r0, r1
-	signbit #1
-
-negc3:
-	clrt
-	mov #0, r0
-	negc r0, r1
-	signbit #0
-
-negc4:
-	sett
-	mov #0, r0
-	negc r0, r1
-	signbit #1
-
-negc5:
-	clrt
-	mov #0, r0
-	or #255, r0
-	negc r0, r1
-	signbit #1
-
-negc6:
-	sett
-	mov #0, r0
-	or #255, r0
-	negc r0, r1
-	signbit #1
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/nop.cgs b/sim/testsuite/sim/sh64/compact/nop.cgs
deleted file mode 100644
index 8ce910c5abd..00000000000
--- a/sim/testsuite/sim/sh64/compact/nop.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for nop
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global nop
-nop:
-	nop
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/not.cgs b/sim/testsuite/sim/sh64/compact/not.cgs
deleted file mode 100644
index 380808ddb57..00000000000
--- a/sim/testsuite/sim/sh64/compact/not.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# sh testcase for not $rm64, $rn64 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global not
-not:
-	mov #0, r0
-	or #192, r0
-	not r0, r1
-
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #63, r0
-
-	cmp/eq r0, r1
-	bf wrong
-
-ones:
-	mov #0, r1
-	not r1, r2
-
-	mov #0, r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	shll8 r0
-	or #255, r0
-	cmp/eq r0, r2
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/ocbi.cgs b/sim/testsuite/sim/sh64/compact/ocbi.cgs
deleted file mode 100644
index 12fb2a116c4..00000000000
--- a/sim/testsuite/sim/sh64/compact/ocbi.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for ocbi @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-	.global ocbi
-ocbi:
-	ocbi @r0
-	ocbi @r1
-	ocbi @r15
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/ocbp.cgs b/sim/testsuite/sim/sh64/compact/ocbp.cgs
deleted file mode 100644
index 153aff2eade..00000000000
--- a/sim/testsuite/sim/sh64/compact/ocbp.cgs
+++ /dev/null
@@ -1,15 +0,0 @@
-# sh testcase for ocbp @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ocbp
-ocbp:
-	ocbp @r0
-	ocbp @r1
-	ocbp @r15
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/ocbwb.cgs b/sim/testsuite/sim/sh64/compact/ocbwb.cgs
deleted file mode 100644
index 6b0a741cbca..00000000000
--- a/sim/testsuite/sim/sh64/compact/ocbwb.cgs
+++ /dev/null
@@ -1,15 +0,0 @@
-# sh testcase for ocbwb @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ocbwb
-ocbwb:
-	ocbwb @r0
-	ocbwb @r1
-	ocbwb @r15
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/or.cgs b/sim/testsuite/sim/sh64/compact/or.cgs
deleted file mode 100644
index a02eee39aaf..00000000000
--- a/sim/testsuite/sim/sh64/compact/or.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for or $rm64, $rn64 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global or
-or:
-	mov #1, r0
-	rotr r0
-	mov #1, r1
-	or r0, r1
-
-	mov #1, r7
-	rotr r7
-	add #1, r7
-	cmp/eq r7, r1
-	bf wrong
-
-	.global or2
-or2:
-	mov #85, r0
-	shll16 r0
-	shll8 r0
-	mov #85, r1
-	shll8 r1
-	or r0, r1
-
-	mov #85, r7
-	shll16 r7
-	add #85 ,r7
-	shll8 r7
-	cmp/eq r1, r7
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/orb.cgs b/sim/testsuite/sim/sh64/compact/orb.cgs
deleted file mode 100644
index 7e962f6fe69..00000000000
--- a/sim/testsuite/sim/sh64/compact/orb.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for or.b #$imm8, @(r0, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global orb
-init:
-	# Init GBR and R0.
-	mov #30, r0
-	ldc r0, gbr	
-	mov #40, r0
-
-orb:
-	or.b #0, @(r0, gbr)
-	or.b #170, @(r0, gbr)
-	or.b #0, @(r0, gbr)
-	or.b #255, @(r0, gbr)
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/ori.cgs b/sim/testsuite/sim/sh64/compact/ori.cgs
deleted file mode 100644
index 63a5fb58740..00000000000
--- a/sim/testsuite/sim/sh64/compact/ori.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for or #$imm8, r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global ori
-ori:
-	mov #1, r0
-	rotr r0
-	or #1, r0
-
-	mov #1, r7
-	rotr r7
-	add #1, r7
-	cmp/eq r0, r7
-	bf wrong
-
-	.global ori2
-ori2:
-	mov #85, r0
-	shll16 r0
-	shll8 r0
-	or #85, r0
-
-	mov #85, r7
-	shll16 r7
-	shll8 r7
-	add #85, r7
-	cmp/eq r0, r7
-	bf wrong
-
-okay:
-	pass
-	
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/pref.cgs b/sim/testsuite/sim/sh64/compact/pref.cgs
deleted file mode 100644
index 065e0932e6c..00000000000
--- a/sim/testsuite/sim/sh64/compact/pref.cgs
+++ /dev/null
@@ -1,15 +0,0 @@
-# sh testcase for pref @$rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global pref
-pref:
-	pref @r0
-	pref @r1
-	pref @r15
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/rotcl.cgs b/sim/testsuite/sim/sh64/compact/rotcl.cgs
deleted file mode 100644
index 5e1a3b91137..00000000000
--- a/sim/testsuite/sim/sh64/compact/rotcl.cgs
+++ /dev/null
@@ -1,121 +0,0 @@
-# sh testcase for rotcl $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global rotcl
-
-rotcl:
-	clrt
-	mov #1, r1
-	rotcl r1
-	assert r1, #2
-	clrt
-	rotcl r1
-	assert r1, #4
-	clrt
-	rotcl r1
-	assert r1, #8
-	clrt
-	rotcl r1
-	assert r1, #16
-	clrt
-	rotcl r1
-	assert r1, #32
-	clrt
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	bf wrong
-	rotcl r1
-	assert r1, #1
-
-	bra trotcl
-	nop
-
-wrong:
-	fail
-
-trotcl:
-	sett
-	mov #1, r1
-	rotcl r1
-	assert r1, #3
-	clrt
-	rotcl r1
-	assert r1, #6
-	clrt
-	rotcl r1
-	assert r1, #12
-	clrt
-	rotcl r1
-	assert r1, #24
-	clrt
-	rotcl r1
-	assert r1, #48
-	clrt
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	rotcl r1
-	bf wrong2
-	assert r1, #1
-	rotcl r1
-	rotcl r1
-
-okay:	
-	pass
-wrong2:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/rotcr.cgs b/sim/testsuite/sim/sh64/compact/rotcr.cgs
deleted file mode 100644
index b53300ec54f..00000000000
--- a/sim/testsuite/sim/sh64/compact/rotcr.cgs
+++ /dev/null
@@ -1,103 +0,0 @@
-# sh testcase for rotcr $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global rotcr
-rotcr:
-	clrt
-	mov #1, r1
-	rotcr r1
-	bf wrong
-	assert r1, #0
-	sett
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	assert r1, #1
-	rotcr r1
-	bf wrong
-
-trotcr:
-	sett
-	mov #1, r1
-	rotcr r1
-	bf wrong
-	sett
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	rotcr r1
-	bf wrong
-	assert r1, #1
-	rotcr r1
-	bf wrong
-	rotcr r1
-
-okay:	
-	pass
-wrong:
-	fail
-	
-
diff --git a/sim/testsuite/sim/sh64/compact/rotl.cgs b/sim/testsuite/sim/sh64/compact/rotl.cgs
deleted file mode 100644
index e292de7e437..00000000000
--- a/sim/testsuite/sim/sh64/compact/rotl.cgs
+++ /dev/null
@@ -1,62 +0,0 @@
-# sh testcase for rotl $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global rotl
-rotl:
-	mov #1, r1
-	rotl r1
-	assert r1, #2
-	rotl r1
-	assert r1, #4
-	rotl r1
-	assert r1, #8
-	rotl r1
-	assert r1, #16
-	rotl r1
-	assert r1, #32
-	rotl r1
-	assert r1, #64
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	rotl r1
-	bf wrong
-	assert r1, #1
-	rotl r1
-	rotl r1
-	rotl r1
-	assert r1, #8
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/rotr.cgs b/sim/testsuite/sim/sh64/compact/rotr.cgs
deleted file mode 100644
index 7f80f993aea..00000000000
--- a/sim/testsuite/sim/sh64/compact/rotr.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for rotr $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global rotr
-rotr:
-	mov #1, r1
-	rotr r1
-	bf wrong
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	rotr r1
-	assert r1, #1
-	rotr r1
-	rotr r1
-	rotr r1
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/rts.cgs b/sim/testsuite/sim/sh64/compact/rts.cgs
deleted file mode 100644
index eeb8dce9332..00000000000
--- a/sim/testsuite/sim/sh64/compact/rts.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for rts -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global rts
-rts:
-	bsr subroutine
-slot:
-	nop
-return:
-	pass
-	fail
-
-subroutine:
-	rts
-rts_slot:
-	nop
-bad:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/sets.cgs b/sim/testsuite/sim/sh64/compact/sets.cgs
deleted file mode 100644
index f031701d6ee..00000000000
--- a/sim/testsuite/sim/sh64/compact/sets.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for sets -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sets
-sets:
-	sets
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/sett.cgs b/sim/testsuite/sim/sh64/compact/sett.cgs
deleted file mode 100644
index 9ae8af536e7..00000000000
--- a/sim/testsuite/sim/sh64/compact/sett.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# sh testcase for sett -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sett
-sett:
-	sett
-	bf wrong
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shad.cgs b/sim/testsuite/sim/sh64/compact/shad.cgs
deleted file mode 100644
index 340743d8f1f..00000000000
--- a/sim/testsuite/sim/sh64/compact/shad.cgs
+++ /dev/null
@@ -1,58 +0,0 @@
-# sh testcase for shad $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global null
-null:
-	mov #1, r0
-	mov #0, r1
-	shad r1, r0
-	# no shift is performed.
-	assert r0, #1
-
-	.global gt0
-gt0:
-	mov #4, r0
-	mov #3, r1
-	shad r1, r0
-	# shift left 3 bits.
-	assert r0, #32
-
-	.global lt0
-lt0:
-	mov #32, r0
-	mov #3, r1
-	neg r1, r1
-	shad r1, r0
-	# shift right 3 bits.
-	assert r0, #4
-
-	.global fillpos
-fillpos:
-	mov #1, r0
-	mov #1, r1
-	rotr r1
-	shad r1, r0
-	# check result.
-	assert r0, #0
-
-	.global fillneg
-fillneg:
-	mov #1, r0
-	neg r0, r0
-	mov #1, r1
-	rotr r1
-	shad r1, r0
-	# check result.
-	not r0, r0
-	assert r0, #0
-	
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shal.cgs b/sim/testsuite/sim/sh64/compact/shal.cgs
deleted file mode 100644
index dfea947e856..00000000000
--- a/sim/testsuite/sim/sh64/compact/shal.cgs
+++ /dev/null
@@ -1,57 +0,0 @@
-# sh testcase for shal $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shal
-shal:
-	mov #1, r1
-	shal r1
-	assert r1, #2
-	shal r1
-	assert r1, #4
-	shal r1
-	assert r1, #8
-	shal r1
-	assert r1, #16
-	shal r1
-	assert r1, #32
-	shal r1
-	assert r1, #64
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	shal r1
-	assert r1, #0
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/shar.cgs b/sim/testsuite/sim/sh64/compact/shar.cgs
deleted file mode 100644
index e3e92fca080..00000000000
--- a/sim/testsuite/sim/sh64/compact/shar.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for shar $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shar
-shar:
-	mov #0, r0
-	or #192, r0
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	shar r0
-	bf wrong
-	shar r0
-	bf wrong
-	shar r0
-	bt wrong
-	shar r0
-	bt wrong
-	assert r0, #0
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/shld.cgs b/sim/testsuite/sim/sh64/compact/shld.cgs
deleted file mode 100644
index 32e4100259d..00000000000
--- a/sim/testsuite/sim/sh64/compact/shld.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for shld $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global null
-null:
-	mov #1, r0
-	mov #0, r1
-	shld r1, r0
-	# no shift is performed.
-	assert r0, #1
-
-	.global gt0
-gt0:
-	mov #4, r0
-	mov #3, r1
-	shld r1, r0
-	# shift left 3 bits.
-	assert r0, #32
-
-	.global lt0
-lt0:
-	mov #32, r0
-	mov #3, r1
-	neg r1, r1
-	shld r1, r0
-	# shift right 3 bits.
-	assert r0, #4
-
-	.global fill
-fill:
-	mov #1, r0
-	rotr r0
-	mov #1, r1
-	rotr r1
-	shld r1, r0
-	assert r0, #0
-	
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/shll.cgs b/sim/testsuite/sim/sh64/compact/shll.cgs
deleted file mode 100644
index 882f2c2e1ef..00000000000
--- a/sim/testsuite/sim/sh64/compact/shll.cgs
+++ /dev/null
@@ -1,57 +0,0 @@
-# sh testcase for shll $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shll
-shll:
-	mov #1, r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	shll r1
-	assert r1, #0
-another:
-	mov #1, r1
-	shll r1
-	shll r1
-	shll r1
-	assert r1, #8
-
-okay:	
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shll16.cgs b/sim/testsuite/sim/sh64/compact/shll16.cgs
deleted file mode 100644
index 0637c3de706..00000000000
--- a/sim/testsuite/sim/sh64/compact/shll16.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# sh testcase for shll16 $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shll16
-shll16:
-	mov #108, r1
-	shll16 r1
-	shll16 r1
-	assert r1, #0
-
-another:
-	mov #1, r1
-	shll16 r1
-	mov #1, r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	cmp/eq r1, r7
-	bf wrong
-		
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shll2.cgs b/sim/testsuite/sim/sh64/compact/shll2.cgs
deleted file mode 100644
index 6e28c664307..00000000000
--- a/sim/testsuite/sim/sh64/compact/shll2.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for shll2 $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shll2
-shll2:
-	mov #1, r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	shll2 r1
-	assert r1, #0
-
-another:
-	mov #1, r1
-	shll2 r1
-	assert r1, #4
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shll8.cgs b/sim/testsuite/sim/sh64/compact/shll8.cgs
deleted file mode 100644
index fe455ec753d..00000000000
--- a/sim/testsuite/sim/sh64/compact/shll8.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# sh testcase for shll8 $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shll8
-shll8:
-	mov #1, r1
-	shll8 r1
-	shll8 r1
-	shll8 r1
-	shll8 r1
-	assert r1, #0
-
-another:
-	mov #1, r1
-	shll8 r1
-	mov #1, r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	shll r7
-	cmp/eq r1, r7
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shlr.cgs b/sim/testsuite/sim/sh64/compact/shlr.cgs
deleted file mode 100644
index 9d86461b959..00000000000
--- a/sim/testsuite/sim/sh64/compact/shlr.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# sh testcase for shlr $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shlr
-shlr:
-	mov #0, r0
-	or #192, r0
-	shlr r0
-	shlr r0
-	shlr r0
-	shlr r0
-	shlr r0
-	shlr r0
-	# Make sure a bit is shifted into T.
-	shlr r0
-	bf wrong
-	# Ditto.
-	shlr r0
-	bf wrong
-	shlr r0
-	assert r0, #0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/shlr16.cgs b/sim/testsuite/sim/sh64/compact/shlr16.cgs
deleted file mode 100644
index 7bfc62788f3..00000000000
--- a/sim/testsuite/sim/sh64/compact/shlr16.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for shlr16 $rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shrl16
-shrl16:
-	shlr16 r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/shlr2.cgs b/sim/testsuite/sim/sh64/compact/shlr2.cgs
deleted file mode 100644
index 6f085979443..00000000000
--- a/sim/testsuite/sim/sh64/compact/shlr2.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for shlr2 $rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shrl2
-shrl2:
-	shlr2 r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/shlr8.cgs b/sim/testsuite/sim/sh64/compact/shlr8.cgs
deleted file mode 100644
index 82040b581b8..00000000000
--- a/sim/testsuite/sim/sh64/compact/shlr8.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for shlr8 $rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global shrl8
-shrl8:
-	shlr8 r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs
deleted file mode 100644
index 1b84008c9d2..00000000000
--- a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for stc gbr, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stc_gbr
-stc_gbr:
-	stc gbr, r1
-	mov #42, r1
-	ldc r1, gbr
-	stc gbr, r2
-	cmp/eq r1, r2
-	bf wrong
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
deleted file mode 100644
index 3e74cc551de..00000000000
--- a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for stc.l gbr, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stcl_gbr
-stcl_gbr:
-	mov #42, r0
-	ldc r0, gbr
-	mov #40, r0
-	shll8 r0
-	# save address
-	mov r0, r1
-	stc.l gbr, @-r0
-
-	add #4, r0
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
deleted file mode 100644
index 42724b44fff..00000000000
--- a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for sts fpscr, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sts_fpscr
-sts_fpscr:
-	sts fpscr, r0
-	mov #42, r0
-	lds r0, fpscr
-	sts fpscr, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-
diff --git a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs
deleted file mode 100644
index ddbdaf15fb2..00000000000
--- a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for sts fpul, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sts_fpul
-sts_fpul:
-	# This is properly exercised by the lds-fpul test case.
-	sts fpul, r1
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/sts-mach.cgs b/sim/testsuite/sim/sh64/compact/sts-mach.cgs
deleted file mode 100644
index 4d34bc17aa8..00000000000
--- a/sim/testsuite/sim/sh64/compact/sts-mach.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for sts mach, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sts_mach
-sts_mach:
-	mov #42, r0
-	lds r0, mach
-	sts mach, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/sts-macl.cgs b/sim/testsuite/sim/sh64/compact/sts-macl.cgs
deleted file mode 100644
index b805f796e44..00000000000
--- a/sim/testsuite/sim/sh64/compact/sts-macl.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for sts macl, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sts_macl
-sts_macl:
-	mov #42, r0
-	lds r0, macl
-	sts macl, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/sts-pr.cgs b/sim/testsuite/sim/sh64/compact/sts-pr.cgs
deleted file mode 100644
index 3e4f6ee880a..00000000000
--- a/sim/testsuite/sim/sh64/compact/sts-pr.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for sts pr, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sts_pr
-sts_pr:
-	mov #42, r0
-	lds r0, pr
-	sts pr, r1
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
deleted file mode 100644
index 032870dc189..00000000000
--- a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for sts.l fpscr, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stsl_fpscr
-stsl_fpscr:
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r7
-	sts.l fpscr, @-r0
-
-check:
-	# Ensure r0 is decremented.
-	add #4, r0
-	cmp/eq r0, r7
-	bf wrong
-
-okay:	
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
deleted file mode 100644
index 89bd9e73849..00000000000
--- a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for sts.l fpul, @-$rn -*- Asm -*_
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stsl_fpul
-stsl_fpul:
-	mov #40, r0
-	shll8 r0
-	# Preserve r0.
-	mov r0, r7
-	sts.l fpul, @-r0
-
-dec:
-	# Check for proper pre-decrementing.
-	add #4, r0
-	cmp/eq r0, r7
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs
deleted file mode 100644
index e15bddece29..00000000000
--- a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for sts.l mach, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stsl_mach
-stsl_mach:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #170, r0
-	
-	lds r0, mach
-	mov #40, r2
-	shll8 r2
-	# Preserve r2.
-	mov r2, r7
-	sts.l mach, @-r2
-
-	# check results.
-	mov.l @r2, r3
-	cmp/eq r0, r3
-	bf wrong
-
-	# Ensure decrement occurred.
-	add #4, r2
-	cmp/eq r2, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs
deleted file mode 100644
index 854ef341552..00000000000
--- a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for sts.l macl, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stsl_macl
-stsl_macl:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #170, r0
-	
-	lds r0, macl
-	mov #40, r2
-	shll8 r2
-	# Preserve r2.
-	mov r2, r7
-	sts.l macl, @-r2
-
-	# check results.
-	mov.l @r2, r3
-	cmp/eq r0, r3
-	bf wrong
-
-	# Ensure decrement occurred.
-	add #4, r2
-	cmp/eq r2, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs
deleted file mode 100644
index b519c9bb5bd..00000000000
--- a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for sts.l pr, @-$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global stsl_pr
-stsl_pr:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #170, r0
-	
-	lds r0, pr
-	mov #40, r2
-	shll8 r2
-	# Preserve r2.
-	mov r2, r7
-	sts.l pr, @-r2
-
-	# check results.
-	mov.l @r2, r3
-	cmp/eq r0, r3
-	bf wrong
-
-	# Ensure decrement occurred.
-	add #4, r2
-	cmp/eq r2, r7
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/sub.cgs b/sim/testsuite/sim/sh64/compact/sub.cgs
deleted file mode 100644
index 3ba29f872aa..00000000000
--- a/sim/testsuite/sim/sh64/compact/sub.cgs
+++ /dev/null
@@ -1,68 +0,0 @@
-# sh testcase for sub $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global sub1
-sub1:
-	# 0 - x.
-	mov #0, r0
-	mov #3, r1
-	sub r1, r0
-
-	mov #2, r7
-	not r7, r7
-	cmp/eq r7, r0
-	bf wrong
-
-	.global sub2
-sub2:
-	# x - 0.
-	mov #0, r0
-	mov #3, r1
-	sub r0, r1
-	assert r1, #3
-
-	.global sub3
-sub3:
-	# x - y.
-	mov #4, r0
-	mov #3, r1
-	sub r0, r1
-
-	mov #0, r7
-	not r7, r7
-	cmp/eq r7, r1
-	bf wrong
-
-	.global sub4
-sub4:
-	# y - x.
-	mov #4, r0
-	mov #3, r1
-	sub r1, r0
-	assert r0, #1
-	
-	.global sub5
-sub5:
-	# y - y == 0 (where y are in two distinct registers).
-	mov #4, r0
-	mov #4, r1
-	sub r1, r0
-	assert r0, #0
-
-	.global sub6
-sub6:
-	# y - y = 0 (where y is the same register).
-	mov #4, r1
-	sub r1, r1
-	assert r1, #0
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/subc.cgs b/sim/testsuite/sim/sh64/compact/subc.cgs
deleted file mode 100644
index cda1e84ae9d..00000000000
--- a/sim/testsuite/sim/sh64/compact/subc.cgs
+++ /dev/null
@@ -1,109 +0,0 @@
-# sh testcase for subc $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-zero:
-	mov #0, r0
-	mov #0, r1
-	clrt
-	subc r0, r1
-	assert r1, #0
-
-zerot:
-	mov #0, r0
-	mov #0, r1
-	sett
-	subc r0, r1
-	# Invert all 1's to all 0's for ease of comparison.
-	not r1, r1
-	assert r1, #0
-
-null:
-	mov #0, r0
-	mov #10, r1
-	clrt
-	subc r0, r1
-	assert r1, #10
-
-nullt:
-	mov #0, r0
-	mov #10, r1
-	sett
-	subc r0, r1
-	assert r1, #9
-
-subc:
-	mov #10, r0
-	mov #0, r1
-	clrt
-	subc r0, r1
-	# Again, invert ..
-	not r1, r1
-	assert r1, #9
-
-subct:
-	mov #10, r0
-	mov #0, r1
-	sett
-	subc r0, r1
-	# Again, invert ..
-	not r1, r1
-	assert r1, #10
-
-subc2:
-	mov #10, r0
-	mov #20, r1
-	clrt
-	subc r0, r1
-	assert r1, #10
-
-subc2t:
-	mov #20, r0
-	mov #10, r1
-	sett
-	subc r0, r1
-	# Again, invert ..
-	not r1, r1
-	assert r1, #10
-
-subc3:
-	mov #5, r0
-	mov #5, r1
-	clrt
-	subc r0, r1
-	assert r1, #0
-
-subc3t:
-	mov #5, r0
-	mov #5, r1
-	sett
-	subc r0, r1
-	# Again, invert ..
-	not r1, r1
-	assert r1, #0
-	
-large:
-	mov #2, r0
-	mov #10, r1
-	clrt
-	subc r1, r0
-	# Again, invert ..
-	not r0, r0
-	assert r0, #7
-
-larget:
-	mov #2, r0
-	mov #10, r1
-	sett
-	subc r0, r1
-	assert r1, #7
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/subv.cgs b/sim/testsuite/sim/sh64/compact/subv.cgs
deleted file mode 100644
index ceb8c64e7fd..00000000000
--- a/sim/testsuite/sim/sh64/compact/subv.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for subv $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-zero:
-	mov #0, r0
-	mov #0, r1
-	subv r0, r1
-	bt wrong
-	assert r1, #0
-
-one:
-	mov #10, r0
-	mov #0, r1
-	subv r0, r1
-	bt wrong
-	not r1, r1
-	assert r1, #9
-
-large:
-	# Produce MAXINT in R0.
-	mov #0, r0
-	not r0, r0
-	shlr r0
-
-	# Put -3 into R1.
-	mov #3, r1
-	neg r1, r1
-
-	# Subtract them and underflow.
-	subv r0, r1
-	bf wrong
-
-another:
-	# Produce MAXINT in R0.
-	mov #0, r0
-	not r0, r0
-	shlr r0
-	
-	# Put -3 into R1.
-	mov #3, r1
-	neg r1, r1
-	
-	# Subtract them and overflow.
-	subv r1, r0
-	bf wrong
-		
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/swapb.cgs b/sim/testsuite/sim/sh64/compact/swapb.cgs
deleted file mode 100644
index 22f6f16a2e1..00000000000
--- a/sim/testsuite/sim/sh64/compact/swapb.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# sh testcase for swap.b $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-init:
-	# Build up a distinctive bit pattern.
-	mov #1, r0
-	shll8 r0
-	add #12, r0
-	shll8 r0
-	add #85, r0
-	shll8 r0
-	add #70, r0
-
-test:	
-	# Swap the lower two bytes into a different register.
-	swap.b r0, r1
-	mov #1, r7
-	shll8 r7
-	add #12, r7
-	shll8 r7
-	add #70, r7
-	shll8 r7
-	add #85, r7
-	cmp/eq r1, r7
-	bf wrong
-
-swapback:
-	# Swap the lower two bytes into the same registers.
-	# R0 should now equal R1.
-	swap.b r1, r2
-	cmp/eq r0, r2
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/swapw.cgs b/sim/testsuite/sim/sh64/compact/swapw.cgs
deleted file mode 100644
index fa1ab697f27..00000000000
--- a/sim/testsuite/sim/sh64/compact/swapw.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for swap.w $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global swapw
-swapw:
-	# Build up a characteristic bit pattern in R0.
-	mov #85, r0
-	shll16 r0
-	add #3, r0
-	rotr r0
-	rotr r0
-	or #170, r0
-	# Preserve for later.
-	mov r0, r8
-
-test:	
-	swap.w r0, r1
-	mov #64, r0
-	shll8 r0
-	or #170, r0
-	shll8 r0
-	or #192, r0
-	shll8 r0
-	or #21, r0
-	cmp/eq r1, r0
-	bf wrong
-
-swapback:
-	swap.w r1, r2
-	cmp/eq r2, r8
-	bf wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/tasb.cgs b/sim/testsuite/sim/sh64/compact/tasb.cgs
deleted file mode 100644
index cb7f61870d2..00000000000
--- a/sim/testsuite/sim/sh64/compact/tasb.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for tas.b @$rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-tasb1:
-	mov #40, r0
-	shll8 r0
-	tas.b @r0
-	bf wrong
-
-tasb2:
-	mov #40, r0
-	shll8 r0
-	tas.b @r0
-	bt wrong
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/testutils.inc b/sim/testsuite/sim/sh64/compact/testutils.inc
deleted file mode 100644
index b1ad830578b..00000000000
--- a/sim/testsuite/sim/sh64/compact/testutils.inc
+++ /dev/null
@@ -1,49 +0,0 @@
-# Support macros for the assembly test cases.
-
-	.macro start
-	.text
-	.global start
-start:
-	.endm
-
-	# Perform a single to double precision floating point conversion.
-	.macro _s2d fpr dpr
-	flds \fpr, fpul
-	_setpr
-	fcnvsd fpul, \dpr
-	_clrpr
-	.endm
-
-	# Set the PR (PRecision) bit in the FPSCR.
-	.macro _setpr
-	sts fpscr, r7
-	mov #8, r8
-	shll16 r8
-	or r8, r7
-	lds r7, fpscr
-	.endm
-
-	# Clear the PR bit.
-	.macro _clrpr
-	sts fpscr, r7
-	mov #8, r8
-	shll16 r8
-	not r8, r8
-	and r8, r7
-	lds r7, fpscr
-	.endm
-
-	# nb: this macro clobbers R7. 
-	.macro assert reg value
-	mov \value, r7
-	cmp/eq \reg, r7
-	bf wrong
-	.endm
-
-	.macro pass
-	trapa #253
-	.endm
-
-	.macro fail
-	trapa #254
-	.endm
diff --git a/sim/testsuite/sim/sh64/compact/trapa.cgs b/sim/testsuite/sim/sh64/compact/trapa.cgs
deleted file mode 100644
index 24f8a6b13ba..00000000000
--- a/sim/testsuite/sim/sh64/compact/trapa.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for trapa #$imm8 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global trapa
-trapa:
-	# pass is a macro for "trapa #253".
-	trapa #253
diff --git a/sim/testsuite/sim/sh64/compact/tst.cgs b/sim/testsuite/sim/sh64/compact/tst.cgs
deleted file mode 100644
index a72b8a9a743..00000000000
--- a/sim/testsuite/sim/sh64/compact/tst.cgs
+++ /dev/null
@@ -1,62 +0,0 @@
-# sh testcase for tst $rm, $rn
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global tst1
-tst1:
-	mov #0, r0
-	mov #0, r1
-	tst r0, r0
-	bf wrong
-
-test2:
-	mov #0, r0
-	mov #1, r1
-	tst r0, r1
-	bf wrong
-
-test3:
-	mov #0, r0
-	mov #1, r1
-	tst r1, r0
-	bf wrong
-
-test4:
-	mov #1, r0
-	mov #1, r1
-	tst r0, r1
-	bt wrong
-
-test5:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	shll16 r0
-	add #12, r0
-	mov #1, r1
-	rotr r1
-	add #85, r1
-	shll16 r1
-	add #12, r1
-	tst r0, r1
-	bt wrong
-
-test6:
-	mov #1, r0
-	rotr r0
-	add #85, r0
-	shll16 r0
-	add #12, r0
-	mov #1, r1
-	tst r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/tstb.cgs b/sim/testsuite/sim/sh64/compact/tstb.cgs
deleted file mode 100644
index 1b3829b1d30..00000000000
--- a/sim/testsuite/sim/sh64/compact/tstb.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for tst.b #$imm8, @(r0, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global orb
-init:
-	# Init GBR and R0.
-	mov #30, r0
-	ldc r0, gbr	
-	mov #40, r0
-
-orb:
-	tst.b #0, @(r0, gbr)
-	bf wrong
-	tst.b #170, @(r0, gbr)
-	bf wrong
-	tst.b #0, @(r0, gbr)
-	bf wrong
-	tst.b #255, @(r0, gbr)
-
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/compact/tsti.cgs b/sim/testsuite/sim/sh64/compact/tsti.cgs
deleted file mode 100644
index e088029b470..00000000000
--- a/sim/testsuite/sim/sh64/compact/tsti.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for tst #$imm8, r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global tsti
-tsti:
-	mov #0, r0
-	tst #0, r0
-
-tsti2:
-	mov #0, r0
-	tst #1, r0
-
-tsti3:
-	mov #1, r0
-	tst #0, r0
-
-tsti4:
-	mov #1, r0
-	tst #1, r0
-
-tsti5:
-	mov #255, r0
-	tst #255, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/xor.cgs b/sim/testsuite/sim/sh64/compact/xor.cgs
deleted file mode 100644
index d158aaf3713..00000000000
--- a/sim/testsuite/sim/sh64/compact/xor.cgs
+++ /dev/null
@@ -1,70 +0,0 @@
-# sh testcase for xor $rm64, $rn64 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global xor
-xor:
-	# 0 (+) 1 = 1.
-	mov #0, r0
-	mov #1, r1
-	xor r0, r1
-	assert r1, #1
-
-xor2:
-	# 1 (+) 0 = 0.
-	mov #1, r0
-	mov #0, r1
-	xor r0, r1
-	assert r1, #1
-
-xor3:
-	# 0 (+) 0 = 0.
-	mov #0, r0
-	mov #0, r1
-	xor r0, r1
-	assert r1, #0
-
-xor4:
-	# 0 (+) 0 = 0.
-	mov #0, r0
-	xor r0, r0
-	assert r0, #0
-
-xor5:
-	mov #0, r0
-	or #85, r0
-	shll16 r0
-	or #170, r0
-	mov r0, r1
-	mov #0, r0
-	or #85, r0
-	shll16 r0
-	or #170, r0
-	xor r1, r0
-	assert r0, #0
-
-xor6:
-	mov #0, r0
-	or #85, r0
-	shll16 r0
-	or #170, r0
-	mov r0, r1
-	mov #0, r0
-	or #85, r0
-	shll16 r0
-	or #12, r0
-	xor r0, r1
-	mov #0, r0
-	or #166, r0
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/xorb.cgs b/sim/testsuite/sim/sh64/compact/xorb.cgs
deleted file mode 100644
index b31464b3c13..00000000000
--- a/sim/testsuite/sim/sh64/compact/xorb.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for xor.b #$imm8, @(r0, gbr) -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global orb
-init:
-	# Init GBR and R0.
-	mov #30, r0
-	ldc r0, gbr	
-	mov #40, r0
-
-orb:
-	xor.b #0, @(r0, gbr)
-	xor.b #170, @(r0, gbr)
-	xor.b #0, @(r0, gbr)
-	xor.b #255, @(r0, gbr)
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/compact/xori.cgs b/sim/testsuite/sim/sh64/compact/xori.cgs
deleted file mode 100644
index 732b9ec5c48..00000000000
--- a/sim/testsuite/sim/sh64/compact/xori.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# sh testcase for xor #$imm8, r0 -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-	.global xori
-xori:
-	# 0 (+) 1 = 1.
-	mov #0, r0
-	xor #1, r0
-	assert r0, #1
-
-xori2:
-	# 1 (+) 0 = 1.
-	mov #1, r0
-	xor #0, r0
-	assert r0, #1
-
-xori3:
-	# 1 (+) 1 = 0.
-	mov #1, r0
-	xor #1, r0
-	assert r0, #0
-
-xori4:
-	# 255 (+) 255 = 0.
-	mov #0, r0
-	or #255, r0
-	xor #255, r0
-	assert r0, #0
-
-xori5:
-	# 0 (+) 255 = 255.
-	mov #0, r0
-	xor #255, r0
-	mov r0, r1
-
-	mov #0, r0
-	or #255, r0
-	cmp/eq r0, r1
-	bf wrong
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/compact/xtrct.cgs b/sim/testsuite/sim/sh64/compact/xtrct.cgs
deleted file mode 100644
index 11dae7cbdec..00000000000
--- a/sim/testsuite/sim/sh64/compact/xtrct.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for xtrct $rm, $rn -*- Asm -*-
-# mach: all
-# as: -isa=shcompact
-# ld: -m shelf32
-
-	.include "compact/testutils.inc"
-
-	start
-
-init:
-	mov #170, r0
-	shll8 r0
-	add #1, r0
-	shll8 r0
-	add #66, r0
-	shll8 r0
-	mov r0, r1
-
-	mov #85, r0
-	shll8 r0
-	add #2, r0
-	shll8 r0
-	add #42, r0
-	shll8 r0
-	add #3, r0
-
-copy:
-	mov r0, r3
-	mov r1, r4
-
-xtrct:
-	xtrct r0, r1
-
-check:
-	# Lower r3, upper r4.
-	shll16 r3
-	shlr16 r4
-	or r3, r4
-	cmp/eq r1, r4
-	bf wrong
-	
-okay:
-	pass
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/interwork.exp b/sim/testsuite/sim/sh64/interwork.exp
deleted file mode 100644
index acd19b3c90c..00000000000
--- a/sim/testsuite/sim/sh64/interwork.exp
+++ /dev/null
@@ -1,20 +0,0 @@
-# SH64 interworking testsuite.
-# In particular, test parts of the instruction set that can be used
-# for SHmedia/SHcompact instruction set mode switches.
-
-if [istarget sh64-*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "sh5"
-
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/misc/*.s]] {
-       # If we're only testing specific files and this isn't one of them,
-       # skip it.
-       if ![runtest_file_p $runtests $src] {
-  	  continue
-	}
-    run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/sh64/media.exp b/sim/testsuite/sim/sh64/media.exp
deleted file mode 100644
index 1a3d9f4c961..00000000000
--- a/sim/testsuite/sim/sh64/media.exp
+++ /dev/null
@@ -1,19 +0,0 @@
-# SHmedia testsuite.
-
-if [istarget sh64-*-*] {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "sh5"
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/media/*.cgs]] {
-       # If we're only testing specific files and this isn't one of them,
-       # skip it.
-       if ![runtest_file_p $runtests $src] {
-  	  continue
-	}
-    run_sim_test $src $all_machs
-    }
-}
diff --git a/sim/testsuite/sim/sh64/media/ChangeLog b/sim/testsuite/sim/sh64/media/ChangeLog
deleted file mode 100644
index e435dbe5278..00000000000
--- a/sim/testsuite/sim/sh64/media/ChangeLog
+++ /dev/null
@@ -1,102 +0,0 @@
-2001-01-09  Ben Elliston  <bje@redhat.com>
-
-	* nsb.cgs: Test consecutive bits of zeros as well as ones.
-	* ptb.cgs: Clean up.
-
-2001-01-08  Ben Elliston  <bje@redhat.com>
-
-	* fcmpund.cgs, fcmpuns.cgs: Complete test cases.
-	* fcnvds.cgs, fcnvsd.cgs, fgetscr.cgs, fiprs.cgs: Ditto.
-	* floatld.cgs, floatls.cgs, floatqd.cgs, floatqs.cgs: Ditto.
-	* fmuld.cgs, fmuls.cgs, fputscr.cgs, fstxp.cgs: Ditto.
-	* fsubd.cgs, fsubs.cgs, ftrcdl.cgs, ftrcdq.cgs: Ditto.
-	* ftrcsl.cgs, ftrcsq.cgs, ftrvs.cgs: Ditto.
-	* ldhil.cgs, ldhiq.cgs, ldlol.cgs, ldloq.cgs: Ditto.
-	* mabsl.cgs, mabsw.cgs, maddl.cgs, maddsl.cgs: Ditto.
-	* maddsub.cgs, maddsw.cgs, maddw.cgs: Ditto.
-	* mcmpeqb.cgs, mcmpeql.cgs, mcmpeqw.cgs: Ditto.
-	* mcmpgtl.cgs, mcmpgtub.cgs, mcmpgtw.cgs: Ditto.
-	* mcmv.cgs, mcnvslw.cgs, mcnvswb.cgs, mcnvswub.cgs: Ditto.
-	* mmacfxwl.cgs, mmacnfx-wl.cgs: Ditto.
-	* mmulfxl.cgs, mmulfxrpw.cgs, mmulfxw.cgs: Ditto.
-	* mmulhiwl.cgs, mmull.cgs, mmullowl.cgs: Ditto.
-	* mmulsumwq.cgs, mmulw.cgs, movi.cgs: Ditto.
-	* mpermw.cgs, msadubq.cgs: Ditto.
-	* mshaldsl.cgs, mshaldsw.cgs: Ditto.
-	* mshardl.cgs, mshardsq.cgs, mshardw.cgs: Ditto.
-	* mshfhib.cgs, mshfhil.cgs, mshfhiw.cgs: Ditto.
-	* mshflob.cgs, mshflol.cgs, mshflow.cgs: Ditto.
-	* mshlldl.cgs, mshlldw.cgs, mshlrdl.cgs: Ditto.
-	* mshlrdw.cgs, msubl.cgs, msubsl.cgs: Ditto.
-	* msubsub.cgs, msubsw.cgs, msubw.cgs: Ditto.
-	* mulsl.cgs, mulul.cgs: Ditto.
-	* ptabs.cgs, ptb.cgs, ptrel.cgs: Ditto.
-	* shard.cgs, shardl.cgs, shari.cgs, sharil.cgs: Ditto.
-	* shlld.cgs, shlldl.cgs, shlli.cgs, shllil.cgs: Ditto.
-	* shlrd.cgs, shlrdl.cgs, shlri.cgs, shlril.cgs: Ditto.
-	* sthil.cgs, sthiq.cgs, swapq.cgs, trapa.cgs: Ditto.
-
-	* testutils.inc (pass): Pass correct "syscall" number.
-	(fail): Ditto.
-
-2000-12-13  Ben Elliston  <bje@redhat.com>
-
-	* sub.cgs, subl.cgs: Complete test cases.
-	* ptrel.cgs: Likewise.
-
-	* shori.cgs: Test for zero extension of immediate operand.
-	* fcmpged.cgs, fcmpges.cgs, fldd.cgs: Complete test cases.
-	* fldp.cgs, flds.cgs, fldxd.cgs, fldxp.cgs: Likewise.
-	* fldxs.cgs, fmacs.cgs, fnegd.cgs, fnegs.cgs: Likewise.
-	* fsqrtd.cgs, fsqrts.cgs, fstd.cgs, fstp.cgs: Likewise.
-	* fsts.cgs, fstxd.cgs, fstxs.cgs: Likewise.
-
-2000-12-12  Ben Elliston  <bje@redhat.com>
-
-	* testutils.inc (pass): Use simple syscall mechanism.
-	(fail): Likewise.
-	(_packb, _packw, _packl): New macros for packing slices.
-
-	* stb.cgs, stq.cgs, stxb.cgs, stxq.cgs: Complete test cases.
-	* stl.cgs, stw.cgs, stxl.cgs, stxw.cgs: Likewise.
-	* ldl.cgs, ldq.cgs, ldub.cgs, lduw.cgs, ldw.cgs: Likewise.
-	* ldxb.cgs, ldxl.cgs, ldxq.cgs, ldxub.cgs: Likewise.
-	* ldxuw.cgs, ldxw.cgs, nsb.cgs, trapa.cgs: Likewise.
-
-	* fcmpeqd.cgs, fcmpeqs.cgs, fcmpgtd.cgs: Complete test cases.
-	* fcmpgts.cgs, fdivd.cgs, fdivs.cgs, fmovd.cgs: Likewise.
-	* fmovdq.cgs, fmovqd.cgs, fmovls.cgs, fmovs.cgs: Likewise.
-	* fmovsl.cgs: Likewise.
-
-2000-12-11  Ben Elliston  <bje@redhat.com>
-
-	* fabss.cgs, fabsd.cgs, fadds.cgs, faddd.cgs: Complete test cases.
-	* getcfg.cgs, getcon.cgs, gettr.cgs, icbi.cgs: Likewise.
-	* prefi.cgs, pta.cgs, ptabs.cgs, ptb.cgs: Likewise.
-	* putcon.cgs, putcfg.cgs, rte.cgs: Likewise.
-
-	* add.cgs, addi.cgs, addl.cgs, addil.cgs: Complete test cases.
-	* addl.cgs, addzl.cgs, alloco.cgs, and.cgs, andc.cgs: Likewise.
-	* andi.cgs, beq.cgs, beqi.cgs, bge.cgs, bgeu.cgs: Likewise.
-	* bgt.cgs, bgtu.cgs, blink.cgs, bne.cgs, bnei.cgs: Likewise.
-	* brk.cgs, byterev.cgs, cmpeq.cgs, cmpgt.cgs: Likewise.
-	* cmpgtu.cgs, cmveq.cgs, cmvne.cgs: Likewise.
-
-2000-12-07  Ben Elliston  <bje@redhat.com>
-
-	* mextr1.cgs, mextr2.cgs, mextr3.cgs: Complete test cases.
-	* mextr4.cgs, mextr5.cgs, mextr6.cgs, mextr7.cgs: Likewise.
-
-2000-12-05  Ben Elliston  <bje@redhat.com>
-
-	* nop.cgs, ocbi.cgs, ocbp.cgs, ocbwb.cgs: Complete test cases.
-	* or.cgs, ori.cgs, xor.cgs, xori.cgs: Ditto.
-	* sleep.cgs, synci.cgs, synco.cgs: Ditto.
-
-2000-11-22  Ben Elliston  <bje@redhat.com>
-
-	* *.cgs: Include "media/testutils.inc", not "testutils.inc" as
-	generated test cases do.  Miscellaneous fixes.
-
-	* testutils.inc: New file.
-	* *.cgs: Generate test cases.
diff --git a/sim/testsuite/sim/sh64/media/add.cgs b/sim/testsuite/sim/sh64/media/add.cgs
deleted file mode 100644
index 9778e8fd62c..00000000000
--- a/sim/testsuite/sim/sh64/media/add.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# sh testcase for add $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global add
-init:
-	pta wrong, tr0
-add:
-	movi 10, r0
-	movi 0, r1
-	add r0, r1, r3
-	movi 10, r4
-	bne r3, r4, tr0
-
-add0:
-	movi 1, r63
-	add r63, r63, r1
-	bnei r1, 0, tr0
-
-add2:
-	movi 0, r0
-	movi 10, r1
-	add r0, r1, r3
-	movi 10, r4
-	bne r3, r4, tr0
-
-add3:
-	movi 10, r1
-	add r63, r1, r3
-	movi 10, r4
-	bne r3, r4, tr0
-
-add4:
-	movi 10, r1
-	add r1, r63, r3
-	movi 10, r4
-	bne r3, r4, tr0
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/addi.cgs b/sim/testsuite/sim/sh64/media/addi.cgs
deleted file mode 100644
index 3d4b49f5995..00000000000
--- a/sim/testsuite/sim/sh64/media/addi.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for addi $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-addi1:
-	movi 1, r0
-	addi r0, 10, r0
-	bnei r0, 11, tr0
-
-addi2:
-	movi 10, r0
-	addi r0, 1, r0
-	bnei r0, 11, tr0
-
-addi3:
-	movi 10, r0
-	addi r0, -1, r0
-	bnei r0, 9, tr0
-
-addi4:
-	movi 20, r0
-	addi r0, -2, r0
-	bnei r0, 18, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/addil.cgs b/sim/testsuite/sim/sh64/media/addil.cgs
deleted file mode 100644
index 5c92e2733a6..00000000000
--- a/sim/testsuite/sim/sh64/media/addil.cgs
+++ /dev/null
@@ -1,49 +0,0 @@
-# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-addil0:
-	movi 1, r63
-	addi.l r63, 0, r1
-	bnei r1, 0, tr0
-
-addil1:
-	movi 10, r0
-	addi.l r0, 0, r3
-	bnei r3, 10, tr0
-
-addil2:
-	movi 0, r0
-	addi.l r0, 10, r2
-	bnei r2, 10, tr0
-
-addil3:
-	addi.l r63, 10, r1
-	bnei r1, 10, tr0
-
-addil4:
-	movi 10, r0
-	addi.l r0, 0, r1
-	bnei r1, 10, tr0
-
-addil5:
-	# Ensure top 32-bits are discarded when adding.
-	movi 10, r0
-	shlli r0, 32, r0
-	addi r0, 10, r0
-	addi.l r0, 10, r2
-	bnei r2, 20, tr0
-	
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/addl.cgs b/sim/testsuite/sim/sh64/media/addl.cgs
deleted file mode 100644
index 7f94b616206..00000000000
--- a/sim/testsuite/sim/sh64/media/addl.cgs
+++ /dev/null
@@ -1,61 +0,0 @@
-# sh testcase for add.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global addl
-init:
-	pta wrong, tr0
-
-addl0:
-	movi 1, r63
-	add.l r63, r63, r1
-	bnei r1, 0, tr0
-
-addl1:
-	movi 10, r0
-	movi 0, r1
-	add.l r0, r1, r3
-	movi 10, r4
-	bne r3, r4, tr0
-
-addl2:
-	movi 0, r0
-	movi 10, r1
-	add.l r0, r1, r2
-	movi 10, r3
-	bne r2, r3, tr0
-
-addl3:
-	movi 10, r0
-	add.l r63, r0, r1
-	movi 10, r2
-	bne r1, r2, tr0
-
-addl4:
-	movi 10, r0
-	add.l r0, r63, r1
-	movi 10, r2
-	bne r1, r2, tr0
-
-addl5:
-	# Ensure top 32-bits are discarded when adding.
-	movi 10, r0
-	shlli r0, 32, r0
-	addi r0, 10, r0
-	movi 10, r1
-	shlli r1, 32, r1
-	addi r1, 10, r1
-	add.l r0, r1, r2
-	movi 20, r3
-	bne r2, r3, tr0
-	
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/addzl.cgs b/sim/testsuite/sim/sh64/media/addzl.cgs
deleted file mode 100644
index b7917d377a6..00000000000
--- a/sim/testsuite/sim/sh64/media/addzl.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for addz.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-addzl1:
-	movi 1, r0
-	movi 2, r1
-	addz.l r0, r1, r2
-	bnei r2, 3, tr0
-
-addzl2:
-	movi 1, r0
-	shlli r0, 32, r0
-	addi r0, 2, r0
-	movi 1, r1
-	shlli r1, 32, r1
-	addi r1, 2, r1
-	addz.l r0, r1, r2
-	bnei r2, 4, tr0
-
-addzl3:
-	movi 1, r0
-	shlli r0, 31, r0
-	addi r0, 2, r0
-	movi 2, r1
-	addz.l r0, r1, r2
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/alloco.cgs b/sim/testsuite/sim/sh64/media/alloco.cgs
deleted file mode 100644
index 5f27359c3b6..00000000000
--- a/sim/testsuite/sim/sh64/media/alloco.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for alloco $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	alloco r0, 32
-	pass
diff --git a/sim/testsuite/sim/sh64/media/and.cgs b/sim/testsuite/sim/sh64/media/and.cgs
deleted file mode 100644
index c2d42339bcf..00000000000
--- a/sim/testsuite/sim/sh64/media/and.cgs
+++ /dev/null
@@ -1,68 +0,0 @@
-# sh testcase for and $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	
-and0:
-	# 0 and 0 is 0.
-	movi 0, r0
-	movi 0, r1
-	and r0, r1, r2
-	bnei r2, 0, tr0
-
-and1:
-	# 0 and 1 is 0.
-	movi 0, r0
-	movi 1, r1
-	and r0, r1, r2
-	bnei r2, 0, tr0
-
-and2:
-	# 1 and 0 is 0.
-	movi 1, r0
-	movi 0, r1
-	and r0, r1, r2
-	bnei r2, 0, tr0
-
-and3:
-	# 1 and 1 is 1.
-	movi 1, r0
-	movi 1, r1
-	and r0, r1, r2
-	bnei r2, 1, tr0
-
-and4:
-	movi 1, r0
-	shlli r0, 63, r0
-	movi 1, r1
-	shlli r1, 63, r1
-	and r0, r1, r2
-	# Check it.
-	movi 1, r3
-	shlli r3, 63, r3
-	bne r2, r3, tr0
-
-and5:
-	movi 1, r0
-	shlli r0, 63, r0
-	movi 1, r1
-	shlli r1, 63, r1
-	ori r1, 1, r1
-	and r0, r1, r2
-	# Check it.
-	movi 1, r3
-	shlli r1, 63, r1
-	bne r1, r2, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/andc.cgs b/sim/testsuite/sim/sh64/media/andc.cgs
deleted file mode 100644
index 60b50ace465..00000000000
--- a/sim/testsuite/sim/sh64/media/andc.cgs
+++ /dev/null
@@ -1,50 +0,0 @@
-# sh testcase for andc $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-andc1:
-	# X . !X = 0.
-	movi 3, r0
-	movi 3, r1
-	andc r0, r1, r2
-	bnei r2, 0, tr0
-
-andc2:
-	# X . 0 = X.
-	movi 3, r0
-	movi 0, r1
-	andc r0, r1, r2
-	bnei r2, 3, tr0
-
-andc3:
-	# wide X . 0 = wide X.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-	movi 0, r1
-	andc r0, r1, r2
-	bne r0, r2, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/andi.cgs b/sim/testsuite/sim/sh64/media/andi.cgs
deleted file mode 100644
index decfc2fc2ec..00000000000
--- a/sim/testsuite/sim/sh64/media/andi.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for andi $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	
-andi0:
-	# 0 and 0 is 0.
-	movi 0, r0
-	andi r0, 0, r2
-	bnei r2, 0, tr0
-
-and1:
-	# 0 and 1 is 0.
-	movi 0, r0
-	andi r0, 1, r2
-	bnei r2, 0, tr0
-
-and2:
-	# 1 and 0 is 0.
-	movi 1, r0
-	andi r0, 0, r2
-	bnei r2, 0, tr0
-
-and3:
-	# 1 and 1 is 1.
-	movi 1, r0
-	andi r0, 1, r2
-	bnei r2, 1, tr0
-
-and4:
-	movi 15, r0
-	andi r0, 3, r2
-	bnei r2, 3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/beq.cgs b/sim/testsuite/sim/sh64/media/beq.cgs
deleted file mode 100644
index 6f96ffdf00f..00000000000
--- a/sim/testsuite/sim/sh64/media/beq.cgs
+++ /dev/null
@@ -1,52 +0,0 @@
-# sh testcase for beq$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global beq
-init:
-	# Load up the branch target registers.
-	pta beq2, tr0
-	pta beq3, tr1
-	pta wrong, tr2
-
-beq1:
-	# Compare r0 with itself.
-	# Always true, so branch likely.
-	movi 1, r0
-	beq/l r0, r0, tr0
-	# We should branch over this.
-	fail
-
-beq2:	
-	# Ensure high order bits are compared, too.
-	movi 1, r0
-	shlli r0, 35, r0
-	addi r0, 10, r0
-	movi 1, r1
-	shlli r1, 35, r1
-	addi r1, 10, r1
-	beq r0, r1, tr1
-	# We should branch over this, too.
-	fail
-
-beq3:
-	movi 1, r0
-	shlli r0, 35, r0
-	addi r0, 10, r0
-	movi 2, r1
-	shlli r1, 35, r1
-	addi r1, 9, r1
-	# Unlikely we'll branch!
-	beq/u r0, r1, tr2
-	# We should proceed to pass here.
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/beqi.cgs b/sim/testsuite/sim/sh64/media/beqi.cgs
deleted file mode 100644
index c2b4ea8acf5..00000000000
--- a/sim/testsuite/sim/sh64/media/beqi.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for beqi$likely $rm, $imm6, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global beqi
-init:
-	# Load up the branch target registers.
-	pta beqi2, tr0
-	pta beqi3, tr1
-	pta wrong, tr2
-
-beqi1:
-	# Always true, so branch likely.
-	movi 1, r0
-	beqi/l r0, 1, tr0
-	# We should branch over this.
-	fail
-
-beqi2:
-	movi 22, r3
-	beqi r3, 22, tr1
-	# We should branch over this.
-	fail
-
-beqi3:	
-	movi 27, r7
-	# We shouldn't branch here.
-	beqi/u r7, 23, tr2
-	# We should proceed to pass here.
-
-okay:
-	pass
-	
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/bge.cgs b/sim/testsuite/sim/sh64/media/bge.cgs
deleted file mode 100644
index 832ff06ac21..00000000000
--- a/sim/testsuite/sim/sh64/media/bge.cgs
+++ /dev/null
@@ -1,40 +0,0 @@
-# sh testcase for bge$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global bge
-init:
-	pta bge2, tr0
-	pta bge3, tr1
-	pta wrong, tr2
-	movi 0, r0
-	
-bge1:
-	# Compare r0 with itself.
-	bge/l r0, r0, tr0
-	# We should branch here.
-	fail
-
-bge2:
-	movi 1, r1
-	movi 1, r2
-	bge r1, r2, tr1
-	# We should branch here.
-	fail
-
-bge3:
-	movi -1, r1
-	movi 1, r2
-	bge r1, r2, tr2
-	# We should not branch here.
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/bgeu.cgs b/sim/testsuite/sim/sh64/media/bgeu.cgs
deleted file mode 100644
index da469d0e4ae..00000000000
--- a/sim/testsuite/sim/sh64/media/bgeu.cgs
+++ /dev/null
@@ -1,47 +0,0 @@
-# sh testcase for bgeu$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global bgeu
-init:
-	movi 0, r0
-	
-bgeu1:
-	# Compare r0 with itself.
-	pta bgeu2, tr0
-	bgeu/l r0, r0, tr0
-	# We should branch here.
-	fail
-
-bgeu2:
-	movi 1, r1
-	movi 1, r2
-	pta bge3, tr0
-	bgeu r1, r2, tr0
-	# We should branch here.
-	fail
-
-bge3:
-	movi -1, r1
-	movi 1, r2
-	# We SHOULD branch here.
-	pta bge4, tr0
-	bgeu r1, r2, tr0
-	fail
-
-bge4:
-	movi 1, r1
-	movi -1, r2
-	# We should not branch here.
-	pta wrong, tr0
-	bgeu r1, r2, tr0
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/bgt.cgs b/sim/testsuite/sim/sh64/media/bgt.cgs
deleted file mode 100644
index 8866635b818..00000000000
--- a/sim/testsuite/sim/sh64/media/bgt.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for bgt$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-
-init:
-	pta wrong, tr0
-
-bgt1:
-	movi 1, r0
-	movi -1, r1
-	bgt r1, r0, tr0
-
-bgt2:
-	bgt r0, r0, tr0
- 
-bgt3:
-	pta okay, tr1
-	movi -1, r0
-	movi 1, r1
-	bgt r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/bgtu.cgs b/sim/testsuite/sim/sh64/media/bgtu.cgs
deleted file mode 100644
index 3cc02696e75..00000000000
--- a/sim/testsuite/sim/sh64/media/bgtu.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for bgtu$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-
-init:
-	pta wrong, tr0
-
-bgtu1:
-	movi 1, r0
-	movi -1, r1
-	pta bgt2, tr1
-	bgtu r1, r0, tr1
-	fail
-
-bgt2:
-	bgtu r0, r0, tr0
- 
-bgt3:
-	pta okay, tr1
-	movi -1, r0
-	movi 1, r1
-	pta okay, tr1
-	bgtu r0, r1, tr1
-	fail
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/blink.cgs b/sim/testsuite/sim/sh64/media/blink.cgs
deleted file mode 100644
index 000d1f597f2..00000000000
--- a/sim/testsuite/sim/sh64/media/blink.cgs
+++ /dev/null
@@ -1,17 +0,0 @@
-# sh testcase for blink $trb, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-blink:
-	pta target, tr0
-	gettr tr0, r1
-	ptabs r1, tr0
-	blink tr0, r0
-	fail
-
-target:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/bne.cgs b/sim/testsuite/sim/sh64/media/bne.cgs
deleted file mode 100644
index f574147e3de..00000000000
--- a/sim/testsuite/sim/sh64/media/bne.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for bne$likely $rm, $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 1, r0
-	pta wrong, tr0
-	pta okay, tr1
-
-bne1:	
-	bne r63, r63, tr0
-bne2:
-	bne r0, r63, tr1
-bad:
-	fail
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/bnei.cgs b/sim/testsuite/sim/sh64/media/bnei.cgs
deleted file mode 100644
index 5ce33991c0d..00000000000
--- a/sim/testsuite/sim/sh64/media/bnei.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for bnei$likely $rm, $imm6, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 1, r0
-	pta wrong, tr0
-	pta okay, tr1
-
-bnei1:
-	bnei r63, 0, tr0
-bnei2:
-	bnei r0, 3, tr1
-bad:
-	fail
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/brk.cgs b/sim/testsuite/sim/sh64/media/brk.cgs
deleted file mode 100644
index 073641443ec..00000000000
--- a/sim/testsuite/sim/sh64/media/brk.cgs
+++ /dev/null
@@ -1,11 +0,0 @@
-# sh testcase for brk -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	# brk will cause the sim to trap, so avoid it.
-	pass
-	brk
diff --git a/sim/testsuite/sim/sh64/media/byterev.cgs b/sim/testsuite/sim/sh64/media/byterev.cgs
deleted file mode 100644
index d97c3adb7b0..00000000000
--- a/sim/testsuite/sim/sh64/media/byterev.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for byterev $rm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	pta wrong, tr0
-init:
-	# Put a distinctive pattern in r0.
-	movi 10, r0
-	shlli r0, 8, r0
-	ori r0, 20, r0
-	shlli r0, 8, r0
-	ori r0, 30, r0
-	shlli r0, 8, r0
-	ori r0, 40, r0
-	shlli r0, 8, r0
-	ori r0, 50, r0
-	shlli r0, 8, r0
-	ori r0, 60, r0
-	shlli r0, 8, r0
-	ori r0, 70, r0
-	shlli r0, 8, r0
-	ori r0, 80, r0
-
-byterev:
-	byterev r0, r1
-
-check:
-	andi r1, 255, r2
-	movi 10, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 20, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 30, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 40, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 50, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 60, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 70, r3
-	bne r2, r3, tr0
-	shlri r1, 8, r1
-	andi r1, 255, r2
-	movi 80, r3
-	bne r2, r3, tr0
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/cmpeq.cgs b/sim/testsuite/sim/sh64/media/cmpeq.cgs
deleted file mode 100644
index 78f51f4a65d..00000000000
--- a/sim/testsuite/sim/sh64/media/cmpeq.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for cmpeq $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-	movi 2, r2
-	movi 2, r3
-	movi 3, r4
-
-cmpeq1:
-	cmpeq r2, r2, r7
-	bne r7, r1, tr0
-
-cmpeq2:
-	cmpeq r2, r3, r7
-	bne r7, r1, tr0
-
-cmpeq3:
-	cmpeq r2, r4, r7
-	bne r7, r0, tr0
-
-cmpeq4:
-	movi 1, r2
-	shlli r2, 63, r2
-	movi 1, r3
-	shlli r3, 63, r3
-	cmpeq r2, r3, r7
-	bne r7, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/cmpgt.cgs b/sim/testsuite/sim/sh64/media/cmpgt.cgs
deleted file mode 100644
index e4a971bd5ee..00000000000
--- a/sim/testsuite/sim/sh64/media/cmpgt.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for cmpgt $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-	movi 2, r2
-	movi 2, r3
-	movi 3, r4
-
-cmpgt1:
-	cmpgt r2, r2, r7
-	bne r7, r0, tr0
-
-cmpgt2:
-	cmpgt r2, r3, r7
-	bne r7, r0, tr0
-
-cmpgt3:
-	cmpgt r4, r2, r7
-	bne r7, r1, tr0
-
-cmpgt4:
-	movi 1, r2
-	shlli r2, 63, r2
-	movi 1, r3
-	shlli r3, 63, r3
-	addi r3, 1, r3
-	cmpgt r3, r2, r7
-	bne r7, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/cmpgtu.cgs b/sim/testsuite/sim/sh64/media/cmpgtu.cgs
deleted file mode 100644
index b896dfcb9fd..00000000000
--- a/sim/testsuite/sim/sh64/media/cmpgtu.cgs
+++ /dev/null
@@ -1,43 +0,0 @@
-# sh testcase for cmpgtu $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-	movi 2, r2
-	movi 2, r3
-	movi 3, r4
-
-cmpgt1:
-	cmpgtu r2, r2, r7
-	bne r7, r0, tr0
-
-cmpgt2:
-	cmpgtu r2, r3, r7
-	bne r7, r0, tr0
-
-cmpgt3:
-	cmpgtu r4, r2, r7
-	bne r7, r1, tr0
-
-cmpgt4:
-	movi 1, r2
-	shlli r2, 63, r2
-	movi 1, r3
-	shlli r3, 63, r3
-	addi r3, 1, r3
-	cmpgtu r3, r2, r7
-	bne r7, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/cmveq.cgs b/sim/testsuite/sim/sh64/media/cmveq.cgs
deleted file mode 100644
index 0f49733de36..00000000000
--- a/sim/testsuite/sim/sh64/media/cmveq.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for cmveq $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-	movi 0, r0
-	movi 1, r1
-	movi 2, r2
-	movi 21, r3
-
-cmveq:
-	# Zap r7.
-	movi 0, r7
-
-	cmveq r0, r2, r7
-	bne r2, r7, tr0
-
-	cmveq r1, r3, r7
-	# Make sure r7 is still equal to r2.
-	bne r2, r7, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/cmvne.cgs b/sim/testsuite/sim/sh64/media/cmvne.cgs
deleted file mode 100644
index 909179afc76..00000000000
--- a/sim/testsuite/sim/sh64/media/cmvne.cgs
+++ /dev/null
@@ -1,32 +0,0 @@
-# sh testcase for cmvne $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-	movi 0, r0
-	movi 1, r1
-	movi 2, r2
-	movi 21, r3
-
-cmvne:
-	# Zap r7.
-	movi 0, r7
-
-	cmvne r1, r2, r7
-	bne r2, r7, tr0
-
-	cmvne r0, r3, r7
-	# Make sure r7 is still equal to r2.
-	bne r2, r7, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fabsd.cgs b/sim/testsuite/sim/sh64/media/fabsd.cgs
deleted file mode 100644
index 47060fcc44b..00000000000
--- a/sim/testsuite/sim/sh64/media/fabsd.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for fabs.d $drgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-
-fabs0:
-	# Ensure fabs(-1) = 1.
-	fmov.ls r0, fr7
-	float.ld fr7, dr0
-	fmov.ls r1, fr7
-	float.ld fr7, dr2
-	fsub.d dr0, dr2, dr4
-	fabs.d dr4, dr6
-	fcmpeq.d dr6, dr2, r7
-	bnei r7, 1, tr0
-
-fabs1:
-	# Ensure fabs(1) = 1.
-	fmov.ls r0, fr7
-	float.ld fr7, dr0
-	fmov.ls r1, fr7
-	float.ld fr7, dr2
-	fabs.d dr2, dr4
-	fcmpeq.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fabss.cgs b/sim/testsuite/sim/sh64/media/fabss.cgs
deleted file mode 100644
index dd9aec7e640..00000000000
--- a/sim/testsuite/sim/sh64/media/fabss.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for fabs.s $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-
-fabs0:
-	# Ensure fabs(-1) = 1.
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	fmov.ls r1, fr7
-	float.ls fr7, fr1
-	fsub.s fr0, fr1, fr2
-	fabs.s fr2, fr3
-	fcmpeq.s fr3, fr1, r7
-	bnei r7, 1, tr0
-
-fabs1:
-	# Ensure fabs(1) = 1.
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	fmov.ls r1, fr7
-	float.ls fr7, fr1
-	fabs.s fr1, fr2
-	fcmpeq.s fr1, fr2, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/faddd.cgs b/sim/testsuite/sim/sh64/media/faddd.cgs
deleted file mode 100644
index 096f8528946..00000000000
--- a/sim/testsuite/sim/sh64/media/faddd.cgs
+++ /dev/null
@@ -1,33 +0,0 @@
-# sh testcase for fadd.d $drg, $drh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	movi 2, r0
-	movi 3, r1
-
-fadd0:
-	# Add 2 and 3.
-	fmov.ls r0, fr7
-	float.ld fr7, dr0
-	fmov.ls r1, fr7
-	float.ld fr7, dr2
-	fadd.d dr0, dr2, dr4
-	# Check to make sure we got 5.
-	movi 5, r2
-	fmov.ls r2, fr7
-	float.ld fr7, dr6
-	fcmpeq.d dr4, dr6, r7
-	bnei r7, 1, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fadds.cgs b/sim/testsuite/sim/sh64/media/fadds.cgs
deleted file mode 100644
index fb93979c737..00000000000
--- a/sim/testsuite/sim/sh64/media/fadds.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for fadd.s $frg, $frh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fadds
-init:
-	pta wrong, tr0
-	movi 2, r0
-	movi 3, r1
-
-fadd0:
-	# Add 2 and 3.
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	fmov.ls r1, fr7
-	float.ls fr7, fr1
-	fadd.s fr0, fr1, fr2
-	# Check to make sure we got 5.
-	movi 5, r2
-	fmov.ls r2, fr7
-	float.ls fr7, fr3
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs
deleted file mode 100644
index c19356476f9..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fcmpeq.d $drg, $drh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpeq1:
-	movi 1, r0
-	fmov.ls r0, fr0
-	fmov.ls r0, fr1
-	float.ld fr0, dr2
-	float.ld fr1, dr4
-	fcmpeq.d dr2, dr2, r7
-	bnei r7, 1, tr0 
-
-fcmpeq2:
-	movi 1, r0
-	fmov.ls r0, fr0
-	movi 2, r1
-	fmov.ls r1, fr1
-	float.ld fr0, dr4
-	float.ld fr1, dr6
-	fcmpeq.d dr4, dr6, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs
deleted file mode 100644
index 216894d7d20..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fcmpeq.s $frg, $frh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpeq1:
-	movi 1, r0
-	fmov.ls r0, fr0
-	fmov.ls r0, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0 
-
-fcmpeq2:
-	movi 1, r0
-	fmov.ls r0, fr0
-	movi 2, r1
-	fmov.ls r1, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpged.cgs b/sim/testsuite/sim/sh64/media/fcmpged.cgs
deleted file mode 100644
index 52496cc6b14..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpged.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for fcmpge.d $drg, $drh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpge1: # 2 = 2.
-	movi 2, r0
-	fmov.ls r0, fr0
-	fmov.ls r0, fr1
-	float.ld fr0, dr2
-	float.ld fr1, dr4
-	fcmpge.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-fcmpge2: # 4 > 2.
-	movi 4, r0
-	fmov.ls r0, fr0
-	movi 2, r0
-	fmov.ls r0, fr1
-	float.ld fr0, dr2
-	float.ld fr1, dr4
-	fcmpge.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-fcmpge3: # 2 < 4.
-	movi 2, r0
-	fmov.ls r0, fr0
-	movi 4, r0
-	fmov.ls r0, fr1
-	float.ld fr0, dr2
-	float.ld fr1, dr4
-	fcmpge.d dr2, dr4, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpges.cgs b/sim/testsuite/sim/sh64/media/fcmpges.cgs
deleted file mode 100644
index 2dd0a35fd27..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpges.cgs
+++ /dev/null
@@ -1,46 +0,0 @@
-# sh testcase for fcmpge.s $frg, $frh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpge1: # 2 = 2.
-	movi 2, r0
-	fmov.ls r0, fr0
-	fmov.ls r0, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpge.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-fcmpge2: # 3 > 2.
-	movi 3, r0
-	fmov.ls r0, fr0
-	movi 2, r0
-	fmov.ls r0, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpge.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-fcmpge3: # 2 < 3.
-	movi 2, r0
-	fmov.ls r0, fr0
-	movi 3, r0
-	fmov.ls r0, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpge.s fr2, fr3, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs
deleted file mode 100644
index aec952097de..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fcmpgt.d $drg, $drh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpgt1:
-	movi 2, r0
-	fmov.qd r0, dr0
-	movi 1, r1
-	fmov.qd r1, dr2
-	float.qd dr0, dr4
-	float.qd dr2, dr6
-	fcmpgt.d dr4, dr6, r7
-	bnei r7, 1, tr0 
-
-fcmpgt2:
-	movi 1, r0
-	fmov.qd r0, dr0
-	fmov.qd r0, dr2
-	float.qd dr0, dr4
-	float.qd dr2, dr6
-	fcmpgt.d dr4, dr6, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpgts.cgs b/sim/testsuite/sim/sh64/media/fcmpgts.cgs
deleted file mode 100644
index 893bbcbf60b..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpgts.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fcmpgt.s $frg, $frh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fcmpgt1:
-	movi 2, r0
-	fmov.ls r0, fr0
-	movi 1, r1
-	fmov.ls r1, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpgt.s fr2, fr3, r7
-	bnei r7, 1, tr0 
-
-fcmpgt2:
-	movi 1, r0
-	fmov.ls r0, fr0
-	fmov.ls r0, fr1
-	float.ls fr0, fr2
-	float.ls fr1, fr3
-	fcmpgt.s fr2, fr3, r7
-	bnei r7, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpund.cgs b/sim/testsuite/sim/sh64/media/fcmpund.cgs
deleted file mode 100644
index b87fb8d9fb6..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpund.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for fcmpun.d $drg, $drh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fcmpund:	
-	movi 0, r0
-	movi 1, r1
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	fmov.qd r1, dr2
-	float.qd dr2, dr2
-	fcmpun.d dr0, dr2, r7
-	bnei r7, 0, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcmpuns.cgs b/sim/testsuite/sim/sh64/media/fcmpuns.cgs
deleted file mode 100644
index 6c2ed96b4a3..00000000000
--- a/sim/testsuite/sim/sh64/media/fcmpuns.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for fcmpun.s $frg, $frh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fcmpuns:	
-	movi 0, r0
-	movi 1, r1
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	fmov.ls r1, fr1
-	float.ls fr1, fr1
-	fcmpun.s fr0, fr1, r7
-	bnei r7, 0, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcnvds.cgs b/sim/testsuite/sim/sh64/media/fcnvds.cgs
deleted file mode 100644
index aa6c993fb85..00000000000
--- a/sim/testsuite/sim/sh64/media/fcnvds.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for fcnv.ds $drgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fcnvds:
-	movi 9, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	fcnv.ds dr0, fr3
-	movi 9, r0
-	fmov.ls r0, fr4
-	float.ls fr4, fr4
-	fcmpeq.s fr3, fr4, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fcnvsd.cgs b/sim/testsuite/sim/sh64/media/fcnvsd.cgs
deleted file mode 100644
index 6c2396fe815..00000000000
--- a/sim/testsuite/sim/sh64/media/fcnvsd.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for fcnv.sd $frgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fcnvsd:	
-	movi 9, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	fcnv.sd fr0, dr2
-	movi 9, r0
-	fmov.qd r0, dr4
-	float.qd dr4, dr4
-	fcmpeq.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fdivd.cgs b/sim/testsuite/sim/sh64/media/fdivd.cgs
deleted file mode 100644
index 62401c6b47e..00000000000
--- a/sim/testsuite/sim/sh64/media/fdivd.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for fdiv.d $drg, $drh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fdivd1:
-	movi 1, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	movi 2, r1
-	fmov.qd r1, dr2
-	float.qd dr2, dr2
-	fdiv.d dr0, dr2, dr4
-
-fdvid2:
-	movi 6, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	movi 2, r1
-	fmov.qd r1, dr2
-	float.qd dr2, dr2
-	fdiv.d dr0, dr2, dr4
-	movi 3, r3
-	fmov.qd r3, dr6
-	float.qd dr6, dr6
-	fcmpeq.d dr4, dr6, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fdivs.cgs b/sim/testsuite/sim/sh64/media/fdivs.cgs
deleted file mode 100644
index 9b20f686b92..00000000000
--- a/sim/testsuite/sim/sh64/media/fdivs.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for fdiv.s $frg, $frh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fdivs1:
-	movi 1, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	movi 2, r1
-	fmov.ls r1, fr1
-	float.ls fr1, fr1
-	fdiv.s fr0, fr1, fr2
-
-fdvis2:
-	movi 6, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	movi 2, r1
-	fmov.ls r1, fr1
-	float.ls fr1, fr1
-	fdiv.s fr0, fr1, fr2
-	movi 3, r3
-	fmov.ls r3, fr3
-	float.ls fr3, fr3
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fgetscr.cgs b/sim/testsuite/sim/sh64/media/fgetscr.cgs
deleted file mode 100644
index 6aa227480ce..00000000000
--- a/sim/testsuite/sim/sh64/media/fgetscr.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for fgetscr $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fgetscr
-fgetscr:
-	fgetscr fr0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fiprs.cgs b/sim/testsuite/sim/sh64/media/fiprs.cgs
deleted file mode 100644
index fef62d11c7c..00000000000
--- a/sim/testsuite/sim/sh64/media/fiprs.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for fipr.s $fvg, $fvh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	.macro _load val, fpreg
-	# This macro clobbers r0.
-	movi \val, r0
-	fmov.ls r0, \fpreg 
-	float.ls \fpreg, \fpreg
-	.endm
-
-	start
-
-	.global fiprs
-init:
-	pta wrong, tr0
-
-	_load 1, fr0
-	_load 2, fr1
-	_load 3, fr2
-	_load 4, fr3
-	_load 1, fr4
-	_load 2, fr5
-	_load 3, fr6
-	_load 4, fr7
-
-fiprs:
-	fipr.s fv0, fv4, fr9
-
-check:
-	_load 30, fr10
-	fcmpeq.s fr9, fr10, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fldd.cgs b/sim/testsuite/sim/sh64/media/fldd.cgs
deleted file mode 100644
index ded2a9fe8f5..00000000000
--- a/sim/testsuite/sim/sh64/media/fldd.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for fld.d $rm, $disp10x8, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 0x2800, r0
-	fld.d r0, 0, dr0
-	fld.d r0, 8, dr0
-	fld.d r0, -8, dr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fldp.cgs b/sim/testsuite/sim/sh64/media/fldp.cgs
deleted file mode 100644
index 8727110378c..00000000000
--- a/sim/testsuite/sim/sh64/media/fldp.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# sh testcase for fld.p $rm, $disp10x8, $fpf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 0x2800, r0
-
-fldp:
-	fld.p r0, 0, fp0
-	fld.p r0, 8, fp2
-	fld.p r0, -8, fp4
-	pass
diff --git a/sim/testsuite/sim/sh64/media/flds.cgs b/sim/testsuite/sim/sh64/media/flds.cgs
deleted file mode 100644
index 75d5e961e26..00000000000
--- a/sim/testsuite/sim/sh64/media/flds.cgs
+++ /dev/null
@@ -1,13 +0,0 @@
-# sh testcase for fld.s $rm, $disp10x4, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 0x2800, r0
-	fld.s r0, 0, fr0
-	fld.s r0, 4, fr0
-	fld.s r0, -4, fr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fldxd.cgs b/sim/testsuite/sim/sh64/media/fldxd.cgs
deleted file mode 100644
index 63cb56bb06f..00000000000
--- a/sim/testsuite/sim/sh64/media/fldxd.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# sh testcase for fldx.d $rm, $rn, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 0x2800, r0
-	movi 0, r1
-	fldx.d r0, r1, dr0
-	movi 8, r1
-	fldx.d r0, r1, dr0
-	movi -8, r1
-	fldx.d r0, r1, dr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fldxp.cgs b/sim/testsuite/sim/sh64/media/fldxp.cgs
deleted file mode 100644
index 3d929c6fef8..00000000000
--- a/sim/testsuite/sim/sh64/media/fldxp.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for fldx.p $rm, $rn, $fpf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 0x2800, r0
-
-fldxp:
-	movi 0, r1
-	fldx.p r0, r1, fp0
-
-	movi 8, r1
-	fldx.p r0, r1, fp2
-
-	movi -8, r1
-	fldx.p r0, r1, fp4
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fldxs.cgs b/sim/testsuite/sim/sh64/media/fldxs.cgs
deleted file mode 100644
index 10feb3e54a9..00000000000
--- a/sim/testsuite/sim/sh64/media/fldxs.cgs
+++ /dev/null
@@ -1,16 +0,0 @@
-# sh testcase for fldx.s $rm, $rn, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 0x2800, r0
-	movi 0, r1
-	fldx.s r0, r1, fr0
-	movi 4, r1
-	fldx.s r0, r1, fr0
-	movi -4, r1
-	fldx.s r0, r1, fr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/floatld.cgs b/sim/testsuite/sim/sh64/media/floatld.cgs
deleted file mode 100644
index 31f6111061b..00000000000
--- a/sim/testsuite/sim/sh64/media/floatld.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# sh testcase for float.ld $frgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 1, r0
-	fmov.ls r0, fr0
-	float.ld fr0, dr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/floatls.cgs b/sim/testsuite/sim/sh64/media/floatls.cgs
deleted file mode 100644
index 4c8fb992798..00000000000
--- a/sim/testsuite/sim/sh64/media/floatls.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# sh testcase for float.ls $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 1, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/floatqd.cgs b/sim/testsuite/sim/sh64/media/floatqd.cgs
deleted file mode 100644
index ea5ddd9e49a..00000000000
--- a/sim/testsuite/sim/sh64/media/floatqd.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# sh testcase for float.qd $drgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 1, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr2
-	pass
diff --git a/sim/testsuite/sim/sh64/media/floatqs.cgs b/sim/testsuite/sim/sh64/media/floatqs.cgs
deleted file mode 100644
index fcf35e29548..00000000000
--- a/sim/testsuite/sim/sh64/media/floatqs.cgs
+++ /dev/null
@@ -1,12 +0,0 @@
-# sh testcase for float.qs $drgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	movi 1, r0
-	fmov.qd r0, dr0
-	float.qs dr0, fr1
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fmacs.cgs b/sim/testsuite/sim/sh64/media/fmacs.cgs
deleted file mode 100644
index 62219c5fafd..00000000000
--- a/sim/testsuite/sim/sh64/media/fmacs.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for fmac.s $frg, $frh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	
-fmacs:
-	movi 2, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-
-	movi 3, r1
-	fmov.ls r1, fr1
-	float.ls fr1, fr1
-
-	movi 4, r2
-	fmov.ls r2, fr2
-	float.ls fr2, fr2
-
-	fmac.s fr0, fr1, fr2
-
-	movi 10, r3
-	fmov.ls r3, fr3
-	float.ls fr3, fr3
-
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmovd.cgs b/sim/testsuite/sim/sh64/media/fmovd.cgs
deleted file mode 100644
index 03c05ad1776..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovd.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for fmov.d $drgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fmovd:	
-	movi 4, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr2
-	fmov.d dr2, dr4
-	fcmpeq.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-	
-wrong:	
-	fail	
diff --git a/sim/testsuite/sim/sh64/media/fmovdq.cgs b/sim/testsuite/sim/sh64/media/fmovdq.cgs
deleted file mode 100644
index ff5c3fe9302..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovdq.cgs
+++ /dev/null
@@ -1,23 +0,0 @@
-# sh testcase for fmov.dq $drgh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fmovdq:
-	movi 4, r0
-	fmov.qd r0, dr0
-	fmov.dq dr0, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmovls.cgs b/sim/testsuite/sim/sh64/media/fmovls.cgs
deleted file mode 100644
index 850ec33d160..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovls.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for fmov.ls $rm, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-fmovls0:
-	movi 0, r0
-	fmov.ls r0, fr0
-
-fmovls1:
-	movi 1, r1
-	fmov.ls r1, fr1
-
-upper:
-	movi 1, r2
-	shlli r2, 63, r2
-	ori r2, 3, r2
-	# Bit 63 should be ignored.
-	fmov.ls r2, fr2
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fmovqd.cgs b/sim/testsuite/sim/sh64/media/fmovqd.cgs
deleted file mode 100644
index 64eac72b3df..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovqd.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for fmov.qd $rm, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fmovdq:
-	movi 4, r0
-	fmov.qd r0, dr0
-	fmov.dq dr0, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmovs.cgs b/sim/testsuite/sim/sh64/media/fmovs.cgs
deleted file mode 100644
index f126aa5a41c..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovs.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for fmov.s $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	
-fmovs:
-	movi 8, r0
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	fmov.s fr0, fr1
-	fcmpeq.s fr0, fr1, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmovsl.cgs b/sim/testsuite/sim/sh64/media/fmovsl.cgs
deleted file mode 100644
index 7dfdab1d145..00000000000
--- a/sim/testsuite/sim/sh64/media/fmovsl.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for fmov.sl $frgh, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-fmovsl:	
-	pta wrong, tr0
-	movi 9, r0
-	fmov.ls r0, fr0
-	fmov.sl fr0, r1
-	bne r0, r1, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmuld.cgs b/sim/testsuite/sim/sh64/media/fmuld.cgs
deleted file mode 100644
index 2ad67cdc532..00000000000
--- a/sim/testsuite/sim/sh64/media/fmuld.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for fmul.d $drg, $drh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-fmuld1:
-	movi 2, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	movi 3, r1
-	fmov.qd r1, dr2
-	float.qd dr2, dr2
-	fmul.d dr0, dr2, dr4
-	movi 6, r2
-	fmov.qd r2, dr6
-	float.qd dr6, dr6
-	fcmpeq.d dr4, dr6, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fmuls.cgs b/sim/testsuite/sim/sh64/media/fmuls.cgs
deleted file mode 100644
index 4b8875f0c59..00000000000
--- a/sim/testsuite/sim/sh64/media/fmuls.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for fmul.s $frg, $frh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-fmuls1:
-	movi 2, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	movi 3, r1
-	fmov.ls r1, fr1
-	float.ls fr1, fr1
-	fmul.s fr0, fr1, fr2
-	movi 6, r2
-	fmov.ls r2, fr3
-	float.ls fr3, fr3
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fnegd.cgs b/sim/testsuite/sim/sh64/media/fnegd.cgs
deleted file mode 100644
index 67b381345b6..00000000000
--- a/sim/testsuite/sim/sh64/media/fnegd.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for fneg.d $drgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-
-fnegd0:
-	# Ensure fnegd(0) = 0.
-	fmov.ls r0, fr7
-	float.ld fr7, dr0
-	fneg.d dr0, dr2
-	fcmpeq.d dr0, dr2, r7
-	bnei r7, 1, tr0
-
-fnegd1:
-	# Ensure fnegd(fnegd(1)) = 1.
-	fmov.ls r1, fr7
-	float.ld fr7, dr0
-	fneg.d dr0, dr2
-	fneg.d dr2, dr4
-	fcmpeq.d dr0, dr4, r7
-	bnei r7, 1, tr0
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fnegs.cgs b/sim/testsuite/sim/sh64/media/fnegs.cgs
deleted file mode 100644
index 9ad625a1f1f..00000000000
--- a/sim/testsuite/sim/sh64/media/fnegs.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for fneg.s $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-
-fnegs0:
-	# Ensure fnegs(0) = 0.
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	fneg.s fr0, fr1
-	fcmpeq.s fr0, fr1, r7
-	bnei r7, 1, tr0
-
-fnegs1:
-	# Ensure fnegs(fnegs(1)) = 1.
-	fmov.ls r1, fr7
-	float.ls fr7, fr0
-	fneg.s fr0, fr1
-	fneg.s fr1, fr2
-	fcmpeq.s fr0, fr2, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fputscr.cgs b/sim/testsuite/sim/sh64/media/fputscr.cgs
deleted file mode 100644
index 28d2e7230ee..00000000000
--- a/sim/testsuite/sim/sh64/media/fputscr.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for fputscr $frgh -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fputscr
-fputscr:
-	fputscr fr0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fsqrtd.cgs b/sim/testsuite/sim/sh64/media/fsqrtd.cgs
deleted file mode 100644
index ae6120002e0..00000000000
--- a/sim/testsuite/sim/sh64/media/fsqrtd.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for fsqrt.d $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 9, r0
-	fmov.ls r0, fr7
-	float.ld fr7, dr0
-	movi 3, r1
-	fmov.ls r1, fr7
-	float.ld fr7, dr2
-
-fsqrtd:
-	fsqrt.d dr0, dr4
-	fcmpeq.d dr2, dr4, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fsqrts.cgs b/sim/testsuite/sim/sh64/media/fsqrts.cgs
deleted file mode 100644
index f1183933159..00000000000
--- a/sim/testsuite/sim/sh64/media/fsqrts.cgs
+++ /dev/null
@@ -1,27 +0,0 @@
-# sh testcase for fsqrt.s $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 9, r0
-	fmov.ls r0, fr7
-	float.ls fr7, fr0
-	movi 3, r1
-	fmov.ls r1, fr7
-	float.ls fr7, fr2
-
-fsqrts:
-	fsqrt.s fr0, fr1
-	fcmpeq.s fr1, fr2, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fstd.cgs b/sim/testsuite/sim/sh64/media/fstd.cgs
deleted file mode 100644
index 16ab5b6672c..00000000000
--- a/sim/testsuite/sim/sh64/media/fstd.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for fst.d $rm, $disp10x8, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fstd
-fstd:	
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-	# Set target address.
-	movi 0x2800, r1
-	fmov.qd r0, dr0
-
-	fst.d r1, 0, dr0
-	fst.d r1, 8, dr0
-	fst.d r1, -8, dr0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fstp.cgs b/sim/testsuite/sim/sh64/media/fstp.cgs
deleted file mode 100644
index e0c396ac59a..00000000000
--- a/sim/testsuite/sim/sh64/media/fstp.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for fst.p $rm, $disp10x8, $fpf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fstp
-fstp:
-	fst.p r0, 0, fp0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fsts.cgs b/sim/testsuite/sim/sh64/media/fsts.cgs
deleted file mode 100644
index fb692cf274c..00000000000
--- a/sim/testsuite/sim/sh64/media/fsts.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for fst.s $rm, $disp10x4, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fsts
-fsts:
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-	# Set target address.
-	movi 0x2800, r1
-	fmov.ls r0, fr0
-
-	fst.s r1, 0, fr0
-	fst.s r1, 4, fr0
-	fst.s r1, -4, fr0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fstxd.cgs b/sim/testsuite/sim/sh64/media/fstxd.cgs
deleted file mode 100644
index 10f6c1436b5..00000000000
--- a/sim/testsuite/sim/sh64/media/fstxd.cgs
+++ /dev/null
@@ -1,31 +0,0 @@
-# sh testcase for fstx.d $rm, $rn, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fstxd
-fstxd:
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-	fmov.qd r0, dr0
-	movi 0x2800, r1
-	movi -8, r2
-	fstx.d r1, r2, dr0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fstxp.cgs b/sim/testsuite/sim/sh64/media/fstxp.cgs
deleted file mode 100644
index 1829f58eb25..00000000000
--- a/sim/testsuite/sim/sh64/media/fstxp.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for fstx.p $rm, $rn, $fpf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fstxp
-fstxp:
-	fstx.p r0, r0, fp0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fstxs.cgs b/sim/testsuite/sim/sh64/media/fstxs.cgs
deleted file mode 100644
index 0b4ff96dba9..00000000000
--- a/sim/testsuite/sim/sh64/media/fstxs.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for fstx.s $rm, $rn, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	.global fstxs
-fstxs:
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-	fmov.ls r0, fr0
-	movi 0x2800, r1
-	movi -8, r2
-	fstx.s r1, r2, fr0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/fsubd.cgs b/sim/testsuite/sim/sh64/media/fsubd.cgs
deleted file mode 100644
index 93dc421b01f..00000000000
--- a/sim/testsuite/sim/sh64/media/fsubd.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fsub.d $drg, $drh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fsubd
-init:
-	pta wrong, tr0
-
-fsubd:
-	movi 9, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-
-	movi 3, r0
-	fmov.qd r0, dr2
-	float.qd dr2, dr2
-
-	fsub.d dr0, dr2, dr4
-	
-	movi 6, r0
-	fmov.qd r0, dr6
-	float.qd dr6, dr6 
-
-	fcmpeq.d dr4, dr6, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/fsubs.cgs b/sim/testsuite/sim/sh64/media/fsubs.cgs
deleted file mode 100644
index b009f094054..00000000000
--- a/sim/testsuite/sim/sh64/media/fsubs.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for fsub.s $frg, $frh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global fsubs
-init:
-	pta wrong, tr0
-
-fsubs:
-	movi 9, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-
-	movi 3, r0
-	fmov.ls r0, fr1 
-	float.ls fr1, fr1
-
-	fsub.s fr0, fr1, fr2
-	
-	movi 6, r0
-	fmov.ls r0, fr3
-	float.ls fr3, fr3
-
-	fcmpeq.s fr2, fr3, r7
-	bnei r7, 1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ftrcdl.cgs b/sim/testsuite/sim/sh64/media/ftrcdl.cgs
deleted file mode 100644
index 3aafb83dca3..00000000000
--- a/sim/testsuite/sim/sh64/media/ftrcdl.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for ftrc.dl $drgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ftrcdl
-init:
-	pta wrong, tr0
-
-ftrcdl:
-	movi -9, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	ftrc.dl dr0, fr0
-	fmov.sl fr0, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ftrcdq.cgs b/sim/testsuite/sim/sh64/media/ftrcdq.cgs
deleted file mode 100644
index 6cd63fb029e..00000000000
--- a/sim/testsuite/sim/sh64/media/ftrcdq.cgs
+++ /dev/null
@@ -1,24 +0,0 @@
-# sh testcase for ftrc.dq $drgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-ftrcdq:
-	movi -9, r0
-	fmov.qd r0, dr0
-	float.qd dr0, dr0
-	ftrc.dq dr0, dr2
-	fmov.dq dr2, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ftrcsl.cgs b/sim/testsuite/sim/sh64/media/ftrcsl.cgs
deleted file mode 100644
index 9fd7faebd1a..00000000000
--- a/sim/testsuite/sim/sh64/media/ftrcsl.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for ftrc.sl $frgh, $frf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ftrcsl
-init:
-	pta wrong, tr0
-
-ftrcsl:
-	movi -9, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	ftrc.sl fr0, fr1
-	fmov.sl fr1, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ftrcsq.cgs b/sim/testsuite/sim/sh64/media/ftrcsq.cgs
deleted file mode 100644
index 8f19d595e10..00000000000
--- a/sim/testsuite/sim/sh64/media/ftrcsq.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# sh testcase for ftrc.sq $frgh, $drf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-ftrcsq:
-	movi -9, r0
-	fmov.ls r0, fr0
-	float.ls fr0, fr0
-	ftrc.sq fr0, dr2
-	fmov.dq dr2, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ftrvs.cgs b/sim/testsuite/sim/sh64/media/ftrvs.cgs
deleted file mode 100644
index be7a75ad885..00000000000
--- a/sim/testsuite/sim/sh64/media/ftrvs.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for ftrv.s $mtrxg, $fvh, $fvf -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	.macro _load val, fpreg
-	# This macro clobbers r0.
-	movi \val, r0
-	fmov.ls r0, \fpreg 
-	float.ls \fpreg, \fpreg
-	.endm
-
-	start
-
-init:
-	pta wrong, tr0
-
-	_load 1,  fr0
-	_load 2,  fr4
-	_load 3,  fr8
-	_load 4,  fr12
-	_load 5,  fr1
-	_load 6,  fr5
-	_load 7,  fr9
-	_load 8,  fr13
-	_load 9,  fr2
-	_load 10, fr6
-	_load 11, fr10
-	_load 12, fr14
-	_load 13, fr3
-	_load 14, fr7
-	_load 15, fr11
-	_load 16, fr15
-
-	_load 1, fr16
-	_load 2, fr17
-	_load 3, fr18
-	_load 4, fr19
-
-ftrvs:
-	ftrv.s mtrx0, fv16, fv20
-
-check:
-	_load 30, fr0
-	_load 70, fr1
-	_load 110, fr2
-	_load 150, fr3
-
-	fcmpeq.s fr0, fr20, r0
-	bnei r0, 1, tr0
-	
-	fcmpeq.s fr1, fr21, r0
-	bnei r0, 1, tr0
-
-	fcmpeq.s fr2, fr22, r0
-	bnei r0, 1, tr0
-
-	fcmpeq.s fr3, fr23, r0
-	bnei r0, 1, tr0
-	
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/getcfg.cgs b/sim/testsuite/sim/sh64/media/getcfg.cgs
deleted file mode 100644
index d151739846e..00000000000
--- a/sim/testsuite/sim/sh64/media/getcfg.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for getcfg $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	getcfg r0, 0, r0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/getcon.cgs b/sim/testsuite/sim/sh64/media/getcon.cgs
deleted file mode 100644
index 8eeb43cd5b0..00000000000
--- a/sim/testsuite/sim/sh64/media/getcon.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for getcon $crk, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-getcon1:	
-	movi 22, r0
-	putcon r0, cr0
-	getcon cr0, r1
-	bne r0, r1, tr0
-
-getcon2:
-	movi 12, r0
-	shlli r0, 35, r0
-	putcon r0, cr20
-	getcon cr20, r20
-	bne r0, r20, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/gettr.cgs b/sim/testsuite/sim/sh64/media/gettr.cgs
deleted file mode 100644
index 8840a361bb0..00000000000
--- a/sim/testsuite/sim/sh64/media/gettr.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for gettr $trb, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	# tr0 is reserved.
-	# don't use it anywhere else in this test.
-	pta wrong, tr0
-
-gettr1:
-	# Put garbage in r1, r2.
-	movi 20, r1
-	movi 30, r2
-
-	pta foo, tr1
-	pta foo, tr2
-
-check1:
-	gettr tr1, r1
-	gettr tr2, r2
-	bne r1, r2, tr0
-
-gettr2:
-	# Put garbage in r3, r4.
-	movi 21, r3
-	movi 42, r4
-	
-check2:
-	pta foo, tr1
-	gettr tr1, r2
-	ptabs r2, tr2
-	gettr tr2, r3
-	ptabs r3, tr3
-	gettr tr3, r4
-	bne r2, r4, tr0
-	
-okay:	
-	pass
-
-wrong:
-	fail
-
-foo:
-	nop
diff --git a/sim/testsuite/sim/sh64/media/icbi.cgs b/sim/testsuite/sim/sh64/media/icbi.cgs
deleted file mode 100644
index 9ba18452ef6..00000000000
--- a/sim/testsuite/sim/sh64/media/icbi.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for icbi $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	icbi r0, 0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldb.cgs b/sim/testsuite/sim/sh64/media/ldb.cgs
deleted file mode 100644
index fad1e6e15ee..00000000000
--- a/sim/testsuite/sim/sh64/media/ldb.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for ld.b $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-ldb1:
-	ld.b r3, 0, r0
-ldb2:
-	ld.b r3, -1, r0
-ldb3:
-	ld.b r3, 1, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldhil.cgs b/sim/testsuite/sim/sh64/media/ldhil.cgs
deleted file mode 100644
index 4323985ea49..00000000000
--- a/sim/testsuite/sim/sh64/media/ldhil.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for ldhi.l $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ldhil
-ldhil:
-	ldhi.l r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldhiq.cgs b/sim/testsuite/sim/sh64/media/ldhiq.cgs
deleted file mode 100644
index c34a952bba7..00000000000
--- a/sim/testsuite/sim/sh64/media/ldhiq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for ldhi.q $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ldhiq
-ldhiq:
-	ldhi.q r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldl.cgs b/sim/testsuite/sim/sh64/media/ldl.cgs
deleted file mode 100644
index b8b8725dee1..00000000000
--- a/sim/testsuite/sim/sh64/media/ldl.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for ld.l $rm, $disp10x4, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-ldl1:
-	ld.l r3, 0, r0
-ldl2:
-	ld.l r3, -4, r0
-ldl3:
-	ld.l r3, 4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldlol.cgs b/sim/testsuite/sim/sh64/media/ldlol.cgs
deleted file mode 100644
index 8204f40ebf4..00000000000
--- a/sim/testsuite/sim/sh64/media/ldlol.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for ldlo.l $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ldlol
-ldlol:
-	ldlo.l r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldloq.cgs b/sim/testsuite/sim/sh64/media/ldloq.cgs
deleted file mode 100644
index 0cf128e2013..00000000000
--- a/sim/testsuite/sim/sh64/media/ldloq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for ldlo.q $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ldloq
-ldloq:
-	ldlo.q r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldq.cgs b/sim/testsuite/sim/sh64/media/ldq.cgs
deleted file mode 100644
index cacc076bb90..00000000000
--- a/sim/testsuite/sim/sh64/media/ldq.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for ld.q $rm, $disp10x8, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-ldl1:
-	ld.q r3, 0, r0
-ldl2:
-	ld.q r3, -8, r0
-ldl3:
-	ld.q r3, 8, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldub.cgs b/sim/testsuite/sim/sh64/media/ldub.cgs
deleted file mode 100644
index 825ce642e31..00000000000
--- a/sim/testsuite/sim/sh64/media/ldub.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for ld.ub $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-ldub1:
-	ld.ub r3, 0, r0
-ldub2:
-	ld.ub r3, -1, r0
-ldub3:
-	ld.ub r3, 1, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/lduw.cgs b/sim/testsuite/sim/sh64/media/lduw.cgs
deleted file mode 100644
index a329802e22b..00000000000
--- a/sim/testsuite/sim/sh64/media/lduw.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for ld.uw $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-lduw1:
-	ld.uw r3, 0, r0
-lduw2:
-	ld.uw r3, -2, r0
-lduw3:
-	ld.uw r3, 2, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldw.cgs b/sim/testsuite/sim/sh64/media/ldw.cgs
deleted file mode 100644
index d39405515a9..00000000000
--- a/sim/testsuite/sim/sh64/media/ldw.cgs
+++ /dev/null
@@ -1,21 +0,0 @@
-# sh testcase for ld.w $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 20, r3
-	shlli r3, 8, r3
-
-ldw1:
-	ld.w r3, 0, r0
-ldw2:
-	ld.w r3, -2, r0
-ldw3:
-	ld.w r3, 2, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxb.cgs b/sim/testsuite/sim/sh64/media/ldxb.cgs
deleted file mode 100644
index 36038df8da4..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxb.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for ldx.b $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-ldxb1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.b r3, r4, r0
-
-ldxb2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 1, r4
-	ldx.b r3, r4, r0
-
-ldxb3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -1, r4
-	ldx.b r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxl.cgs b/sim/testsuite/sim/sh64/media/ldxl.cgs
deleted file mode 100644
index 0596e9f325b..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxl.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for ldx.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-ldxl1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.l r3, r4, r0
-
-ldxl2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 4, r4
-	ldx.l r3, r4, r0
-
-ldxl3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -4, r4
-	ldx.l r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxq.cgs b/sim/testsuite/sim/sh64/media/ldxq.cgs
deleted file mode 100644
index 1247f220562..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxq.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for ldx.q $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-ldxq1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.q r3, r4, r0
-
-ldxq2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 8, r4
-	ldx.q r3, r4, r0
-
-ldxq3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -8, r4
-	ldx.q r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxub.cgs b/sim/testsuite/sim/sh64/media/ldxub.cgs
deleted file mode 100644
index e863a3bfccf..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxub.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for ldx.ub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-ldxub1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.ub r3, r4, r0
-
-ldxub2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 1, r4
-	ldx.ub r3, r4, r0
-
-ldxub3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -1, r4
-	ldx.ub r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxuw.cgs b/sim/testsuite/sim/sh64/media/ldxuw.cgs
deleted file mode 100644
index 282812db895..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxuw.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for ldx.uw $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-ldxuw1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.uw r3, r4, r0
-
-ldxuw2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 2, r4
-	ldx.uw r3, r4, r0
-
-ldxuw3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -2, r4
-	ldx.uw r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ldxw.cgs b/sim/testsuite/sim/sh64/media/ldxw.cgs
deleted file mode 100644
index d377fef6177..00000000000
--- a/sim/testsuite/sim/sh64/media/ldxw.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for ldx.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-ldxw1:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 0, r4
-	ldx.w r3, r4, r0
-
-ldxw2:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi 2, r4
-	ldx.w r3, r4, r0
-
-ldxw3:
-	movi 20, r3
-	shlli r3, 8, r3
-	movi -2, r4
-	ldx.w r3, r4, r0
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mabsl.cgs b/sim/testsuite/sim/sh64/media/mabsl.cgs
deleted file mode 100644
index a8af663ea12..00000000000
--- a/sim/testsuite/sim/sh64/media/mabsl.cgs
+++ /dev/null
@@ -1,39 +0,0 @@
-# sh testcase for mabs.l $rm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mabsl
-init:
-	pta wrong, tr0
-
-mabsl1:
-	# Pack { 1 3 } into R0.
-	_packl 1, 3, r0
-
-	mabs.l r0, r1
-
-	# Test for { 1 3 } in R0.
-	_packl 1, 3, r2
-	bne r0, r2, tr0
-	
-mabsl2:
-	# Pack { -1, -1 } into R0.
-	_packl 1, 1, r0
-	
-	# Set the left sign bit.
-	movi 1, r1
-	shlli r1, 63, r1
-	or r0, r1, r0
-
-	mabs.l r0, r2
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mabsw.cgs b/sim/testsuite/sim/sh64/media/mabsw.cgs
deleted file mode 100644
index f4e980a19c6..00000000000
--- a/sim/testsuite/sim/sh64/media/mabsw.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# sh testcase for mabs.w $rm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-mabsw1:
-	# Pack { 1 3 5 7 } into R0.
-	_packw 1, 3, 5, 7, r0
-
-	mabs.l r0, r1
-
-	# Test for { 1 3 5 7 } in R0.
-	_packw 1, 3, 5, 7, r2
-	bne r0, r2, tr0
-
-mabsw2:
-	# Pack { -1, -1, -1, -1 } into R0.
-	_packw 1, 1, 1, 1, r0
-
-	# Set the left sign bit
-	movi 1, r1
-	shlli r1, 63, r1
-	or r0, r1, r0
-
-	mabs.w r0, r2
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/maddl.cgs b/sim/testsuite/sim/sh64/media/maddl.cgs
deleted file mode 100644
index 4bdf5463866..00000000000
--- a/sim/testsuite/sim/sh64/media/maddl.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for madd.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-maddl:
-	# Load { 1 2 } into r0.
-	_packl 1, 2, r0
-	# Load { 3 4 } into r1.
-	_packl 3, 4, r1
-	
-	# Add slices to produce { 4 6 }.
-	madd.l r0, r1, r2
-
-	_packl 4, 6, r3
-	bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/maddsl.cgs b/sim/testsuite/sim/sh64/media/maddsl.cgs
deleted file mode 100644
index 3977275dc89..00000000000
--- a/sim/testsuite/sim/sh64/media/maddsl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for madds.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global maddsl
-maddsl:
-	madds.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/maddsub.cgs b/sim/testsuite/sim/sh64/media/maddsub.cgs
deleted file mode 100644
index a55f927a3e1..00000000000
--- a/sim/testsuite/sim/sh64/media/maddsub.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for madds.ub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global maddsub
-maddsub:
-	madds.ub r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/maddsw.cgs b/sim/testsuite/sim/sh64/media/maddsw.cgs
deleted file mode 100644
index 45a774ed2fc..00000000000
--- a/sim/testsuite/sim/sh64/media/maddsw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for madds.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global maddsw
-maddsw:
-	madds.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/maddw.cgs b/sim/testsuite/sim/sh64/media/maddw.cgs
deleted file mode 100644
index b220ef4aee6..00000000000
--- a/sim/testsuite/sim/sh64/media/maddw.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for madd.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-maddw:
-	# Load { 1 2 3 4 } into R0.
-	_packw 1, 2, 3, 4, r0
-
-	# Load { 3 4 5 6 } into R1.
-	_packw 3, 4, 5, 6, r1
-
-	# Add slices to produce { 4 6 8 10 }.
-	madd.w r0, r1, r2
-
-	_packw 4, 6, 8, 10, r3
-	bne r2, r3, tr0
-
-okay:
-	pass
-	
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs
deleted file mode 100644
index d7af6fa5f58..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpeq.b $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpeqb
-mcmpeqb:
-	mcmpeq.b r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmpeql.cgs b/sim/testsuite/sim/sh64/media/mcmpeql.cgs
deleted file mode 100644
index 2851e80fc5e..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpeql.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpeq.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpeql
-mcmpeql:
-	mcmpeq.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs
deleted file mode 100644
index 085df84eeb9..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpeq.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpeqw
-mcmpeqw:
-	mcmpeq.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs
deleted file mode 100644
index 2ace0480506..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpgt.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpgtl
-mcmpgtl:
-	mcmpgt.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs
deleted file mode 100644
index 540ce966092..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpgt.ub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpgtub
-mcmpgtub:
-	mcmpgt.ub r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs
deleted file mode 100644
index 83274512d5e..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmpgt.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmpgtw
-mcmpgtw:
-	mcmpgt.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcmv.cgs b/sim/testsuite/sim/sh64/media/mcmv.cgs
deleted file mode 100644
index c1f59aa4f88..00000000000
--- a/sim/testsuite/sim/sh64/media/mcmv.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcmv $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcmv
-mcmv:
-	mcmv r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcnvslw.cgs b/sim/testsuite/sim/sh64/media/mcnvslw.cgs
deleted file mode 100644
index 005108b7669..00000000000
--- a/sim/testsuite/sim/sh64/media/mcnvslw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcnvs.lw $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcnvslw
-mcnvslw:
-	mcnvs.lw r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcnvswb.cgs b/sim/testsuite/sim/sh64/media/mcnvswb.cgs
deleted file mode 100644
index 0d25920f310..00000000000
--- a/sim/testsuite/sim/sh64/media/mcnvswb.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcnvs.wb $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcnvswb
-mcnvswb:
-	mcnvs.wb r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mcnvswub.cgs b/sim/testsuite/sim/sh64/media/mcnvswub.cgs
deleted file mode 100644
index 2fc74466dd0..00000000000
--- a/sim/testsuite/sim/sh64/media/mcnvswub.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mcnvs.wub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mcnvswub
-mcnvswub:
-	mcnvs.wub r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mextr1.cgs b/sim/testsuite/sim/sh64/media/mextr1.cgs
deleted file mode 100644
index b2cb3c3ff29..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr1.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr1 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr1:
-	mextr1 r0, r1, r2
-
-check:
-	# Put the result in R3.
-	movi 0x2535, r3
-	shlli r3, 8, r3
-	ori r3, 0x45, r3
-	shlli r3, 8, r3
-	ori r3, 0x55, r3
-	shlli r3, 8, r3
-	ori r3, 0x65, r3
-	shlli r3, 8, r3
-	ori r3, 0x75, r3
-	shlli r3, 8, r3
-	ori r3, 0x85, r3
-	shlli r3, 8, r3
-	ori r3, 0x10, r3
-
-	pta wrong, tr0
-	bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr2.cgs b/sim/testsuite/sim/sh64/media/mextr2.cgs
deleted file mode 100644
index cf136be8176..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr2.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr2:
-	mextr2 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x3545, r3
-        shlli r3, 8, r3
-        ori r3, 0x55, r3
-        shlli r3, 8, r3
-        ori r3, 0x65, r3
-        shlli r3, 8, r3
-        ori r3, 0x75, r3
-        shlli r3, 8, r3
-        ori r3, 0x85, r3
-        shlli r3, 8, r3
-        ori r3, 0x10, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr3.cgs b/sim/testsuite/sim/sh64/media/mextr3.cgs
deleted file mode 100644
index b8d60a447bc..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr3.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr3 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr3:
-	mextr3 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x4555, r3
-        shlli r3, 8, r3
-        ori r3, 0x65, r3
-        shlli r3, 8, r3
-        ori r3, 0x75, r3
-        shlli r3, 8, r3
-        ori r3, 0x85, r3
-        shlli r3, 8, r3
-        ori r3, 0x10, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-        shlli r3, 8, r3
-        ori r3, 0x30, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr4.cgs b/sim/testsuite/sim/sh64/media/mextr4.cgs
deleted file mode 100644
index e9ebff9be7b..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr4.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr4 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr4:
-	mextr4 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x5565, r3
-        shlli r3, 8, r3
-        ori r3, 0x75, r3
-        shlli r3, 8, r3
-        ori r3, 0x85, r3
-        shlli r3, 8, r3
-        ori r3, 0x10, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-        shlli r3, 8, r3
-        ori r3, 0x30, r3
-        shlli r3, 8, r3
-        ori r3, 0x40, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr5.cgs b/sim/testsuite/sim/sh64/media/mextr5.cgs
deleted file mode 100644
index c61a0c89f52..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr5.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr5 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr5:
-	mextr5 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x6575, r3
-        shlli r3, 8, r3
-        ori r3, 0x85, r3
-        shlli r3, 8, r3
-        ori r3, 0x10, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-        shlli r3, 8, r3
-        ori r3, 0x30, r3
-        shlli r3, 8, r3
-        ori r3, 0x40, r3
-        shlli r3, 8, r3
-        ori r3, 0x50, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr6.cgs b/sim/testsuite/sim/sh64/media/mextr6.cgs
deleted file mode 100644
index 5c6c7f60c79..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr6.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr6 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr6:
-	mextr6 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x7585, r3
-        shlli r3, 8, r3
-        ori r3, 0x10, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-        shlli r3, 8, r3
-        ori r3, 0x30, r3
-        shlli r3, 8, r3
-        ori r3, 0x40, r3
-        shlli r3, 8, r3
-        ori r3, 0x50, r3
-        shlli r3, 8, r3
-        ori r3, 0x60, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mextr7.cgs b/sim/testsuite/sim/sh64/media/mextr7.cgs
deleted file mode 100644
index e05ec7f9ab3..00000000000
--- a/sim/testsuite/sim/sh64/media/mextr7.cgs
+++ /dev/null
@@ -1,67 +0,0 @@
-# sh testcase for mextr7 $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	# Put a distinguised bit pattern in R0.
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	# Put another distinguished bit pattern in R1.
-	movi 0x1525, r1
-	shlli r1, 8, r1
-	ori r1, 0x35, r1
-	shlli r1, 8, r1
-	ori r1, 0x45, r1
-	shlli r1, 8, r1
-	ori r1, 0x55, r1
-	shlli r1, 8, r1
-	ori r1, 0x65, r1
-	shlli r1, 8, r1
-	ori r1, 0x75, r1
-	shlli r1, 8, r1
-	ori r1, 0x85, r1
- 
-mextr7:
-	mextr7 r0, r1, r2
-
-check:
-        # Put the result in R3.
-        movi 0x8510, r3
-        shlli r3, 8, r3
-        ori r3, 0x20, r3
-        shlli r3, 8, r3
-        ori r3, 0x30, r3
-        shlli r3, 8, r3
-        ori r3, 0x40, r3
-        shlli r3, 8, r3
-        ori r3, 0x50, r3
-        shlli r3, 8, r3
-        ori r3, 0x60, r3
-        shlli r3, 8, r3
-        ori r3, 0x70, r3
-
-        pta wrong, tr0
-        bne r2, r3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs
deleted file mode 100644
index dd2d9a41ae7..00000000000
--- a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmacfx.wl $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmacfxwl
-mmacfxwl:
-	mmacfx.wl r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
deleted file mode 100644
index ba634d207a3..00000000000
--- a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmacnfx.wl $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmacnfx_wl
-mmacnfx_wl:
-	mmacnfx.wl r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulfxl.cgs b/sim/testsuite/sim/sh64/media/mmulfxl.cgs
deleted file mode 100644
index 7d2d1a63268..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulfxl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmulfx.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulfxl
-mmulfxl:
-	mmulfx.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
deleted file mode 100644
index 13fdcc71d0e..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmulfxrp.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulfxrpw
-mmulfxrpw:
-	mmulfxrp.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulfxw.cgs b/sim/testsuite/sim/sh64/media/mmulfxw.cgs
deleted file mode 100644
index e2a66a7c11d..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulfxw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmulfx.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulfxw
-mmulfxw:
-	mmulfx.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs
deleted file mode 100644
index 1a41ac59286..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmulhi.wl $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulhiwl
-mmulhiwl:
-	mmulhi.wl r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmull.cgs b/sim/testsuite/sim/sh64/media/mmull.cgs
deleted file mode 100644
index b3ed9df3f35..00000000000
--- a/sim/testsuite/sim/sh64/media/mmull.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmul.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmull
-mmull:
-	mmul.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmullowl.cgs b/sim/testsuite/sim/sh64/media/mmullowl.cgs
deleted file mode 100644
index b50ccfcb5dd..00000000000
--- a/sim/testsuite/sim/sh64/media/mmullowl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmullo.wl $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmullowl
-mmullowl:
-	mmullo.wl r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs
deleted file mode 100644
index 344710b0e98..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmulsum.wq $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulsumwq
-mmulsumwq:
-	mmulsum.wq r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mmulw.cgs b/sim/testsuite/sim/sh64/media/mmulw.cgs
deleted file mode 100644
index 675c620fadc..00000000000
--- a/sim/testsuite/sim/sh64/media/mmulw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mmul.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mmulw
-mmulw:
-	mmul.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/movi.cgs b/sim/testsuite/sim/sh64/media/movi.cgs
deleted file mode 100644
index a01bcae84df..00000000000
--- a/sim/testsuite/sim/sh64/media/movi.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for movi $imm16, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-movi0:
-	movi 0, r0
-	bnei r0, 0, tr0
-movi1:
-	movi 1, r0
-	bnei r0, 1, tr0
-movi2:
-	movi 23, r0
-	bnei r0, 23, tr0
-movn:
-	movi -1, r0
-	addi r0, 1, r0
-	bnei r0, 0, tr0
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/mpermw.cgs b/sim/testsuite/sim/sh64/media/mpermw.cgs
deleted file mode 100644
index 3b6741e8107..00000000000
--- a/sim/testsuite/sim/sh64/media/mpermw.cgs
+++ /dev/null
@@ -1,51 +0,0 @@
-# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-	movi 27, r1
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-mpermw:
-	mperm.w r0, r1, r2
-
-check:
-	# Expect 0x7080506030401020.
-	movi 0x7080, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x10, r0
-	shlli r0, 8, r0
-	ori r0, 0x20, r0
-
-	bne r0, r2, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/msadubq.cgs b/sim/testsuite/sim/sh64/media/msadubq.cgs
deleted file mode 100644
index 4361883b870..00000000000
--- a/sim/testsuite/sim/sh64/media/msadubq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msad.ubq $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msadubq
-msadubq:
-	msad.ubq r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshaldsl.cgs b/sim/testsuite/sim/sh64/media/mshaldsl.cgs
deleted file mode 100644
index 1dd86ec6bb6..00000000000
--- a/sim/testsuite/sim/sh64/media/mshaldsl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshalds.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshaldsl
-mshaldsl:
-	mshalds.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshaldsw.cgs b/sim/testsuite/sim/sh64/media/mshaldsw.cgs
deleted file mode 100644
index 7ab6797e9a6..00000000000
--- a/sim/testsuite/sim/sh64/media/mshaldsw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshalds.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshaldsw
-mshaldsw:
-	mshalds.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshardl.cgs b/sim/testsuite/sim/sh64/media/mshardl.cgs
deleted file mode 100644
index 0dc102e337a..00000000000
--- a/sim/testsuite/sim/sh64/media/mshardl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshard.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshardl
-mshardl:
-	mshard.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshardsq.cgs b/sim/testsuite/sim/sh64/media/mshardsq.cgs
deleted file mode 100644
index 5f29afb8b1b..00000000000
--- a/sim/testsuite/sim/sh64/media/mshardsq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshards.q $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshardsq
-mshardsq:
-	mshards.q r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshardw.cgs b/sim/testsuite/sim/sh64/media/mshardw.cgs
deleted file mode 100644
index ecc7004febd..00000000000
--- a/sim/testsuite/sim/sh64/media/mshardw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshard.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshardw
-mshardw:
-	mshard.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshfhib.cgs b/sim/testsuite/sim/sh64/media/mshfhib.cgs
deleted file mode 100644
index b7b245e79ae..00000000000
--- a/sim/testsuite/sim/sh64/media/mshfhib.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshfhi.b $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshfhib
-mshfhib:
-	mshfhi.b r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshfhil.cgs b/sim/testsuite/sim/sh64/media/mshfhil.cgs
deleted file mode 100644
index 2fab7ae1fd9..00000000000
--- a/sim/testsuite/sim/sh64/media/mshfhil.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshfhi.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshfhil
-mshfhil:
-	mshfhi.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshfhiw.cgs b/sim/testsuite/sim/sh64/media/mshfhiw.cgs
deleted file mode 100644
index 03111413cf1..00000000000
--- a/sim/testsuite/sim/sh64/media/mshfhiw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshfhi.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshfhiw
-mshfhiw:
-	mshfhi.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshflob.cgs b/sim/testsuite/sim/sh64/media/mshflob.cgs
deleted file mode 100644
index 400e81a0598..00000000000
--- a/sim/testsuite/sim/sh64/media/mshflob.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshflo.b $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshflob
-mshflob:
-	mshflo.b r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshflol.cgs b/sim/testsuite/sim/sh64/media/mshflol.cgs
deleted file mode 100644
index 2fbdf894e60..00000000000
--- a/sim/testsuite/sim/sh64/media/mshflol.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshflo.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshflol
-mshflol:
-	mshflo.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshflow.cgs b/sim/testsuite/sim/sh64/media/mshflow.cgs
deleted file mode 100644
index 542eb042c52..00000000000
--- a/sim/testsuite/sim/sh64/media/mshflow.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshflo.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshflow
-mshflow:
-	mshflo.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshlldl.cgs b/sim/testsuite/sim/sh64/media/mshlldl.cgs
deleted file mode 100644
index 2a17c33002e..00000000000
--- a/sim/testsuite/sim/sh64/media/mshlldl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshlld.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshlldl
-mshlldl:
-	mshlld.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshlldw.cgs b/sim/testsuite/sim/sh64/media/mshlldw.cgs
deleted file mode 100644
index e4afe3d732a..00000000000
--- a/sim/testsuite/sim/sh64/media/mshlldw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshlld.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshlldw
-mshlldw:
-	mshlld.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshlrdl.cgs b/sim/testsuite/sim/sh64/media/mshlrdl.cgs
deleted file mode 100644
index 89e70772b7f..00000000000
--- a/sim/testsuite/sim/sh64/media/mshlrdl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshlrd.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshlrdl
-mshlrdl:
-	mshlrd.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mshlrdw.cgs b/sim/testsuite/sim/sh64/media/mshlrdw.cgs
deleted file mode 100644
index 4cbf2807f9c..00000000000
--- a/sim/testsuite/sim/sh64/media/mshlrdw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for mshlrd.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mshlrdw
-mshlrdw:
-	mshlrd.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/msubl.cgs b/sim/testsuite/sim/sh64/media/msubl.cgs
deleted file mode 100644
index 87151fad728..00000000000
--- a/sim/testsuite/sim/sh64/media/msubl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msub.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msubl
-msubl:
-	msub.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/msubsl.cgs b/sim/testsuite/sim/sh64/media/msubsl.cgs
deleted file mode 100644
index 014422ed8f3..00000000000
--- a/sim/testsuite/sim/sh64/media/msubsl.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msubs.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msubsl
-msubsl:
-	msubs.l r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/msubsub.cgs b/sim/testsuite/sim/sh64/media/msubsub.cgs
deleted file mode 100644
index c92c77ee72e..00000000000
--- a/sim/testsuite/sim/sh64/media/msubsub.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msubs.ub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msubsub
-msubsub:
-	msubs.ub r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/msubsw.cgs b/sim/testsuite/sim/sh64/media/msubsw.cgs
deleted file mode 100644
index 83b76a1b4b3..00000000000
--- a/sim/testsuite/sim/sh64/media/msubsw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msubs.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msubsw
-msubsw:
-	msubs.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/msubw.cgs b/sim/testsuite/sim/sh64/media/msubw.cgs
deleted file mode 100644
index 9d5e639f240..00000000000
--- a/sim/testsuite/sim/sh64/media/msubw.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for msub.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global msubw
-msubw:
-	msub.w r0, r0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/mulsl.cgs b/sim/testsuite/sim/sh64/media/mulsl.cgs
deleted file mode 100644
index d65c80cadf2..00000000000
--- a/sim/testsuite/sim/sh64/media/mulsl.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for muls.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mulsl
-init:
-	pta wrong, tr0
-	
-mulsl1:
-	movi 0, r0
-	muls.l r0, r0, r1
-	bnei r1, 0, tr0
-
-mulsl2:
-	movi 0, r0
-	movi 1, r1
-	muls.l r0, r1, r2
-	bnei r2, 0, tr0
-
-mulsl3:
-	movi 1, r0
-	movi 0, r1
-	muls.l r0, r1, r2
-	bnei r2, 0, tr0
-
-mulsl4:
-	movi 1, r0
-	movi 1, r1
-	muls.l r0, r1, r2
-	bnei r2, 1, tr0
-
-mulsl5:
-	movi 2, r0
-	movi 9, r1
-	muls.l r0, r1, r2
-	bnei r2, 18, tr0
-
-mulsl6:
-	movi 2, r0
-	movi -9, r1
-	muls.l r0, r1, r2
-	bnei r2, -18, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/media/mulul.cgs b/sim/testsuite/sim/sh64/media/mulul.cgs
deleted file mode 100644
index b795cf79ec0..00000000000
--- a/sim/testsuite/sim/sh64/media/mulul.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for mulu.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global mulul
-init:
-	pta wrong, tr0
-	
-mulul1:
-	movi 0, r0
-	mulu.l r0, r0, r1
-	bnei r1, 0, tr0
-
-mulul2:
-	movi 0, r0
-	movi 1, r1
-	mulu.l r0, r1, r2
-	bnei r2, 0, tr0
-
-mulul3:
-	movi 1, r0
-	movi 0, r1
-	mulu.l r0, r1, r2
-	bnei r2, 0, tr0
-
-mulul4:
-	movi 1, r0
-	movi 1, r1
-	mulu.l r0, r1, r2
-	bnei r2, 1, tr0
-
-mulul5:
-	movi 2, r0
-	movi 9, r1
-	mulu.l r0, r1, r2
-	bnei r2, 18, tr0
-
-mulul6:
-	movi 2, r0
-	movi -9, r1
-	mulu.l r0, r1, r2
-	beqi r2, -18, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/media/nop.cgs b/sim/testsuite/sim/sh64/media/nop.cgs
deleted file mode 100644
index a0e57530542..00000000000
--- a/sim/testsuite/sim/sh64/media/nop.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for nop -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	nop
-	pass
diff --git a/sim/testsuite/sim/sh64/media/nsb.cgs b/sim/testsuite/sim/sh64/media/nsb.cgs
deleted file mode 100644
index 8b3cffef4a8..00000000000
--- a/sim/testsuite/sim/sh64/media/nsb.cgs
+++ /dev/null
@@ -1,66 +0,0 @@
-# sh testcase for nsb $rm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-nsb0:
-	movi 0, r0
-	nsb r0, r1
-check0:
-	movi 63, r4
-	bne r1, r4, tr0
-
-nsb1:
-	# set up a loop target reg.
-	pta again1, tr1
-	# r4 holds the loop count.
-	movi 62, r4
-	movi 1, r0
-again1:
-	nsb r0, r1
-	bne r1, r4, tr0
-	# okay? go around again.
-	shlli r0, 1, r0
-	addi r4, -1, r4
-	bnei r4, 0, tr1
-
-nsb2:
-	# set up a loop target reg.
-	pta again2, tr1
-	# r4 holds the loop count.
-	movi 63, r4
-	movi -1, r0
-again2:
-	nsb r0, r1
-	bne r1, r4, tr0
-	# okay? go around again.
-	shlli r0, 1, r0
-	addi r4, -1, r4
-	bnei r4, 0, tr1
-
-nsb3:
-	movi 1, r0
-	shlli r0, 63, r0
-	nsb r0, r1
-check3:
-	movi 0, r4
-	bne r1, r4, tr0
-
-nsb4:
-	movi 7, r0
-	shlli r0, 61, r0
-	nsb r0, r1
-check4:
-	movi 2, r4
-	bne r1, r4, tr0
-
-okay:
-	pass
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ocbi.cgs b/sim/testsuite/sim/sh64/media/ocbi.cgs
deleted file mode 100644
index b210216e3db..00000000000
--- a/sim/testsuite/sim/sh64/media/ocbi.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for ocbi $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	ocbi r0, 0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ocbp.cgs b/sim/testsuite/sim/sh64/media/ocbp.cgs
deleted file mode 100644
index 9158c6f4518..00000000000
--- a/sim/testsuite/sim/sh64/media/ocbp.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for ocbp $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	ocbp r0, 0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ocbwb.cgs b/sim/testsuite/sim/sh64/media/ocbwb.cgs
deleted file mode 100644
index 6addabcf461..00000000000
--- a/sim/testsuite/sim/sh64/media/ocbwb.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for ocbwb $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	ocbwb r0, 0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/or.cgs b/sim/testsuite/sim/sh64/media/or.cgs
deleted file mode 100644
index e06759225ba..00000000000
--- a/sim/testsuite/sim/sh64/media/or.cgs
+++ /dev/null
@@ -1,44 +0,0 @@
-# sh testcase for or $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-or1:
-	movi 0, r0
-	or r0, r0, r1
-	bnei r1, 0, tr0
-
-or2:
-	movi 0, r0
-	movi 1, r1
-	or r0, r1, r2
-	bnei r2, 1, tr0
-
-or3:
-	movi 1, r0
-	movi 0, r1
-	or r0, r1, r2
-	bnei r2, 1, tr0
-
-or4:
-	movi 1, r0
-	or r0, r0, r1
-	bnei r1, 1, tr0
-
-or5:
-	movi 1, r0
-	shlli r0, 63, r0
-	movi 1, r1
-	or r0, r1, r2
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ori.cgs b/sim/testsuite/sim/sh64/media/ori.cgs
deleted file mode 100644
index 7b2554227da..00000000000
--- a/sim/testsuite/sim/sh64/media/ori.cgs
+++ /dev/null
@@ -1,41 +0,0 @@
-# sh testcase for ori $rm, $imm10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-or1:
-	movi 0, r0
-	ori r0, 0, r1
-	bnei r1, 0, tr0
-
-or2:
-	movi 0, r0
-	ori r0, 1, r2
-	bnei r2, 1, tr0
-
-or3:
-	movi 1, r0
-	ori r0, 0, r2
-	bnei r2, 1, tr0
-
-or4:
-	movi 1, r0
-	ori r0, 1, r1
-	bnei r1, 1, tr0
-
-or5:
-	movi 1, r0
-	shlli r0, 63, r0
-	ori r0, 1, r2
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/prefi.cgs b/sim/testsuite/sim/sh64/media/prefi.cgs
deleted file mode 100644
index 68d7bfe29a4..00000000000
--- a/sim/testsuite/sim/sh64/media/prefi.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for prefi $rm, $disp6x32 -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	prefi r0, 0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/pta.cgs b/sim/testsuite/sim/sh64/media/pta.cgs
deleted file mode 100644
index 9f6484a8d4c..00000000000
--- a/sim/testsuite/sim/sh64/media/pta.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for pta$likely $disp16, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-pta0:
-	pta foo, tr0
-pta1:
-	pta/l bar, tr1
-pta2:
-	pta/u baz, tr2
-	movi 0, r0
-	bnei r0, 1, tr2
-	fail
-
-foo:
-bar:
-baz:
-	pass
-	fail
-	fail
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/media/ptabs.cgs b/sim/testsuite/sim/sh64/media/ptabs.cgs
deleted file mode 100644
index 0c01f838eb8..00000000000
--- a/sim/testsuite/sim/sh64/media/ptabs.cgs
+++ /dev/null
@@ -1,25 +0,0 @@
-# sh testcase for ptabs$likely $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global ptabs
-ptabs:
-	movi 16, r0
-	shlli r0, 8, r0
-	# Add one to stay in SHmedia mode.
-	addi r0, 29, r0
-	ptabs r0, tr0
-
-	# Now jump.
-	beqi r63, 0, tr0
-
-wrong:
-	fail
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/ptb.cgs b/sim/testsuite/sim/sh64/media/ptb.cgs
deleted file mode 100644
index 129d6260439..00000000000
--- a/sim/testsuite/sim/sh64/media/ptb.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for ptb$likely $disp16, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-ptb0:
-	ptb foo, tr0
-ptb:
-	ptb/l bar, tr1
-ptb2:
-	ptb/u baz, tr2
-	movi 0, r0
-	bnei r0, 1, tr2
-	fail
-
-.mode SHcompact
-
-foo:
-bar:
-baz:
-	trapa #253
-        trapa #254
-        trapa #254 
-        trapa #254 
-        trapa #254 
diff --git a/sim/testsuite/sim/sh64/media/ptrel.cgs b/sim/testsuite/sim/sh64/media/ptrel.cgs
deleted file mode 100644
index 7e5f19b1b9c..00000000000
--- a/sim/testsuite/sim/sh64/media/ptrel.cgs
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for ptrel$likely $rn, $tra -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	# Add one to stay in SHmedia mode.
-	movi 53, r0
-	ptrel r0, tr0
-	movi 0, r0
-	# Always branch.
-	bnei r0, 1, tr0
-	fail
-	fail
-	fail
-	fail
-	fail
-	pass
-	fail
-	fail
diff --git a/sim/testsuite/sim/sh64/media/putcfg.cgs b/sim/testsuite/sim/sh64/media/putcfg.cgs
deleted file mode 100644
index 85385754a48..00000000000
--- a/sim/testsuite/sim/sh64/media/putcfg.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for putcfg $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	putcfg r0, 0, r0
-	pass
diff --git a/sim/testsuite/sim/sh64/media/putcon.cgs b/sim/testsuite/sim/sh64/media/putcon.cgs
deleted file mode 100644
index 39dfc036280..00000000000
--- a/sim/testsuite/sim/sh64/media/putcon.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for putcon $rm, $crj -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-putcon1:
-	movi 22, r0
-	putcon r0, cr0
-	getcon cr0, r1
-	bne r0, r1, tr0
-
-putcon2:
-	movi 12, r0
-	shlli r0, 35, r0
-	putcon r0, cr20
-	getcon cr20, r20
-	bne r0, r20, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/rte.cgs b/sim/testsuite/sim/sh64/media/rte.cgs
deleted file mode 100644
index e80f08541cc..00000000000
--- a/sim/testsuite/sim/sh64/media/rte.cgs
+++ /dev/null
@@ -1,11 +0,0 @@
-# sh testcase for rte -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	# Unimplemented.
-	rte
-	pass
diff --git a/sim/testsuite/sim/sh64/media/shard.cgs b/sim/testsuite/sim/sh64/media/shard.cgs
deleted file mode 100644
index 029e52902a2..00000000000
--- a/sim/testsuite/sim/sh64/media/shard.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for shard $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shard1:
-	movi 128, r0
-	movi 3, r1
-	shard r0, r1, r2
-	bnei r2, 16, tr0
-
-shard2:
-	movi -4, r0
-	movi 2, r1
-	shard r0, r1, r2
-	addi r2, 1, r2
-	bnei r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shardl.cgs b/sim/testsuite/sim/sh64/media/shardl.cgs
deleted file mode 100644
index d9acaa54f69..00000000000
--- a/sim/testsuite/sim/sh64/media/shardl.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# sh testcase for shard.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shardl1:
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	movi 1, r1
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	shard.l r0, r1, r0
-	movi  20, r1
-	shard.l r0, r1, r0
-	bnei r0, 5, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shari.cgs b/sim/testsuite/sim/sh64/media/shari.cgs
deleted file mode 100644
index 3d3a650fb0c..00000000000
--- a/sim/testsuite/sim/sh64/media/shari.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for shari $rm, $imm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shari1:
-	movi 128, r0
-	shari r0, 3, r2
-	bnei r2, 16, tr0
-
-shari2:
-	movi -4, r0
-	shari r0, 2, r2
-	addi r2, 1, r2
-	bnei r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/sharil.cgs b/sim/testsuite/sim/sh64/media/sharil.cgs
deleted file mode 100644
index be946e0c84d..00000000000
--- a/sim/testsuite/sim/sh64/media/sharil.cgs
+++ /dev/null
@@ -1,45 +0,0 @@
-# sh testcase for shari.l $rm, $imm6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-sharil1:
-	movi 0x1020, r0
-	shlli r0, 8, r0
-	ori r0, 0x30, r0
-	shlli r0, 8, r0
-	ori r0, 0x40, r0
-	shlli r0, 8, r0
-	ori r0, 0x50, r0
-	shlli r0, 8, r0
-	ori r0, 0x60, r0
-	shlli r0, 8, r0
-	ori r0, 0x70, r0
-	shlli r0, 8, r0
-	ori r0, 0x80, r0
-
-	movi 1, r1
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 1, r0
-	shari.l r0, 20, r0
-	bnei r0, 5, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
-
diff --git a/sim/testsuite/sim/sh64/media/shlld.cgs b/sim/testsuite/sim/sh64/media/shlld.cgs
deleted file mode 100644
index 05d2da4cd68..00000000000
--- a/sim/testsuite/sim/sh64/media/shlld.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for shlld $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shlld1:
-	movi 1, r0
-	movi 5, r1
-	shlld r0, r1, r2
-	movi 32, r7
-	bne r2, r7, tr0
-
-shlld2:
-	movi 2, r1
-	shlld r2, r1, r3
-	movi 128, r7
-	bne r3, r7, tr0
-
-shlld3:
-	movi 32, r1
-	shlld r0, r1, r7
-	shlld r7, r1, r2
-	bnei r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shlldl.cgs b/sim/testsuite/sim/sh64/media/shlldl.cgs
deleted file mode 100644
index 3d37f53a76b..00000000000
--- a/sim/testsuite/sim/sh64/media/shlldl.cgs
+++ /dev/null
@@ -1,34 +0,0 @@
-# sh testcase for shlld.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-shlldl1:
-	movi 1, r0
-	shlli r0, 32, r0
-	ori r0, 1, r0
-	movi 1, r1
-	shlli r1, 7, r1
-	ori r1, 3, r1
-	
-	shlld.l r0, r1, r2
-	
-check1:
-	bnei r2, 8, tr0
-
-shlldl2:
-	movi 1, r0
-	movi 31, r1
-	shlld.l r0, r1, r2
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shlli.cgs b/sim/testsuite/sim/sh64/media/shlli.cgs
deleted file mode 100644
index 9ab331c0930..00000000000
--- a/sim/testsuite/sim/sh64/media/shlli.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for shlli $rm, $imm6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shlli:
-	movi 1, r0
-	shlli r0, 3, r0
-	bnei r0, 8, tr0
-
-shlli2:
-	shlli r0, 3, r0
-
-shlli3:
-	# Shift all bits out of sight.
-	shlli r0, 63, r0
-	bnei r0, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shllil.cgs b/sim/testsuite/sim/sh64/media/shllil.cgs
deleted file mode 100644
index 347acd64084..00000000000
--- a/sim/testsuite/sim/sh64/media/shllil.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for shlli.l $rm, $imm6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global shllil
-shllil:
-	shlli.l r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/shlrd.cgs b/sim/testsuite/sim/sh64/media/shlrd.cgs
deleted file mode 100644
index 56f10bf1c0e..00000000000
--- a/sim/testsuite/sim/sh64/media/shlrd.cgs
+++ /dev/null
@@ -1,30 +0,0 @@
-# sh testcase for shlrd $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shlrd1:
-	movi 128, r0
-	movi 3, r1
-	shlrd r0, r1, r2
-	bnei r2, 16, tr0
-
-shlrd2:
-	movi -4, r0
-	movi 2, r1
-	shlrd r0, r1, r2
-	addi r2, 1, r2
-	beqi r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shlrdl.cgs b/sim/testsuite/sim/sh64/media/shlrdl.cgs
deleted file mode 100644
index 32b20c0a3cd..00000000000
--- a/sim/testsuite/sim/sh64/media/shlrdl.cgs
+++ /dev/null
@@ -1,37 +0,0 @@
-# sh testcase for shlrd.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shlrdl1:
-	movi 1, r0
-	shlli r0, 32, r0
-	ori r0, 8, r0
-	movi 1, r1
-	shlli r1, 7, r1
-	ori r1, 3, r1
-	
-	shlrd.l r0, r1, r2
-	
-check1:
-	bnei r2, 1, tr0
-
-shlrdl2:
-	movi 1, r0
-	shlli r0, 31, r0
-	movi 31, r1
-	shlld.l r0, r1, r2
-	bnei r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shlri.cgs b/sim/testsuite/sim/sh64/media/shlri.cgs
deleted file mode 100644
index 488cac9aec8..00000000000
--- a/sim/testsuite/sim/sh64/media/shlri.cgs
+++ /dev/null
@@ -1,28 +0,0 @@
-# sh testcase for shlri $rm, $imm, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shlri1:
-	movi 128, r0
-	shlri r0, 3, r2
-	bnei r2, 16, tr0
-
-shlri2:
-	movi -4, r0
-	shlri r0, 2, r2
-	addi r2, 1, r2
-	beqi r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/shlril.cgs b/sim/testsuite/sim/sh64/media/shlril.cgs
deleted file mode 100644
index bb1b2a6eaf0..00000000000
--- a/sim/testsuite/sim/sh64/media/shlril.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for shlri.l $rm, $imm6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global shlril
-shlril:
-	shlri.l r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/shori.cgs b/sim/testsuite/sim/sh64/media/shori.cgs
deleted file mode 100644
index 5f02b7d2c5f..00000000000
--- a/sim/testsuite/sim/sh64/media/shori.cgs
+++ /dev/null
@@ -1,35 +0,0 @@
-# sh testcase for shori $imm16, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-shori1:
-	movi 1, r0
-	shori 7, r0
-	# check it.
-	andi r0, 15, r7
-	bnei r7, 7, tr0
-	shlri r0, 16, r0
-	bnei r0, 1, tr0
-
-shori2:
-	# Test for zero extension bug reported by
-	# Alexandre Oliva <aoliva@redhat.com>.
-	movi 0, r0
-	shori 65535, r0
-	# check it.
-	movi 0xffff, r1
-	bne r0, r1, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/sleep.cgs b/sim/testsuite/sim/sh64/media/sleep.cgs
deleted file mode 100644
index b4c35ee8f96..00000000000
--- a/sim/testsuite/sim/sh64/media/sleep.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for sleep -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	sleep
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stb.cgs b/sim/testsuite/sim/sh64/media/stb.cgs
deleted file mode 100644
index 09de47b14a9..00000000000
--- a/sim/testsuite/sim/sh64/media/stb.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for st.b $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stb1:
-	st.b r0, 0, r7
-
-stb2:
-	st.b r0, 1, r7
-
-stb3:
-	st.b r0, -1, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/sthil.cgs b/sim/testsuite/sim/sh64/media/sthil.cgs
deleted file mode 100644
index cfee28444f8..00000000000
--- a/sim/testsuite/sim/sh64/media/sthil.cgs
+++ /dev/null
@@ -1,55 +0,0 @@
-# sh testcase for sthi.l $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-	movi 40, r0
-	shlli r0, 8, r0
-	
-	movi 0x1020, r1
-	shlli r1, 8, r1
-	addi r1, 0x30, r1
-	shlli r1, 8, r1
-	addi r1, 0x40, r1
-	shlli r1, 8, r1
-	addi r1, 0x50, r1
-	shlli r1, 8, r1
-	addi r1, 0x60, r1
-	shlli r1, 8, r1
-	addi r1, 0x70, r1
-	shlli r1, 8, r1
-	addi r1, 0x80, r1
-
-sthil1:
-	sthi.l r0, 0, r1
-
-sthil2:
-	sthi.l r0, 1, r1
-
-sthil3:	
-	sthi.l r0, 2, r1
-
-sthil4:	
-	sthi.l r0, 3, r1
-
-sthil5:	
-	sthi.l r0, -1, r1
-
-sthil6:	
-	sthi.l r0, -2, r1
-
-sthil7:	
-	sthi.l r0, -3, r1
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/sthiq.cgs b/sim/testsuite/sim/sh64/media/sthiq.cgs
deleted file mode 100644
index 6310d43e5ad..00000000000
--- a/sim/testsuite/sim/sh64/media/sthiq.cgs
+++ /dev/null
@@ -1,79 +0,0 @@
-# sh testcase for sthi.q $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-	movi 40, r0
-	shlli r0, 8, r0
-	
-	movi 0x1020, r1
-	shlli r1, 8, r1
-	addi r1, 0x30, r1
-	shlli r1, 8, r1
-	addi r1, 0x40, r1
-	shlli r1, 8, r1
-	addi r1, 0x50, r1
-	shlli r1, 8, r1
-	addi r1, 0x60, r1
-	shlli r1, 8, r1
-	addi r1, 0x70, r1
-	shlli r1, 8, r1
-	addi r1, 0x80, r1
-
-sthiq1:
-	sthi.q r0, 0, r1
-
-sthiq2:
-	sthi.q r0, 1, r1
-
-sthiq3:	
-	sthi.q r0, 2, r1
-
-sthiq4:	
-	sthi.q r0, 3, r1
-
-sthiq5:	
-	sthi.q r0, 4, r1
-
-sthiq6:	
-	sthi.q r0, 5, r1
-
-sthiq7:	
-	sthi.q r0, 6, r1
-
-sthiq8:	
-	sthi.q r0, 7, r1
-
-sthiq9:	
-	sthi.q r0, -1, r1
-
-sthiq10:	
-	sthi.q r0, -2, r1
-
-sthiq11:
-	sthi.q r0, -3, r1
-
-sthiq12:	
-	sthi.q r0, -4, r1
-
-sthiq13:	
-	sthi.q r0, -5, r1
-
-sthiq14:
-	sthi.q r0, -6, r1
-
-sthiq15:	
-	sthi.q r0, -7, r1
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/stl.cgs b/sim/testsuite/sim/sh64/media/stl.cgs
deleted file mode 100644
index 8737e354c5b..00000000000
--- a/sim/testsuite/sim/sh64/media/stl.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for st.l $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stl1:
-	st.l r0, 0, r7
-
-stl2:
-	st.l r0, 4, r7
-
-stl3:
-	st.l r0, -4, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stlol.cgs b/sim/testsuite/sim/sh64/media/stlol.cgs
deleted file mode 100644
index f2d90552509..00000000000
--- a/sim/testsuite/sim/sh64/media/stlol.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for stlo.l $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global stlol
-stlol:
-	stlo.l r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stloq.cgs b/sim/testsuite/sim/sh64/media/stloq.cgs
deleted file mode 100644
index 35c84c255cc..00000000000
--- a/sim/testsuite/sim/sh64/media/stloq.cgs
+++ /dev/null
@@ -1,14 +0,0 @@
-# sh testcase for stlo.q $rm, $disp6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-	.global stloq
-stloq:
-	stlo.q r0, 0, r0
-
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stq.cgs b/sim/testsuite/sim/sh64/media/stq.cgs
deleted file mode 100644
index e1af7956b84..00000000000
--- a/sim/testsuite/sim/sh64/media/stq.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stq1:
-	st.q r0, 0, r7
-
-stq2:
-	st.q r0, 8, r7
-
-stq3:
-	st.q r0, -8, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stw.cgs b/sim/testsuite/sim/sh64/media/stw.cgs
deleted file mode 100644
index 2446aa62795..00000000000
--- a/sim/testsuite/sim/sh64/media/stw.cgs
+++ /dev/null
@@ -1,26 +0,0 @@
-# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stw1:
-	st.w r0, 0, r7
-
-stw2:
-	st.w r0, 2, r7
-
-stw3:
-	st.w r0, -2, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stxb.cgs b/sim/testsuite/sim/sh64/media/stxb.cgs
deleted file mode 100644
index 8ab2ae31d23..00000000000
--- a/sim/testsuite/sim/sh64/media/stxb.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for stx.b $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stxb1:
-	movi 0, r1
-	stx.b r0, r1, r7
-
-stxb2:
-	movi 1, r1
-	stx.b r0, r1, r7
-
-stxb3:
-	movi -1, r1
-	stx.b r0, r1, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stxl.cgs b/sim/testsuite/sim/sh64/media/stxl.cgs
deleted file mode 100644
index 8ed2e366ab3..00000000000
--- a/sim/testsuite/sim/sh64/media/stxl.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for stx.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stxl1:
-	movi 0, r1
-	stx.l r0, r1, r7
-
-stxl2:
-	movi 4, r1
-	stx.l r0, r1, r7
-
-stxl3:
-	movi -4, r1
-	stx.l r0, r1, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stxq.cgs b/sim/testsuite/sim/sh64/media/stxq.cgs
deleted file mode 100644
index 10759fd4414..00000000000
--- a/sim/testsuite/sim/sh64/media/stxq.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for stx.q $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stxq1:
-	movi 0, r1
-	stx.q r0, r1, r7
-
-stxq2:
-	movi 8, r1
-	stx.q r0, r1, r7
-
-stxq3:
-	movi -8, r1
-	stx.q r0, r1, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/stxw.cgs b/sim/testsuite/sim/sh64/media/stxw.cgs
deleted file mode 100644
index d03981146a2..00000000000
--- a/sim/testsuite/sim/sh64/media/stxw.cgs
+++ /dev/null
@@ -1,29 +0,0 @@
-# sh testcase for stx.w $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	movi -1, r7
-	xori r7, 13, r7
-	movi 40, r0
-	shlli r0, 8, r0
-
-stxw1:
-	movi 0, r1
-	stx.w r0, r1, r7
-
-stxw2:
-	movi 2, r1
-	stx.w r0, r1, r7
-
-stxw3:
-	movi -2, r1
-	stx.w r0, r1, r7
-
-okay:
-	pass
diff --git a/sim/testsuite/sim/sh64/media/sub.cgs b/sim/testsuite/sim/sh64/media/sub.cgs
deleted file mode 100644
index e5e7530100b..00000000000
--- a/sim/testsuite/sim/sh64/media/sub.cgs
+++ /dev/null
@@ -1,42 +0,0 @@
-# sh testcase for sub $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-	movi 0, r0
-	movi 1, r1
-
-sub1:
-	# 0 - 0 = 0.
-	sub r0, r0, r2
-	bnei r2, 0, tr0
-
-sub2:
-	# 1 - 0 = 1.
-	sub r1, r0, r2
-	bnei r2, 1, tr0
-
-sub3:
-	# 0 - 1 = -1.
-	sub r0, r1, r2
-	addi r2, 1, r2
-	bnei r2, 0, tr0
-
-sub4:
-	# 5 - 2 = 3.
-	movi 5, r0
-	movi 2, r1
-	sub r0, r1, r2
-	bnei r2, 3, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/subl.cgs b/sim/testsuite/sim/sh64/media/subl.cgs
deleted file mode 100644
index 98abe59f666..00000000000
--- a/sim/testsuite/sim/sh64/media/subl.cgs
+++ /dev/null
@@ -1,38 +0,0 @@
-# sh testcase for sub.l $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-
-init:
-	pta wrong, tr0
-
-subl1:
-	# Test that the top 32 bits are ignored.
-	movi 1, r0
-	shlli r0, 32, r0
-	ori r0, 7, r0
-
-	movi 1, r1
-	shlli r1, 32, r1
-	ori r1, 2, r1
-
-	sub.l r0, r1, r2
-	bnei r2, 5, tr0
-
-subl2:
-	# Test that 0 - 1 is sign extended.
-	movi 0, r0
-	movi 1, r1
-	sub.l r0, r1, r2
-	addi r2, 1, r2
-	bnei r2, 0, tr0
-
-okay:
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/media/swapq.cgs b/sim/testsuite/sim/sh64/media/swapq.cgs
deleted file mode 100644
index 6f168b1ff48..00000000000
--- a/sim/testsuite/sim/sh64/media/swapq.cgs
+++ /dev/null
@@ -1,36 +0,0 @@
-# sh testcase for swap.q $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	movi 10, r0
-	shlli r0, 8, r0
-	ori r0, 20, r0
-	shlli r0, 8, r0
-	ori r0, 30, r0
-	shlli r0, 8, r0
-	ori r0, 40, r0
-	shlli r0, 8, r0
-	ori r0, 50, r0
-	shlli r0, 8, r0
-	ori r0, 60, r0
-	shlli r0, 8, r0
-	ori r0, 70, r0
-	shlli r0, 8, r0
-	ori r0, 80, r0
-
-	# Set up two address operands.
-	
-	movi 40, r1
-	shlli r1, 8, r1
-	movi 8, r2
-	
-swapq:
-	swap.q r1, r2, r0
-
-okay:	
-	pass
diff --git a/sim/testsuite/sim/sh64/media/synci.cgs b/sim/testsuite/sim/sh64/media/synci.cgs
deleted file mode 100644
index 65e06213a50..00000000000
--- a/sim/testsuite/sim/sh64/media/synci.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for synci -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	synci
-	pass
diff --git a/sim/testsuite/sim/sh64/media/synco.cgs b/sim/testsuite/sim/sh64/media/synco.cgs
deleted file mode 100644
index 2db6df343d4..00000000000
--- a/sim/testsuite/sim/sh64/media/synco.cgs
+++ /dev/null
@@ -1,10 +0,0 @@
-# sh testcase for synco -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	synco
-	pass
diff --git a/sim/testsuite/sim/sh64/media/testutils.inc b/sim/testsuite/sim/sh64/media/testutils.inc
deleted file mode 100644
index d3b383a1efb..00000000000
--- a/sim/testsuite/sim/sh64/media/testutils.inc
+++ /dev/null
@@ -1,51 +0,0 @@
-# Support macros for the assembly test cases.
-
-	.macro start
-	.text
-	.global start
-start:
-	.endm
-
-	.macro pass
-	movi 253, r0
-	trapa r0
-	.endm
-
-	.macro fail
-	movi 254, r0
-	trapa r0
-	.endm
-
-	.macro _packb v1 v2 v3 v4 v5 v6 v7 v8 reg
-	movi \v1, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v2, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v3, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v4, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v5, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v6, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v7, \reg
-	shlli \reg, 8, \reg
-	addi \reg, \v8, \reg
-	.endm
-
-	.macro _packw v1 v2 v3 v4 reg
-	movi \v1, \reg
-	shlli \reg, 16, \reg
-	addi \reg, \v2, \reg
-	shlli \reg, 16, \reg
-	addi \reg, \v3, \reg
-	shlli \reg, 16, \reg
-	addi \reg, \v4, \reg
-	.endm
-
-	.macro _packl v1 v2 reg
-	movi \v1, \reg
-	shlli \reg, 32, \reg
-	addi \reg, \v2, \reg 
-	.endm
diff --git a/sim/testsuite/sim/sh64/media/trapa.cgs b/sim/testsuite/sim/sh64/media/trapa.cgs
deleted file mode 100644
index c961bac73ba..00000000000
--- a/sim/testsuite/sim/sh64/media/trapa.cgs
+++ /dev/null
@@ -1,11 +0,0 @@
-# sh testcase for trapa $rm -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-	# This performs a trap to emit "pass".
-	movi 253, r0
-	trapa r0
diff --git a/sim/testsuite/sim/sh64/media/xor.cgs b/sim/testsuite/sim/sh64/media/xor.cgs
deleted file mode 100644
index 80278f0a3e0..00000000000
--- a/sim/testsuite/sim/sh64/media/xor.cgs
+++ /dev/null
@@ -1,54 +0,0 @@
-# sh testcase for xor $rm, $rn, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-xor1:
-	# 0 xor 0 = 0.
-	movi 0, r0
-	movi 0, r1
-	xor r0, r1, r2
-	bnei r2, 0, tr0
-
-xor2:
-	# 0 xor 1 = 1.
-	movi 0, r0
-	movi 1, r1
-	xor r0, r1, r2
-	bnei r2, 1, tr0
-
-xor3:
-	# 1 xor 0 = 1.
-	movi 1, r0
-	movi 0, r1
-	xor r0, r1, r2
-	bnei r2, 1, tr0
-
-xor4:
-	# 1 xor 1 = 0.
-	movi 1, r0
-	movi 1, r1
-	xor r0, r1, r2
-	bnei r2, 0, tr0
-
-xor5:
-	movi 1, r0
-	shlli r0, 63, r0
-	ori r0, 1, r0
-	movi 3, r1
-	xor r0, r1, r2
-	andi r2, 255, r2
-	bnei r2, 2, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
-	
diff --git a/sim/testsuite/sim/sh64/media/xori.cgs b/sim/testsuite/sim/sh64/media/xori.cgs
deleted file mode 100644
index 0d4d96a779d..00000000000
--- a/sim/testsuite/sim/sh64/media/xori.cgs
+++ /dev/null
@@ -1,48 +0,0 @@
-# sh testcase for xori $rm, $imm6, $rd -*- Asm -*-
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-	.include "media/testutils.inc"
-
-	start
-init:
-	pta wrong, tr0
-
-xori1:
-	# 0 xor 0 = 0.
-	movi 0, r0
-	xori r0, 0, r2
-	bnei r2, 0, tr0
-
-xori2:
-	# 0 xor 1 = 1.
-	movi 0, r0
-	xori r0, 1, r2
-	bnei r2, 1, tr0
-
-xori3:
-	# 1 xor 0 = 1.
-	movi 1, r0
-	xori r0, 0, r2
-	bnei r2, 1, tr0
-
-xori4:
-	# 1 xor 1 = 0.
-	movi 1, r0
-	xori r0, 1, r2
-	bnei r2, 0, tr0
-
-xori5:
-	movi 1, r0
-	shlli r0, 63, r0
-	ori r0, 1, r0
-	xori r0, 3, r2
-	andi r2, 255, r2
-	bnei r2, 2, tr0
-
-okay:	
-	pass
-
-wrong:
-	fail
diff --git a/sim/testsuite/sim/sh64/misc/fr-dr.s b/sim/testsuite/sim/sh64/misc/fr-dr.s
deleted file mode 100644
index 52f0e136638..00000000000
--- a/sim/testsuite/sim/sh64/misc/fr-dr.s
+++ /dev/null
@@ -1,22 +0,0 @@
-# sh testcase for floating point register shared state (see below).
-# mach: all
-# as: -isa=shmedia
-# ld: -m shelf64
-
-# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state).
-# Hitachi SH-5 CPU volume 1, p. 15.
-
-	.include "media/testutils.inc"
-
-	start
-
-	movi 42, r0
-	fmov.ls r0, fr12
-	# save this reg.
-	fmov.s fr12, fr14
-
-	movi 42, r0
-	fmov.qd r0, dr12
-	
-okay:
-	pass
author	nobody <>	2005-11-01 22:57:24 +0000
committer	nobody <>	2005-11-01 22:57:24 +0000
commit	e97bf4462428241425b287215aa9fd48478b3c36 (patch)
tree	fc92693b860773c8fdb9bd836cae7434dc790216
parent	25cf6930c89092db8bd48cf98b88dd2e258f93f6 (diff)
download	binutils-gdb-e97bf4462428241425b287215aa9fd48478b3c36.tar.gz